URL https://opencores.org/ocsvn/sc2v/sc2v/trunk

Subversion Repositories sc2v

[/] [sc2v/] [trunk/] [src/] [sc2v_step3.l] - Diff between revs 14 and 16

Rev 14	Rev 16
Line 1...	Line 1...
`/* -----------------------------------------------------------------------------`	`/* -----------------------------------------------------------------------------`
`*`	`*`
`* SystemC to Verilog Translator v0.3`	`* SystemC to Verilog Translator v0.4`
`* Provided by OpenSoc Design`	`* Provided by OpenSoc Design`
`*`	`*`
`* www.opensocdesign.com`	`* www.opensocdesign.com`
`*`	`*`
`* -----------------------------------------------------------------------------`	`* -----------------------------------------------------------------------------`
Line 30...	Line 30...

`%}`	`%}`

`%%`	`%%`
`"module"[" "][a-zA-Z][_a-zA-Z0-9][" "]*["("] yylval=(int)strdup(yytext); return MODULE;`	`"module"[" "][a-zA-Z][_a-zA-Z0-9][" "]*["("] yylval=(int)strdup(yytext); return MODULE;`
`"("[" "][a-zA-Z][_a-zA-Z0-9" "\[\]:][,] yylval=(int)strdup(yytext); return WORD;`	`"("[" "][a-zA-Z][_a-zA-Z0-9" "\[\]:][,][ ]* yylval=(int)strdup(yytext); return WORDCOLON;`
`"(" return OPENPAR;`	`[" "][a-zA-Z][_a-zA-Z0-9" "\[\]:] yylval=(int)strdup(yytext); return WORD;`
`")" return CLOSEPAR;`	`"("[ ]* return OPENPAR;`
	`[ ]*")" return CLOSEPAR;`
	`[.:"^"!%=/+_"&""-"<>"?""\|""\\"][ ] yylval=(int)strdup(yytext); return SYMBOL;`


`%%`	`%%`