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AUTHOR
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AUTHOR
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David Fick - dfick@umich.edu
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David Fick - dfick@umich.edu
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VERSION
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VERSION
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1.0 - June 27, 2010
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1.0 - June 27, 2010
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1.1 - January 7, 2011
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SCAN DESCRIPTION
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SCAN DESCRIPTION
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This is a simple scan chain implemented with deperlify. It has been
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This is a simple scan chain implemented with deperlify. It has been
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used, successfully, on multiple tapeouts.
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used, successfully, on multiple tapeouts.
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from the chip, first raise "scan_load_chain" high, pulse the two
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from the chip, first raise "scan_load_chain" high, pulse the two
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clocks once as normal, then lower "scan_load_chain". Now that
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clocks once as normal, then lower "scan_load_chain". Now that
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the chip data has been loaded into the scan chain, clock out the
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the chip data has been loaded into the scan chain, clock out the
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data as normal.
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data as normal.
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Due to the buffering latch, complex internal interfaces can be
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To create a large number of bits, address and data fields may
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be created for a signal. 2^addr_bits*data_bits must be greater
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than the size. In this way, only addr_bits+data_bits number of
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bits may be generated in the scan chain, which reduces the
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length of the scan chain, as well as the area, since latches
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are much smaller than the muxing elements needed for the
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chain. Since this is a new feature, the size specified by the
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address and data bits should most likely match the total size
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in order to avoid bugs.
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Due to the buffering latches, complex internal interfaces can be
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emulated using the scan chain. For instance, an SRAM could be
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emulated using the scan chain. For instance, an SRAM could be
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connected to a clock, chip select, write enable, 64-bit data-in,
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connected to a clock, chip select, write enable, 64-bit data-in,
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and 64-bit data-out, all of which are connected to the scan
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and 64-bit data-out, all of which are connected to the scan
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chain. The scan chain would need to be used a few times for each
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chain. The scan chain would need to be used a few times for each
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"cycle" of the SRAM. For instance, each time the clock signal
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"cycle" of the SRAM. For instance, each time the clock signal
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The example description below has additional information about
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The example description below has additional information about
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how to use the scan chain.
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how to use the scan chain.
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EXAMPLE DESCRIPTION
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EXAMPLE DESCRIPTION
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To run the example, use deperlify to generate scan.v and
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To run the example, call "make". The example uses Synopsys VCS.
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scan_testbench.v:
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perl deperlify.pl scan.perl.v
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perl depeflify.pl scan_testbench.perl.v
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Then use your Verilog simulator of choice.
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This example takes advantage of the DEPERLIFY_INCLUDE command. The
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This example takes advantage of the DEPERLIFY_INCLUDE command. The
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scan.perl.v file reads in the data structure scan_signal_list.pl
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scan.perl.v file reads in the data structure scan_signal_list.pl
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in order to generate the scan chain. The file scan_testbench.perl.v
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in order to generate the scan chain. The file scan_testbench.perl.v
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uses the same data structure to generate variables and functions
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uses the same data structure to generate variables and functions
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