| Line 74... |
Line 74... |
# Print scan chain latches
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# Print scan chain latches
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print " reg [$scan_chain_length-1:0] scan_master;\n";
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print " reg [$scan_chain_length-1:0] scan_master;\n";
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print " reg [$scan_chain_length-1:0] scan_slave;\n\n";
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print " reg [$scan_chain_length-1:0] scan_slave;\n\n";
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# Print scan_load and scan_next logic
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# Print scan_load and scan_next logic
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print " wire [$scan_chain_length-1:0] scan_load;\n";
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print " reg [$scan_chain_length-1:0] scan_load;\n";
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print " wire [$scan_chain_length-1:0] scan_next;\n\n";
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print " wire [$scan_chain_length-1:0] scan_next;\n\n";
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print " always @ (*) begin\n";
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for (my $i = 0; $i < scalar @signal_list; $i++) {
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for (my $i = 0; $i < scalar @signal_list; $i++) {
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my $begin = $signal_list[$i]{start};
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my $name = $signal_list[$i]{name};
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my $end = $signal_list[$i]{start} + $signal_list[$i]{size} - 1;
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my $size = $signal_list[$i]{size};
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my $addr_bits = $signal_list[$i]{addr_bits};
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my $data_bits = $signal_list[$i]{data_bits};
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my $size_begin = $signal_list[$i]{start};
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my $size_end = $size_begin + $size - 1;
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my $addr_begin = $signal_list[$i]{start};
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my $addr_end = $addr_begin + $addr_bits - 1;
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my $data_begin = $addr_end + 1;
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my $data_end = $data_begin + $data_bits - 1;
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print " assign scan_load[$end:$begin] = " . $signal_list[$i]{name} . ";\n";
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if ($signal_list[$i]{addr_bits} == 0) {
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print " scan_load[$size_end:$size_begin] = ${name};\n";
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} else {
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print " scan_load[$addr_end:$addr_begin] = scan_slave[$addr_end:$addr_begin];\n";
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print " case (scan_slave[$addr_end:$addr_begin])\n";
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for (my $a = 0; ($a+1-1)*$data_bits < $size; $a++) {
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print " ${addr_bits}'d${a}: scan_load[$data_end:$data_begin] = ${name}[$a*$data_bits +: $data_bits];\n";
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}
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print " endcase\n";
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}
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}
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}
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print "\n assign scan_next = scan_load_chain ? scan_load : {scan_data_in, scan_slave[$'$scan_chain_length-1:1]};\n\n";
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print " end\n\n";
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print " assign scan_next = scan_load_chain ? scan_load : {scan_data_in, scan_slave[$'$scan_chain_length-1:1]};\n\n";
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# Print latches
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# Print latches
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print " //synopsys one_hot \"scan_phi, scan_phi_bar\"\n";
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print " //synopsys one_hot \"scan_phi, scan_phi_bar\"\n";
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print " always @ (*) begin\n";
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print " always @ (*) begin\n";
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print " if (scan_phi)\n";
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print " if (scan_phi)\n";
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| Line 97... |
Line 121... |
print " if (scan_phi_bar)\n";
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print " if (scan_phi_bar)\n";
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print " scan_slave = scan_master;\n";
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print " scan_slave = scan_master;\n";
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print " end\n\n";
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print " end\n\n";
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# Print input latches
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# Print input latches
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print " always @ (*) if (scan_load_chip) begin\n";
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for (my $i = 0; $i < scalar @signal_list; $i++) {
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for (my $i = 0; $i < scalar @signal_list; $i++) {
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if ($signal_list[$i]{writable} == 1) {
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if ($signal_list[$i]{writable} == 1) {
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my $begin = $signal_list[$i]{start};
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my $end = $signal_list[$i]{start} + $signal_list[$i]{size} - 1;
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my $name = $signal_list[$i]{name};
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my $name = $signal_list[$i]{name};
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print " always @ (*) if (scan_load_chip) $name = scan_slave[$end:$begin];\n";
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my $size = $signal_list[$i]{size};
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my $addr_bits = $signal_list[$i]{addr_bits};
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my $data_bits = $signal_list[$i]{data_bits};
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my $size_begin = $signal_list[$i]{start};
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my $size_end = $size_begin + $size - 1;
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my $addr_begin = $signal_list[$i]{start};
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my $addr_end = $addr_begin + $addr_bits - 1;
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my $data_begin = $addr_end + 1;
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my $data_end = $data_begin + $data_bits - 1;
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if ($signal_list[$i]{addr_bits} == 0) {
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print " $name = scan_slave[$size_end:$size_begin];\n";
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} else {
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if ($scan_reset_exists) {
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print " if (scan_slave[$scan_reset_bit]) ${name} = ${size}'d0; else\n";
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}
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}
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print " case (scan_slave[$addr_end:$addr_begin])\n";
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for (my $a = 0; ($a+1-1)*$data_bits < $size; $a++) {
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print " ${addr_bits}'d${a}: ${name}[$a*$data_bits +: $data_bits] = scan_slave[$data_end:$data_begin];\n";
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}
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}
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print " endcase\n";
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}
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}
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}
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print " end\n\n";
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# Print data_out
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# Print data_out
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print " assign scan_data_out = scan_slave[0];\n";
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print " assign scan_data_out = scan_slave[0];\n";
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*/
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*/
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