URL https://opencores.org/ocsvn/sd_card_controller/sd_card_controller/trunk

Subversion Repositories sd_card_controller

[/] [sd_card_controller/] [trunk/] [rtl/] [verilog/] [sd_data_serial_host.v] - Diff between revs 8 and 12

Rev 8	Rev 12
Line 246...	Line 246...
`data_in[31-(data_send_index[2:0]<<2)],`	`data_in[31-(data_send_index[2:0]<<2)],`
`data_in[30-(data_send_index[2:0]<<2)],`	`data_in[30-(data_send_index[2:0]<<2)],`
`data_in[29-(data_send_index[2:0]<<2)],`	`data_in[29-(data_send_index[2:0]<<2)],`
`data_in[28-(data_send_index[2:0]<<2)]`	`data_in[28-(data_send_index[2:0]<<2)]`
`};`	`};`
`if (data_send_index[2:0] == 3'h7) begin`	`if (data_send_index[2:0] == 3'h5/not 7 - read delay !!!/) begin`
`rd <= 1;`	`rd <= 1;`
	`end`
	`if (data_send_index[2:0] == 3'h7) begin`
`data_send_index <= 0;`	`data_send_index <= 0;`
`end`	`end`
`else`	`else`
`data_send_index<=data_send_index + 5'h1;`	`data_send_index<=data_send_index + 5'h1;`
`end`	`end`
`else begin`	`else begin`
`last_din <= {3'h7, data_in[31-data_send_index]};`	`last_din <= {3'h7, data_in[31-data_send_index]};`
`crc_in <= {3'h7, data_in[31-data_send_index]};`	`crc_in <= {3'h7, data_in[31-data_send_index]};`
`if (data_send_index == 31) begin`	`if (data_send_index == 29/not 31 - read delay !!!/) begin`
`rd <= 1;`	`rd <= 1;`
	`end`
	`if (data_send_index == 31) begin`
`data_send_index <= 0;`	`data_send_index <= 0;`
`end`	`end`
`else`	`else`
`data_send_index<=data_send_index + 5'h1;`	`data_send_index<=data_send_index + 5'h1;`
`end`	`end`