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Line 4... |
//// ////
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//// ////
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//// sdc_controller.v ////
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//// sdc_controller.v ////
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//// ////
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//// ////
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//// This file is part of the WISHBONE SD Card ////
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//// This file is part of the WISHBONE SD Card ////
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//// Controller IP Core project ////
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//// Controller IP Core project ////
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//// http://www.opencores.org/cores/xxx/ ////
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//// http://opencores.org/project,sd_card_controller ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Top level entity. ////
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//// Top level entity. ////
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//// This core is based on SD Card IP core project from ////
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//// This core is based on the "sd card controller" project from ////
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//// http://opencores.org/project,sdcard_mass_storage_controller ////
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//// http://opencores.org/project,sdcard_mass_storage_controller ////
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//// and is a major rewrite of original work. Effort was put to ////
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//// but has been largely rewritten. A lot of effort has been ////
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//// make the core more generic and be able to be used with ////
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//// made to make the core more generic and easily usable ////
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//// OS's like Linux. ////
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//// with OSs like Linux. ////
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//// - data transfer commands are not fixed ////
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//// - data transfer commands are not fixed ////
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//// - data transfer block size is configurable ////
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//// - data transfer block size is configurable ////
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//// - multiple block transfer support ////
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//// - multiple block transfer support ////
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//// - R2 responses (136 bit) support ////
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//// - R2 responses (136 bit) support ////
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//// ////
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//// ////
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