| Line 56... |
Line 56... |
reg [15:0] RCA;
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reg [15:0] RCA;
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reg [31:0] OCR;
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reg [31:0] OCR;
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reg [120:0] CID;
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reg [120:0] CID;
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reg Busy; //0 when busy
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reg Busy; //0 when busy
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wire [6:0] crcOut;
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wire [6:0] crcOut;
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reg [3:0] crc_c;
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reg [4:0] crc_c;
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reg [3:0] CurrentState;
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reg [3:0] CurrentState;
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reg [3:0] DataCurrentState;
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reg [3:0] DataCurrentState;
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`define RCASTART 16'h20
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`define RCASTART 16'h20
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`define OCRSTART 32'hff8000
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`define OCRSTART 32'hff8000
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| Line 673... |
Line 673... |
end
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end
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else begin
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else begin
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crcDat_en<=0;
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crcDat_en<=0;
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crcDat_rst<=1;
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crcDat_rst<=1;
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oeDat<=1;
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oeDat<=1;
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crc_c<=15;
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crc_c<=16;
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end
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end
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if (transf_cnt==1) begin
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if (transf_cnt==1) begin
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last_din <= FLASHmem[BlockAddr+(write_out_index)][7:4];
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last_din <= FLASHmem[BlockAddr+(write_out_index)][7:4];
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datOut<=0;
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datOut<=0;
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crcDat_in<= FLASHmem[BlockAddr+(write_out_index)][7:4];
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crcDat_in<= FLASHmem[BlockAddr+(write_out_index)][7:4];
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data_send_index<=1;
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data_send_index<=1;
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end
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end
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else if ( (transf_cnt>=2) && (transf_cnt<=`BIT_BLOCK-`CRC_OFF )) begin
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else if ( (transf_cnt>=2) && (transf_cnt<=`BIT_BLOCK-`CRC_OFF )) begin
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data_send_index=~data_send_index;
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data_send_index<=~data_send_index;
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if (!data_send_index) begin
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if (!data_send_index) begin
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last_din<=FLASHmem[BlockAddr+(write_out_index)][7:4];
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last_din<=FLASHmem[BlockAddr+(write_out_index)][7:4];
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crcDat_in<= FLASHmem[BlockAddr+(write_out_index)][7:4];
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crcDat_in<= FLASHmem[BlockAddr+(write_out_index)][7:4];
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end
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end
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else begin
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else begin
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| Line 704... |
Line 704... |
crcDat_en<=0;
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crcDat_en<=0;
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end
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end
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end
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end
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else if (transf_cnt>`BIT_BLOCK-`CRC_OFF & crc_c!=0) begin
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else if (transf_cnt>`BIT_BLOCK-`CRC_OFF & crc_c!=0) begin
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datOut<= last_din;
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crcDat_en<=0;
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crcDat_en<=0;
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crc_c<=crc_c-1;
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crc_c<=crc_c-1;
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if (crc_c<= 16) begin
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datOut[0]<=crcDat_out[0][crc_c-1];
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datOut[0]<=crcDat_out[0][crc_c-1];
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datOut[1]<=crcDat_out[1][crc_c-1];
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datOut[1]<=crcDat_out[1][crc_c-1];
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datOut[2]<=crcDat_out[2][crc_c-1];
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datOut[2]<=crcDat_out[2][crc_c-1];
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datOut[3]<=crcDat_out[3][crc_c-1];
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datOut[3]<=crcDat_out[3][crc_c-1];
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end
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end
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end
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else if (transf_cnt==`BIT_BLOCK-2) begin
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else if (transf_cnt==`BIT_BLOCK-2) begin
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datOut<=4'b1111;
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datOut<=4'b1111;
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end
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end
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else if ((transf_cnt !=0) && (crc_c == 0 ))begin
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else if ((transf_cnt !=0) && (crc_c == 0 ))begin
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oeDat<=0;
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oeDat<=0;
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