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//`include "timescale.v"
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`define tTLH 10 //Clock rise time
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`define tHL 10 //Clock fall time
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`define tISU 6 //Input setup time
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`define tIH 0 //Input hold time
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`define tODL 14 //Output delay
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`define BLOCKSIZE 512
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`define MEMSIZE 1000
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`define BLOCK_BUFFER_SIZE 1
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`define TIME_BUSY 64
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module sdModel(
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input sdClk,
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tri cmd,
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tri [3:0] dat
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);
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reg oeCmd;
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reg oeDat;
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reg cmdOut;
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reg datOut;
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reg [5:0] lastCMD;
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reg cardIdentificationState;
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assign cmd = oeCmd ? cmdOut : 1'bz;
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assign dat = oeDat ? datOut : 4'bz;
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reg [`MEMSIZE:0] FLASHmem [0:`BLOCKSIZE-1];
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reg [`BLOCK_BUFFER_SIZE-1:0] indatabuffer [0:`BLOCKSIZE-1];
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reg [46:0]inCmd;
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reg [5:0]cmdRead;
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reg [7:0] cmdWrite;
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reg crcIn;
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reg crcEn;
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reg crcRst;
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reg [31:0] CardStatus;
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reg [15:0] RCA;
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reg [31:0] OCR;
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reg [120:0] CID;
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reg Busy; //0 when busy
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wire [6:0] crcOut;
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reg [3 :0]CurrentState;
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`define RCASTART 16'h20
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`define OCRSTART 32'hff8000
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`define STATUSSTART 32'h0
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`define CIDSTART 128'h00ffffffddddddddaaaaaaaa99999999 //Just some random data not really usefull anyway
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`define outDelay 4
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reg [2:0] outDelayCnt;
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parameter SIZE = 10;
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parameter CONTENT_SIZE = 40;
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parameter
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IDLE = 10'b0000_0000_01,
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READ_CMD = 10'b0000_0000_10,
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ANALYZE_CMD = 10'b0000_0001_00,
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SEND_CMD = 10'b0000_0010_00;
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reg [SIZE-1:0] state;
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reg [SIZE-1:0] next_state;
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reg ValidCmd;
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reg inValidCmd;
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reg [7:0] response_S;
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reg [135:0] response_CMD;
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integer responseType;
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CRC_7 CRC_7(
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crcIn,
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crcEn,
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sdClk,
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crcRst,
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crcOut);
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reg appendCrc;
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reg [5:0] startUppCnt;
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//Card initinCMd
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initial $readmemh("FLASH.txt",FLASHmem);
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integer k;
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initial begin
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$display("Contents of Mem after reading data file:");
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for (k=0; k<10; k=k+1) $display("%d:%h",k,FLASHmem[k]);
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end
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reg qCmd;
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reg [2:0] crcCnt;
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initial begin
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cardIdentificationState<=1;
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state<=IDLE;
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Busy<=0;
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oeCmd<=0;
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crcCnt<=0;
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qCmd<=1;
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oeDat<=0;
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cmdOut<=0;
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cmdWrite<=0;
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datOut<=0;
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inCmd<=0;
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responseType=0;
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crcIn<=0;
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response_S<=0;
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crcEn<=0;
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crcRst<=0;
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cmdRead<=0;
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ValidCmd<=0;
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inValidCmd=0;
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appendCrc<=0;
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RCA<= `RCASTART;
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OCR<= `OCRSTART;
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CardStatus <= `STATUSSTART;
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CID<=`CIDSTART;
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response_CMD<=0;
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outDelayCnt<=0;
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end
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//CARD logic
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always @ (state or cmd or cmdRead or ValidCmd or inValidCmd or cmdWrite or outDelayCnt)
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begin : FSM_COMBO
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next_state = 0;
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case(state)
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IDLE: begin
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if (!cmd)
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next_state = READ_CMD;
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else
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next_state = IDLE;
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end
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READ_CMD: begin
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if (cmdRead>= 47)
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next_state = ANALYZE_CMD;
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else
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next_state = READ_CMD;
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end
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ANALYZE_CMD: begin
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if ((ValidCmd ) && (outDelayCnt >= `outDelay ))
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next_state = SEND_CMD;
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else if (inValidCmd)
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next_state = IDLE;
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else
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next_state = ANALYZE_CMD;
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end
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SEND_CMD: begin
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if (cmdWrite>= response_S)
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next_state = IDLE;
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else
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next_state = SEND_CMD;
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end
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endcase
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end
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always @ (posedge sdClk )
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begin : FSM_SEQ
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state <= next_state;
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end
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always @ (posedge sdClk) begin
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startUppCnt<=startUppCnt+1;
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OCR[31]<=Busy;
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if (startUppCnt == `TIME_BUSY)
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Busy <=1;
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end
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always @ (posedge sdClk) begin
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qCmd<=cmd;
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end
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//read data and cmd on rising edge
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always @ (posedge sdClk) begin
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case(state)
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IDLE: begin
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crcIn<=0;
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crcEn<=0;
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crcRst<=1;
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oeCmd<=0;
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oeDat<=0;
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cmdRead<=0;
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appendCrc<=0;
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ValidCmd<=0;
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inValidCmd=0;
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cmdWrite<=0;
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crcCnt<=0;
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response_CMD<=0;
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response_S<=0;
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outDelayCnt<=0;
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responseType=0;
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end
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READ_CMD: begin //read cmd
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crcEn<=1;
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crcRst<=0;
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crcIn <= #`tIH qCmd;
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inCmd[47-cmdRead] <= #`tIH qCmd;
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cmdRead <= #1 cmdRead+1;
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if (cmdRead >= 40)
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crcEn<=0;
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if (cmdRead == 46) begin
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oeCmd<=1;
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cmdOut<=1;
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end
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end
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ANALYZE_CMD: begin//check for valid cmd
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//Wrong CRC go idle
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if (inCmd[46] == 0) //start
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inValidCmd=1;
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else if (inCmd[7:1] != crcOut) begin
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inValidCmd=1;
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$fdisplay(sdModel_file_desc, "**sd_Model Commando CRC Error") ;
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$display(sdModel_file_desc, "**sd_Model Commando CRC Error") ;
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end
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else if (inCmd[0] != 1) begin//stop
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inValidCmd=1;
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$fdisplay(sdModel_file_desc, "**sd_Model Commando No Stop Bit Error") ;
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$display(sdModel_file_desc, "**sd_Model Commando No Stop Bit Error") ;
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end
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else begin
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case(inCmd[45:40])
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0 : response_S <= 0;
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2 : response_S <= 136;
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3 : response_S <= 48;
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7 : response_S <= 48;
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8 : response_S <= 0;
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14 : response_S <= 0;
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17 : response_S <= 48;
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24 : response_S <= 48;
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33 : response_S <= 48;
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55 : response_S <= 48;
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41 : response_S <= 48;
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endcase
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case(inCmd[45:40])
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0 : begin
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response_CMD <= 0;
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cardIdentificationState<=1;
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ResetCard;
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end
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2 : begin
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if (lastCMD != 41 && outDelayCnt==0) begin
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$fdisplay(sdModel_file_desc, "**Error in sequnce, ACMD 41 should precede 2 in Startup state") ;
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$display(sdModel_file_desc, "**Error in sequnce, ACMD 41 should precede 2 in Startup state") ;
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CardStatus[3]<=1;
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end
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response_CMD[127:8] <= CID;
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appendCrc<=0;
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CardStatus[12:9] <=2;
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end
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3 : begin
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if (lastCMD != 3 && outDelayCnt==0 ) begin
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$fdisplay(sdModel_file_desc, "**Error in sequnce, CMD 2 should precede 3 in Startup state") ;
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$display(sdModel_file_desc, "**Error in sequnce, CMD 2 should precede 3 in Startup state") ;
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CardStatus[3]<=1;
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end
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response_CMD[127:112] <= RCA[15:0] ;
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response_CMD[111:96] <= CardStatus[15:0] ;
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appendCrc<=1;
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CardStatus[12:9] <=3;
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cardIdentificationState<=0;
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end
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8 : response_CMD[127:96] <= 0; //V1.0 card
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17 : response_CMD[127:96]<= 48;
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24 : response_CMD[127:96] <= 48;
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33 : response_CMD[127:96] <= 48;
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55 :
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begin
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response_CMD[127:96] <= CardStatus ;
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CardStatus[5] <=1; //Next CMD is AP specific CMD
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appendCrc<=1;
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end
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41 :
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begin
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if (cardIdentificationState) begin
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if (lastCMD != 55 && outDelayCnt==0) begin
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$fdisplay(sdModel_file_desc, "**Error in sequnce, CMD 55 should precede 41 in Startup state") ;
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$display(sdModel_file_desc, "**Error in sequnce, CMD 55 should precede 41 in Startup state") ;
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CardStatus[3]<=1;
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end
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else begin
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responseType=3;
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response_CMD[127:96] <= OCR;
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appendCrc<=0;
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CardStatus[5] <=0;
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if (Busy==1)
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CardStatus[12:9] <=1;
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end
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end
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end
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endcase
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ValidCmd<=1;
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crcIn<=0;
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outDelayCnt<=outDelayCnt+1;
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if (outDelayCnt==`outDelay)
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crcRst<=1;
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oeCmd<=1;
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cmdOut<=1;
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response_CMD[135:134] <=0;
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if (responseType != 3)
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response_CMD[133:128] <=inCmd[45:40];
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if (responseType == 3)
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response_CMD[133:128] <=6'b111111;
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lastCMD <=inCmd[45:40];
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end
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end
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endcase
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end
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always @ ( negedge sdClk) begin
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case(state)
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SEND_CMD: begin
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crcRst<=0;
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crcEn<=1;
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cmdWrite<=cmdWrite+1;
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if (response_S!=0)
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cmdOut<=0;
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else
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cmdOut<=1;
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if ((cmdWrite>0) && (cmdWrite < response_S-8)) begin
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cmdOut<=response_CMD[135-cmdWrite];
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crcIn<=response_CMD[134-cmdWrite];
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if (cmdWrite >= response_S-9)
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crcEn<=0;
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end
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else if (cmdWrite!=0) begin
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crcEn<=0;
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cmdOut<=crcOut[6-crcCnt];
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crcCnt<=crcCnt+1;
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if (responseType == 3)
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cmdOut<=1;
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end
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if (cmdWrite == response_S-1)
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cmdOut<=1;
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end
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endcase
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end
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integer sdModel_file_desc;
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initial
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begin
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sdModel_file_desc = $fopen("log/sd_model.log");
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if (sdModel_file_desc < 2)
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begin
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$display("*E Could not open/create testbench log file in ../log/ directory!");
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$finish;
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end
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end
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task ResetCard; // MAC registers
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begin
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cardIdentificationState<=1;
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state<=IDLE;
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Busy<=0;
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oeCmd<=0;
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crcCnt<=0;
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qCmd<=1;
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oeDat<=0;
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cmdOut<=0;
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cmdWrite<=0;
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datOut<=0;
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inCmd<=0;
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responseType=0;
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crcIn<=0;
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response_S<=0;
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crcEn<=0;
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crcRst<=0;
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cmdRead<=0;
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ValidCmd<=0;
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inValidCmd=0;
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appendCrc<=0;
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RCA<= `RCASTART;
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OCR<= `OCRSTART;
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CardStatus <= `STATUSSTART;
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CID<=`CIDSTART;
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response_CMD<=0;
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outDelayCnt<=0;
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end
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endtask
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endmodule
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