| Line 3... |
Line 3... |
`define tTLH 10 //Clock rise time
|
`define tTLH 10 //Clock rise time
|
`define tHL 10 //Clock fall time
|
`define tHL 10 //Clock fall time
|
`define tISU 6 //Input setup time
|
`define tISU 6 //Input setup time
|
`define tIH 0 //Input hold time
|
`define tIH 0 //Input hold time
|
`define tODL 14 //Output delay
|
`define tODL 14 //Output delay
|
|
`define DLY_TO_OUTP 47
|
|
|
`define BLOCKSIZE 512
|
`define BLOCKSIZE 512
|
`define MEMSIZE 2048 // 4 block
|
`define MEMSIZE 2048 // 4 block
|
`define BLOCK_BUFFER_SIZE 1
|
`define BLOCK_BUFFER_SIZE 1
|
`define TIME_BUSY 64
|
`define TIME_BUSY 64
|
| Line 149... |
Line 150... |
CardTransferActive<=0;
|
CardTransferActive<=0;
|
qCmd<=1;
|
qCmd<=1;
|
oeDat<=0;
|
oeDat<=0;
|
cmdOut<=0;
|
cmdOut<=0;
|
cmdWrite<=0;
|
cmdWrite<=0;
|
|
|
InbuffStatus<=0;
|
InbuffStatus<=0;
|
datOut<=0;
|
datOut<=0;
|
inCmd<=0;
|
inCmd<=0;
|
BusWidth<=1;
|
BusWidth<=1;
|
responseType=0;
|
responseType=0;
|
| Line 222... |
Line 222... |
|
|
|
|
endcase
|
endcase
|
end
|
end
|
|
|
always @ (dataState or CardStatus or crc_c or flash_write_cnt or q_start_bit)
|
always @ (dataState or CardStatus or crc_c or flash_write_cnt or dat[0] )
|
begin : FSM_COMBODAT
|
begin : FSM_COMBODAT
|
next_datastate = 0;
|
next_datastate = 0;
|
case(dataState)
|
case(dataState)
|
DATA_IDLE: begin
|
DATA_IDLE: begin
|
if (CardStatus[12:9]==`RCV )
|
if (CardStatus[12:9]==`RCV )
|
| Line 236... |
Line 236... |
else
|
else
|
next_datastate = DATA_IDLE;
|
next_datastate = DATA_IDLE;
|
end
|
end
|
|
|
READ_WAITS: begin
|
READ_WAITS: begin
|
if (q_start_bit == 1'b0 )
|
if ( dat[0] == 1'b0 )
|
next_datastate = READ_DATA;
|
next_datastate = READ_DATA;
|
else
|
else
|
next_datastate = READ_WAITS;
|
next_datastate = READ_WAITS;
|
end
|
end
|
|
|
| Line 253... |
Line 253... |
WRITE_FLASH : begin
|
WRITE_FLASH : begin
|
if (flash_write_cnt>265 )
|
if (flash_write_cnt>265 )
|
next_datastate = DATA_IDLE;
|
next_datastate = DATA_IDLE;
|
else
|
else
|
next_datastate = WRITE_FLASH;
|
next_datastate = WRITE_FLASH;
|
|
end
|
|
WRITE_DATA : begin
|
|
if (transf_cnt >= `BIT_BLOCK)
|
|
next_datastate= DATA_IDLE;
|
|
else
|
|
next_datastate=WRITE_DATA;
|
end
|
end
|
|
|
|
|
|
|
|
|
| Line 312... |
Line 316... |
|
|
crcIn<=0;
|
crcIn<=0;
|
crcEn<=0;
|
crcEn<=0;
|
crcRst<=1;
|
crcRst<=1;
|
oeCmd<=0;
|
oeCmd<=0;
|
oeDat<=0;
|
|
cmdRead<=0;
|
cmdRead<=0;
|
appendCrc<=0;
|
appendCrc<=0;
|
ValidCmd<=0;
|
ValidCmd<=0;
|
inValidCmd=0;
|
inValidCmd=0;
|
cmdWrite<=0;
|
cmdWrite<=0;
|
| Line 436... |
Line 440... |
8 : response_CMD[127:96] <= 0; //V1.0 card
|
8 : response_CMD[127:96] <= 0; //V1.0 card
|
16 : begin
|
16 : begin
|
response_CMD[127:96] <= CardStatus ;
|
response_CMD[127:96] <= CardStatus ;
|
|
|
end
|
end
|
17 : response_CMD[127:96]<= 48;
|
17 : begin
|
|
if (outDelayCnt==0) begin
|
|
if (CardStatus[12:9] == `TRAN) begin //If card is in transferstate
|
|
CardStatus[12:9] <=`DATAS;//Put card in data state
|
|
response_CMD[127:96] <= CardStatus ;
|
|
BlockAddr = inCmd[39:8];
|
|
if (BlockAddr%512 !=0)
|
|
$display("**Block Misalign Error");
|
|
end
|
|
else begin
|
|
response_S <= 0;
|
|
response_CMD[127:96] <= 0;
|
|
end
|
|
end
|
|
|
|
end
|
|
|
24 : begin
|
24 : begin
|
if (outDelayCnt==0) begin
|
if (outDelayCnt==0) begin
|
if (CardStatus[12:9] == 4) begin //If card is in transferstate
|
if (CardStatus[12:9] == `TRAN) begin //If card is in transferstate
|
if (CardStatus[8]) begin //If Free write buffer
|
if (CardStatus[8]) begin //If Free write buffer
|
CardStatus[12:9] <=`RCV;//Put card in Rcv state
|
CardStatus[12:9] <=`RCV;//Put card in Rcv state
|
response_CMD[127:96] <= CardStatus ;
|
response_CMD[127:96] <= CardStatus ;
|
BlockAddr = inCmd[39:8];
|
BlockAddr = inCmd[39:8];
|
if (BlockAddr%512 !=0)
|
if (BlockAddr%512 !=0)
|
| Line 543... |
Line 563... |
|
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
|
|
|
|
|
integer outdly_cnt;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
always @ (posedge sdClk) begin
|
always @ (posedge sdClk) begin
|
|
|
case (dataState)
|
case (dataState)
|
DATA_IDLE: begin
|
DATA_IDLE: begin
|
oeDat<=0;
|
|
end
|
end
|
|
|
READ_WAITS: begin
|
READ_WAITS: begin
|
oeDat<=0;
|
oeDat<=0;
|
crcDat_rst<=0;
|
crcDat_rst<=0;
|
| Line 574... |
Line 604... |
crc_ok<=1;
|
crc_ok<=1;
|
transf_cnt<=transf_cnt+1;
|
transf_cnt<=transf_cnt+1;
|
if (wptr)
|
if (wptr)
|
block_cnt<=block_cnt+1;
|
block_cnt<=block_cnt+1;
|
wptr<=~wptr;
|
wptr<=~wptr;
|
|
|
|
|
end
|
end
|
else if ( transf_cnt <= (`BIT_BLOCK_REC +`BIT_CRC_CYCLE-1)) begin
|
else if ( transf_cnt <= (`BIT_BLOCK_REC +`BIT_CRC_CYCLE-1)) begin
|
transf_cnt<=transf_cnt+1;
|
transf_cnt<=transf_cnt+1;
|
crcDat_en<=0;
|
crcDat_en<=0;
|
last_din <=dat;
|
last_din <=dat;
|
| Line 613... |
Line 645... |
|
|
end
|
end
|
|
|
|
|
|
|
|
reg data_send_index;
|
always @ (posedge sdClk) begin
|
integer write_out_index;
|
|
always @ (negedge sdClk) begin
|
|
|
case (dataState)
|
case (dataState)
|
IDLE: begin
|
DATA_IDLE: begin
|
|
write_out_index<=0;
|
|
transf_cnt<=0;
|
|
data_send_index<=0;
|
|
outdly_cnt<=0;
|
|
|
|
end
|
|
|
|
|
|
WRITE_DATA: begin
|
|
oeDat<=1;
|
|
outdly_cnt<=outdly_cnt+1;
|
|
|
|
if ( outdly_cnt > `DLY_TO_OUTP) begin
|
|
transf_cnt <= transf_cnt+1;
|
|
crcDat_en<=1;
|
|
crcDat_rst<=0;
|
|
|
|
end
|
|
else begin
|
|
crcDat_en<=0;
|
|
crcDat_rst<=1;
|
|
oeDat<=1;
|
|
crc_c<=15;
|
|
end
|
|
|
|
if (transf_cnt==1) begin
|
|
|
|
last_din <= FLASHmem[BlockAddr+(write_out_index)][7:4];
|
|
datOut<=0;
|
|
crcDat_in<= FLASHmem[BlockAddr+(write_out_index)][7:4];
|
|
data_send_index<=1;
|
end
|
end
|
|
else if ( (transf_cnt>=2) && (transf_cnt<=`BIT_BLOCK-`CRC_OFF )) begin
|
|
data_send_index=~data_send_index;
|
|
if (!data_send_index) begin
|
|
last_din<=FLASHmem[BlockAddr+(write_out_index)][7:4];
|
|
crcDat_in<= FLASHmem[BlockAddr+(write_out_index)][7:4];
|
|
end
|
|
else begin
|
|
last_din<=FLASHmem[BlockAddr+(write_out_index)][3:0];
|
|
crcDat_in<= FLASHmem[BlockAddr+(write_out_index)][3:0];
|
|
write_out_index<=write_out_index+1;
|
|
end
|
|
|
|
datOut<= last_din;
|
|
|
|
|
|
if ( transf_cnt >=`BIT_BLOCK-`CRC_OFF ) begin
|
|
crcDat_en<=0;
|
|
end
|
|
|
|
end
|
|
else if (transf_cnt>`BIT_BLOCK-`CRC_OFF & crc_c!=0) begin
|
|
crcDat_en<=0;
|
|
crc_c<=crc_c-1;
|
|
datOut[0]<=crcDat_out[0][crc_c-1];
|
|
datOut[1]<=crcDat_out[1][crc_c-1];
|
|
datOut[2]<=crcDat_out[2][crc_c-1];
|
|
datOut[3]<=crcDat_out[3][crc_c-1];
|
|
end
|
|
else if (transf_cnt==`BIT_BLOCK-2) begin
|
|
datOut<=4'b1111;
|
|
end
|
|
else if ((transf_cnt !=0) && (crc_c == 0 ))begin
|
|
oeDat<=0;
|
|
CardStatus[12:9] <= `TRAN;
|
|
end
|
|
|
|
|
|
|
|
end
|
|
|
|
|
|
|
WRITE_FLASH: begin
|
WRITE_FLASH: begin
|
flash_write_cnt<=flash_write_cnt+1;
|
flash_write_cnt<=flash_write_cnt+1;
|
CardStatus[12:9] <= `PRG;
|
CardStatus[12:9] <= `PRG;
|
|
datOut[0]<=0;
|
|
datOut[1]<=1;
|
|
datOut[2]<=1;
|
|
datOut[3]<=1;
|
if (flash_write_cnt == 0)
|
if (flash_write_cnt == 0)
|
datOut<=1;
|
datOut<=1;
|
else if(flash_write_cnt == 1)
|
else if(flash_write_cnt == 1)
|
|
datOut[0]<=1;
|
|
else if(flash_write_cnt == 2)
|
datOut[0]<=0;
|
datOut[0]<=0;
|
|
|
else if ((flash_write_cnt > 1) && (flash_write_cnt < 6)) begin
|
|
|
else if ((flash_write_cnt > 2) && (flash_write_cnt < 7)) begin
|
if (crc_ok)
|
if (crc_ok)
|
datOut[0] <=okcrctoken[5-flash_write_cnt];
|
datOut[0] <=okcrctoken[6-flash_write_cnt];
|
else
|
else
|
datOut[0] <= invalidcrctoken[5-flash_write_cnt];
|
datOut[0] <= invalidcrctoken[6-flash_write_cnt];
|
end
|
end
|
else if ((flash_write_cnt >= 6) && (flash_write_cnt < 263)) begin
|
else if ((flash_write_cnt >= 7) && (flash_write_cnt < 264)) begin
|
datOut[0]<=0;
|
datOut[0]<=0;
|
datOut[1]<=1;
|
|
datOut[2]<=1;
|
|
datOut[3]<=1;
|
|
flash_blockwrite_cnt<=flash_blockwrite_cnt+2;
|
flash_blockwrite_cnt<=flash_blockwrite_cnt+2;
|
FLASHmem[BlockAddr+(flash_blockwrite_cnt)]<=Inbuff[flash_blockwrite_cnt];
|
FLASHmem[BlockAddr+(flash_blockwrite_cnt)]<=Inbuff[flash_blockwrite_cnt];
|
FLASHmem[BlockAddr+(flash_blockwrite_cnt+1)]<=Inbuff[flash_blockwrite_cnt+1];
|
FLASHmem[BlockAddr+(flash_blockwrite_cnt+1)]<=Inbuff[flash_blockwrite_cnt+1];
|
end
|
end
|
else begin
|
else begin
|
