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//////////////////////////////////////////////////////////////////////
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//// ////
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//// File name "wb_bus_mon.v" ////
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//// ////
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//// This file is part of the "PCI bridge" project ////
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//// http://www.opencores.org/cores/pci/ ////
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//// ////
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//// Author(s): ////
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//// - mihad@opencores.org ////
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//// - Miha Dolenc ////
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//// ////
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//// All additional information is avaliable in the README.pdf ////
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//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2002/10/09 13:16:51 tadejm
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// Just back-up; not completed testbench and some testcases are not
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// wotking properly yet.
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//
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// Revision 1.2 2002/09/13 12:29:14 mohor
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// Headers changed.
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//
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// Revision 1.1 2002/09/13 11:57:20 mohor
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// New testbench. Thanks to Tadej M - "The Spammer".
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//
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// Revision 1.1 2002/02/01 13:39:43 mihad
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// Initial testbench import. Still under development
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//
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// Revision 1.1 2001/08/06 18:12:58 mihad
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// Pocasi delamo kompletno zadevo
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//
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//
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`include "timescale.v"
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`include "wb_model_defines.v"
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// WISHBONE bus monitor module - it connects to WISHBONE master signals and
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// monitors for any illegal combinations appearing on the bus.
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module WB_BUS_MON(
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CLK_I,
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RST_I,
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ACK_I,
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ADDR_O,
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CYC_O,
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DAT_I,
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DAT_O,
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ERR_I,
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RTY_I,
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SEL_O,
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STB_O,
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WE_O,
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TAG_I,
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TAG_O,
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CAB_O,
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check_CTI,
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log_file_desc
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) ;
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input CLK_I ;
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input RST_I ;
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input ACK_I ;
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input [(`WB_ADDR_WIDTH-1):0] ADDR_O ;
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input CYC_O ;
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input [(`WB_DATA_WIDTH-1):0] DAT_I ;
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input [(`WB_DATA_WIDTH-1):0] DAT_O ;
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input ERR_I ;
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input RTY_I ;
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input [(`WB_SEL_WIDTH-1):0] SEL_O ;
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input STB_O ;
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input WE_O ;
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input [(`WB_TAG_WIDTH-1):0] TAG_I ;
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input [(`WB_TAG_WIDTH-1):0] TAG_O ;
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input CAB_O ;
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input check_CTI ;
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input [31:0] log_file_desc ;
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always@(posedge CLK_I)
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begin
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if (RST_I !== 1'b0)
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begin
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// when reset is applied, all control signals must be low
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if (CYC_O !== 1'b0)
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begin
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message_out("CYC_O active under reset") ;
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end
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if (STB_O !== 1'b0)
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begin
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message_out("STB_O active under reset") ;
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end
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if (ACK_I !== 1'b0)
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message_out("ACK_I active under reset") ;
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if (ERR_I !== 1'b0)
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begin
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message_out("ERR_I active under reset") ;
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end
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if (RTY_I !== 1'b0)
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begin
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message_out("RTY_I active under reset") ;
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end
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end // reset
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else
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if (CYC_O !== 1'b1)
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begin
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// when cycle indicator is low, all control signals must be low
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if (STB_O !== 1'b0)
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begin
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message_out("STB_O active without CYC_O being active") ;
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end
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if (ACK_I !== 1'b0)
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begin
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message_out("ACK_I active without CYC_O being active") ;
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end
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if (ERR_I !== 1'b0)
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begin
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message_out("ERR_I active without CYC_O being active") ;
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end
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if (RTY_I !== 1'b0)
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begin
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message_out("RTY_I active without CYC_O being active") ;
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end
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end // ~CYC_O
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end
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reg [`WB_DATA_WIDTH-1:0] previous_data_o ;
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reg [`WB_DATA_WIDTH-1:0] previous_data_i ;
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reg [`WB_ADDR_WIDTH-1:0] previous_address ;
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reg [`WB_SEL_WIDTH-1:0] previous_sel ;
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reg [`WB_TAG_WIDTH-1:0] previous_tag ;
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reg previous_stb ;
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reg previous_ack ;
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reg previous_err ;
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reg previous_rty ;
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reg previous_cyc ;
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reg previous_we ;
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always@(posedge CLK_I or posedge RST_I)
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begin
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if (RST_I)
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begin
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previous_stb <= 1'b0 ;
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previous_ack <= 1'b0 ;
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previous_err <= 1'b0 ;
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previous_rty <= 1'b0 ;
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previous_cyc <= 1'b0 ;
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previous_tag <= 'd0 ;
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previous_we <= 1'b0 ;
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previous_data_o <= 0 ;
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previous_data_i <= 0 ;
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previous_address <= 0 ;
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previous_sel <= 0 ;
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end
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else
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begin
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previous_stb <= STB_O ;
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previous_ack <= ACK_I ;
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previous_err <= ERR_I ;
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previous_rty <= RTY_I ;
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previous_cyc <= CYC_O ;
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previous_tag <= TAG_O ;
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previous_we <= WE_O ;
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previous_data_o <= DAT_O ;
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previous_data_i <= DAT_I ;
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previous_address <= ADDR_O ;
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previous_sel <= SEL_O ;
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end
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end
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// cycle monitor
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always@(posedge CLK_I)
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begin:cycle_monitor_blk
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reg master_can_change ;
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reg slave_can_change ;
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if ((CYC_O !== 1'b0) & (RST_I !== 1'b1)) // cycle in progress
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begin
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// check for two control signals active at same edge
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if ( (ACK_I !== 1'b0) & (RTY_I !== 1'b0) )
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begin
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message_out("ACK_I and RTY_I asserted at the same time during cycle") ;
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end
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if ( (ACK_I !== 1'b0) & (ERR_I !== 1'b0) )
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begin
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message_out("ACK_I and ERR_I asserted at the same time during cycle") ;
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end
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if ( (RTY_I !== 1'b0) & (ERR_I !== 1'b0) )
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begin
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message_out("RTY_I and ERR_I asserted at the same time during cycle") ;
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end
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if (previous_cyc === 1'b1)
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begin
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if (previous_stb === 1'b1)
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begin
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if ((previous_ack === 1'b1) | (previous_rty === 1'b1) | (previous_err === 1'b1))
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master_can_change = 1'b1 ;
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else
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master_can_change = 1'b0 ;
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end
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else
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begin
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master_can_change = 1'b1 ;
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end
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if ((previous_ack === 1'b1) | (previous_err === 1'b1) | (previous_rty === 1'b1))
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begin
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if (previous_stb === 1'b1)
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slave_can_change = 1'b1 ;
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else
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slave_can_change = 1'b0 ;
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end
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else
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begin
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slave_can_change = 1'b1 ;
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end
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end
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else
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begin
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master_can_change = 1'b1 ;
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slave_can_change = 1'b1 ;
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end
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end
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else
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begin
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master_can_change = 1'b1 ;
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slave_can_change = 1'b1 ;
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end
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if (master_can_change !== 1'b1)
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begin
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if (CYC_O !== previous_cyc)
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begin
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message_out("Master violated WISHBONE protocol by changing the value of CYC_O signal at inappropriate time!") ;
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end
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if (STB_O !== previous_stb)
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begin
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message_out("Master violated WISHBONE protocol by changing the value of STB_O signal at inappropriate time!") ;
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end
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if (TAG_O !== previous_tag)
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begin
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message_out("Master violated WISHBONE protocol by changing the value of TAG_O signals at inappropriate time!") ;
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end
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if (ADDR_O !== previous_address)
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begin
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message_out("Master violated WISHBONE protocol by changing the value of ADR_O signals at inappropriate time!") ;
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end
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if (SEL_O !== previous_sel)
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begin
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message_out("Master violated WISHBONE protocol by changing the value of SEL_O signals at inappropriate time!") ;
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end
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if (WE_O !== previous_we)
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begin
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message_out("Master violated WISHBONE protocol by changing the value of WE_O signal at inappropriate time!") ;
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end
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if (WE_O !== 1'b0)
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begin
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if (DAT_O !== previous_data_o)
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begin
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message_out("Master violated WISHBONE protocol by changing the value of DAT_O signals at inappropriate time!") ;
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end
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end
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end
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if (slave_can_change !== 1'b1)
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begin
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if (previous_ack !== ACK_I)
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begin
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message_out("Slave violated WISHBONE protocol by changing the value of ACK_O signal at inappropriate time!") ;
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end
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if (previous_rty !== RTY_I)
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begin
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message_out("Slave violated WISHBONE protocol by changing the value of RTY_O signal at inappropriate time!") ;
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end
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if (previous_err !== ERR_I)
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begin
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message_out("Slave violated WISHBONE protocol by changing the value of ERR_O signal at inappropriate time!") ;
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end
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if (previous_data_i !== DAT_I)
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begin
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message_out("Slave violated WISHBONE protocol by changing the value of DAT_O signals at inappropriate time!") ;
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end
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end
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end // cycle monitor
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// CAB_O monitor - CAB_O musn't change during one cycle
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reg [1:0] first_cab_val ;
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always@(posedge CLK_I or RST_I)
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begin
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if ((CYC_O === 0) || RST_I)
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first_cab_val <= 2'b00 ;
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else
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begin
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// cycle in progress - is this first clock edge in a cycle ?
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if (first_cab_val[1] === 1'b0)
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first_cab_val <= {1'b1, CAB_O} ;
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else if ( first_cab_val[0] !== CAB_O )
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begin
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$display("CAB_O value changed during cycle") ;
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$fdisplay(log_file_desc, "CAB_O value changed during cycle") ;
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end
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end
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end // CAB_O monitor
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// CTI_O[2:0] (TAG_O[4:2]) monitor for bursts
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reg [2:0] first_cti_val ;
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always@(posedge CLK_I or posedge RST_I)
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begin
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if (RST_I)
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first_cti_val <= 3'b000 ;
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// logging for burst cycle
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else if ( check_CTI && ((CYC_O === 0) && (first_cti_val == 3'b011) && ~(previous_rty || previous_err)))
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begin
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message_out("Master violated WISHBONE protocol by NOT changing the CTI_O signals to '111' when end of burst!") ;
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$display("CTI_O didn't change to '111' when end of burst") ;
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$fdisplay(log_file_desc, "CTI_O didn't change to '111' when end of burst") ;
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first_cti_val <= 3'b000 ;
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end
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else if (CYC_O === 0)
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first_cti_val <= 3'b000 ;
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else
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begin
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if ((first_cti_val == 3'b000) && (TAG_O[4:2] === 3'b000) && (ACK_I || ERR_I || RTY_I))
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first_cti_val <= 3'b001 ;
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else if ((first_cti_val == 3'b000) && (TAG_O[4:2] === 3'b111) && (ACK_I || ERR_I || RTY_I))
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first_cti_val <= 3'b010 ;
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else if ((first_cti_val == 3'b000) && (TAG_O[4:2] === 3'b010) && (ACK_I || ERR_I || RTY_I))
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first_cti_val <= 3'b011 ;
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else if ((first_cti_val == 3'b011) && (TAG_O[4:2] === 3'b111) && (ACK_I || ERR_I || RTY_I))
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first_cti_val <= 3'b010 ;
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// logging for clasic cycles
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else if (check_CTI && ((first_cti_val == 3'b001) && (TAG_O[4:2] !== 3'b000)))
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begin
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message_out("Master violated WISHBONE protocol by changing the CTI_O signals during CYC_O when clasic cycle!") ;
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$display("CTI_O change during CYC_O when clasic cycle") ;
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$fdisplay(log_file_desc, "CTI_O change during CYC_O when clasic cycle") ;
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end
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// logging for end of burs cycle
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else if (check_CTI && (first_cti_val == 3'b010))
|
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begin
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message_out("Master violated WISHBONE protocol by changing the CTI_O signals to '111' before end of burst!") ;
|
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$display("CTI_O change to '111' before end of burst") ;
|
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$fdisplay(log_file_desc, "CTI_O change to '111' before end of burst") ;
|
|
end
|
|
end
|
|
end
|
|
|
|
// WE_O monitor for consecutive address bursts
|
|
reg [1:0] first_we_val ;
|
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always@(posedge CLK_I or posedge RST_I)
|
|
begin
|
|
if (~CYC_O || ~CAB_O || RST_I)
|
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first_we_val <= 2'b00 ;
|
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else
|
|
if (STB_O)
|
|
begin
|
|
// cycle in progress - is this first clock edge in a cycle ?
|
|
if (first_we_val[1] == 1'b0)
|
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first_we_val <= {1'b1, WE_O} ;
|
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else if ( first_we_val[0] != WE_O )
|
|
begin
|
|
$display("WE_O value changed during CAB cycle") ;
|
|
$fdisplay(log_file_desc, "WE_O value changed during CAB cycle") ;
|
|
end
|
|
end
|
|
end // CAB_O monitor
|
|
|
|
// address monitor for consecutive address bursts
|
|
reg [`WB_ADDR_WIDTH:0] address ;
|
|
always@(posedge CLK_I or posedge RST_I)
|
|
begin
|
|
if (~CYC_O || ~CAB_O || RST_I)
|
|
address <= {(`WB_ADDR_WIDTH + 1){1'b0}} ;
|
|
else
|
|
begin
|
|
if (STB_O && ACK_I)
|
|
begin
|
|
if (address[`WB_ADDR_WIDTH] == 1'b0)
|
|
begin
|
|
address <= (ADDR_O + `WB_SEL_WIDTH) | { 1'b1, {`WB_ADDR_WIDTH{1'b0}} } ;
|
|
end
|
|
else
|
|
begin
|
|
if ( address[(`WB_ADDR_WIDTH-1):0] != ADDR_O)
|
|
begin
|
|
$display("Expected ADR_O = 0x%h, Actual = 0x%h", address[(`WB_ADDR_WIDTH-1):0], ADDR_O) ;
|
|
message_out("Consecutive address burst address incrementing incorrect") ;
|
|
end
|
|
else
|
|
address <= (ADDR_O + `WB_SEL_WIDTH) | { 1'b1, {`WB_ADDR_WIDTH{1'b0}} } ;
|
|
end
|
|
end
|
|
end
|
|
end // address monitor
|
|
|
|
// data monitor
|
|
always@(posedge CLK_I or posedge RST_I)
|
|
begin:data_monitor_blk
|
|
reg last_valid_we ;
|
|
reg [`WB_SEL_WIDTH - 1:0] last_valid_sel ;
|
|
|
|
if ((CYC_O !== 1'b0) & (RST_I !== 1'b1))
|
|
begin
|
|
if (STB_O !== 1'b0)
|
|
begin
|
|
last_valid_we = WE_O ;
|
|
last_valid_sel = SEL_O ;
|
|
|
|
if ( (ADDR_O ^ ADDR_O) !== 0 )
|
|
begin
|
|
message_out("Master provided invalid ADR_O and qualified it with STB_O") ;
|
|
end
|
|
|
|
if ( (SEL_O ^ SEL_O) !== 0 )
|
|
begin
|
|
message_out("Master provided invalid SEL_O and qualified it with STB_O") ;
|
|
end
|
|
|
|
if ( WE_O )
|
|
begin
|
|
if (
|
|
( SEL_O[0] & ((DAT_O[ 7:0 ] ^ DAT_O[ 7:0 ]) !== 0) ) |
|
|
( SEL_O[1] & ((DAT_O[15:8 ] ^ DAT_O[15:8 ]) !== 0) ) |
|
|
( SEL_O[2] & ((DAT_O[23:16] ^ DAT_O[23:16]) !== 0) ) |
|
|
( SEL_O[3] & ((DAT_O[31:24] ^ DAT_O[31:24]) !== 0) )
|
|
)
|
|
begin
|
|
message_out("Master provided invalid data during write and qualified it with STB_O") ;
|
|
$display("Byte select value: SEL_O = %b, Data bus value: DAT_O = %h ", SEL_O, DAT_O) ;
|
|
$fdisplay(log_file_desc, "Byte select value: SEL_O = %b, Data bus value: DAT_O = %h ", SEL_O, DAT_O) ;
|
|
end
|
|
end
|
|
|
|
if ((TAG_O ^ TAG_O) !== 0)
|
|
begin
|
|
message_out("Master provided invalid TAG_O and qualified it with STB_O!") ;
|
|
end
|
|
end
|
|
|
|
if ((last_valid_we !== 1'b1) & (ACK_I !== 1'b0))
|
|
begin
|
|
if (
|
|
( SEL_O[0] & ((DAT_I[ 7:0 ] ^ DAT_I[ 7:0 ]) !== 0) ) |
|
|
( SEL_O[1] & ((DAT_I[15:8 ] ^ DAT_I[15:8 ]) !== 0) ) |
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( SEL_O[2] & ((DAT_I[23:16] ^ DAT_I[23:16]) !== 0) ) |
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( SEL_O[3] & ((DAT_I[31:24] ^ DAT_I[31:24]) !== 0) )
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)
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begin
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message_out("Slave provided invalid data during read and qualified it with ACK_I") ;
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$display("Byte select value: SEL_O = %b, Data bus value: DAT_I = %h ", last_valid_sel, DAT_I) ;
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$fdisplay(log_file_desc, "Byte select value: SEL_O = %b, Data bus value: DAT_I = %h ", last_valid_sel, DAT_I) ;
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end
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end
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end
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else
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begin
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last_valid_sel = {`WB_SEL_WIDTH{1'bx}} ;
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last_valid_we = 1'bx ;
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end
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end
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task message_out ;
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input [7999:0] message_i ;
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begin
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$display("Time: %t", $time) ;
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$display("%m, %0s", message_i) ;
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$fdisplay(log_file_desc, "Time: %t", $time) ;
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$fdisplay(log_file_desc, "%m, %0s", message_i) ;
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end
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endtask // display message
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endmodule // BUS_MON
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No newline at end of file
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No newline at end of file
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