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//////////////////////////////////////////////////////////////////////
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//// ////
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//// File name "wb_master32.v" ////
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//// ////
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//// This file is part of the Ethernet IP core project ////
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//// http://www.opencores.org/projects/ethmac/ ////
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//// ////
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//// Author(s): ////
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//// - Miha Dolenc (mihad@opencores.org) ////
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//// ////
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//// All additional information is available in the README.pdf ////
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//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2002 Authors ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2002/09/13 11:57:20 mohor
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// New testbench. Thanks to Tadej M - "The Spammer".
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//
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// Revision 1.1 2002/07/29 11:25:20 mihad
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// Adding test bench for memory interface
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//
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// Revision 1.1 2002/02/01 13:39:43 mihad
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// Initial testbench import. Still under development
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//
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//
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`include "wb_model_defines.v"
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`include "timescale.v"
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module WB_MASTER32
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(
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CLK_I,
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RST_I,
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TAG_I,
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TAG_O,
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ACK_I,
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ADR_O,
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CYC_O,
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DAT_I,
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DAT_O,
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ERR_I,
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RTY_I,
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SEL_O,
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STB_O,
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WE_O,
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CAB_O
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);
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input CLK_I;
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input RST_I;
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input `WB_TAG_TYPE TAG_I;
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output `WB_TAG_TYPE TAG_O;
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input ACK_I;
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output `WB_ADDR_TYPE ADR_O;
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output CYC_O;
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input `WB_DATA_TYPE DAT_I;
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output `WB_DATA_TYPE DAT_O;
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input ERR_I;
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input RTY_I;
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output `WB_SEL_TYPE SEL_O;
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output STB_O;
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output WE_O;
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output CAB_O ;
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// period length
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real Tp ;
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reg `WB_ADDR_TYPE ADR_O;
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reg `WB_SEL_TYPE SEL_O;
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reg `WB_TAG_TYPE TAG_O;
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reg CYC_O;
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reg WE_O;
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reg `WB_DATA_TYPE DAT_O;
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reg CAB_O ;
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reg STB_O ;
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// variable used for indication on whether cycle was already started
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reg in_use ;
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// because of non-blocking assignments CYC_O is not sufficient indicator for cycle starting - this var is used in its place
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reg cycle_in_progress ;
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// same goes for CAB_O signal
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reg cab ;
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reg we ;
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task start_cycle ;
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input is_cab ;
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input write ;
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output ok ; // ok indicates to the caller that cycle was started succesfully - if not, caller must take appropriate action
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begin:main
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ok = 1 ;
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// just check if valid value is provided for CAB_O signal (no x's or z's allowed)
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if ( (is_cab !== 1'b0) && (is_cab !== 1'b1) )
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begin
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$display("*E, invalid CAB value for cycle! Requested CAB_O value = %b, Time %t ", is_cab, $time) ;
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ok = 0 ;
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disable main ;
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end
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if ( (cycle_in_progress === 1) || (CYC_O === 1))
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begin
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// cycle was previously started - allow cycle to continue if CAB and WE values match
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$display("*W, cycle already in progress when start_cycle routine was called! Time %t ", $time) ;
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if ((CAB_O !== is_cab) || (WE_O !== write) )
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begin
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ok = 0 ;
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if ( is_cab === 1 )
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$display("*E, cab cycle start attempted when non-cab cycle was in progress! Time %t", $time) ;
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else
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$display("*E, non-cab cycle start attempted when cab cycle was in progress! Time %t", $time) ;
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if ( we === 1 )
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$display("*E, write cycle start attempted when read cycle was in progress! Time %t", $time) ;
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else
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$display("*E, read cycle start attempted when write cycle was in progress! Time %t", $time) ;
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disable main ;
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end
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end
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CYC_O <= #(Tp - `Tsetup) 1'b1 ;
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CAB_O <= #(Tp - `Tsetup) is_cab ;
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WE_O <= #(Tp - `Tsetup) write ;
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// this non-blocking assignments are made to internal variables, so read and write tasks can be called immediately after cycle start task
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cycle_in_progress = 1'b1 ;
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cab = is_cab ;
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we = write ;
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end
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endtask //start_cycle
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task end_cycle ;
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begin
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if ( CYC_O !== 1'b1 )
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$display("*W, end_cycle routine called when CYC_O value was %b! Time %t ", CYC_O, $time) ;
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CYC_O <= #`Thold 1'b0 ;
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CAB_O <= #`Thold 1'b0 ;
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cycle_in_progress = 1'b0 ;
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end
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endtask //end_cycle
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task modify_cycle ;
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begin
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if ( CYC_O !== 1'b1 )
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$display("*W, modify_cycle routine called when CYC_O value was %b! Time %t ", CYC_O, $time) ;
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we = ~we ;
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WE_O <= #(Tp - `Tsetup) we ;
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end
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endtask //modify_cycle
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task wbm_read ;
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input `READ_STIM_TYPE input_data ;
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inout `READ_RETURN_TYPE output_data ;
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reg `WB_ADDR_TYPE address ;
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reg `WB_DATA_TYPE data ;
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reg `WB_SEL_TYPE sel ;
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reg `WB_TAG_TYPE tag ;
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integer num_of_cyc ;
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begin:main
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output_data`TB_ERROR_BIT = 1'b0 ;
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// check if task was called before previous call to read or write finished
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if ( in_use === 1 )
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begin
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$display("*E, wbm_read routine re-entered or called concurently with write routine! Time %t ", $time) ;
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output_data`TB_ERROR_BIT = 1'b1 ;
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disable main ;
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end
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if ( cycle_in_progress !== 1 )
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begin
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$display("*E, wbm_read routine called without start_cycle routine being called first! Time %t ", $time) ;
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output_data`TB_ERROR_BIT = 1'b1 ;
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disable main ;
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end
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if ( we !== 0 )
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begin
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$display("*E, wbm_read routine called after write cycle was started! Time %t ", $time) ;
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output_data`TB_ERROR_BIT = 1'b1 ;
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disable main ;
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end
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// this branch contains timing controls - claim the use of WISHBONE
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in_use = 1 ;
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num_of_cyc = `WAIT_FOR_RESPONSE ;
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// assign data outputs
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ADR_O <= #(Tp - `Tsetup) input_data`READ_ADDRESS ;
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SEL_O <= #(Tp - `Tsetup) input_data`READ_SEL ;
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TAG_O <= #(Tp - `Tsetup) input_data`READ_TAG_STIM ;
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// assign control output
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STB_O <= #(Tp - `Tsetup) 1'b1 ;
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output_data`CYC_ACK = 0 ;
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output_data`CYC_RTY = 0 ;
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output_data`CYC_ERR = 0 ;
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@(posedge CLK_I) ;
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output_data`CYC_ACK = ACK_I ;
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output_data`CYC_RTY = RTY_I ;
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output_data`CYC_ERR = ERR_I ;
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while ( (num_of_cyc > 0) && (output_data`CYC_RESPONSE === 0) )
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begin
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@(posedge CLK_I) ;
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output_data`CYC_ACK = ACK_I ;
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output_data`CYC_RTY = RTY_I ;
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output_data`CYC_ERR = ERR_I ;
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num_of_cyc = num_of_cyc - 1 ;
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end
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output_data`READ_DATA = DAT_I ;
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output_data`READ_TAG_RET = TAG_I ;
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if ( output_data`CYC_RESPONSE === 0 )
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begin
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$display("*W, Terminating read cycle because no response was received in %d cycles! Time %t ", `WAIT_FOR_RESPONSE, $time) ;
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end
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if ( output_data`CYC_ACK === 1 && output_data`CYC_RTY === 0 && output_data`CYC_ERR === 0 )
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output_data`CYC_ACTUAL_TRANSFER = output_data`CYC_ACTUAL_TRANSFER + 1 ;
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STB_O <= #`Thold 1'b0 ;
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ADR_O <= #`Thold {`WB_ADDR_WIDTH{1'bx}} ;
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SEL_O <= #`Thold {`WB_SEL_WIDTH{1'bx}} ;
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TAG_O <= #`Thold {`WB_TAG_WIDTH{1'bx}} ;
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in_use = 0 ;
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end
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endtask // wbm_read
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task wbm_write ;
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input `WRITE_STIM_TYPE input_data ;
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inout `WRITE_RETURN_TYPE output_data ;
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reg `WB_ADDR_TYPE address ;
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reg `WB_DATA_TYPE data ;
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reg `WB_SEL_TYPE sel ;
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reg `WB_TAG_TYPE tag ;
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integer num_of_cyc ;
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begin:main
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output_data`TB_ERROR_BIT = 1'b0 ;
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// check if task was called before previous call to read or write finished
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if ( in_use === 1 )
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begin
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$display("*E, wbm_write routine re-entered or called concurently with read routine! Time %t ", $time) ;
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output_data`TB_ERROR_BIT = 1'b1 ;
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disable main ;
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end
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if ( cycle_in_progress !== 1 )
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begin
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$display("*E, wbm_write routine called without start_cycle routine being called first! Time %t ", $time) ;
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output_data`TB_ERROR_BIT = 1'b1 ;
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disable main ;
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end
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if ( we !== 1 )
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begin
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$display("*E, wbm_write routine after read cycle was started! Time %t ", $time) ;
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output_data`TB_ERROR_BIT = 1'b1 ;
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disable main ;
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end
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// this branch contains timing controls - claim the use of WISHBONE
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in_use = 1 ;
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num_of_cyc = `WAIT_FOR_RESPONSE ;
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ADR_O <= #(Tp - `Tsetup) input_data`WRITE_ADDRESS ;
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DAT_O <= #(Tp - `Tsetup) input_data`WRITE_DATA ;
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SEL_O <= #(Tp - `Tsetup) input_data`WRITE_SEL ;
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TAG_O <= #(Tp - `Tsetup) input_data`WRITE_TAG_STIM ;
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STB_O <= #(Tp - `Tsetup) 1'b1 ;
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output_data`CYC_ACK = 0 ;
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output_data`CYC_RTY = 0 ;
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output_data`CYC_ERR = 0 ;
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@(posedge CLK_I) ;
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output_data`CYC_ACK = ACK_I ;
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output_data`CYC_RTY = RTY_I ;
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output_data`CYC_ERR = ERR_I ;
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while ( (num_of_cyc > 0) && (output_data`CYC_RESPONSE === 0) )
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begin
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@(posedge CLK_I) ;
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output_data`CYC_ACK = ACK_I ;
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output_data`CYC_RTY = RTY_I ;
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output_data`CYC_ERR = ERR_I ;
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num_of_cyc = num_of_cyc - 1 ;
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end
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output_data`WRITE_TAG_RET = TAG_I ;
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if ( output_data`CYC_RESPONSE === 0 )
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begin
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$display("*W, Terminating write cycle because no response was received in %d cycles! Time %t ", `WAIT_FOR_RESPONSE, $time) ;
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end
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if ( output_data`CYC_ACK === 1 && output_data`CYC_RTY === 0 && output_data`CYC_ERR === 0 )
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output_data`CYC_ACTUAL_TRANSFER = output_data`CYC_ACTUAL_TRANSFER + 1 ;
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ADR_O <= #`Thold {`WB_ADDR_WIDTH{1'bx}} ;
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DAT_O <= #`Thold {`WB_DATA_WIDTH{1'bx}} ;
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SEL_O <= #`Thold {`WB_SEL_WIDTH{1'bx}} ;
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TAG_O <= #`Thold {`WB_TAG_WIDTH{1'bx}} ;
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STB_O <= #`Thold 1'b0 ;
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in_use = 0 ;
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end
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endtask //wbm_write
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initial
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begin
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Tp = 1 / `WB_FREQ ;
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in_use = 0 ;
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cycle_in_progress = 0 ;
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cab = 0 ;
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ADR_O <= {`WB_ADDR_WIDTH{1'bx}} ;
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DAT_O <= {`WB_DATA_WIDTH{1'bx}} ;
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SEL_O <= {`WB_SEL_WIDTH{1'bx}} ;
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TAG_O <= {`WB_TAG_WIDTH{1'bx}} ;
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CYC_O <= 1'b0 ;
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STB_O <= 1'b0 ;
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CAB_O <= 1'b0 ;
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WE_O <= 1'b0 ;
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if ( `Tsetup > Tp || `Thold >= Tp )
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begin
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$display("Either Tsetup or Thold values for WISHBONE BFMs are too large!") ;
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$stop ;
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end
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end
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endmodule
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