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//////////////////////////////////////////////////////////////////////
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//// ////
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//// File name "wb_master_behavioral.v" ////
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//// ////
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//// This file is part of the Ethernet IP core project ////
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//// http://www.opencores.org/projects/ethmac/ ////
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//// ////
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//// Author(s): ////
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//// - Miha Dolenc (mihad@opencores.org) ////
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//// ////
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//// All additional information is available in the Readme.txt ////
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//// file. ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2002 Authors ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2002/09/13 11:57:20 mohor
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// New testbench. Thanks to Tadej M - "The Spammer".
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//
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// Revision 1.1 2002/07/29 11:25:20 mihad
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// Adding test bench for memory interface
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//
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// Revision 1.1 2002/02/01 13:39:43 mihad
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// Initial testbench import. Still under development
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//
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`include "wb_model_defines.v"
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`include "timescale.v"
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module WB_MASTER_BEHAVIORAL
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(
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CLK_I,
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RST_I,
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TAG_I,
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TAG_O,
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ACK_I,
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ADR_O,
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CYC_O,
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DAT_I,
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DAT_O,
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ERR_I,
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RTY_I,
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SEL_O,
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STB_O,
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WE_O,
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CAB_O
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);
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input CLK_I;
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input RST_I;
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input `WB_TAG_TYPE TAG_I;
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output `WB_TAG_TYPE TAG_O;
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input ACK_I;
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output `WB_ADDR_TYPE ADR_O;
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output CYC_O;
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input `WB_DATA_TYPE DAT_I;
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output `WB_DATA_TYPE DAT_O;
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input ERR_I;
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input RTY_I;
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output `WB_SEL_TYPE SEL_O;
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output STB_O;
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output WE_O;
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output CAB_O;
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// instantiate low level master module
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WB_MASTER32 wbm_low_level
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(
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.CLK_I(CLK_I),
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.RST_I(RST_I),
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.TAG_I(TAG_I),
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.TAG_O(TAG_O),
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.ACK_I(ACK_I),
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.ADR_O(ADR_O),
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.CYC_O(CYC_O),
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.DAT_I(DAT_I),
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.DAT_O(DAT_O),
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.ERR_I(ERR_I),
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.RTY_I(RTY_I),
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.SEL_O(SEL_O),
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.STB_O(STB_O),
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.WE_O(WE_O),
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.CAB_O(CAB_O)
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) ;
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// block read and write buffers definition
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// single write buffer
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reg `WRITE_STIM_TYPE blk_write_data [0:(`MAX_BLK_SIZE - 1)] ;
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// read stimulus buffer - addresses, tags, selects etc.
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reg `READ_STIM_TYPE blk_read_data_in [0:(`MAX_BLK_SIZE - 1)] ;
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// read return buffer - data and tags received while performing block reads
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reg `READ_RETURN_TYPE blk_read_data_out [0:(`MAX_BLK_SIZE - 1)] ;
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// single write task
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task wb_single_write ;
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input `WRITE_STIM_TYPE write_data ;
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input `WB_TRANSFER_FLAGS write_flags ;
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inout `WRITE_RETURN_TYPE return ;
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reg in_use ;
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reg cab ;
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reg ok ;
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integer cyc_count ;
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integer rty_count ;
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reg retry ;
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begin:main
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return`TB_ERROR_BIT = 1'b0 ;
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cab = 0 ;
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return`CYC_ACTUAL_TRANSFER = 0 ;
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rty_count = 0 ;
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// check if task was called before previous call finished
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if ( in_use === 1 )
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begin
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$display("*E, wb_single_write routine re-entered! Time %t ", $time) ;
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return`TB_ERROR_BIT = 1'b1 ;
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disable main ;
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end
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in_use = 1 ;
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retry = 1 ;
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while (retry === 1)
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begin
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// synchronize operation to clock
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@(posedge CLK_I) ;
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wbm_low_level.start_cycle(cab, 1'b1, ok) ;
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if ( ok !== 1 )
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begin
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$display("*E, Failed to initialize cycle! Routine wb_single_write, Time %t ", $time) ;
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return`TB_ERROR_BIT = 1'b1 ;
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disable main ;
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end
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// first insert initial wait states
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cyc_count = write_flags`INIT_WAITS ;
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while ( cyc_count > 0 )
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begin
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@(posedge CLK_I) ;
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cyc_count = cyc_count - 1 ;
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end
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wbm_low_level.wbm_write(write_data, return) ;
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if ( return`CYC_ERR === 0 && return`CYC_ACK === 0 && return`CYC_RTY === 1 && write_flags`WB_TRANSFER_AUTO_RTY === 1 && return`TB_ERROR_BIT === 0)
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begin
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if ( rty_count === `WB_TB_MAX_RTY )
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begin
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$display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_single_write, Time %t ", $time) ;
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retry = 0 ;
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end
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else
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begin
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retry = 1 ;
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rty_count = rty_count + 1 ;
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end
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end
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else
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retry = 0 ;
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// if test bench error bit is set, there is no meaning in introducing subsequent wait states
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if ( return`TB_ERROR_BIT !== 0 )
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begin
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@(posedge CLK_I) ;
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wbm_low_level.end_cycle ;
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disable main ;
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end
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cyc_count = write_flags`SUBSEQ_WAITS ;
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while ( cyc_count > 0 )
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begin
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@(posedge CLK_I) ;
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cyc_count = cyc_count - 1 ;
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end
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wbm_low_level.end_cycle ;
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end
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in_use = 0 ;
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end //main
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endtask // wb_single_write
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task wb_single_read ;
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input `READ_STIM_TYPE read_data ;
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input `WB_TRANSFER_FLAGS read_flags ;
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inout `READ_RETURN_TYPE return ;
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reg in_use ;
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reg cab ;
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reg ok ;
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integer cyc_count ;
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integer rty_count ;
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reg retry ;
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begin:main
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return`TB_ERROR_BIT = 1'b0 ;
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cab = 0 ;
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rty_count = 0 ;
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return`CYC_ACTUAL_TRANSFER = 0 ;
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// check if task was called before previous call finished
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if ( in_use === 1 )
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begin
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$display("*E, wb_single_read routine re-entered! Time %t ", $time) ;
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return`TB_ERROR_BIT = 1'b1 ;
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disable main ;
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end
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in_use = 1 ;
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retry = 1 ;
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while (retry === 1)
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begin
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// synchronize operation to clock
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@(posedge CLK_I) ;
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wbm_low_level.start_cycle(cab, 1'b0, ok) ;
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if ( ok !== 1 )
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begin
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$display("*E, Failed to initialize cycle! Routine wb_single_read, Time %t ", $time) ;
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return`TB_ERROR_BIT = 1'b1 ;
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disable main ;
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end
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// first insert initial wait states
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cyc_count = read_flags`INIT_WAITS ;
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while ( cyc_count > 0 )
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begin
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@(posedge CLK_I) ;
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cyc_count = cyc_count - 1 ;
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end
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wbm_low_level.wbm_read(read_data, return) ;
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if ( return`CYC_ERR === 0 && return`CYC_ACK === 0 && return`CYC_RTY === 1 && read_flags`WB_TRANSFER_AUTO_RTY === 1 && return`TB_ERROR_BIT === 0)
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begin
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if ( rty_count === `WB_TB_MAX_RTY )
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begin
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$display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_single_read, Time %t ", $time) ;
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retry = 0 ;
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end
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else
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begin
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retry = 1 ;
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rty_count = rty_count + 1 ;
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end
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end
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else
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begin
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retry = 0 ;
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end
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// if test bench error bit is set, there is no meaning in introducing subsequent wait states
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if ( return`TB_ERROR_BIT !== 0 )
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begin
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@(posedge CLK_I) ;
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wbm_low_level.end_cycle ;
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disable main ;
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end
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cyc_count = read_flags`SUBSEQ_WAITS ;
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while ( cyc_count > 0 )
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begin
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@(posedge CLK_I) ;
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cyc_count = cyc_count - 1 ;
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end
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wbm_low_level.end_cycle ;
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end
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in_use = 0 ;
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end //main
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endtask // wb_single_read
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task wb_RMW_read ;
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input `READ_STIM_TYPE read_data ;
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input `WB_TRANSFER_FLAGS read_flags ;
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inout `READ_RETURN_TYPE return ;
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reg in_use ;
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reg cab ;
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reg ok ;
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integer cyc_count ;
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integer rty_count ;
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reg retry ;
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begin:main
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return`TB_ERROR_BIT = 1'b0 ;
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cab = 0 ;
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rty_count = 0 ;
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return`CYC_ACTUAL_TRANSFER = 0 ;
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// check if task was called before previous call finished
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if ( in_use === 1 )
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begin
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$display("*E, wb_RMW_read routine re-entered! Time %t ", $time) ;
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return`TB_ERROR_BIT = 1'b1 ;
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disable main ;
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end
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in_use = 1 ;
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retry = 1 ;
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while (retry === 1)
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begin
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// synchronize operation to clock
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@(posedge CLK_I) ;
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|
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wbm_low_level.start_cycle(cab, 1'b0, ok) ;
|
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if ( ok !== 1 )
|
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begin
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$display("*E, Failed to initialize cycle! Routine wb_RMW_read, Time %t ", $time) ;
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return`TB_ERROR_BIT = 1'b1 ;
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disable main ;
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end
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|
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// first insert initial wait states
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cyc_count = read_flags`INIT_WAITS ;
|
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while ( cyc_count > 0 )
|
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begin
|
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@(posedge CLK_I) ;
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cyc_count = cyc_count - 1 ;
|
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end
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wbm_low_level.wbm_read(read_data, return) ;
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|
|
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if ( return`CYC_ERR === 0 && return`CYC_ACK === 0 && return`CYC_RTY === 1 && read_flags`WB_TRANSFER_AUTO_RTY === 1 && return`TB_ERROR_BIT === 0)
|
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begin
|
|
if ( rty_count === `WB_TB_MAX_RTY )
|
|
begin
|
|
$display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_RMW_read, Time %t ", $time) ;
|
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retry = 0 ;
|
|
end
|
|
else
|
|
begin
|
|
retry = 1 ;
|
|
rty_count = rty_count + 1 ;
|
|
end
|
|
end
|
|
else
|
|
begin
|
|
retry = 0 ;
|
|
end
|
|
|
|
// if test bench error bit is set, there is no meaning in introducing subsequent wait states
|
|
if ( return`TB_ERROR_BIT !== 0 )
|
|
begin
|
|
@(posedge CLK_I) ;
|
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wbm_low_level.end_cycle ;
|
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disable main ;
|
|
end
|
|
|
|
cyc_count = read_flags`SUBSEQ_WAITS ;
|
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while ( cyc_count > 0 )
|
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begin
|
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@(posedge CLK_I) ;
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cyc_count = cyc_count - 1 ;
|
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end
|
|
|
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if (retry === 1)
|
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wbm_low_level.end_cycle ;
|
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else
|
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wbm_low_level.modify_cycle ;
|
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end
|
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in_use = 0 ;
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|
|
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end //main
|
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endtask // wb_RMW_read
|
|
|
|
task wb_RMW_write ;
|
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input `WRITE_STIM_TYPE write_data ;
|
|
input `WB_TRANSFER_FLAGS write_flags ;
|
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inout `WRITE_RETURN_TYPE return ;
|
|
reg in_use ;
|
|
reg cab ;
|
|
reg ok ;
|
|
integer cyc_count ;
|
|
integer rty_count ;
|
|
reg retry ;
|
|
begin:main
|
|
|
|
return`TB_ERROR_BIT = 1'b0 ;
|
|
cab = 0 ;
|
|
return`CYC_ACTUAL_TRANSFER = 0 ;
|
|
rty_count = 0 ;
|
|
|
|
// check if task was called before previous call finished
|
|
if ( in_use === 1 )
|
|
begin
|
|
$display("*E, wb_RMW_write routine re-entered! Time %t ", $time) ;
|
|
return`TB_ERROR_BIT = 1'b1 ;
|
|
disable main ;
|
|
end
|
|
|
|
in_use = 1 ;
|
|
|
|
retry = 1 ;
|
|
|
|
while (retry === 1)
|
|
begin
|
|
// synchronize operation to clock
|
|
//@(posedge CLK_I) ;
|
|
ok = 1 ;
|
|
if (rty_count !== 0)
|
|
wbm_low_level.start_cycle(cab, 1'b1, ok) ;
|
|
|
|
if ( ok !== 1 )
|
|
begin
|
|
$display("*E, Failed to initialize cycle! Routine wb_single_write, Time %t ", $time) ;
|
|
return`TB_ERROR_BIT = 1'b1 ;
|
|
disable main ;
|
|
end
|
|
|
|
// first insert initial wait states
|
|
cyc_count = write_flags`INIT_WAITS ;
|
|
while ( cyc_count > 0 )
|
|
begin
|
|
@(posedge CLK_I) ;
|
|
cyc_count = cyc_count - 1 ;
|
|
end
|
|
|
|
wbm_low_level.wbm_write(write_data, return) ;
|
|
|
|
if ( return`CYC_ERR === 0 && return`CYC_ACK === 0 && return`CYC_RTY === 1 && write_flags`WB_TRANSFER_AUTO_RTY === 1 && return`TB_ERROR_BIT === 0)
|
|
begin
|
|
if ( rty_count === `WB_TB_MAX_RTY )
|
|
begin
|
|
$display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_single_write, Time %t ", $time) ;
|
|
retry = 0 ;
|
|
end
|
|
else
|
|
begin
|
|
retry = 1 ;
|
|
rty_count = rty_count + 1 ;
|
|
end
|
|
end
|
|
else
|
|
retry = 0 ;
|
|
|
|
// if test bench error bit is set, there is no meaning in introducing subsequent wait states
|
|
if ( return`TB_ERROR_BIT !== 0 )
|
|
begin
|
|
@(posedge CLK_I) ;
|
|
wbm_low_level.end_cycle ;
|
|
disable main ;
|
|
end
|
|
|
|
cyc_count = write_flags`SUBSEQ_WAITS ;
|
|
while ( cyc_count > 0 )
|
|
begin
|
|
@(posedge CLK_I) ;
|
|
cyc_count = cyc_count - 1 ;
|
|
end
|
|
|
|
wbm_low_level.end_cycle ;
|
|
end
|
|
|
|
in_use = 0 ;
|
|
|
|
end //main
|
|
endtask // wb_RMW_write
|
|
|
|
task wb_block_write ;
|
|
input `WB_TRANSFER_FLAGS write_flags ;
|
|
inout `WRITE_RETURN_TYPE return ;
|
|
|
|
reg in_use ;
|
|
reg `WRITE_STIM_TYPE current_write ;
|
|
reg cab ;
|
|
reg ok ;
|
|
integer cyc_count ;
|
|
integer rty_count ;
|
|
reg end_blk ;
|
|
begin:main
|
|
|
|
return`CYC_ACTUAL_TRANSFER = 0 ;
|
|
rty_count = 0 ;
|
|
|
|
// check if task was called before previous call finished
|
|
if ( in_use === 1 )
|
|
begin
|
|
$display("*E, wb_block_write routine re-entered! Time %t ", $time) ;
|
|
return`TB_ERROR_BIT = 1'b1 ;
|
|
disable main ;
|
|
end
|
|
|
|
if (write_flags`WB_TRANSFER_SIZE > `MAX_BLK_SIZE)
|
|
begin
|
|
$display("*E, number of transfers passed to wb_block_write routine exceeds defined maximum transaction length! Time %t", $time) ;
|
|
return`TB_ERROR_BIT = 1'b1 ;
|
|
disable main ;
|
|
end
|
|
|
|
in_use = 1 ;
|
|
@(posedge CLK_I) ;
|
|
cab = write_flags`WB_TRANSFER_CAB ;
|
|
wbm_low_level.start_cycle(cab, 1'b1, ok) ;
|
|
if ( ok !== 1 )
|
|
begin
|
|
$display("*E, Failed to initialize cycle! Routine wb_block_write, Time %t ", $time) ;
|
|
return`TB_ERROR_BIT = 1'b1 ;
|
|
disable main ;
|
|
end
|
|
|
|
// insert initial wait states
|
|
cyc_count = write_flags`INIT_WAITS ;
|
|
while ( cyc_count > 0 )
|
|
begin
|
|
@(posedge CLK_I) ;
|
|
cyc_count = cyc_count - 1 ;
|
|
end
|
|
|
|
end_blk = 0 ;
|
|
while (end_blk === 0)
|
|
begin
|
|
// collect data for current data beat
|
|
current_write = blk_write_data[return`CYC_ACTUAL_TRANSFER] ;
|
|
wbm_low_level.wbm_write(current_write, return) ;
|
|
|
|
// check result of write operation
|
|
// check for severe test error
|
|
if (return`TB_ERROR_BIT !== 0)
|
|
begin
|
|
@(posedge CLK_I) ;
|
|
wbm_low_level.end_cycle ;
|
|
disable main ;
|
|
end
|
|
|
|
// slave returned error or error signal had invalid value
|
|
if (return`CYC_ERR !== 0)
|
|
end_blk = 1 ;
|
|
|
|
if (
|
|
(return`CYC_RTY !== 0) && (return`CYC_RTY !== 1) ||
|
|
(return`CYC_ACK !== 0) && (return`CYC_ACK !== 1) ||
|
|
(return`CYC_ERR !== 0) && (return`CYC_ERR !== 1)
|
|
)
|
|
begin
|
|
end_blk = 1 ;
|
|
$display("*E, at least one slave response signal was invalid when cycle finished! Routine wb_block_write, Time %t ", $time) ;
|
|
$display("ACK = %b \t RTY_O = %b \t ERR_O = %b \t", return`CYC_ACK, return`CYC_RTY, return`CYC_ERR) ;
|
|
end
|
|
|
|
if ((return`CYC_RTY === 1) && (write_flags`WB_TRANSFER_AUTO_RTY !== 1))
|
|
end_blk = 1 ;
|
|
|
|
if ((return`CYC_RTY === 1) && (write_flags`WB_TRANSFER_AUTO_RTY === 1))
|
|
begin
|
|
if ( rty_count === `WB_TB_MAX_RTY )
|
|
begin
|
|
$display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_block_write, Time %t ", $time) ;
|
|
end_blk = 1 ;
|
|
end
|
|
else
|
|
begin
|
|
rty_count = rty_count + 1 ;
|
|
end
|
|
end
|
|
else
|
|
rty_count = 0 ;
|
|
|
|
// check if slave responded at all
|
|
if (return`CYC_RESPONSE === 0)
|
|
end_blk = 1 ;
|
|
|
|
// check if all intended data was transfered
|
|
if (return`CYC_ACTUAL_TRANSFER === write_flags`WB_TRANSFER_SIZE)
|
|
end_blk = 1 ;
|
|
|
|
// insert subsequent wait cycles, if transfer is supposed to continue
|
|
if ( end_blk === 0 )
|
|
begin
|
|
cyc_count = write_flags`SUBSEQ_WAITS ;
|
|
while ( cyc_count > 0 )
|
|
begin
|
|
@(posedge CLK_I) ;
|
|
cyc_count = cyc_count - 1 ;
|
|
end
|
|
end
|
|
|
|
if ( (end_blk === 0) && (return`CYC_RTY === 1) )
|
|
begin
|
|
wbm_low_level.end_cycle ;
|
|
@(posedge CLK_I) ;
|
|
wbm_low_level.start_cycle(cab, 1'b1, ok) ;
|
|
if ( ok !== 1 )
|
|
begin
|
|
$display("*E, Failed to initialize cycle! Routine wb_block_write, Time %t ", $time) ;
|
|
return`TB_ERROR_BIT = 1'b1 ;
|
|
end_blk = 1 ;
|
|
end
|
|
end
|
|
end //while
|
|
|
|
wbm_low_level.end_cycle ;
|
|
in_use = 0 ;
|
|
end //main
|
|
endtask //wb_block_write
|
|
|
|
task wb_block_read ;
|
|
input `WB_TRANSFER_FLAGS read_flags ;
|
|
inout `READ_RETURN_TYPE return ;
|
|
|
|
reg in_use ;
|
|
reg `READ_STIM_TYPE current_read ;
|
|
reg cab ;
|
|
reg ok ;
|
|
integer cyc_count ;
|
|
integer rty_count ;
|
|
reg end_blk ;
|
|
integer transfered ;
|
|
begin:main
|
|
|
|
return`CYC_ACTUAL_TRANSFER = 0 ;
|
|
transfered = 0 ;
|
|
rty_count = 0 ;
|
|
|
|
// check if task was called before previous call finished
|
|
if ( in_use === 1 )
|
|
begin
|
|
$display("*E, wb_block_read routine re-entered! Time %t ", $time) ;
|
|
return`TB_ERROR_BIT = 1'b1 ;
|
|
disable main ;
|
|
end
|
|
|
|
if (read_flags`WB_TRANSFER_SIZE > `MAX_BLK_SIZE)
|
|
begin
|
|
$display("*E, number of transfers passed to wb_block_read routine exceeds defined maximum transaction length! Time %t", $time) ;
|
|
return`TB_ERROR_BIT = 1'b1 ;
|
|
disable main ;
|
|
end
|
|
|
|
in_use = 1 ;
|
|
@(posedge CLK_I) ;
|
|
cab = read_flags`WB_TRANSFER_CAB ;
|
|
|
|
wbm_low_level.start_cycle(cab, 1'b0, ok) ;
|
|
|
|
if ( ok !== 1 )
|
|
begin
|
|
$display("*E, Failed to initialize cycle! Routine wb_block_read, Time %t ", $time) ;
|
|
return`TB_ERROR_BIT = 1'b1 ;
|
|
disable main ;
|
|
end
|
|
|
|
// insert initial wait states
|
|
cyc_count = read_flags`INIT_WAITS ;
|
|
while ( cyc_count > 0 )
|
|
begin
|
|
@(posedge CLK_I) ;
|
|
cyc_count = cyc_count - 1 ;
|
|
end
|
|
|
|
end_blk = 0 ;
|
|
while (end_blk === 0)
|
|
begin
|
|
// collect data for current data beat
|
|
current_read = blk_read_data_in[return`CYC_ACTUAL_TRANSFER] ;
|
|
|
|
wbm_low_level.wbm_read(current_read, return) ;
|
|
|
|
if ( transfered !== return`CYC_ACTUAL_TRANSFER )
|
|
begin
|
|
blk_read_data_out[transfered] = return ;
|
|
transfered = return`CYC_ACTUAL_TRANSFER ;
|
|
end
|
|
|
|
// check result of read operation
|
|
// check for severe test error
|
|
if (return`TB_ERROR_BIT !== 0)
|
|
begin
|
|
@(posedge CLK_I) ;
|
|
wbm_low_level.end_cycle ;
|
|
disable main ;
|
|
end
|
|
|
|
// slave returned error or error signal had invalid value
|
|
if (return`CYC_ERR !== 0)
|
|
end_blk = 1 ;
|
|
|
|
if (
|
|
(return`CYC_RTY !== 0) && (return`CYC_RTY !== 1) ||
|
|
(return`CYC_ACK !== 0) && (return`CYC_ACK !== 1) ||
|
|
(return`CYC_ERR !== 0) && (return`CYC_ERR !== 1)
|
|
)
|
|
begin
|
|
end_blk = 1 ;
|
|
$display("*E, at least one slave response signal was invalid when cycle finished! Routine wb_block_read, Time %t ", $time) ;
|
|
$display("ACK = %b \t RTY_O = %b \t ERR_O = %b \t", return`CYC_ACK, return`CYC_RTY, return`CYC_ERR) ;
|
|
end
|
|
|
|
if ((return`CYC_RTY === 1) && (read_flags`WB_TRANSFER_AUTO_RTY !== 1))
|
|
end_blk = 1 ;
|
|
|
|
if ((return`CYC_RTY === 1) && (read_flags`WB_TRANSFER_AUTO_RTY === 1))
|
|
begin
|
|
if ( rty_count === `WB_TB_MAX_RTY )
|
|
begin
|
|
$display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_block_read, Time %t ", $time) ;
|
|
end_blk = 1 ;
|
|
end
|
|
else
|
|
begin
|
|
rty_count = rty_count + 1 ;
|
|
end
|
|
end
|
|
else
|
|
rty_count = 0 ;
|
|
|
|
// check if slave responded at all
|
|
if (return`CYC_RESPONSE === 0)
|
|
end_blk = 1 ;
|
|
|
|
// check if all intended data was transfered
|
|
if (return`CYC_ACTUAL_TRANSFER === read_flags`WB_TRANSFER_SIZE)
|
|
end_blk = 1 ;
|
|
|
|
// insert subsequent wait cycles, if transfer is supposed to continue
|
|
if ( end_blk === 0 )
|
|
begin
|
|
cyc_count = read_flags`SUBSEQ_WAITS ;
|
|
while ( cyc_count > 0 )
|
|
begin
|
|
@(posedge CLK_I) ;
|
|
cyc_count = cyc_count - 1 ;
|
|
end
|
|
end
|
|
|
|
if ( (end_blk === 0) && (return`CYC_RTY === 1) )
|
|
begin
|
|
wbm_low_level.end_cycle ;
|
|
@(posedge CLK_I) ;
|
|
wbm_low_level.start_cycle(cab, 1'b0, ok) ;
|
|
if ( ok !== 1 )
|
|
begin
|
|
$display("*E, Failed to initialize cycle! Routine wb_block_read, Time %t ", $time) ;
|
|
return`TB_ERROR_BIT = 1'b1 ;
|
|
end_blk = 1 ;
|
|
end
|
|
end
|
|
end //while
|
|
|
|
wbm_low_level.end_cycle ;
|
|
in_use = 0 ;
|
|
end //main
|
|
endtask //wb_block_read
|
|
|
|
endmodule
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
