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//////////////////////////////////////////////////////////////////////
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//// ////
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//// File name: wb_slave_behavioral.v ////
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//// ////
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//// This file is part of the Ethernet IP core project ////
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//// http://www.opencores.org/projects/ethmac/ ////
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//// ////
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//// Author(s): ////
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//// - Tadej Markovic, tadej@opencores.org ////
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//// ////
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//// All additional information is available in the README.txt ////
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//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2002 Tadej Markovic, tadej@opencores.org ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2002/09/13 12:29:14 mohor
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// Headers changed.
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//
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// Revision 1.1 2002/09/13 11:57:21 mohor
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// New testbench. Thanks to Tadej M - "The Spammer".
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//
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// Revision 1.2 2002/03/06 09:10:56 mihad
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// Added missing include statements
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//
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// Revision 1.1 2002/02/01 13:39:43 mihad
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// Initial testbench import. Still under development
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//
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//
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`include "timescale.v"
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`include "wb_model_defines.v"
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module WB_SLAVE_BEHAVIORAL
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(
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CLK_I,
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RST_I,
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ACK_O,
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ADR_I,
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CYC_I,
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DAT_O,
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DAT_I,
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ERR_O,
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RTY_O,
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SEL_I,
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STB_I,
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WE_I,
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CAB_I
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);
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/*------------------------------------------------------------------------------------------------------
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WISHBONE signals
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------------------------------------------------------------------------------------------------------*/
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input CLK_I;
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input RST_I;
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output ACK_O;
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input `WB_ADDR_TYPE ADR_I;
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input CYC_I;
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output `WB_DATA_TYPE DAT_O;
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input `WB_DATA_TYPE DAT_I;
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output ERR_O;
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output RTY_O;
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input `WB_SEL_TYPE SEL_I;
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input STB_I;
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input WE_I;
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input CAB_I;
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reg `WB_DATA_TYPE DAT_O;
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/*------------------------------------------------------------------------------------------------------
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Asynchronous dual-port RAM signals for storing and fetching the data
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------------------------------------------------------------------------------------------------------*/
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//reg `WB_DATA_TYPE wb_memory [0:16777215]; // WB memory - 24 addresses connected - 2 LSB not used
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reg `WB_DATA_TYPE wb_memory [0:1048575]; // WB memory - 20 addresses connected - 2 LSB not used
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reg `WB_DATA_TYPE mem_wr_data_out;
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reg `WB_DATA_TYPE mem_rd_data_in;
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/*------------------------------------------------------------------------------------------------------
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Maximum values for WAIT and RETRY counters and which response !!!
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------------------------------------------------------------------------------------------------------*/
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reg [2:0] a_e_r_resp; // tells with which cycle_termination_signal must wb_slave respond !
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reg [3:0] wait_cyc;
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reg [7:0] max_retry;
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// assign registers to default state while in reset
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always@(RST_I)
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begin
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if (RST_I)
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begin
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a_e_r_resp <= 3'b000; // do not respond
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wait_cyc <= 4'b0; // no wait cycles
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max_retry <= 8'h0; // no retries
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end
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end //reset
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task cycle_response;
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input [2:0] ack_err_rty_resp; // acknowledge, error or retry response input flags
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input [3:0] wait_cycles; // if wait cycles before each data termination cycle (ack, err or rty)
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input [7:0] retry_cycles; // noumber of retry cycles before acknowledge cycle
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begin
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// assign values
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a_e_r_resp <= #1 ack_err_rty_resp;
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wait_cyc <= #1 wait_cycles;
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max_retry <= #1 retry_cycles;
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end
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endtask // cycle_response
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/*------------------------------------------------------------------------------------------------------
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Tasks for writing and reading to and from memory !!!
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------------------------------------------------------------------------------------------------------*/
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reg `WB_ADDR_TYPE task_wr_adr_i;
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reg `WB_ADDR_TYPE task_rd_adr_i;
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reg `WB_DATA_TYPE task_dat_i;
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reg `WB_DATA_TYPE task_dat_o;
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reg `WB_SEL_TYPE task_sel_i;
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reg task_wr_data;
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reg task_data_written;
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reg `WB_DATA_TYPE task_mem_wr_data;
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// write to memory
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task wr_mem;
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input `WB_ADDR_TYPE adr_i;
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input `WB_DATA_TYPE dat_i;
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input `WB_SEL_TYPE sel_i;
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begin
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task_data_written = 0;
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task_wr_adr_i = adr_i;
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task_dat_i = dat_i;
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task_sel_i = sel_i;
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task_wr_data = 1;
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wait(task_data_written);
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task_wr_data = 0;
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end
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endtask
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// read from memory
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task rd_mem;
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input `WB_ADDR_TYPE adr_i;
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output `WB_DATA_TYPE dat_o;
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input `WB_SEL_TYPE sel_i;
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begin
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task_rd_adr_i = adr_i;
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task_sel_i = sel_i;
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#1;
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dat_o = task_dat_o;
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end
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endtask
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/*------------------------------------------------------------------------------------------------------
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Internal signals and logic
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------------------------------------------------------------------------------------------------------*/
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reg calc_ack;
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reg calc_err;
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reg calc_rty;
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reg [7:0] retry_cnt;
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reg [7:0] retry_num;
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reg retry_expired;
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// Retry counter
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always@(posedge RST_I or posedge CLK_I)
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begin
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if (RST_I)
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retry_cnt <= #1 8'h00;
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else
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begin
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if (calc_ack || calc_err)
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retry_cnt <= #1 8'h00;
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else if (calc_rty)
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retry_cnt <= #1 retry_num;
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end
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end
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always@(retry_cnt or max_retry)
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begin
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if (retry_cnt < max_retry)
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begin
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retry_num = retry_cnt + 1'b1;
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retry_expired = 1'b0;
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end
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else
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begin
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retry_num = retry_cnt;
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retry_expired = 1'b1;
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end
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end
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reg [3:0] wait_cnt;
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reg [3:0] wait_num;
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reg wait_expired;
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// Wait counter
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always@(posedge RST_I or posedge CLK_I)
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begin
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if (RST_I)
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wait_cnt <= #1 4'h0;
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else
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begin
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if (wait_expired || ~STB_I)
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wait_cnt <= #1 4'h0;
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else
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wait_cnt <= #1 wait_num;
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end
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end
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always@(wait_cnt or wait_cyc or STB_I or a_e_r_resp or retry_expired)
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begin
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if ((wait_cyc > 0) && (STB_I))
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begin
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if (wait_cnt < wait_cyc) // 4'h2)
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begin
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wait_num = wait_cnt + 1'b1;
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wait_expired = 1'b0;
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calc_ack = 1'b0;
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calc_err = 1'b0;
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calc_rty = 1'b0;
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end
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else
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begin
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wait_num = wait_cnt;
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wait_expired = 1'b1;
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if (a_e_r_resp == 3'b100)
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begin
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calc_ack = 1'b1;
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calc_err = 1'b0;
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calc_rty = 1'b0;
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end
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else
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if (a_e_r_resp == 3'b010)
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begin
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calc_ack = 1'b0;
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calc_err = 1'b1;
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calc_rty = 1'b0;
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end
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else
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if (a_e_r_resp == 3'b001)
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begin
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calc_err = 1'b0;
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if (retry_expired)
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begin
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calc_ack = 1'b1;
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calc_rty = 1'b0;
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end
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else
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begin
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calc_ack = 1'b0;
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calc_rty = 1'b1;
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end
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end
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else
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begin
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calc_ack = 1'b0;
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calc_err = 1'b0;
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calc_rty = 1'b0;
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end
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end
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end
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else
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if ((wait_cyc == 0) && (STB_I))
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begin
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wait_num = 2'h0;
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wait_expired = 1'b1;
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if (a_e_r_resp == 3'b100)
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begin
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calc_ack = 1'b1;
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calc_err = 1'b0;
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calc_rty = 1'b0;
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end
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else if (a_e_r_resp == 3'b010)
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begin
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calc_ack = 1'b0;
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calc_err = 1'b1;
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calc_rty = 1'b0;
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end
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else if (a_e_r_resp == 3'b001)
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begin
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calc_err = 1'b0;
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if (retry_expired)
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begin
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calc_ack = 1'b1;
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calc_rty = 1'b0;
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end
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else
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begin
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calc_ack = 1'b0;
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calc_rty = 1'b1;
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end
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end
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else
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begin
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calc_ack = 1'b0;
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calc_err = 1'b0;
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calc_rty = 1'b0;
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end
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end
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else
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begin
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wait_num = 2'h0;
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wait_expired = 1'b0;
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calc_ack = 1'b0;
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calc_err = 1'b0;
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calc_rty = 1'b0;
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end
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end
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wire rd_sel = (CYC_I && STB_I && ~WE_I);
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wire wr_sel = (CYC_I && STB_I && WE_I);
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// Generate cycle termination signals
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assign ACK_O = calc_ack && STB_I;
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assign ERR_O = calc_err && STB_I;
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assign RTY_O = calc_rty && STB_I;
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// Assign address to asynchronous memory
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always@(RST_I or ADR_I)
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begin
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if (RST_I) // this is added because at start of test bench we need address change in order to get data!
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begin
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#1 mem_rd_data_in = `WB_DATA_WIDTH'hxxxx_xxxx;
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end
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else
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begin
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// #1 mem_rd_data_in = wb_memory[ADR_I[25:2]];
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#1 mem_rd_data_in = wb_memory[ADR_I[21:2]];
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end
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end
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// Data input/output interface
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always@(rd_sel or mem_rd_data_in or RST_I)
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begin
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if (RST_I)
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DAT_O <=#1 `WB_DATA_WIDTH'hxxxx_xxxx; // assign outputs to unknown state while in reset
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else if (rd_sel)
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DAT_O <=#1 mem_rd_data_in;
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else
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DAT_O <=#1 `WB_DATA_WIDTH'hxxxx_xxxx;
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end
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always@(RST_I or task_rd_adr_i)
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begin
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if (RST_I)
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task_dat_o = `WB_DATA_WIDTH'hxxxx_xxxx;
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else
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task_dat_o = wb_memory[task_rd_adr_i[21:2]];
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end
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always@(CLK_I or wr_sel or task_wr_data or ADR_I or task_wr_adr_i or
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mem_wr_data_out or DAT_I or task_mem_wr_data or task_dat_i or
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SEL_I or task_sel_i)
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begin
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if (task_wr_data)
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begin
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task_mem_wr_data = wb_memory[task_wr_adr_i[21:2]];
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if (task_sel_i[3])
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task_mem_wr_data[31:24] = task_dat_i[31:24];
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if (task_sel_i[2])
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task_mem_wr_data[23:16] = task_dat_i[23:16];
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if (task_sel_i[1])
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task_mem_wr_data[15: 8] = task_dat_i[15: 8];
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if (task_sel_i[0])
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task_mem_wr_data[ 7: 0] = task_dat_i[ 7: 0];
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wb_memory[task_wr_adr_i[21:2]] = task_mem_wr_data; // write data
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task_data_written = 1;
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end
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else if (wr_sel && ~CLK_I)
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begin
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// mem_wr_data_out = wb_memory[ADR_I[25:2]]; // if no SEL_I is active, old value will be written
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mem_wr_data_out = wb_memory[ADR_I[21:2]]; // if no SEL_I is active, old value will be written
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if (SEL_I[3])
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mem_wr_data_out[31:24] = DAT_I[31:24];
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if (SEL_I[2])
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mem_wr_data_out[23:16] = DAT_I[23:16];
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if (SEL_I[1])
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mem_wr_data_out[15: 8] = DAT_I[15: 8];
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if (SEL_I[0])
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mem_wr_data_out[ 7: 0] = DAT_I[ 7: 0];
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// wb_memory[ADR_I[25:2]] <= mem_wr_data_out; // write data
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wb_memory[ADR_I[21:2]] = mem_wr_data_out; // write data
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end
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end
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endmodule
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