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Line 100... |
//reg `WB_DATA_TYPE wb_memory [0:16777215]; // WB memory - 24 addresses connected - 2 LSB not used
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//reg `WB_DATA_TYPE wb_memory [0:16777215]; // WB memory - 24 addresses connected - 2 LSB not used
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reg `WB_DATA_TYPE wb_memory [0:1048575]; // WB memory - 20 addresses connected - 2 LSB not used
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reg `WB_DATA_TYPE wb_memory [0:1048575]; // WB memory - 20 addresses connected - 2 LSB not used
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reg `WB_DATA_TYPE mem_wr_data_out;
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reg `WB_DATA_TYPE mem_wr_data_out;
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reg `WB_DATA_TYPE mem_rd_data_in;
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reg `WB_DATA_TYPE mem_rd_data_in;
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initial $readmemh("wb_memory.txt",wb_memory);
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integer k;
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initial begin
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$display("Contents of Mem after reading data file:");
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for (k=0; k<10; k=k+1) $display("%d:%h",k,wb_memory[k]);
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end
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/*------------------------------------------------------------------------------------------------------
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/*------------------------------------------------------------------------------------------------------
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Maximum values for WAIT and RETRY counters and which response !!!
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Maximum values for WAIT and RETRY counters and which response !!!
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------------------------------------------------------------------------------------------------------*/
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------------------------------------------------------------------------------------------------------*/
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reg [2:0] a_e_r_resp; // tells with which cycle_termination_signal must wb_slave respond !
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reg [2:0] a_e_r_resp; // tells with which cycle_termination_signal must wb_slave respond !
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reg [3:0] wait_cyc;
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reg [3:0] wait_cyc;
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Line 122... |
// assign registers to default state while in reset
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// assign registers to default state while in reset
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always@(RST_I)
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always@(RST_I)
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begin
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begin
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if (RST_I)
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if (RST_I)
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begin
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begin
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a_e_r_resp <= 3'b000; // do not respond
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a_e_r_resp <= 3'b100; // do not respond
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wait_cyc <= 4'b0; // no wait cycles
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wait_cyc <= 4'b0; // no wait cycles
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max_retry <= 8'h0; // no retries
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max_retry <= 8'h0; // no retries
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end
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end
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end //reset
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end //reset
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