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`include "SD_defines.v"
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module sd_controller_fifo_wba
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(
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// WISHBONE common
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wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o,
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// WISHBONE slave
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wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o,
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// WISHBONE master
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m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
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m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
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m_wb_stb_o, m_wb_ack_i,
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m_wb_cti_o, m_wb_bte_o,
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//SD BUS
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sd_cmd_dat_i,sd_cmd_out_o, sd_cmd_oe_o,
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sd_dat_dat_i, sd_dat_out_o , sd_dat_oe_o, sd_clk_o_pad
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//PLL CLK_IN
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// sd_clk_i_pad
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);
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input wb_clk_i; // WISHBONE clock
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input wb_rst_i; // WISHBONE reset
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input [7:0] wb_dat_i; // WISHBONE data input
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output [7:0] wb_dat_o; // WISHBONE data output
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// WISHBONE error output
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// WISHBONE slave
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input [2:0] wb_adr_i; // WISHBONE address input
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input [3:0] wb_sel_i; // WISHBONE byte select input
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input wb_we_i; // WISHBONE write enable input
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input wb_cyc_i; // WISHBONE cycle input
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input wb_stb_i; // WISHBONE strobe input
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output reg wb_ack_o; // WISHBONE acknowledge output
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// WISHBONE master
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output [31:0] m_wb_adr_o;
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output [3:0] m_wb_sel_o;
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output m_wb_we_o;
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input [31:0] m_wb_dat_i;
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output [31:0] m_wb_dat_o;
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output m_wb_cyc_o;
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output m_wb_stb_o;
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input m_wb_ack_i;
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output [2:0] m_wb_cti_o;
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output [1:0] m_wb_bte_o;
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input wire [3:0] sd_dat_dat_i;
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output wire [3:0] sd_dat_out_o;
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output wire sd_dat_oe_o;
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input wire sd_cmd_dat_i;
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output wire sd_cmd_out_o;
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output wire sd_cmd_oe_o;
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output sd_clk_o_pad;
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wire sd_clk_i;
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//input sd_clk_i_pad;
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`define tx_cmd_fifo 4'h0
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`define rx_cmd_fifo 4'h1
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`define tx_data_fifo 4'h2
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`define rx_data_fifo 4'h3
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`define status 4'h4
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`define controll 4'h5
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`define timer 4'h6
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reg [7:0] controll_reg;
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reg [7:0] status_reg;
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reg [7:0] command_timeout_reg;
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`ifdef SD_CLK_BUS_CLK
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assign sd_clk_i = wb_clk_i;
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`endif
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`ifdef SD_CLK_SEP
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//assign sd_clk_i = sd_clk_i_pad;
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`endif
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assign sd_clk_o=sd_clk_i;
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reg [1:0] wb_fifo_adr_i_writer;
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reg [1:0] wb_fifo_adr_i_reader;
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wire [1:0] wb_fifo_adr_i;
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reg add_token_read;
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wire [7:0] wb_fifo_dat_i;
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wire [7:0] wb_fifo_dat_o;
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reg [7:0] wb_dat_i_storage;
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reg [7:0] wb_dat_o_i;
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reg time_enable;
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assign sd_clk_o_pad = sd_clk_i ;
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assign wb_fifo_adr_i = add_token_read ? wb_fifo_adr_i_reader : wb_fifo_adr_i_writer;
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assign wb_fifo_dat_i =wb_dat_i_storage;
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assign wb_dat_o = wb_adr_i[0] ? wb_fifo_dat_o : wb_dat_o_i ;
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wire [1:4]fifo_full ;
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wire [1:4]fifo_empty;
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reg wb_fifo_we_i;
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reg wb_fifo_re_i;
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wire [1:0] sd_adr_o;
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wire [7:0] sd_dat_o;
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wire [7:0] sd_dat_i;
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sd_fifo sd_fifo_0
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(
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.wb_adr_i (wb_fifo_adr_i ),
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.wb_dat_i (wb_fifo_dat_i),
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.wb_dat_o (wb_fifo_dat_o ),
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.wb_we_i (wb_fifo_we_i),
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.wb_re_i (wb_fifo_re_i),
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.wb_clk (wb_clk_i),
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.sd_adr_i (sd_adr_o ),
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.sd_dat_i (sd_dat_o),
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.sd_dat_o (sd_dat_i ),
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.sd_we_i (sd_we_o),
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.sd_re_i (sd_re_o),
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.sd_clk (sd_clk_o),
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.fifo_full ( fifo_full ),
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.fifo_empty (fifo_empty ),
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.rst (wb_rst_i) // | controll_reg[0])
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) ;
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wire [1:0] sd_adr_o_cmd;
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wire [7:0] sd_dat_i_cmd;
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wire [7:0] sd_dat_o_cmd;
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wire [1:0] sd_adr_o_dat;
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wire [7:0] sd_dat_i_dat;
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wire [7:0] sd_dat_o_dat;
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wire [1:0] st_dat_t;
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sd_cmd_phy sdc_cmd_phy_0
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(
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.sd_clk (sd_clk_o),
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.rst (wb_rst_i ),//| controll_reg[0]),
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.cmd_dat_i ( sd_cmd_dat_i ),
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.cmd_dat_o (sd_cmd_out_o ),
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.cmd_oe_o (sd_cmd_oe_o ),
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.sd_adr_o (sd_adr_o_cmd),
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.sd_dat_i (sd_dat_i_cmd),
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.sd_dat_o (sd_dat_o_cmd),
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.sd_we_o (sd_we_o_cmd),
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.sd_re_o (sd_re_o_cmd),
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.fifo_full ( fifo_full[1:2] ),
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.fifo_empty ( fifo_empty [1:2]),
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.start_dat_t (st_dat_t),
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.fifo_acces_token (fifo_acces_token)
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);
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sd_data_phy sd_data_phy_0 (
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.sd_clk (sd_clk_o),
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.rst (wb_rst_i | controll_reg[0]),
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.DAT_oe_o ( sd_dat_oe_o ),
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.DAT_dat_o (sd_dat_out_o),
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.DAT_dat_i (sd_dat_dat_i ),
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.sd_adr_o (sd_adr_o_dat ),
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.sd_dat_i (sd_dat_i_dat ),
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.sd_dat_o (sd_dat_o_dat ),
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.sd_we_o (sd_we_o_dat),
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.sd_re_o (sd_re_o_dat),
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.fifo_full ( fifo_full[3:4] ),
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.fifo_empty ( fifo_empty [3:4]),
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.start_dat (st_dat_t),
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.fifo_acces (~fifo_acces_token)
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);
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assign sd_adr_o = fifo_acces_token ? sd_adr_o_cmd : sd_adr_o_dat;
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assign sd_dat_o = fifo_acces_token ? sd_dat_o_cmd : sd_dat_o_dat;
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assign sd_we_o = fifo_acces_token ? sd_we_o_cmd : sd_we_o_dat;
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assign sd_re_o = fifo_acces_token ? sd_re_o_cmd : sd_re_o_dat;
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assign sd_dat_i_dat = sd_dat_i;
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assign sd_dat_i_cmd = sd_dat_i;
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always @(posedge wb_clk_i or posedge wb_rst_i)
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begin
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if (wb_rst_i)
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status_reg<=0;
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else begin
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status_reg[0] <= fifo_full[1];
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status_reg[1] <= fifo_empty[2];
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status_reg[2] <= fifo_full[3];
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status_reg[3] <= fifo_empty[4];
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end
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end
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reg delayed_ack;
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always @(posedge wb_clk_i or posedge wb_rst_i)
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begin
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if (wb_rst_i)
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wb_ack_o <=0;
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else
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wb_ack_o <=wb_stb_i & wb_cyc_i & ~wb_ack_o & delayed_ack;
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end
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always @(posedge wb_clk_i or posedge wb_rst_i)
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begin
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if ( wb_rst_i )begin
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command_timeout_reg<=`TIME_OUT_TIME;
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wb_dat_i_storage<=0;
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controll_reg<=0;
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wb_fifo_we_i<=0;
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wb_fifo_adr_i_writer<=0;
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time_enable<=0;
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end
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else if (wb_stb_i & wb_cyc_i & (~wb_ack_o))begin //CS
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if (wb_we_i) begin
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case (wb_adr_i)
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`tx_cmd_fifo : begin
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wb_fifo_adr_i_writer<=0;
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wb_fifo_we_i<=1&!delayed_ack;
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wb_dat_i_storage<=wb_dat_i;
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command_timeout_reg<=`TIME_OUT_TIME;
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time_enable<=1;
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end
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`tx_data_fifo : begin
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wb_fifo_adr_i_writer<=2;
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wb_fifo_we_i<=1&!delayed_ack;
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wb_dat_i_storage<=wb_dat_i;
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command_timeout_reg<=`TIME_OUT_TIME;
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time_enable<=0;
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end
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`controll : controll_reg <= wb_dat_i;
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endcase
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end
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end
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else begin
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// wb_fifo_adr_i_writer<=0;
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wb_fifo_we_i<=0;
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if (!status_reg[1])
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time_enable<=0;
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if ((command_timeout_reg!=0) && (time_enable))
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command_timeout_reg<=command_timeout_reg-1;
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end
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end
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always @(posedge wb_clk_i or posedge wb_rst_i )begin
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if ( wb_rst_i) begin
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add_token_read<=0;
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delayed_ack<=0;
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wb_fifo_re_i<=0;
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wb_fifo_adr_i_reader<=0;
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wb_dat_o_i<=0;
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end
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else begin
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delayed_ack<=0;
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wb_fifo_re_i<=0;
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if (wb_stb_i & wb_cyc_i & (~wb_ack_o)) begin //C
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delayed_ack<=delayed_ack+1;
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add_token_read<=0;
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if (!wb_we_i) begin
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case (wb_adr_i)
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`rx_cmd_fifo : begin
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add_token_read<=1;
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wb_fifo_adr_i_reader<=1;
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wb_fifo_re_i<=1&delayed_ack;
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end
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`rx_data_fifo :begin
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add_token_read<=1;
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wb_fifo_adr_i_reader<=3;
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wb_fifo_re_i<=1 & delayed_ack;
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end
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`status : wb_dat_o_i <= status_reg;
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`timer : wb_dat_o_i <= command_timeout_reg;
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endcase
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end
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end
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end
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end
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//just to get rid of warnings....
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assign m_wb_adr_o =0;
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assign m_wb_sel_o =0;
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assign m_wb_we_o=0;
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assign m_wb_dat_o =0;
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assign m_wb_cyc_o=0;
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assign m_wb_stb_o=0;
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assign m_wb_cti_o=0;
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assign m_wb_bte_o=0;
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endmodule
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