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URL https://opencores.org/ocsvn/sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk

Subversion Repositories sdcard_mass_storage_controller

[/] [sdcard_mass_storage_controller/] [trunk/] [rtl/] [sdc_fifo/] [verilog/] [sd_controller_fifo_wb.v] - Diff between revs 10 and 26

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Rev 10 Rev 26
Line 17... Line 17... 
  m_wb_cti_o, m_wb_bte_o,
 
  m_wb_cti_o, m_wb_bte_o,
 
  //SD BUS
 
  //SD BUS
 
  sd_cmd_dat_i,sd_cmd_out_o,  sd_cmd_oe_o,
 
  sd_cmd_dat_i,sd_cmd_out_o,  sd_cmd_oe_o,
 
  sd_dat_dat_i, sd_dat_out_o , sd_dat_oe_o, sd_clk_o_pad
 
  sd_dat_dat_i, sd_dat_out_o , sd_dat_oe_o, sd_clk_o_pad
 
  //PLL CLK_IN
 
  //PLL CLK_IN
 
  // sd_clk_i_pad
 
   `ifdef SD_CLK_EXT
 
 
 
    ,sd_clk_i_pad
 
 
 
   `endif
 
 
 
 
 
 
 
 
 
);
 
);
 
input           wb_clk_i;     // WISHBONE clock
 
input           wb_clk_i;     // WISHBONE clock
 
input           wb_rst_i;     // WISHBONE reset
 
input           wb_rst_i;     // WISHBONE reset
 
input   [7:0]  wb_dat_i;     // WISHBONE data input
 
input   [7:0]  wb_dat_i;     // WISHBONE data input
Line 36... Line 39... 
input           wb_stb_i;     // WISHBONE strobe input
 
input           wb_stb_i;     // WISHBONE strobe input
 
 
 
 
 
output reg          wb_ack_o;     // WISHBONE acknowledge output
 
output reg          wb_ack_o;     // WISHBONE acknowledge output
 
 
 
 
 
// WISHBONE master
 
// WISHBONE master
 
output  [31:0]  m_wb_adr_o;
 
 
 
output   [3:0]  m_wb_sel_o;
 
 
 
output          m_wb_we_o;
 
 
 
 
 
 
 
input   [31:0]  m_wb_dat_i;
 
 
 
output  [31:0]  m_wb_dat_o;
 
 
 
output          m_wb_cyc_o;
 
 
 
output          m_wb_stb_o;
 
 
 
input           m_wb_ack_i;
 
 
 
output          [2:0] m_wb_cti_o;
 
 
 
output  [1:0]     m_wb_bte_o;
 
 
 
 
 
 
 
input wire [3:0] sd_dat_dat_i;
 
input wire [3:0] sd_dat_dat_i;
 
output wire [3:0] sd_dat_out_o;
 
output wire [3:0] sd_dat_out_o;
 
output wire sd_dat_oe_o;
 
output wire sd_dat_oe_o;
 
 
 
 
Line 58... Line 51... 
output wire sd_cmd_out_o;
 
output wire sd_cmd_out_o;
 
output wire sd_cmd_oe_o;
 
output wire sd_cmd_oe_o;
 
 
 
 
 
output sd_clk_o_pad;
 
output sd_clk_o_pad;
 
wire sd_clk_i;
 
wire sd_clk_i;
 
//input sd_clk_i_pad;
 
input sd_clk_i_pad;
 
 
 
 
 
`define tx_cmd_fifo 4'h0
 
`define tx_cmd_fifo 4'h0
 
`define rx_cmd_fifo 4'h1
 
`define rx_cmd_fifo 4'h1
 
`define tx_data_fifo 4'h2
 
`define tx_data_fifo 4'h2
 
`define rx_data_fifo 4'h3
 
`define rx_data_fifo 4'h3

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