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//-------------------------
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//-------------------------
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`include "SD_defines.v"
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`define BUFFER_OFFSET 2
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module sd_data_phy(
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input sd_clk,
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input rst,
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output reg DAT_oe_o,
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output reg[3:0] DAT_dat_o,
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input [3:0] DAT_dat_i,
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output [1:0] sd_adr_o,
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input [7:0] sd_dat_i,
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output reg [7:0] sd_dat_o,
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output reg sd_we_o,
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output reg sd_re_o,
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input [3:4] fifo_full,
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input [3:4] fifo_empty,
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input [1:0] start_dat,
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input fifo_acces
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);
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reg [5:0] in_buff_ptr_read;
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reg [5:0] out_buff_ptr_read;
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reg crc_ok;
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reg [3:0] last_din_read;
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reg [7:0] tmp_crc_token ;
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reg[2:0] crc_read_count;
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//CRC16
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reg [3:0] crc_in_write;
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reg crc_en_write;
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reg crc_rst_write;
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wire [15:0] crc_out_write [3:0];
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reg [3:0] crc_in_read;
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reg crc_en_read;
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reg crc_rst_read;
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wire [15:0] crc_out_read [3:0];
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reg[7:0] next_out;
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reg data_read_index;
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reg [10:0] transf_cnt_write;
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reg [10:0] transf_cnt_read;
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parameter SIZE = 6;
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reg [SIZE-1:0] state;
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reg [SIZE-1:0] next_state;
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parameter IDLE = 6'b000001;
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parameter WRITE_DAT = 6'b000010;
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parameter READ_CRC = 6'b000100;
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parameter WRITE_CRC = 6'b001000;
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parameter READ_WAIT = 6'b010000;
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parameter READ_DAT = 6'b100000;
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reg in_dat_buffer_empty;
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reg [2:0] crc_status_token;
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reg busy_int;
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reg add_token;
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genvar i;
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generate
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for(i=0; i<4; i=i+1) begin:CRC_16_gen_write
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CRC_16 CRC_16_i (crc_in_write[i],crc_en_write, sd_clk, crc_rst_write, crc_out_write[i]);
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end
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endgenerate
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generate
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for(i=0; i<4; i=i+1) begin:CRC_16_gen_read
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CRC_16 CRC_16_i (crc_in_read[i],crc_en_read, sd_clk, crc_rst_read, crc_out_read[i]);
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end
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endgenerate
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reg q_start_bit;
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always @ (state or start_dat or DAT_dat_i[0] or transf_cnt_write or transf_cnt_read or busy_int or crc_read_count or sd_we_o or in_dat_buffer_empty )
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begin : FSM_COMBO
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next_state = 0;
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case(state)
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IDLE: begin
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if (start_dat == 2'b01)
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next_state=WRITE_DAT;
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else if (start_dat == 2'b10)
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next_state=READ_WAIT;
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else
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next_state=IDLE;
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end
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WRITE_DAT: begin
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if (transf_cnt_write >= `BIT_BLOCK+`BUFFER_OFFSET)
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next_state= READ_CRC;
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else if (start_dat == 2'b11)
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next_state=IDLE;
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else
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next_state=WRITE_DAT;
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end
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READ_WAIT: begin
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if (DAT_dat_i[0]== 0 )
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next_state= READ_DAT;
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else
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next_state=READ_WAIT;
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end
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READ_CRC: begin
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if ( (crc_read_count == 3'b111) &&(busy_int ==1) )
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next_state= WRITE_CRC;
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else
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next_state=READ_CRC;
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end
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WRITE_CRC: begin
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next_state= IDLE;
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end
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READ_DAT: begin
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if ((transf_cnt_read >= `BIT_BLOCK-3) && (in_dat_buffer_empty)) //Startbit consumed...
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next_state= IDLE;
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else if (start_dat == 2'b11)
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next_state=IDLE;
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else
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next_state=READ_DAT;
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end
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endcase
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end
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always @ (posedge sd_clk or posedge rst )
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begin
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if (rst ) begin
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q_start_bit<=1;
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end
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else begin
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q_start_bit <= DAT_dat_i[0];
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end
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end
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//----------------Seq logic------------
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always @ (posedge sd_clk or posedge rst )
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begin : FSM_SEQ
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if (rst ) begin
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state <= #1 IDLE;
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end
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else begin
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state <= #1 next_state;
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end
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end
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reg [4:0] crc_cnt_write;
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reg [4:0]crc_cnt_read;
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reg [3:0] last_din;
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reg [2:0] crc_s ;
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reg [7:0] write_buf_0,write_buf_1, sd_data_out;
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reg out_buff_ptr,in_buff_ptr;
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reg data_send_index;
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reg [1:0] sd_adr_o_read;
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reg [1:0] sd_adr_o_write;
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reg read_byte_cnt;
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assign sd_adr_o = add_token ? sd_adr_o_read : sd_adr_o_write;
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assign sd_adr_o = add_token ? sd_adr_o_read : sd_adr_o_write;
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reg [3:0] in_dat_buffer [63:0];
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always @ (negedge sd_clk or posedge rst )
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begin
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if (rst) begin
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DAT_oe_o<=0;
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crc_en_write<=0;
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crc_rst_write<=1;
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transf_cnt_write<=0;
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crc_cnt_write<=15;
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crc_status_token<=7;
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data_send_index<=0;
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out_buff_ptr<=0;
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in_buff_ptr<=0;
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read_byte_cnt<=0;
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write_buf_0<=0;
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write_buf_1<=0;
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sd_re_o<=0;
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sd_data_out<=0;
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sd_adr_o_write<=0;
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crc_in_write<=0;
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DAT_dat_o<=0;
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last_din<=0;
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end
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else begin
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case(state)
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IDLE: begin
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DAT_oe_o<=0;
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crc_en_write<=0;
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crc_rst_write<=1;
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crc_cnt_write<=16;
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read_byte_cnt<=0;
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crc_status_token<=7;
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data_send_index<=0;
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out_buff_ptr<=0;
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in_buff_ptr<=0;
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sd_re_o<=0;
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transf_cnt_write<=0;
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end
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WRITE_DAT: begin
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transf_cnt_write<=transf_cnt_write+1;
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if ( (in_buff_ptr != out_buff_ptr) || (transf_cnt_write<2) ) begin
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read_byte_cnt<=read_byte_cnt+1;
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sd_re_o<=0;
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case (read_byte_cnt)
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0:begin
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sd_adr_o_write <=2;
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sd_re_o<=1;
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end
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1:begin
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if (!in_buff_ptr)
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write_buf_0<=sd_dat_i;
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else
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write_buf_1 <=sd_dat_i;
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in_buff_ptr<=in_buff_ptr+1;
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end
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endcase
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end
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if (!out_buff_ptr)
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sd_data_out<=write_buf_0;
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else
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sd_data_out<=write_buf_1;
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if (transf_cnt_write==1+`BUFFER_OFFSET) begin
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crc_rst_write<=0;
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crc_en_write<=1;
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last_din <=write_buf_0[3:0];
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DAT_oe_o<=1;
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DAT_dat_o<=0;
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crc_in_write<= write_buf_0[3:0];
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data_send_index<=1;
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out_buff_ptr<=out_buff_ptr+1;
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end
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else if ( (transf_cnt_write>=2+`BUFFER_OFFSET) && (transf_cnt_write<=`BIT_BLOCK-`CRC_OFF+`BUFFER_OFFSET )) begin
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DAT_oe_o<=1;
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case (data_send_index)
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0:begin
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last_din <=sd_data_out[3:0];
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crc_in_write <=sd_data_out[3:0];
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out_buff_ptr<=out_buff_ptr+1;
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end
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1:begin
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last_din <=sd_data_out[7:4];
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crc_in_write <=sd_data_out[7:4];
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end
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endcase
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data_send_index<=data_send_index+1;
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DAT_dat_o<= last_din;
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if ( transf_cnt_write >=`BIT_BLOCK-`CRC_OFF +`BUFFER_OFFSET) begin
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crc_en_write<=0;
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end
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end
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else if (transf_cnt_write>`BIT_BLOCK-`CRC_OFF +`BUFFER_OFFSET & crc_cnt_write!=0) begin
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crc_en_write<=0;
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crc_cnt_write<=crc_cnt_write-1;
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DAT_oe_o<=1;
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DAT_dat_o[0]<=crc_out_write[0][crc_cnt_write-1];
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DAT_dat_o[1]<=crc_out_write[1][crc_cnt_write-1];
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DAT_dat_o[2]<=crc_out_write[2][crc_cnt_write-1];
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DAT_dat_o[3]<=crc_out_write[3][crc_cnt_write-1];
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end
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else if (transf_cnt_write==`BIT_BLOCK-2+`BUFFER_OFFSET) begin
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DAT_oe_o<=1;
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DAT_dat_o<=4'b1111;
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end
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else if (transf_cnt_write !=0) begin
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DAT_oe_o<=0;
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end
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end
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endcase
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end
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end
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always @ (posedge sd_clk or posedge rst )
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begin
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if (rst) begin
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add_token<=0;
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sd_adr_o_read<=0;
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crc_read_count<=0;
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sd_we_o<=0;
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tmp_crc_token<=0;
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crc_rst_read<=0;
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crc_en_read<=0;
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in_buff_ptr_read<=0;
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out_buff_ptr_read<=0;
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crc_cnt_read<=0;
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transf_cnt_read<=0;
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data_read_index<=0;
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in_dat_buffer_empty<=0;
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next_out<=0;
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busy_int<=0;
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sd_dat_o<=0;
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end
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else begin
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case(state)
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IDLE: begin
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add_token<=0;
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crc_read_count<=0;
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sd_we_o<=0;
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tmp_crc_token<=0;
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crc_rst_read<=1;
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crc_en_read<=0;
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in_buff_ptr_read<=0;
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out_buff_ptr_read<=0;
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crc_cnt_read<=15;
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transf_cnt_read<=0;
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data_read_index<=0;
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in_dat_buffer_empty<=0;
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end
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READ_DAT: begin
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add_token<=1;
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crc_rst_read<=0;
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crc_en_read<=1;
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if (fifo_acces) begin
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if ( (in_buff_ptr_read - out_buff_ptr_read) >=2) begin
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data_read_index<=~data_read_index;
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case(data_read_index)
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0: begin
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sd_adr_o_read<=3;
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sd_we_o<=0;
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next_out[3:0]<=in_dat_buffer[out_buff_ptr_read ];
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next_out[7:4]<=in_dat_buffer[out_buff_ptr_read+1 ];
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end
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1: begin
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out_buff_ptr_read<=out_buff_ptr_read+2;
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sd_dat_o<=next_out;
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sd_we_o<=1;
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end
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endcase
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end
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else
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in_dat_buffer_empty<=1;
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end
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if (transf_cnt_read<`BIT_BLOCK_REC) begin
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in_dat_buffer[in_buff_ptr_read]<=DAT_dat_i;
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crc_in_read<=DAT_dat_i;
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crc_ok<=1;
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transf_cnt_read<=transf_cnt_read+1;
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in_buff_ptr_read<=in_buff_ptr_read+1;
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end
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else if ( transf_cnt_read <= (`BIT_BLOCK_REC +`BIT_CRC_CYCLE)) begin
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transf_cnt_read<=transf_cnt_read+1;
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crc_en_read<=0;
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last_din_read <=DAT_dat_i;
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if (transf_cnt_read> `BIT_BLOCK_REC) begin
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crc_cnt_read <=crc_cnt_read-1;
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if (crc_out_read[0][crc_cnt_read] != last_din[0])
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crc_ok<=0;
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if (crc_out_read[1][crc_cnt_read] != last_din[1])
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crc_ok<=0;
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if (crc_out_read[2][crc_cnt_read] != last_din[2])
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crc_ok<=0;
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if (crc_out_read[3][crc_cnt_read] != last_din[3])
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crc_ok<=0;
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if (crc_cnt_read==0) begin
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//in_dat_buffer[in_buff_ptr_read] <= {7'b0,crc_ok}
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end
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end
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end
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end
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READ_CRC: begin
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if (crc_read_count<3'b111) begin
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crc_read_count<=crc_read_count+1;
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tmp_crc_token[crc_read_count] <= DAT_dat_i[0];
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end
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busy_int <=DAT_dat_i[0];
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end
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WRITE_CRC: begin
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add_token<=1;
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sd_adr_o_read<=3;
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sd_we_o<=1;
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sd_dat_o<=tmp_crc_token;
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end
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endcase
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end
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end
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//Sync
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endmodule
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