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/*$$HEADER*/
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/******************************************************************************/
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/* */
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/* H E A D E R I N F O R M A T I O N */
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/* */
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/******************************************************************************/
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// Project Name : Development Board Debugger Example
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// File Name : BootReset.S
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// Prepared By : jb
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// Project Start : 2009-01-01
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/*$$COPYRIGHT NOTICE*/
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/******************************************************************************/
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/* */
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/* C O P Y R I G H T N O T I C E */
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/* */
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/******************************************************************************/
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// Copyright (c) ORSoC 2009 All rights reserved.
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// The information in this document is the property of ORSoC.
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// Except as specifically authorized in writing by ORSoC, the receiver of
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// this document shall keep the information contained herein confidential and
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// shall protect the same in whole or in part thereof from disclosure and
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// dissemination to third parties. Disclosure and disseminations to the receiver's
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// employees shall only be made on a strict need to know basis.
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/*$$DESCRIPTION*/
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/******************************************************************************/
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/* */
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/* D E S C R I P T I O N */
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/* */
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/******************************************************************************/
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/*$$CHANGE HISTORY*/
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/******************************************************************************/
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/* */
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/* C H A N G E H I S T O R Y */
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/* */
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/******************************************************************************/
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// Date Version Description
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//------------------------------------------------------------------------
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// 090101 1.0 First version jb
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/*$$DESCRIPTION*/
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/******************************************************************************/
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/* */
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/* D E S C R I P T I O N */
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/* */
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/******************************************************************************/
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// spr_defs.h -- Defines OR1K architecture specific special-purpose registers
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/*$$DEFINES*/
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/******************************************************************************/
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/* */
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/* D E F I N E S */
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/* */
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/******************************************************************************/
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#define MAX_GRPS (32)
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#define MAX_SPRS_PER_GRP_BITS (11)
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#define MAX_SPRS_PER_GRP (1 << MAX_SPRS_PER_GRP_BITS)
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#define MAX_SPRS (0x10000)
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/* Base addresses for the groups */
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#define SPRGROUP_SYS (0<< MAX_SPRS_PER_GRP_BITS)
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#define SPRGROUP_DMMU (1<< MAX_SPRS_PER_GRP_BITS)
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#define SPRGROUP_IMMU (2<< MAX_SPRS_PER_GRP_BITS)
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#define SPRGROUP_DC (3<< MAX_SPRS_PER_GRP_BITS)
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#define SPRGROUP_IC (4<< MAX_SPRS_PER_GRP_BITS)
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#define SPRGROUP_MAC (5<< MAX_SPRS_PER_GRP_BITS)
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#define SPRGROUP_D (6<< MAX_SPRS_PER_GRP_BITS)
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#define SPRGROUP_PC (7<< MAX_SPRS_PER_GRP_BITS)
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#define SPRGROUP_PM (8<< MAX_SPRS_PER_GRP_BITS)
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#define SPRGROUP_PIC (9<< MAX_SPRS_PER_GRP_BITS)
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#define SPRGROUP_TT (10<< MAX_SPRS_PER_GRP_BITS)
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/* System control and status group */
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#define SPR_VR (SPRGROUP_SYS + 0)
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#define SPR_UPR (SPRGROUP_SYS + 1)
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#define SPR_CPUCFGR (SPRGROUP_SYS + 2)
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#define SPR_DMMUCFGR (SPRGROUP_SYS + 3)
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#define SPR_IMMUCFGR (SPRGROUP_SYS + 4)
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#define SPR_DCCFGR (SPRGROUP_SYS + 5)
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#define SPR_ICCFGR (SPRGROUP_SYS + 6)
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#define SPR_DCFGR (SPRGROUP_SYS + 7)
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#define SPR_PCCFGR (SPRGROUP_SYS + 8)
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#define SPR_NPC (SPRGROUP_SYS + 16) /* CZ 21/06/01 */
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#define SPR_SR (SPRGROUP_SYS + 17) /* CZ 21/06/01 */
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#define SPR_PPC (SPRGROUP_SYS + 18) /* CZ 21/06/01 */
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#define SPR_EPCR_BASE (SPRGROUP_SYS + 32) /* CZ 21/06/01 */
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#define SPR_EPCR_LAST (SPRGROUP_SYS + 47) /* CZ 21/06/01 */
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#define SPR_EEAR_BASE (SPRGROUP_SYS + 48)
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#define SPR_EEAR_LAST (SPRGROUP_SYS + 63)
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#define SPR_ESR_BASE (SPRGROUP_SYS + 64)
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#define SPR_ESR_LAST (SPRGROUP_SYS + 79)
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/* Data MMU group */
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#define SPR_DMMUCR (SPRGROUP_DMMU + 0)
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#define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x200)
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#define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x200)
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#define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x300 + (WAY) * 0x200)
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#define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x3ff + (WAY) * 0x200)
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/* Instruction MMU group */
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#define SPR_IMMUCR (SPRGROUP_IMMU + 0)
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#define SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x200)
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#define SPR_ITLBMR_LAST(WAY) (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x200)
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#define SPR_ITLBTR_BASE(WAY) (SPRGROUP_IMMU + 0x300 + (WAY) * 0x200)
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#define SPR_ITLBTR_LAST(WAY) (SPRGROUP_IMMU + 0x3ff + (WAY) * 0x200)
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/* Data cache group */
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#define SPR_DCCR (SPRGROUP_DC + 0)
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#define SPR_DCBPR (SPRGROUP_DC + 1)
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#define SPR_DCBFR (SPRGROUP_DC + 2)
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#define SPR_DCBIR (SPRGROUP_DC + 3)
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#define SPR_DCBWR (SPRGROUP_DC + 4)
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#define SPR_DCBLR (SPRGROUP_DC + 5)
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#define SPR_DCR_BASE(WAY) (SPRGROUP_DC + 0x200 + (WAY) * 0x200)
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#define SPR_DCR_LAST(WAY) (SPRGROUP_DC + 0x3ff + (WAY) * 0x200)
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/* Instruction cache group */
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#define SPR_ICCR (SPRGROUP_IC + 0)
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#define SPR_ICBPR (SPRGROUP_IC + 1)
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#define SPR_ICBIR (SPRGROUP_IC + 2)
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#define SPR_ICBLR (SPRGROUP_IC + 3)
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#define SPR_ICR_BASE(WAY) (SPRGROUP_IC + 0x200 + (WAY) * 0x200)
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#define SPR_ICR_LAST(WAY) (SPRGROUP_IC + 0x3ff + (WAY) * 0x200)
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/* MAC group */
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#define SPR_MACLO (SPRGROUP_MAC + 1)
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#define SPR_MACHI (SPRGROUP_MAC + 2)
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/* Debug group */
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#define SPR_DVR(N) (SPRGROUP_D + (N))
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#define SPR_DCR(N) (SPRGROUP_D + 8 + (N))
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#define SPR_DMR1 (SPRGROUP_D + 16)
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#define SPR_DMR2 (SPRGROUP_D + 17)
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#define SPR_DWCR0 (SPRGROUP_D + 18)
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#define SPR_DWCR1 (SPRGROUP_D + 19)
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#define SPR_DSR (SPRGROUP_D + 20)
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#define SPR_DRR (SPRGROUP_D + 21)
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/* Performance counters group */
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#define SPR_PCCR(N) (SPRGROUP_PC + (N))
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#define SPR_PCMR(N) (SPRGROUP_PC + 8 + (N))
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/* Power management group */
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#define SPR_PMR (SPRGROUP_PM + 0)
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/* PIC group */
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#define SPR_PICMR (SPRGROUP_PIC + 0)
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#define SPR_PICPR (SPRGROUP_PIC + 1)
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#define SPR_PICSR (SPRGROUP_PIC + 2)
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/* Tick Timer group */
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#define SPR_TTMR (SPRGROUP_TT + 0)
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#define SPR_TTCR (SPRGROUP_TT + 1)
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/*
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* Bit definitions for the Version Register
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*
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*/
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#define SPR_VR_VER 0xffff0000 /* Processor version */
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#define SPR_VR_REV 0x0000003f /* Processor revision */
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/*
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* Bit definitions for the Unit Present Register
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*
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*/
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#define SPR_UPR_UP 0x00000001 /* UPR present */
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#define SPR_UPR_DCP 0x00000002 /* Data cache present */
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#define SPR_UPR_ICP 0x00000004 /* Instruction cache present */
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#define SPR_UPR_DMP 0x00000008 /* Data MMU present */
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#define SPR_UPR_IMP 0x00000010 /* Instruction MMU present */
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#define SPR_UPR_OB32P 0x00000020 /* ORBIS32 present */
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#define SPR_UPR_OB64P 0x00000040 /* ORBIS64 present */
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#define SPR_UPR_OF32P 0x00000080 /* ORFPX32 present */
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#define SPR_UPR_OF64P 0x00000100 /* ORFPX64 present */
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#define SPR_UPR_OV32P 0x00000200 /* ORVDX32 present */
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#define SPR_UPR_OV64P 0x00000400 /* ORVDX64 present */
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#define SPR_UPR_DUP 0x00000800 /* Debug unit present */
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#define SPR_UPR_PCUP 0x00001000 /* Performance counters unit present */
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#define SPR_UPR_PMP 0x00002000 /* Power management present */
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#define SPR_UPR_PICP 0x00004000 /* PIC present */
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#define SPR_UPR_TTP 0x00008000 /* Tick timer present */
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#define SPR_UPR_SRP 0x00010000 /* Shadow registers present */
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#define SPR_UPR_RES 0x00fe0000 /* ORVDX32 present */
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#define SPR_UPR_CUST 0xff000000 /* Custom units */
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/*
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* Bit definitions for the Supervision Register
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*
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*/
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#define SPR_SR_CID 0xf0000000 /* Context ID */
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#define SPR_SR_FO 0x00008000 /* Fixed one */
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#define SPR_SR_EPH 0x00004000 /* Exception Prefixi High */
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#define SPR_SR_DSX 0x00002000 /* Delay Slot Exception */
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#define SPR_SR_OVE 0x00001000 /* Overflow flag Exception */
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#define SPR_SR_OV 0x00000800 /* Overflow flag */
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#define SPR_SR_CY 0x00000400 /* Carry flag */
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#define SPR_SR_F 0x00000200 /* Condition Flag */
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#define SPR_SR_CE 0x00000100 /* CID Enable */
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#define SPR_SR_LEE 0x00000080 /* Little Endian Enable */
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#define SPR_SR_IME 0x00000040 /* Instruction MMU Enable */
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#define SPR_SR_DME 0x00000020 /* Data MMU Enable */
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#define SPR_SR_ICE 0x00000010 /* Instruction Cache Enable */
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#define SPR_SR_DCE 0x00000008 /* Data Cache Enable */
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#define SPR_SR_IEE 0x00000004 /* Interrupt Exception Enable */
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#define SPR_SR_TEE 0x00000002 /* Tick timer Exception Enable */
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#define SPR_SR_SM 0x00000001 /* Supervisor Mode */
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/*
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* Bit definitions for the Data MMU Control Register
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*
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*/
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#define SPR_DMMUCR_P2S 0x0000003e /* Level 2 Page Size */
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#define SPR_DMMUCR_P1S 0x000007c0 /* Level 1 Page Size */
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#define SPR_DMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */
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#define SPR_DMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */
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/*
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* Bit definitions for the Instruction MMU Control Register
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*
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*/
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#define SPR_IMMUCR_P2S 0x0000003e /* Level 2 Page Size */
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#define SPR_IMMUCR_P1S 0x000007c0 /* Level 1 Page Size */
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#define SPR_IMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */
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#define SPR_IMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */
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/*
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* Bit definitions for the Data TLB Match Register
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*
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*/
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#define SPR_DTLBMR_V 0x00000001 /* Valid */
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#define SPR_DTLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */
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#define SPR_DTLBMR_CID 0x0000003c /* Context ID */
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#define SPR_DTLBMR_LRU 0x000000c0 /* Least Recently Used */
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#define SPR_DTLBMR_VPN 0xfffff000 /* Virtual Page Number */
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/*
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* Bit definitions for the Data TLB Translate Register
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*
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*/
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#define SPR_DTLBTR_CC 0x00000001 /* Cache Coherency */
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#define SPR_DTLBTR_CI 0x00000002 /* Cache Inhibit */
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#define SPR_DTLBTR_WBC 0x00000004 /* Write-Back Cache */
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#define SPR_DTLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */
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#define SPR_DTLBTR_A 0x00000010 /* Accessed */
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#define SPR_DTLBTR_D 0x00000020 /* Dirty */
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#define SPR_DTLBTR_URE 0x00000040 /* User Read Enable */
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#define SPR_DTLBTR_UWE 0x00000080 /* User Write Enable */
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#define SPR_DTLBTR_SRE 0x00000100 /* Supervisor Read Enable */
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#define SPR_DTLBTR_SWE 0x00000200 /* Supervisor Write Enable */
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#define SPR_DTLBTR_PPN 0xfffff000 /* Physical Page Number */
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/*
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* Bit definitions for the Instruction TLB Match Register
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*
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*/
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#define SPR_ITLBMR_V 0x00000001 /* Valid */
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#define SPR_ITLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */
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#define SPR_ITLBMR_CID 0x0000003c /* Context ID */
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#define SPR_ITLBMR_LRU 0x000000c0 /* Least Recently Used */
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#define SPR_ITLBMR_VPN 0xfffff000 /* Virtual Page Number */
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/*
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* Bit definitions for the Instruction TLB Translate Register
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*
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*/
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#define SPR_ITLBTR_CC 0x00000001 /* Cache Coherency */
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#define SPR_ITLBTR_CI 0x00000002 /* Cache Inhibit */
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#define SPR_ITLBTR_WBC 0x00000004 /* Write-Back Cache */
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#define SPR_ITLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */
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#define SPR_ITLBTR_A 0x00000010 /* Accessed */
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#define SPR_ITLBTR_D 0x00000020 /* Dirty */
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#define SPR_ITLBTR_SXE 0x00000040 /* User Read Enable */
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#define SPR_ITLBTR_UXE 0x00000080 /* User Write Enable */
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#define SPR_ITLBTR_PPN 0xfffff000 /* Physical Page Number */
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/*
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* Bit definitions for Data Cache Control register
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*
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*/
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#define SPR_DCCR_EW 0x000000ff /* Enable ways */
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/*
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* Bit definitions for Insn Cache Control register
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*
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*/
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#define SPR_ICCR_EW 0x000000ff /* Enable ways */
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/*
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* Bit definitions for Debug Control registers
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*
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*/
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#define SPR_DCR_DP 0x00000001 /* DVR/DCR present */
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#define SPR_DCR_CC 0x0000000e /* Compare condition */
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#define SPR_DCR_SC 0x00000010 /* Signed compare */
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#define SPR_DCR_CT 0x000000e0 /* Compare to */
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/* Bit results with SPR_DCR_CC mask */
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#define SPR_DCR_CC_MASKED 0x00000000
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#define SPR_DCR_CC_EQUAL 0x00000001
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#define SPR_DCR_CC_LESS 0x00000002
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#define SPR_DCR_CC_LESSE 0x00000003
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#define SPR_DCR_CC_GREAT 0x00000004
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#define SPR_DCR_CC_GREATE 0x00000005
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#define SPR_DCR_CC_NEQUAL 0x00000006
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/* Bit results with SPR_DCR_CT mask */
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#define SPR_DCR_CT_DISABLED 0x00000000
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#define SPR_DCR_CT_IFEA 0x00000020
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#define SPR_DCR_CT_LEA 0x00000040
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#define SPR_DCR_CT_SEA 0x00000060
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#define SPR_DCR_CT_LD 0x00000080
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#define SPR_DCR_CT_SD 0x000000a0
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#define SPR_DCR_CT_LSEA 0x000000c0
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/*
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* Bit definitions for Debug Mode 1 register
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*
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*/
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#define SPR_DMR1_CW0 0x00000003 /* Chain watchpoint 0 */
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#define SPR_DMR1_CW1 0x0000000c /* Chain watchpoint 1 */
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#define SPR_DMR1_CW2 0x00000030 /* Chain watchpoint 2 */
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#define SPR_DMR1_CW3 0x000000c0 /* Chain watchpoint 3 */
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#define SPR_DMR1_CW4 0x00000300 /* Chain watchpoint 4 */
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#define SPR_DMR1_CW5 0x00000c00 /* Chain watchpoint 5 */
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#define SPR_DMR1_CW6 0x00003000 /* Chain watchpoint 6 */
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#define SPR_DMR1_CW7 0x0000c000 /* Chain watchpoint 7 */
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#define SPR_DMR1_CW8 0x00030000 /* Chain watchpoint 8 */
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#define SPR_DMR1_CW9 0x000c0000 /* Chain watchpoint 9 */
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#define SPR_DMR1_CW10 0x00300000 /* Chain watchpoint 10 */
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#define SPR_DMR1_ST 0x00400000 /* Single-step trace*/
|
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#define SPR_DMR1_BT 0x00800000 /* Branch trace */
|
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#define SPR_DMR1_DXFW 0x01000000 /* Disable external force watchpoint */
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|
|
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/*
|
|
* Bit definitions for Debug Mode 2 register
|
|
*
|
|
*/
|
|
#define SPR_DMR2_WCE0 0x00000001 /* Watchpoint counter 0 enable */
|
|
#define SPR_DMR2_WCE1 0x00000002 /* Watchpoint counter 0 enable */
|
|
#define SPR_DMR2_AWTC 0x00001ffc /* Assign watchpoints to counters */
|
|
#define SPR_DMR2_WGB 0x00ffe000 /* Watchpoints generating breakpoint */
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|
|
|
/*
|
|
* Bit definitions for Debug watchpoint counter registers
|
|
*
|
|
*/
|
|
#define SPR_DWCR_COUNT 0x0000ffff /* Count */
|
|
#define SPR_DWCR_MATCH 0xffff0000 /* Match */
|
|
|
|
/*
|
|
* Bit definitions for Debug stop register
|
|
*
|
|
*/
|
|
#define SPR_DSR_RSTE 0x00000001 /* Reset exception */
|
|
#define SPR_DSR_BUSEE 0x00000002 /* Bus error exception */
|
|
#define SPR_DSR_DPFE 0x00000004 /* Data Page Fault exception */
|
|
#define SPR_DSR_IPFE 0x00000008 /* Insn Page Fault exception */
|
|
#define SPR_DSR_TTE 0x00000010 /* iTick Timer exception */
|
|
#define SPR_DSR_AE 0x00000020 /* Alignment exception */
|
|
#define SPR_DSR_IIE 0x00000040 /* Illegal Instruction exception */
|
|
#define SPR_DSR_IE 0x00000080 /* Interrupt exception */
|
|
#define SPR_DSR_DME 0x00000100 /* DTLB miss exception */
|
|
#define SPR_DSR_IME 0x00000200 /* ITLB miss exception */
|
|
#define SPR_DSR_RE 0x00000400 /* Range exception */
|
|
#define SPR_DSR_SCE 0x00000800 /* System call exception */
|
|
#define SPR_DSR_SSE 0x00001000 /* Single Step Exception */
|
|
#define SPR_DSR_TE 0x00002000 /* Trap exception */
|
|
|
|
/*
|
|
* Bit definitions for Debug reason register
|
|
*
|
|
*/
|
|
#define SPR_DRR_RSTE 0x00000001 /* Reset exception */
|
|
#define SPR_DRR_BUSEE 0x00000002 /* Bus error exception */
|
|
#define SPR_DRR_DPFE 0x00000004 /* Data Page Fault exception */
|
|
#define SPR_DRR_IPFE 0x00000008 /* Insn Page Fault exception */
|
|
#define SPR_DRR_TTE 0x00000010 /* Tick Timer exception */
|
|
#define SPR_DRR_AE 0x00000020 /* Alignment exception */
|
|
#define SPR_DRR_IIE 0x00000040 /* Illegal Instruction exception */
|
|
#define SPR_DRR_IE 0x00000080 /* Interrupt exception */
|
|
#define SPR_DRR_DME 0x00000100 /* DTLB miss exception */
|
|
#define SPR_DRR_IME 0x00000200 /* ITLB miss exception */
|
|
#define SPR_DRR_RE 0x00000400 /* Range exception */
|
|
#define SPR_DRR_SCE 0x00000800 /* System call exception */
|
|
#define SPR_DRR_TE 0x00001000 /* Trap exception */
|
|
|
|
/*
|
|
* Bit definitions for Performance counters mode registers
|
|
*
|
|
*/
|
|
#define SPR_PCMR_CP 0x00000001 /* Counter present */
|
|
#define SPR_PCMR_UMRA 0x00000002 /* User mode read access */
|
|
#define SPR_PCMR_CISM 0x00000004 /* Count in supervisor mode */
|
|
#define SPR_PCMR_CIUM 0x00000008 /* Count in user mode */
|
|
#define SPR_PCMR_LA 0x00000010 /* Load access event */
|
|
#define SPR_PCMR_SA 0x00000020 /* Store access event */
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#define SPR_PCMR_IF 0x00000040 /* Instruction fetch event*/
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#define SPR_PCMR_DCM 0x00000080 /* Data cache miss event */
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#define SPR_PCMR_ICM 0x00000100 /* Insn cache miss event */
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#define SPR_PCMR_IFS 0x00000200 /* Insn fetch stall event */
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#define SPR_PCMR_LSUS 0x00000400 /* LSU stall event */
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#define SPR_PCMR_BS 0x00000800 /* Branch stall event */
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#define SPR_PCMR_DTLBM 0x00001000 /* DTLB miss event */
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#define SPR_PCMR_ITLBM 0x00002000 /* ITLB miss event */
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#define SPR_PCMR_DDS 0x00004000 /* Data dependency stall event */
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#define SPR_PCMR_WPE 0x03ff8000 /* Watchpoint events */
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/*
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* Bit definitions for the Power management register
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*
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*/
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#define SPR_PMR_SDF 0x0000000f /* Slow down factor */
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#define SPR_PMR_DME 0x00000010 /* Doze mode enable */
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#define SPR_PMR_SME 0x00000020 /* Sleep mode enable */
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#define SPR_PMR_DCGE 0x00000040 /* Dynamic clock gating enable */
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#define SPR_PMR_SUME 0x00000080 /* Suspend mode enable */
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/*
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* Bit definitions for PICMR
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*
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*/
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#define SPR_PICMR_IUM 0xfffffffc /* Interrupt unmask */
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/*
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* Bit definitions for PICPR
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*
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*/
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#define SPR_PICPR_IPRIO 0xfffffffc /* Interrupt priority */
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/*
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* Bit definitions for PICSR
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*
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*/
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#define SPR_PICSR_IS 0xffffffff /* Interrupt status */
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/*
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* Bit definitions for Tick Timer Control Register
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*
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*/
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#define SPR_TTCR_PERIOD 0x0fffffff /* Time Period */
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#define SPR_TTMR_PERIOD SPR_TTCR_PERIOD
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#define SPR_TTMR_IP 0x10000000 /* Interrupt Pending */
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#define SPR_TTMR_IE 0x20000000 /* Interrupt Enable */
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#define SPR_TTMR_RT 0x40000000 /* Restart tick */
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#define SPR_TTMR_SR 0x80000000 /* Single run */
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#define SPR_TTMR_CR 0xc0000000 /* Continuous run */
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#define SPR_TTMR_M 0xc0000000 /* Tick mode */
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/*
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* l.nop constants
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*
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*/
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#define NOP_NOP 0x0000 /* Normal nop instruction */
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#define NOP_EXIT 0x0001 /* End of simulation */
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#define NOP_REPORT 0x0002 /* Simple report */
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#define NOP_PRINTF 0x0003 /* Simprintf instruction */
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#define NOP_REPORT_FIRST 0x0400 /* Report with number */
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#define NOP_REPORT_LAST 0x03ff /* Report with number */
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