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-- SDHC-SC-Core
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-- Secure Digital High Capacity Self Configuring Core
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--
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-- (C) Copyright 2010, Rainer Kastl
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- * Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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-- * Neither the name of the <organization> nor the
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-- names of its contributors may be used to endorse or promote products
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-- derived from this software without specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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-- File : SdWb-p.vhdl
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-- Owner : Rainer Kastl
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-- Description : SD Wishbone interface package
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-- Links :
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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package SdWb is
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-- data and address types
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subtype aData is std_ulogic_vector(31 downto 0);
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subtype aSdBlockAddr is std_ulogic_vector(31 downto 0);
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subtype aWbAddr is std_ulogic_vector(6 downto 4);
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-- operation type
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subtype aOperation is std_ulogic_vector(31 downto 0);
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-- different valid operation values
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constant cOperationRead : aOperation := X"00000001";
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constant cOperationWrite : aOperation := X"00000010";
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-- addresses for register banks in SdWbSlave
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constant cOperationAddr : aWbAddr := "000";
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constant cStartAddrAddr : aWbAddr := "001";
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constant cEndAddrAddr : aWbAddr := "010";
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constant cReadDataAddr : aWbAddr := "011";
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constant cWriteDataAddr : aWbAddr := "100";
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-- configuration of the next operation
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type aOperationBlock is record
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StartAddr : aSdBlockAddr; -- start block address for SD card the next operation
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EndAddr : aSdBlockAddr; -- last block address
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Operation : aOperation; -- operation to execute (Read, write, etc.)
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end record aOperationBlock;
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constant cDefaultOperationBlock : aOperationBlock := (
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StartAddr => (others => '0'),
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EndAddr => (others => '0'),
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Operation => (others => '0'));
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-- ports
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type aSdWbSlaveToSdController is record
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AckOperation : std_ulogic; -- every edge signals that the OperationBlock is valid
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OperationBlock : aOperationBlock;
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WriteData : aData; -- data to write to the card (32 bit blocks)
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end record aSdWbSlaveToSdController;
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type aSdControllerToSdWbSlave is record
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ReqOperation : std_ulogic; -- Request a new OperationBlock
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ReadData : aData;
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end record aSdControllerToSdWbSlave;
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type aSdWbSlaveDataOutput is record
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Dat : aData;
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end record aSdWbSlaveDataOutput;
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type aSdWbSlaveDataInput is record
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Sel : std_ulogic_vector(0 downto 0);
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Adr : aWbAddr;
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Dat : aData;
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end record aSdWbSlaveDataInput;
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-- default port values
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constant cDefaultSdWbSlaveToSdController : aSdWbSlaveToSdController := (
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OperationBlock => cDefaultOperationBlock,
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WriteData => (others => '0'),
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AckOperation => '0');
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constant cDefaultSdControllerToSdWbSlave : aSdControllerToSdWbSlave := (
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ReqOperation => '0',
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ReadData => (others => '0'));
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-- to fifo
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type aoWriteFifo is record
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data : aData;
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wrreq : std_ulogic; -- write request
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end record aoWriteFifo;
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constant cDefaultoWriteFifo : aoWriteFifo := (
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data => (others => '0'),
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wrreq => '0');
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type aiWriteFifo is record
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wrfull : std_ulogic; -- write full
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end record aiWriteFifo;
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type aoReadFifo is record
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rdreq : std_ulogic; -- read request
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end record aoReadFifo;
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constant cDefaultoReadFifo : aoReadFifo := (rdreq => '0');
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type aiReadFifo is record
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q : std_ulogic_vector(31 downto 0); -- read data (1 cycle after rdreq)
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rdempty : std_ulogic; -- no data available
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end record aiReadFifo;
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end package SdWb;
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