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-- SDHC-SC-Core
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-- Secure Digital High Capacity Self Configuring Core
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--
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-- (C) Copyright 2010, Rainer Kastl
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- * Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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-- * Neither the name of the <organization> nor the
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-- names of its contributors may be used to endorse or promote products
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-- derived from this software without specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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-- File : TbdSd-Rtl-ea.vhdl
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-- Owner : Rainer Kastl
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-- Description : Testbed for SDHC-SC-Core for SbX
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-- Links :
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.Global.all;
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use work.Ics307Values.all;
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use work.Rs232.all;
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use work.Sd.all;
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entity TbdSd is
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generic (
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gClkFrequency : natural := 100E6
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);
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port (
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iClk : std_ulogic;
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inResetAsync : std_ulogic;
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-- SD Card
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ioCmd : inout std_logic; -- Cmd line to and from card
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oSclk : out std_ulogic;
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ioData : inout std_logic_vector(3 downto 0);
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-- Ics307
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oIcs307Sclk : out std_ulogic;
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oIcs307Data : out std_ulogic;
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oIcs307Strobe : out std_ulogic;
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-- Rs232
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oTx : out std_ulogic;
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-- LEDs
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oLedBank : out aLedBank;
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oDigitAdr : out std_ulogic_vector(1 to 3)); -- A,B,C
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end entity TbdSd;
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architecture Rtl of TbdSd is
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signal RstSync : std_ulogic_vector(1 downto 0);
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signal iCyc : std_ulogic := '0';
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signal iLock : std_ulogic := '0';
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signal iStb : std_ulogic := '0';
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signal iWe : std_ulogic := '0';
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signal iCti : std_ulogic_vector(2 downto 0) := (others => '0');
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signal iBte : std_ulogic_vector(1 downto 0) := (others => '0');
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signal iSel : std_ulogic_vector(0 downto 0) := (others => '0');
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signal iAdr : std_ulogic_vector(6 downto 4) := (others => '0');
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signal iDat : std_ulogic_vector(31 downto 0) := (others => '0');
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signal oDat : std_ulogic_vector(31 downto 0);
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signal oAck : std_ulogic;
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signal oErr : std_ulogic;
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signal oRty : std_ulogic;
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signal LedBank : std_ulogic_vector(7 downto 0);
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signal LedBank2 : std_ulogic_vector(7 downto 0);
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begin
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oLedBank <= LedBank;
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Reg : process (iClk) is
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begin
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if (rising_edge(iClk)) then
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RstSync(0) <= inResetAsync;
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RstSync(1) <= not RstSync(0);
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end if;
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end process Reg;
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oDigitAdr <= "101"; -- DIGIT_6
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oTx <= '1';
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Gen100MHz: if gClkFrequency = 100E6 generate
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-- Configure clock to 100MHz
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Ics307Configurator_inst : entity work.Ics307Configurator(Rtl)
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generic map(
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gCrystalLoadCapacitance_C => cCrystalLoadCapacitance_C_100MHz,
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gReferenceDivider_RDW => cReferenceDivider_RDW_100MHz,
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gVcoDividerWord_VDW => cVcoDividerWord_VDW_100MHz,
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gOutputDivide_S => cOutputDivide_S_100MHz,
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gClkFunctionSelect_R => cClkFunctionSelect_R_100MHz,
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gOutputDutyCycleVoltage_TTL => cOutputDutyCycleVoltage_TTL_100MHz
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)
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port map(
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iClk => iClk,
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inResetAsync => inResetAsync,
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oSclk => oIcs307Sclk,
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oData => oIcs307Data,
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oStrobe => oIcs307Strobe
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);
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end generate;
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SDTop_inst : entity work.SdTop(Rtl)
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generic map (
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gClkFrequency => gClkFrequency,
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gHighSpeedMode => true
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)
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port map (
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iWbClk => iClk,
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iWbRstSync => RstSync(1),
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iCyc => iCyc,
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iLock => iLock,
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iStb => iStb,
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iWe => iWe,
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iCti => iCti,
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iBte => iBte,
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iSel => iSel,
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iAdr => iAdr,
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iDat => iDat,
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oDat => oDat,
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oAck => oAck,
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oErr => oErr,
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oRty => oRty,
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iSdClk => iClk,
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iSdRstSync => RstSync(1),
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ioCmd => ioCmd,
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oSclk => oSclk,
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ioData => ioData,
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oLedBank => LedBank
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);
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TestWbMaster_inst : entity work.TestWbMaster
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port map (
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CLK_I => iClk,
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RST_I => RstSync(1),
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ERR_I => oErr,
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RTY_I => oRty,
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ACK_I => oAck,
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DAT_I => oDat,
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CYC_O => iCyc,
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STB_O => iStb,
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WE_O => iWe,
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CTI_O => iCti,
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BTE_O => iBte,
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ADR_O => iAdr,
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DAT_O => iDat,
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SEL_O => iSel,
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LEDBANK_O => LedBank2
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);
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end architecture Rtl;
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