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-- SDHC-SC-Core
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-- Secure Digital High Capacity Self Configuring Core
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--
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-- (C) Copyright 2010, Rainer Kastl
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- * Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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-- * Neither the name of the <organization> nor the
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-- names of its contributors may be used to endorse or promote products
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-- derived from this software without specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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-- File : EdgeDetector-Rtl-a.vhdl
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-- Owner : Rainer Kastl
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-- Description :
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-- Links : See EDS at FH Hagenberg
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.global.all;
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architecture Rtl of EdgeDetector is
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signal nQ, detection, Q : std_ulogic;
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begin -- Rtl
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FF1 : process (iClk, inResetAsync) is
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begin -- process FF1
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if inResetAsync = cnActivated then
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nQ <= cnInactivated;
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elsif iClk'event and iClk = cActivated then -- rising clock edge
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if (iRstSync = cActivated) then
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nQ <= cnInactivated;
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else
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nQ <= not iLine;
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end if;
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end if;
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end process FF1;
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Gen : if gOutputRegistered = true generate -- only generate 2nd FF, if
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-- condition is true
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FF2 : process (iClk, iClearEdgeDetected, inResetAsync) is
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begin -- process FF2
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if inResetAsync = cnActivated then
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Q <= cInactivated;
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elsif iClk'event and iClk = cActivated then -- rising clock edge
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if (iRstSync = cActivated) then
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Q <= cInactivated;
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else
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if iClearEdgeDetected = cActivated then
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Q <= cInactivated;
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elsif detection = cActivated then
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Q <= cActivated;
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end if;
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end if;
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end if;
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end process FF2;
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oEdgeDetected <= Q;
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end generate;
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Gen2 : if gOutputRegistered = false generate
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-- else detection is Output
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oEdgeDetected <= detection;
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end generate;
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Detect : process (nQ, iLine) is
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begin
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case gEdgeDetection is
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when cDetectRisingEdge => detection <= (iLine and nQ);
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when cDetectFallingEdge => detection <= (iLine nor nQ);
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when cDetectAnyEdge => detection <= (iLine and nQ) or (iLine nor nQ);
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when others => null;
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end case;
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end process Detect;
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end Rtl;
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