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-- SDHC-SC-Core
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-- Secure Digital High Capacity Self Configuring Core
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--
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-- (C) Copyright 2010, Rainer Kastl
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- * Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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-- * Neither the name of the <organization> nor the
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-- names of its contributors may be used to endorse or promote products
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-- derived from this software without specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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-- File : tbStrobeGen-Bhv-ea.vhdl
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-- Owner : Rainer Kastl
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-- Description :
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-- Links : See EDS at FH Hagenberg
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use work.Global.all;
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entity tbStrobeGen is
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end entity tbStrobeGen;
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architecture Bhv of tbStrobeGen is
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-- component generics
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constant cClkFrequency : natural := 25E6;
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constant cInResetDuration : time := 140 ns;
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constant cStrobeCycleTime : time := 1 us;
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-- component ports
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signal Clk : std_ulogic := cInactivated;
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signal nResetAsync : std_ulogic := cnInactivated;
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signal Strobe : std_ulogic;
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begin -- architecture Bhv
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-- component instantiation
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DUT : entity work.StrobeGen
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generic map (
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gClkFrequency => cClkFrequency,
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gStrobeCycleTime => cStrobeCycleTime)
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port map (
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iClk => Clk,
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inResetAsync => nResetAsync,
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oStrobe => Strobe);
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Clk <= not Clk after (1 sec / cClkFrequency) / 2;
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nResetAsync <= cnInactivated after 0 ns,
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cnActivated after cInResetDuration,
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cnInactivated after 2*cInResetDuration;
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-- Process to measure the frequency of the strobe signal and the
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-- active strobe time.
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DetermineStrobeFreq : process
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variable vHighLevel : boolean := false;
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variable vTimestamp : time := 0 sec;
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begin
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wait until (Strobe'event);
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if Strobe = '1' then
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vHighLevel := true;
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if now > vTimestamp then
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assert false
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report "Frequency Value (Strobe) = " &
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integer'image((1 sec / (now-vTimestamp))) &
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"Hz; Period (Strobe) = " &
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time'image(now-vTimestamp)
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severity note;
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end if;
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vTimestamp := now;
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elsif vHighLevel and Strobe = '0' and
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((now-vTimestamp)<(1 sec / cClkFrequency)) then
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assert false
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report "Strobe Active Time: " & time'image(now-vTimestamp) & "; " &
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"Clock Cycle time: " & time'image((1 sec / cClkFrequency))
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severity error;
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end if;
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end process DetermineStrobeFreq;
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-- Simulation is finished after predefined time.
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SimulationFinished : process
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begin
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wait for (10*cStrobeCycleTime);
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assert false
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report "This is not a failure: Simulation finished !!!"
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severity failure;
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end process SimulationFinished;
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end architecture Bhv;
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