| Line 46... |
Line 46... |
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`include "sdrc.def"
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`include "sdrc.def"
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module sdrc_bank_ctl (clk,
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module sdrc_bank_ctl (clk,
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reset_n,
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reset_n,
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a2b_req_depth, // Number of requests we can buffer
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/* Req from req_gen */
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/* Req from req_gen */
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r2b_req, // request
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r2b_req, // request
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r2b_req_id, // ID
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r2b_req_id, // ID
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r2b_start, // First chunk of burst
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r2b_start, // First chunk of burst
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r2b_last, // Last chunk of burst
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r2b_last, // Last chunk of burst
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r2b_wrap,
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r2b_wrap,
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r2b_ba, // bank address
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r2b_raddr, // row address
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r2b_raddr, // row address
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r2b_caddr, // col address
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r2b_caddr, // col address
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r2b_len, // length
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r2b_len, // length
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r2b_write, // write request
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r2b_write, // write request
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b2r_arb_ok, // OK to arbitrate for next xfr
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b2r_ack,
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b2r_ack,
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sdr_dma_last,
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/* Transfer request to xfr_ctl */
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/* Transfer request to xfr_ctl */
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b2x_idle, // All banks are idle
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b2x_req, // Request to xfr_ctl
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b2x_req, // Request to xfr_ctl
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b2x_start, // first chunk of transfer
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b2x_start, // first chunk of transfer
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b2x_last, // last chunk of transfer
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b2x_last, // last chunk of transfer
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b2x_wrap,
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b2x_wrap,
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b2x_id, // Transfer ID
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b2x_id, // Transfer ID
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b2x_ba, // bank address
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b2x_addr, // row/col address
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b2x_addr, // row/col address
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b2x_len, // transfer length
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b2x_len, // transfer length
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b2x_cmd, // transfer command
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b2x_cmd, // transfer command
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x2b_ack, // command accepted
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x2b_ack, // command accepted
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/* Status to/from xfr_ctl */
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/* Status to/from xfr_ctl */
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tras_ok, // TRAS OK for this bank
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b2x_tras_ok, // TRAS OK for all banks
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xfr_ok,
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x2b_refresh, // We did a refresh
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x2b_refresh, // We did a refresh
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x2b_pre_ok, // OK to do a precharge (per bank)
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x2b_pre_ok, // OK to do a precharge (per bank)
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x2b_act_ok, // OK to do an activate
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x2b_act_ok, // OK to do an activate
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x2b_rdok, // OK to do a read
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x2b_rdok, // OK to do a read
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x2b_wrok, // OK to do a write
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x2b_wrok, // OK to do a write
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/* current xfr row address of the bank */
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/* xfr msb address */
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bank_row,
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sdr_dev_config,
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xfr_bank_sel,
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xfr_addr_msb,
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sdr_req_norm_dma_last,
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/* SDRAM Timing */
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/* SDRAM Timing */
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tras_delay, // Active to precharge delay
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tras_delay, // Active to precharge delay
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trp_delay, // Precharge to active delay
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trp_delay, // Precharge to active delay
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trcd_delay); // Active to R/W delay
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trcd_delay); // Active to R/W delay
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| Line 97... |
Line 103... |
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parameter SDR_DW = 16; // SDR Data Width
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parameter SDR_DW = 16; // SDR Data Width
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parameter SDR_BW = 2; // SDR Byte Width
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parameter SDR_BW = 2; // SDR Byte Width
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input clk, reset_n;
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input clk, reset_n;
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input [1:0] a2b_req_depth;
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/* Req from bank_ctl */
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/* Req from bank_ctl */
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input r2b_req, r2b_start, r2b_last,
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input r2b_req, r2b_start, r2b_last,
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r2b_write, r2b_wrap;
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r2b_write, r2b_wrap;
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input [`SDR_REQ_ID_W-1:0] r2b_req_id;
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input [`SDR_REQ_ID_W-1:0] r2b_req_id;
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input [1:0] r2b_ba;
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input [11:0] r2b_raddr;
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input [11:0] r2b_raddr;
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input [11:0] r2b_caddr;
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input [11:0] r2b_caddr;
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input [APP_RW-1:0] r2b_len;
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input [APP_RW-1:0] r2b_len;
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output b2r_ack;
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output b2r_arb_ok, b2r_ack;
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input sdr_dma_last;
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input sdr_req_norm_dma_last;
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/* Req to xfr_ctl */
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/* Req to xfr_ctl */
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output b2x_req, b2x_start, b2x_last,
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output b2x_idle, b2x_req, b2x_start, b2x_last,
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tras_ok, b2x_wrap;
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b2x_tras_ok, b2x_wrap;
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output [`SDR_REQ_ID_W-1:0] b2x_id;
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output [`SDR_REQ_ID_W-1:0] b2x_id;
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output [1:0] b2x_ba;
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output [11:0] b2x_addr;
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output [11:0] b2x_addr;
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output [APP_RW-1:0] b2x_len;
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output [APP_RW-1:0] b2x_len;
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output [1:0] b2x_cmd;
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output [1:0] b2x_cmd;
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input x2b_ack;
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input x2b_ack;
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/* Status from xfr_ctl */
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/* Status from xfr_ctl */
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input [3:0] x2b_pre_ok;
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input x2b_refresh, x2b_act_ok, x2b_rdok,
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input x2b_refresh, x2b_act_ok, x2b_rdok,
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x2b_wrok, x2b_pre_ok, xfr_ok;
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x2b_wrok;
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input [3:0] tras_delay, trp_delay, trcd_delay;
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input [3:0] tras_delay, trp_delay, trcd_delay;
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output [11:0] bank_row;
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input [1:0] sdr_dev_config;
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input [1:0] xfr_bank_sel;
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output [13:0] xfr_addr_msb;
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/****************************************************************************/
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/****************************************************************************/
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// Internal Nets
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// Internal Nets
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`define BANK_IDLE 3'b000
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wire [3:0] r2i_req, i2r_ack, i2x_req,
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`define BANK_PRE 3'b001
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i2x_start, i2x_last, i2x_wrap, tras_ok;
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`define BANK_ACT 3'b010
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wire [11:0] i2x_addr0, i2x_addr1, i2x_addr2, i2x_addr3;
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`define BANK_XFR 3'b011
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wire [APP_RW-1:0] i2x_len0, i2x_len1, i2x_len2, i2x_len3;
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`define BANK_DMA_LAST_PRE 3'b100
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wire [1:0] i2x_cmd0, i2x_cmd1, i2x_cmd2, i2x_cmd3;
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wire [`SDR_REQ_ID_W-1:0] i2x_id0, i2x_id1, i2x_id2, i2x_id3;
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reg [2:0] bank_st, next_bank_st;
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wire b2x_start, b2x_last;
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reg b2x_req;
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reg l_start, l_last;
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wire b2x_idle, b2x_start, b2x_last, b2x_wrap;
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reg b2x_req, b2r_ack;
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wire [`SDR_REQ_ID_W-1:0] b2x_id;
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wire [`SDR_REQ_ID_W-1:0] b2x_id;
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reg [`SDR_REQ_ID_W-1:0] l_id;
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wire [11:0] b2x_addr;
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reg [11:0] b2x_addr;
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reg [APP_RW-1:0] l_len;
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wire [APP_RW-1:0] b2x_len;
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wire [APP_RW-1:0] b2x_len;
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reg [1:0] b2x_cmd;
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wire [1:0] b2x_cmd;
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reg bank_valid;
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wire [3:0] x2i_ack;
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reg [11:0] bank_row;
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reg [1:0] b2x_ba;
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reg [3:0] tras_cntr, timer0;
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reg l_wrap, l_write;
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reg [`SDR_REQ_ID_W-1:0] curr_id;
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wire b2x_wrap;
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reg [11:0] l_raddr;
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wire [1:0] xfr_ba;
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reg [11:0] l_caddr;
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wire xfr_ba_last;
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reg l_sdr_dma_last;
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wire [3:0] xfr_ok;
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reg bank_prech_page_closed;
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// This 8 bit register stores the bank addresses for upto 4 requests.
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reg [7:0] rank_ba;
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reg [3:0] rank_ba_last;
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// This 3 bit counter counts the number of requests we have
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// buffered so far, legal values are 0, 1, 2, 3, or 4.
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reg [2:0] rank_cnt;
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wire [3:0] rank_req, rank_wr_sel;
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wire rank_fifo_wr, rank_fifo_rd;
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wire rank_fifo_full, rank_fifo_mt;
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wire [11:0] bank0_row, bank1_row, bank2_row, bank3_row;
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assign b2x_tras_ok = &tras_ok;
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// Distribute the request from req_gen
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assign r2i_req[0] = (r2b_ba == 2'b00) ? r2b_req & ~rank_fifo_full : 1'b0;
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assign r2i_req[1] = (r2b_ba == 2'b01) ? r2b_req & ~rank_fifo_full : 1'b0;
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assign r2i_req[2] = (r2b_ba == 2'b10) ? r2b_req & ~rank_fifo_full : 1'b0;
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assign r2i_req[3] = (r2b_ba == 2'b11) ? r2b_req & ~rank_fifo_full : 1'b0;
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assign b2r_ack = (r2b_ba == 2'b00) ? i2r_ack[0] :
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(r2b_ba == 2'b01) ? i2r_ack[1] :
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(r2b_ba == 2'b10) ? i2r_ack[2] :
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(r2b_ba == 2'b11) ? i2r_ack[3] : 1'b0;
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assign b2r_arb_ok = ~rank_fifo_full;
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// Put the requests from the 4 bank_fsms into a 4 deep shift
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// register file. The earliest request is prioritized over the
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// later requests. Also the number of requests we are allowed to
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// buffer is limited by a 2 bit external input
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// Mux the req/cmd to xfr_ctl. Allow RD/WR commands from the request in
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// rank0, allow only PR/ACT commands from the requests in other ranks
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// If the rank_fifo is empty, send the request from the bank addressed by
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// r2b_ba
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assign xfr_ba = (rank_fifo_mt) ? r2b_ba : rank_ba[1:0];
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assign xfr_ba_last = (rank_fifo_mt) ? sdr_req_norm_dma_last : rank_ba_last[0];
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assign rank_req[0] = i2x_req[xfr_ba]; // each rank generates requests
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assign rank_req[1] = (rank_cnt < 3'h2) ? 1'b0 :
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(rank_ba[3:2] == 2'b00) ? i2x_req[0] & ~i2x_cmd0[1] :
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(rank_ba[3:2] == 2'b01) ? i2x_req[1] & ~i2x_cmd1[1] :
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(rank_ba[3:2] == 2'b10) ? i2x_req[2] & ~i2x_cmd2[1] :
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i2x_req[3] & ~i2x_cmd3[1];
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assign rank_req[2] = (rank_cnt < 3'h3) ? 1'b0 :
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(rank_ba[5:4] == 2'b00) ? i2x_req[0] & ~i2x_cmd0[1] :
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(rank_ba[5:4] == 2'b01) ? i2x_req[1] & ~i2x_cmd1[1] :
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(rank_ba[5:4] == 2'b10) ? i2x_req[2] & ~i2x_cmd2[1] :
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i2x_req[3] & ~i2x_cmd3[1];
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assign rank_req[3] = (rank_cnt < 3'h4) ? 1'b0 :
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(rank_ba[7:6] == 2'b00) ? i2x_req[0] & ~i2x_cmd0[1] :
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(rank_ba[7:6] == 2'b01) ? i2x_req[1] & ~i2x_cmd1[1] :
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(rank_ba[7:6] == 2'b10) ? i2x_req[2] & ~i2x_cmd2[1] :
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i2x_req[3] & ~i2x_cmd3[1];
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always @ (rank_req or rank_ba or xfr_ba or xfr_ba_last) begin
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if (rank_req[0]) begin
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b2x_req = 1'b1;
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b2x_ba = xfr_ba;
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end // if (rank_req[0])
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else if (rank_req[1]) begin
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b2x_req = 1'b1;
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b2x_ba = rank_ba[3:2];
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end // if (rank_req[1])
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else if (rank_req[2]) begin
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b2x_req = 1'b1;
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b2x_ba = rank_ba[5:4];
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end // if (rank_req[2])
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else if (rank_req[3]) begin
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b2x_req = 1'b1;
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b2x_ba = rank_ba[7:6];
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end // if (rank_req[3])
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else begin
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b2x_req = 1'b0;
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b2x_ba = 2'b00;
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end // else: !if(rank_req[3])
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end // always @ (rank_req or rank_fifo_mt or r2b_ba or rank_ba)
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assign b2x_idle = rank_fifo_mt;
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assign b2x_start = i2x_start[b2x_ba];
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assign b2x_last = i2x_last[b2x_ba];
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assign b2x_wrap = i2x_wrap[b2x_ba];
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assign b2x_addr = (b2x_ba == 2'b11) ? i2x_addr3 :
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(b2x_ba == 2'b10) ? i2x_addr2 :
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(b2x_ba == 2'b01) ? i2x_addr1 : i2x_addr0;
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assign b2x_len = (b2x_ba == 2'b11) ? i2x_len3 :
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(b2x_ba == 2'b10) ? i2x_len2 :
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(b2x_ba == 2'b01) ? i2x_len1 : i2x_len0;
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assign b2x_cmd = (b2x_ba == 2'b11) ? i2x_cmd3 :
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(b2x_ba == 2'b10) ? i2x_cmd2 :
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(b2x_ba == 2'b01) ? i2x_cmd1 : i2x_cmd0;
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assign b2x_id = (b2x_ba == 2'b11) ? i2x_id3 :
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(b2x_ba == 2'b10) ? i2x_id2 :
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(b2x_ba == 2'b01) ? i2x_id1 : i2x_id0;
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assign x2i_ack[0] = (b2x_ba == 2'b00) ? x2b_ack : 1'b0;
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assign x2i_ack[1] = (b2x_ba == 2'b01) ? x2b_ack : 1'b0;
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assign x2i_ack[2] = (b2x_ba == 2'b10) ? x2b_ack : 1'b0;
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assign x2i_ack[3] = (b2x_ba == 2'b11) ? x2b_ack : 1'b0;
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// Rank Fifo
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// On a write write to selected rank and increment rank_cnt
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// On a read shift rank_ba right 2 bits and decrement rank_cnt
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assign rank_fifo_wr = b2r_ack;
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assign rank_fifo_rd = b2x_req & b2x_cmd[1] & x2b_ack;
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assign rank_wr_sel[0] = (rank_cnt == 3'h0) ? rank_fifo_wr :
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(rank_cnt == 3'h1) ? rank_fifo_wr & rank_fifo_rd :
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1'b0;
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assign rank_wr_sel[1] = (rank_cnt == 3'h1) ? rank_fifo_wr & ~rank_fifo_rd :
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(rank_cnt == 3'h2) ? rank_fifo_wr & rank_fifo_rd :
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1'b0;
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assign rank_wr_sel[2] = (rank_cnt == 3'h2) ? rank_fifo_wr & ~rank_fifo_rd :
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(rank_cnt == 3'h3) ? rank_fifo_wr & rank_fifo_rd :
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1'b0;
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assign rank_wr_sel[3] = (rank_cnt == 3'h3) ? rank_fifo_wr & ~rank_fifo_rd :
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(rank_cnt == 3'h4) ? rank_fifo_wr & rank_fifo_rd :
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1'b0;
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assign rank_fifo_mt = (rank_cnt == 3'b0) ? 1'b1 : 1'b0;
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wire tras_ok_internal, tras_ok, activate_bank;
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assign rank_fifo_full = (rank_cnt[2]) ? 1'b1 :
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(rank_cnt[1:0] == a2b_req_depth) ? 1'b1 : 1'b0;
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wire page_hit, timer0_tc, ld_trp, ld_trcd;
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// FIFO Check
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// synopsys translate_off
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always @ (posedge clk) begin
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if (~rank_fifo_wr & rank_fifo_rd && rank_cnt == 3'h0) begin
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$display ("%t: %m: ERROR!!! Read from empty Fifo", $time);
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$stop;
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end // if (rank_fifo_rd && rank_cnt == 3'h0)
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if (rank_fifo_wr && ~rank_fifo_rd && rank_cnt == 3'h4) begin
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$display ("%t: %m: ERROR!!! Write to full Fifo", $time);
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$stop;
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end // if (rank_fifo_wr && ~rank_fifo_rd && rank_cnt == 3'h4)
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end // always @ (posedge clk)
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// synopsys translate_on
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always @ (posedge clk)
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always @ (posedge clk)
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if (~reset_n) begin
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if (~reset_n) begin
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bank_valid <= 1'b0;
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rank_cnt <= 3'b0;
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tras_cntr <= 4'b0;
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rank_ba <= 8'b0;
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timer0 <= 4'b0;
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rank_ba_last <= 4'b0;
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bank_st <= `BANK_IDLE;
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end // if (~reset_n)
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end // if (~reset_n)
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else begin
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else begin
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bank_valid <= (x2b_refresh || bank_prech_page_closed) ? 1'b0 : // force the bank status to be invalid
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rank_cnt <= (rank_fifo_wr & ~rank_fifo_rd) ? rank_cnt + 3'b1 :
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// bank_valid <= (x2b_refresh) ? 1'b0 :
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(~rank_fifo_wr & rank_fifo_rd) ? rank_cnt - 3'b1 :
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(activate_bank) ? 1'b1 : bank_valid;
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rank_cnt;
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tras_cntr <= (activate_bank) ? tras_delay :
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rank_ba[1:0] <= (rank_wr_sel[0]) ? r2b_ba :
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(~tras_ok_internal) ? tras_cntr - 4'b1 : 4'b0;
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(rank_fifo_rd) ? rank_ba[3:2] : rank_ba[1:0];
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timer0 <= (ld_trp) ? trp_delay :
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(ld_trcd) ? trcd_delay :
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(~timer0_tc) ? timer0 - 4'b1 : timer0;
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bank_st <= next_bank_st;
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rank_ba[3:2] <= (rank_wr_sel[1]) ? r2b_ba :
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(rank_fifo_rd) ? rank_ba[5:4] : rank_ba[3:2];
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rank_ba[5:4] <= (rank_wr_sel[2]) ? r2b_ba :
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(rank_fifo_rd) ? rank_ba[7:6] : rank_ba[5:4];
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rank_ba[7:6] <= (rank_wr_sel[3]) ? r2b_ba :
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(rank_fifo_rd) ? 2'b00 : rank_ba[7:6];
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rank_ba_last[0] <= (rank_wr_sel[0]) ? sdr_req_norm_dma_last :
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(rank_fifo_rd) ? rank_ba_last[1] : rank_ba_last[0];
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rank_ba_last[1] <= (rank_wr_sel[1]) ? sdr_req_norm_dma_last :
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(rank_fifo_rd) ? rank_ba_last[2] : rank_ba_last[1];
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rank_ba_last[2] <= (rank_wr_sel[2]) ? sdr_req_norm_dma_last :
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(rank_fifo_rd) ? rank_ba_last[3] : rank_ba_last[2];
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|
|
rank_ba_last[3] <= (rank_wr_sel[3]) ? sdr_req_norm_dma_last :
|
|
(rank_fifo_rd) ? 1'b0 : rank_ba_last[3];
|
|
|
end // else: !if(~reset_n)
|
end // else: !if(~reset_n)
|
|
|
always @ (posedge clk) begin
|
assign xfr_ok[0] = (xfr_ba == 2'b00) ? 1'b1 : 1'b0;
|
|
assign xfr_ok[1] = (xfr_ba == 2'b01) ? 1'b1 : 1'b0;
|
|
assign xfr_ok[2] = (xfr_ba == 2'b10) ? 1'b1 : 1'b0;
|
|
assign xfr_ok[3] = (xfr_ba == 2'b11) ? 1'b1 : 1'b0;
|
|
|
bank_row <= (activate_bank) ? b2x_addr : bank_row;
|
/****************************************************************************/
|
|
// Instantiate Bank Ctl FSM 0
|
|
|
if (~reset_n) begin
|
sdrc_bank_fsm bank0_fsm (.clk (clk),
|
l_start <= 1'b0;
|
.reset_n (reset_n),
|
l_last <= 1'b0;
|
|
l_id <= 1'b0;
|
|
l_len <= 1'b0;
|
|
l_wrap <= 1'b0;
|
|
l_write <= 1'b0;
|
|
l_raddr <= 1'b0;
|
|
l_caddr <= 1'b0;
|
|
l_sdr_dma_last <= 1'b0;
|
|
end
|
|
else begin
|
|
if (b2r_ack) begin
|
|
l_start <= r2b_start;
|
|
l_last <= r2b_last;
|
|
l_id <= r2b_req_id;
|
|
l_len <= r2b_len;
|
|
l_wrap <= r2b_wrap;
|
|
l_write <= r2b_write;
|
|
l_raddr <= r2b_raddr;
|
|
l_caddr <= r2b_caddr;
|
|
l_sdr_dma_last <= sdr_dma_last;
|
|
end // if (b2r_ack)
|
|
end
|
|
|
|
end // always @ (posedge clk)
|
/* Req from req_gen */
|
|
.r2b_req (r2i_req[0]),
|
|
.r2b_req_id (r2b_req_id),
|
|
.r2b_start (r2b_start),
|
|
.r2b_last (r2b_last),
|
|
.r2b_wrap (r2b_wrap),
|
|
.r2b_raddr (r2b_raddr),
|
|
.r2b_caddr (r2b_caddr),
|
|
.r2b_len (r2b_len),
|
|
.r2b_write (r2b_write),
|
|
.b2r_ack (i2r_ack[0]),
|
|
.sdr_dma_last(rank_ba_last[0]),
|
|
|
assign tras_ok_internal = ~|tras_cntr;
|
/* Transfer request to xfr_ctl */
|
assign tras_ok = tras_ok_internal;
|
.b2x_req (i2x_req[0]),
|
|
.b2x_start (i2x_start[0]),
|
|
.b2x_last (i2x_last[0]),
|
|
.b2x_wrap (i2x_wrap[0]),
|
|
.b2x_id (i2x_id0),
|
|
.b2x_addr (i2x_addr0),
|
|
.b2x_len (i2x_len0),
|
|
.b2x_cmd (i2x_cmd0),
|
|
.x2b_ack (x2i_ack[0]),
|
|
|
assign activate_bank = (b2x_cmd == `OP_ACT) & x2b_ack;
|
/* Status to/from xfr_ctl */
|
|
.tras_ok (tras_ok[0]),
|
|
.xfr_ok (xfr_ok[0]),
|
|
.x2b_refresh (x2b_refresh),
|
|
.x2b_pre_ok (x2b_pre_ok[0]),
|
|
.x2b_act_ok (x2b_act_ok),
|
|
.x2b_rdok (x2b_rdok),
|
|
.x2b_wrok (x2b_wrok),
|
|
|
assign page_hit = (r2b_raddr == bank_row) ? bank_valid : 1'b0; // its a hit only if bank is valid
|
.bank_row(bank0_row),
|
|
|
assign timer0_tc = ~|timer0;
|
/* SDRAM Timing */
|
|
.tras_delay (tras_delay),
|
|
.trp_delay (trp_delay),
|
|
.trcd_delay (trcd_delay));
|
|
|
assign ld_trp = (b2x_cmd == `OP_PRE) ? x2b_ack : 1'b0;
|
/****************************************************************************/
|
|
// Instantiate Bank Ctl FSM 1
|
|
|
assign ld_trcd = (b2x_cmd == `OP_ACT) ? x2b_ack : 1'b0;
|
sdrc_bank_fsm bank1_fsm (.clk (clk),
|
|
.reset_n (reset_n),
|
|
|
always @ (*) begin
|
/* Req from req_gen */
|
|
.r2b_req (r2i_req[1]),
|
|
.r2b_req_id (r2b_req_id),
|
|
.r2b_start (r2b_start),
|
|
.r2b_last (r2b_last),
|
|
.r2b_wrap (r2b_wrap),
|
|
.r2b_raddr (r2b_raddr),
|
|
.r2b_caddr (r2b_caddr),
|
|
.r2b_len (r2b_len),
|
|
.r2b_write (r2b_write),
|
|
.b2r_ack (i2r_ack[1]),
|
|
.sdr_dma_last(rank_ba_last[1]),
|
|
|
bank_prech_page_closed = 1'b0;
|
/* Transfer request to xfr_ctl */
|
b2x_req = 1'b0;
|
.b2x_req (i2x_req[1]),
|
b2x_cmd = 2'bx;
|
.b2x_start (i2x_start[1]),
|
b2r_ack = 1'b0;
|
.b2x_last (i2x_last[1]),
|
b2x_addr = 12'bx;
|
.b2x_wrap (i2x_wrap[1]),
|
next_bank_st = bank_st;
|
.b2x_id (i2x_id1),
|
|
.b2x_addr (i2x_addr1),
|
|
.b2x_len (i2x_len1),
|
|
.b2x_cmd (i2x_cmd1),
|
|
.x2b_ack (x2i_ack[1]),
|
|
|
case (bank_st)
|
/* Status to/from xfr_ctl */
|
|
.tras_ok (tras_ok[1]),
|
|
.xfr_ok (xfr_ok[1]),
|
|
.x2b_refresh (x2b_refresh),
|
|
.x2b_pre_ok (x2b_pre_ok[1]),
|
|
.x2b_act_ok (x2b_act_ok),
|
|
.x2b_rdok (x2b_rdok),
|
|
.x2b_wrok (x2b_wrok),
|
|
|
`BANK_IDLE : begin
|
.bank_row(bank1_row),
|
|
|
|
/* SDRAM Timing */
|
|
.tras_delay (tras_delay),
|
|
.trp_delay (trp_delay),
|
|
.trcd_delay (trcd_delay));
|
|
|
|
/****************************************************************************/
|
|
// Instantiate Bank Ctl FSM 2
|
|
|
|
sdrc_bank_fsm bank2_fsm (.clk (clk),
|
|
.reset_n (reset_n),
|
|
|
|
/* Req from req_gen */
|
|
.r2b_req (r2i_req[2]),
|
|
.r2b_req_id (r2b_req_id),
|
|
.r2b_start (r2b_start),
|
|
.r2b_last (r2b_last),
|
|
.r2b_wrap (r2b_wrap),
|
|
.r2b_raddr (r2b_raddr),
|
|
.r2b_caddr (r2b_caddr),
|
|
.r2b_len (r2b_len),
|
|
.r2b_write (r2b_write),
|
|
.b2r_ack (i2r_ack[2]),
|
|
.sdr_dma_last(rank_ba_last[2]),
|
|
|
|
/* Transfer request to xfr_ctl */
|
|
.b2x_req (i2x_req[2]),
|
|
.b2x_start (i2x_start[2]),
|
|
.b2x_last (i2x_last[2]),
|
|
.b2x_wrap (i2x_wrap[2]),
|
|
.b2x_id (i2x_id2),
|
|
.b2x_addr (i2x_addr2),
|
|
.b2x_len (i2x_len2),
|
|
.b2x_cmd (i2x_cmd2),
|
|
.x2b_ack (x2i_ack[2]),
|
|
|
|
/* Status to/from xfr_ctl */
|
|
.tras_ok (tras_ok[2]),
|
|
.xfr_ok (xfr_ok[2]),
|
|
.x2b_refresh (x2b_refresh),
|
|
.x2b_pre_ok (x2b_pre_ok[2]),
|
|
.x2b_act_ok (x2b_act_ok),
|
|
.x2b_rdok (x2b_rdok),
|
|
.x2b_wrok (x2b_wrok),
|
|
|
|
.bank_row(bank2_row),
|
|
|
|
/* SDRAM Timing */
|
|
.tras_delay (tras_delay),
|
|
.trp_delay (trp_delay),
|
|
.trcd_delay (trcd_delay));
|
|
|
|
/****************************************************************************/
|
|
// Instantiate Bank Ctl FSM 3
|
|
|
|
sdrc_bank_fsm bank3_fsm (.clk (clk),
|
|
.reset_n (reset_n),
|
|
|
|
/* Req from req_gen */
|
|
.r2b_req (r2i_req[3]),
|
|
.r2b_req_id (r2b_req_id),
|
|
.r2b_start (r2b_start),
|
|
.r2b_last (r2b_last),
|
|
.r2b_wrap (r2b_wrap),
|
|
.r2b_raddr (r2b_raddr),
|
|
.r2b_caddr (r2b_caddr),
|
|
.r2b_len (r2b_len),
|
|
.r2b_write (r2b_write),
|
|
.b2r_ack (i2r_ack[3]),
|
|
.sdr_dma_last(rank_ba_last[3]),
|
|
|
|
/* Transfer request to xfr_ctl */
|
|
.b2x_req (i2x_req[3]),
|
|
.b2x_start (i2x_start[3]),
|
|
.b2x_last (i2x_last[3]),
|
|
.b2x_wrap (i2x_wrap[3]),
|
|
.b2x_id (i2x_id3),
|
|
.b2x_addr (i2x_addr3),
|
|
.b2x_len (i2x_len3),
|
|
.b2x_cmd (i2x_cmd3),
|
|
.x2b_ack (x2i_ack[3]),
|
|
|
|
/* Status to/from xfr_ctl */
|
|
.tras_ok (tras_ok[3]),
|
|
.xfr_ok (xfr_ok[3]),
|
|
.x2b_refresh (x2b_refresh),
|
|
.x2b_pre_ok (x2b_pre_ok[3]),
|
|
.x2b_act_ok (x2b_act_ok),
|
|
.x2b_rdok (x2b_rdok),
|
|
.x2b_wrok (x2b_wrok),
|
|
|
|
.bank_row(bank3_row),
|
|
|
|
/* SDRAM Timing */
|
|
.tras_delay (tras_delay),
|
|
.trp_delay (trp_delay),
|
|
.trcd_delay (trcd_delay));
|
|
|
if (~r2b_req) begin
|
|
bank_prech_page_closed = 1'b0;
|
|
b2x_req = 1'b0;
|
|
b2x_cmd = 2'bx;
|
|
b2r_ack = 1'b0;
|
|
b2x_addr = 12'bx;
|
|
next_bank_st = `BANK_IDLE;
|
|
end // if (~r2b_req)
|
|
else if (page_hit) begin
|
|
b2x_req = (r2b_write) ? x2b_wrok & xfr_ok :
|
|
x2b_rdok & xfr_ok;
|
|
b2x_cmd = (r2b_write) ? `OP_WR : `OP_RD;
|
|
b2r_ack = 1'b1;
|
|
b2x_addr = r2b_caddr;
|
|
next_bank_st = (x2b_ack) ? `BANK_IDLE : `BANK_XFR; // in case of hit, stay here till xfr sm acks
|
|
end // if (page_hit)
|
|
else begin // page_miss
|
|
b2x_req = tras_ok_internal & x2b_pre_ok;
|
|
b2x_cmd = `OP_PRE;
|
|
b2r_ack = 1'b1;
|
|
b2x_addr = r2b_raddr & 12'hBFF; // Dont want to pre all banks!
|
|
next_bank_st = (l_sdr_dma_last) ? `BANK_PRE : (x2b_ack) ? `BANK_ACT : `BANK_PRE; // bank was precharged on l_sdr_dma_last
|
|
end // else: !if(page_hit)
|
|
|
|
end // case: `BANK_IDLE
|
|
|
|
`BANK_PRE : begin
|
|
b2x_req = tras_ok_internal & x2b_pre_ok;
|
|
b2x_cmd = `OP_PRE;
|
|
b2r_ack = 1'b0;
|
|
b2x_addr = l_raddr & 12'hBFF; // Dont want to pre all banks!
|
|
bank_prech_page_closed = 1'b0;
|
|
next_bank_st = (x2b_ack) ? `BANK_ACT : `BANK_PRE;
|
|
end // case: `BANK_PRE
|
|
|
|
`BANK_ACT : begin
|
|
b2x_req = timer0_tc & x2b_act_ok;
|
|
b2x_cmd = `OP_ACT;
|
|
b2r_ack = 1'b0;
|
|
b2x_addr = l_raddr;
|
|
bank_prech_page_closed = 1'b0;
|
|
next_bank_st = (x2b_ack) ? `BANK_XFR : `BANK_ACT;
|
|
end // case: `BANK_ACT
|
|
|
|
`BANK_XFR : begin
|
|
b2x_req = (l_write) ? timer0_tc & x2b_wrok & xfr_ok :
|
|
timer0_tc & x2b_rdok & xfr_ok;
|
|
b2x_cmd = (l_write) ? `OP_WR : `OP_RD;
|
|
b2r_ack = 1'b0;
|
|
b2x_addr = l_caddr;
|
|
bank_prech_page_closed = 1'b0;
|
|
next_bank_st = (x2b_refresh) ? `BANK_ACT :
|
|
(x2b_ack & l_sdr_dma_last) ? `BANK_DMA_LAST_PRE :
|
|
(x2b_ack) ? `BANK_IDLE : `BANK_XFR;
|
|
end // case: `BANK_XFR
|
|
|
|
`BANK_DMA_LAST_PRE : begin
|
|
b2x_req = tras_ok_internal & x2b_pre_ok;
|
|
b2x_cmd = `OP_PRE;
|
|
b2r_ack = 1'b0;
|
|
b2x_addr = l_raddr & 12'hBFF; // Dont want to pre all banks!
|
|
bank_prech_page_closed = 1'b1;
|
|
next_bank_st = (x2b_ack) ? `BANK_IDLE : `BANK_DMA_LAST_PRE;
|
|
end // case: `BANK_DMA_LAST_PRE
|
|
|
|
endcase // case(bank_st)
|
|
|
|
end // always @ (bank_st or ...)
|
|
|
|
assign b2x_start = (bank_st == `BANK_IDLE) ? r2b_start : l_start;
|
|
|
|
assign b2x_last = (bank_st == `BANK_IDLE) ? r2b_last : l_last;
|
|
|
|
assign b2x_id = (bank_st == `BANK_IDLE) ? r2b_req_id : l_id;
|
/* address for current xfr, debug only */
|
|
wire [11:0] cur_row = (xfr_bank_sel==3) ? bank3_row:
|
|
(xfr_bank_sel==2) ? bank2_row:
|
|
(xfr_bank_sel==1) ? bank1_row: bank0_row;
|
|
|
assign b2x_len = (bank_st == `BANK_IDLE) ? r2b_len : l_len;
|
assign xfr_addr_msb = (sdr_dev_config == 2'b11) ? {cur_row, xfr_bank_sel[1:0]}:
|
|
{cur_row, xfr_bank_sel[0]};
|
|
|
assign b2x_wrap = (bank_st == `BANK_IDLE) ? r2b_wrap : l_wrap;
|
|
|
|
endmodule // sdr_bank_fsm
|
endmodule // sdr_bank_ctl
|
|
|
No newline at end of file
|
No newline at end of file
|
