Line 84... |
Line 84... |
x2b_act_ok, // OK to do an activate
|
x2b_act_ok, // OK to do an activate
|
x2b_rdok, // OK to do a read
|
x2b_rdok, // OK to do a read
|
x2b_wrok, // OK to do a write
|
x2b_wrok, // OK to do a write
|
|
|
/* xfr msb address */
|
/* xfr msb address */
|
sdr_dev_config,
|
|
xfr_bank_sel,
|
xfr_bank_sel,
|
xfr_addr_msb,
|
|
sdr_req_norm_dma_last,
|
sdr_req_norm_dma_last,
|
|
|
/* SDRAM Timing */
|
/* SDRAM Timing */
|
tras_delay, // Active to precharge delay
|
tras_delay, // Active to precharge delay
|
trp_delay, // Precharge to active delay
|
trp_delay, // Precharge to active delay
|
Line 133... |
Line 131... |
input x2b_refresh, x2b_act_ok, x2b_rdok,
|
input x2b_refresh, x2b_act_ok, x2b_rdok,
|
x2b_wrok;
|
x2b_wrok;
|
|
|
input [3:0] tras_delay, trp_delay, trcd_delay;
|
input [3:0] tras_delay, trp_delay, trcd_delay;
|
|
|
input [1:0] sdr_dev_config;
|
|
input [1:0] xfr_bank_sel;
|
input [1:0] xfr_bank_sel;
|
output [13:0] xfr_addr_msb;
|
|
|
|
/****************************************************************************/
|
/****************************************************************************/
|
// Internal Nets
|
// Internal Nets
|
|
|
wire [3:0] r2i_req, i2r_ack, i2x_req,
|
wire [3:0] r2i_req, i2r_ack, i2x_req,
|
Line 561... |
Line 557... |
/* address for current xfr, debug only */
|
/* address for current xfr, debug only */
|
wire [11:0] cur_row = (xfr_bank_sel==3) ? bank3_row:
|
wire [11:0] cur_row = (xfr_bank_sel==3) ? bank3_row:
|
(xfr_bank_sel==2) ? bank2_row:
|
(xfr_bank_sel==2) ? bank2_row:
|
(xfr_bank_sel==1) ? bank1_row: bank0_row;
|
(xfr_bank_sel==1) ? bank1_row: bank0_row;
|
|
|
assign xfr_addr_msb = (sdr_dev_config == 2'b11) ? {cur_row, xfr_bank_sel[1:0]}:
|
|
{cur_row, xfr_bank_sel[0]};
|
|
|
|
|
|
endmodule // sdr_bank_ctl
|
endmodule // sdr_bank_ctl
|
|
|
No newline at end of file
|
No newline at end of file
|