| Line 98... |
Line 98... |
parameter APP_DW = 32; // Application Data Width
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parameter APP_DW = 32; // Application Data Width
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parameter APP_BW = 4; // Application Byte Width
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parameter APP_BW = 4; // Application Byte Width
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parameter SDR_DW = 16; // SDR Data Width
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parameter SDR_DW = 16; // SDR Data Width
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parameter SDR_BW = 2; // SDR Byte Width
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parameter SDR_BW = 2; // SDR Byte Width
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parameter REQ_BW = 12; // Request Width
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// 12 bit subtractor is not feasibile for FPGA, so changed to 8 bits
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parameter REQ_BW = (`TARGET_DESIGN == `FPGA) ? 8 : 12; // Request Width
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input clk, reset_n;
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input clk, reset_n;
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input [1:0] a2b_req_depth;
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input [1:0] a2b_req_depth;
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/* Req from bank_ctl */
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/* Req from bank_ctl */
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| Line 172... |
Line 173... |
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wire [11:0] bank0_row, bank1_row, bank2_row, bank3_row;
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wire [11:0] bank0_row, bank1_row, bank2_row, bank3_row;
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assign b2x_tras_ok = &tras_ok;
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assign b2x_tras_ok = &tras_ok;
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// Distribute the request from req_gen
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// Distribute the request from req_gen
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assign r2i_req[0] = (r2b_ba == 2'b00) ? r2b_req & ~rank_fifo_full : 1'b0;
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assign r2i_req[0] = (r2b_ba == 2'b00) ? r2b_req & ~rank_fifo_full : 1'b0;
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assign r2i_req[1] = (r2b_ba == 2'b01) ? r2b_req & ~rank_fifo_full : 1'b0;
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assign r2i_req[1] = (r2b_ba == 2'b01) ? r2b_req & ~rank_fifo_full : 1'b0;
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assign r2i_req[2] = (r2b_ba == 2'b10) ? r2b_req & ~rank_fifo_full : 1'b0;
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assign r2i_req[2] = (r2b_ba == 2'b10) ? r2b_req & ~rank_fifo_full : 1'b0;
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assign r2i_req[3] = (r2b_ba == 2'b11) ? r2b_req & ~rank_fifo_full : 1'b0;
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assign r2i_req[3] = (r2b_ba == 2'b11) ? r2b_req & ~rank_fifo_full : 1'b0;
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assign b2r_ack = (r2b_ba == 2'b00) ? i2r_ack[0] :
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/******************
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(r2b_ba == 2'b01) ? i2r_ack[1] :
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Modified the Better FPGA Timing Purpose
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(r2b_ba == 2'b10) ? i2r_ack[2] :
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assign b2r_ack = (r2b_ba == 2'b00) ? i2r_ack[0] :
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(r2b_ba == 2'b11) ? i2r_ack[3] : 1'b0;
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(r2b_ba == 2'b01) ? i2r_ack[1] :
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(r2b_ba == 2'b10) ? i2r_ack[2] :
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(r2b_ba == 2'b11) ? i2r_ack[3] : 1'b0;
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********************/
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// Assumption: Only one Ack Will be asserted at a time.
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assign b2r_ack =|i2r_ack;
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assign b2r_arb_ok = ~rank_fifo_full;
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assign b2r_arb_ok = ~rank_fifo_full;
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// Put the requests from the 4 bank_fsms into a 4 deep shift
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// Put the requests from the 4 bank_fsms into a 4 deep shift
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// register file. The earliest request is prioritized over the
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// register file. The earliest request is prioritized over the
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Line 203... |
// Mux the req/cmd to xfr_ctl. Allow RD/WR commands from the request in
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// Mux the req/cmd to xfr_ctl. Allow RD/WR commands from the request in
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// rank0, allow only PR/ACT commands from the requests in other ranks
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// rank0, allow only PR/ACT commands from the requests in other ranks
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// If the rank_fifo is empty, send the request from the bank addressed by
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// If the rank_fifo is empty, send the request from the bank addressed by
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// r2b_ba
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// r2b_ba
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assign xfr_ba = (rank_fifo_mt) ? r2b_ba : rank_ba[1:0];
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// In FPGA Mode, to improve the timing, also send the rank_ba
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assign xfr_ba_last = (rank_fifo_mt) ? sdr_req_norm_dma_last : rank_ba_last[0];
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assign xfr_ba = (`TARGET_DESIGN == `FPGA) ? rank_ba[1:0]:
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((rank_fifo_mt) ? r2b_ba : rank_ba[1:0]);
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assign xfr_ba_last = (`TARGET_DESIGN == `FPGA) ? rank_ba_last[0]:
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((rank_fifo_mt) ? sdr_req_norm_dma_last : rank_ba_last[0]);
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assign rank_req[0] = i2x_req[xfr_ba]; // each rank generates requests
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assign rank_req[0] = i2x_req[xfr_ba]; // each rank generates requests
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assign rank_req[1] = (rank_cnt < 3'h2) ? 1'b0 :
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assign rank_req[1] = (rank_cnt < 3'h2) ? 1'b0 :
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(rank_ba[3:2] == 2'b00) ? i2x_req[0] & ~i2x_cmd0[1] :
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(rank_ba[3:2] == 2'b00) ? i2x_req[0] & ~i2x_cmd0[1] :
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| Line 348... |
Line 358... |
(rank_fifo_rd) ? rank_ba[7:6] : rank_ba[5:4];
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(rank_fifo_rd) ? rank_ba[7:6] : rank_ba[5:4];
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rank_ba[7:6] <= (rank_wr_sel[3]) ? r2b_ba :
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rank_ba[7:6] <= (rank_wr_sel[3]) ? r2b_ba :
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(rank_fifo_rd) ? 2'b00 : rank_ba[7:6];
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(rank_fifo_rd) ? 2'b00 : rank_ba[7:6];
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if(`TARGET_DESIGN == `ASIC) begin // This Logic is implemented for ASIC Only
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// Note: Currenly top-level does not generate the
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// sdr_req_norm_dma_last signal and can be tied zero at top-level
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rank_ba_last[0] <= (rank_wr_sel[0]) ? sdr_req_norm_dma_last :
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rank_ba_last[0] <= (rank_wr_sel[0]) ? sdr_req_norm_dma_last :
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(rank_fifo_rd) ? rank_ba_last[1] : rank_ba_last[0];
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(rank_fifo_rd) ? rank_ba_last[1] : rank_ba_last[0];
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rank_ba_last[1] <= (rank_wr_sel[1]) ? sdr_req_norm_dma_last :
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rank_ba_last[1] <= (rank_wr_sel[1]) ? sdr_req_norm_dma_last :
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(rank_fifo_rd) ? rank_ba_last[2] : rank_ba_last[1];
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(rank_fifo_rd) ? rank_ba_last[2] : rank_ba_last[1];
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| Line 359... |
Line 372... |
rank_ba_last[2] <= (rank_wr_sel[2]) ? sdr_req_norm_dma_last :
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rank_ba_last[2] <= (rank_wr_sel[2]) ? sdr_req_norm_dma_last :
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(rank_fifo_rd) ? rank_ba_last[3] : rank_ba_last[2];
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(rank_fifo_rd) ? rank_ba_last[3] : rank_ba_last[2];
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rank_ba_last[3] <= (rank_wr_sel[3]) ? sdr_req_norm_dma_last :
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rank_ba_last[3] <= (rank_wr_sel[3]) ? sdr_req_norm_dma_last :
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(rank_fifo_rd) ? 1'b0 : rank_ba_last[3];
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(rank_fifo_rd) ? 1'b0 : rank_ba_last[3];
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end
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end // else: !if(~reset_n)
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end // else: !if(~reset_n)
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assign xfr_ok[0] = (xfr_ba == 2'b00) ? 1'b1 : 1'b0;
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assign xfr_ok[0] = (xfr_ba == 2'b00) ? 1'b1 : 1'b0;
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assign xfr_ok[1] = (xfr_ba == 2'b01) ? 1'b1 : 1'b0;
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assign xfr_ok[1] = (xfr_ba == 2'b01) ? 1'b1 : 1'b0;
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