| Line 94... |
Line 94... |
parameter APP_DW = 32; // Application Data Width
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parameter APP_DW = 32; // Application Data Width
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parameter APP_BW = 4; // Application Byte Width
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parameter APP_BW = 4; // Application Byte Width
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parameter SDR_DW = 16; // SDR Data Width
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parameter SDR_DW = 16; // SDR Data Width
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parameter SDR_BW = 2; // SDR Byte Width
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parameter SDR_BW = 2; // SDR Byte Width
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parameter REQ_BW = 12; // Request Width
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// 12 bit subtractor is not feasibile for FPGA, so changed to 8 bits
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parameter REQ_BW = (`TARGET_DESIGN == `FPGA) ? 8 : 12; // Request Width
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input clk, reset_n;
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input clk, reset_n;
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/* Req from bank_ctl */
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/* Req from bank_ctl */
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input r2b_req, r2b_start, r2b_last,
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input r2b_req, r2b_start, r2b_last,
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r2b_write, r2b_wrap;
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r2b_write, r2b_wrap;
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| Line 142... |
Line 144... |
wire [`SDR_REQ_ID_W-1:0] b2x_id;
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wire [`SDR_REQ_ID_W-1:0] b2x_id;
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reg [`SDR_REQ_ID_W-1:0] l_id;
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reg [`SDR_REQ_ID_W-1:0] l_id;
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reg [11:0] b2x_addr;
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reg [11:0] b2x_addr;
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reg [REQ_BW-1:0] l_len;
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reg [REQ_BW-1:0] l_len;
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wire [REQ_BW-1:0] b2x_len;
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wire [REQ_BW-1:0] b2x_len;
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reg [1:0] b2x_cmd;
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reg [1:0] b2x_cmd_t;
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reg bank_valid;
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reg bank_valid;
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reg [11:0] bank_row;
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reg [11:0] bank_row;
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reg [3:0] tras_cntr, timer0;
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reg [3:0] tras_cntr, timer0;
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reg l_wrap, l_write;
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reg l_wrap, l_write;
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wire b2x_wrap;
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wire b2x_wrap;
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| Line 155... |
Line 157... |
reg l_sdr_dma_last;
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reg l_sdr_dma_last;
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reg bank_prech_page_closed;
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reg bank_prech_page_closed;
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wire tras_ok_internal, tras_ok, activate_bank;
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wire tras_ok_internal, tras_ok, activate_bank;
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wire page_hit, timer0_tc, ld_trp, ld_trcd;
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wire page_hit, timer0_tc_t, ld_trp, ld_trcd;
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/*** Timing Break Logic Added for FPGA - Start ****/
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reg x2b_wrok_r, xfr_ok_r , x2b_rdok_r;
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reg [1:0] b2x_cmd_r,timer0_tc_r,tras_ok_r,x2b_pre_ok_r,x2b_act_ok_r;
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always @ (posedge clk)
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if (~reset_n) begin
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x2b_wrok_r <= 1'b0;
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xfr_ok_r <= 1'b0;
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x2b_rdok_r <= 1'b0;
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b2x_cmd_r <= 2'b0;
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timer0_tc_r <= 1'b0;
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tras_ok_r <= 1'b0;
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x2b_pre_ok_r <= 1'b0;
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x2b_act_ok_r <= 1'b0;
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end
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else begin
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x2b_wrok_r <= x2b_wrok;
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xfr_ok_r <= xfr_ok;
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x2b_rdok_r <= x2b_rdok;
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b2x_cmd_r <= b2x_cmd_t;
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timer0_tc_r <= (ld_trp | ld_trcd) ? 1'b0 : timer0_tc_t;
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tras_ok_r <= tras_ok_internal;
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x2b_pre_ok_r <= x2b_pre_ok;
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x2b_act_ok_r <= x2b_act_ok;
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end
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wire x2b_wrok_t = (`TARGET_DESIGN == `FPGA) ? x2b_wrok_r : x2b_wrok;
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wire xfr_ok_t = (`TARGET_DESIGN == `FPGA) ? xfr_ok_r : xfr_ok;
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wire x2b_rdok_t = (`TARGET_DESIGN == `FPGA) ? x2b_rdok_r : x2b_rdok;
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wire [1:0] b2x_cmd = (`TARGET_DESIGN == `FPGA) ? b2x_cmd_r : b2x_cmd_t;
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wire timer0_tc = (`TARGET_DESIGN == `FPGA) ? timer0_tc_r : timer0_tc_t;
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assign tras_ok = (`TARGET_DESIGN == `FPGA) ? tras_ok_r : tras_ok_internal;
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wire x2b_pre_ok_t = (`TARGET_DESIGN == `FPGA) ? x2b_pre_ok_r : x2b_pre_ok;
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wire x2b_act_ok_t = (`TARGET_DESIGN == `FPGA) ? x2b_act_ok_r : x2b_act_ok;
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/*** Timing Break Logic Added for FPGA - End****/
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always @ (posedge clk)
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always @ (posedge clk)
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if (~reset_n) begin
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if (~reset_n) begin
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bank_valid <= 1'b0;
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bank_valid <= 1'b0;
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tras_cntr <= 4'b0;
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tras_cntr <= 4'b0;
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| Line 175... |
Line 214... |
tras_cntr <= (activate_bank) ? tras_delay :
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tras_cntr <= (activate_bank) ? tras_delay :
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(~tras_ok_internal) ? tras_cntr - 4'b1 : 4'b0;
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(~tras_ok_internal) ? tras_cntr - 4'b1 : 4'b0;
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timer0 <= (ld_trp) ? trp_delay :
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timer0 <= (ld_trp) ? trp_delay :
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(ld_trcd) ? trcd_delay :
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(ld_trcd) ? trcd_delay :
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(~timer0_tc) ? timer0 - 4'b1 : timer0;
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(timer0 != 'h0) ? timer0 - 4'b1 : timer0;
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bank_st <= next_bank_st;
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bank_st <= next_bank_st;
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end // else: !if(~reset_n)
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end // else: !if(~reset_n)
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| Line 213... |
Line 252... |
end
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end
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end // always @ (posedge clk)
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end // always @ (posedge clk)
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assign tras_ok_internal = ~|tras_cntr;
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assign tras_ok_internal = ~|tras_cntr;
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assign tras_ok = tras_ok_internal;
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assign activate_bank = (b2x_cmd == `OP_ACT) & x2b_ack;
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assign activate_bank = (b2x_cmd == `OP_ACT) & x2b_ack;
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assign page_hit = (r2b_raddr == bank_row) ? bank_valid : 1'b0; // its a hit only if bank is valid
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assign page_hit = (r2b_raddr == bank_row) ? bank_valid : 1'b0; // its a hit only if bank is valid
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assign timer0_tc = ~|timer0;
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assign timer0_tc_t = ~|timer0;
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assign ld_trp = (b2x_cmd == `OP_PRE) ? x2b_ack : 1'b0;
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assign ld_trp = (b2x_cmd == `OP_PRE) ? x2b_ack : 1'b0;
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assign ld_trcd = (b2x_cmd == `OP_ACT) ? x2b_ack : 1'b0;
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assign ld_trcd = (b2x_cmd == `OP_ACT) ? x2b_ack : 1'b0;
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always @ (*) begin
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always @ (*) begin
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bank_prech_page_closed = 1'b0;
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bank_prech_page_closed = 1'b0;
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b2x_req = 1'b0;
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b2x_req = 1'b0;
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b2x_cmd = 2'bx;
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b2x_cmd_t = 2'bx;
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b2r_ack = 1'b0;
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b2r_ack = 1'b0;
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b2x_addr = 12'bx;
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b2x_addr = 12'bx;
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next_bank_st = bank_st;
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next_bank_st = bank_st;
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case (bank_st)
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case (bank_st)
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`BANK_IDLE : begin
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`BANK_IDLE : begin
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if(`TARGET_DESIGN == `FPGA) begin // To break the timing, b2x request are generated delayed
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if (~r2b_req) begin
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next_bank_st = `BANK_IDLE;
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end // if (~r2b_req)
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else if (page_hit) begin
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b2r_ack = 1'b1;
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b2x_cmd_t = (r2b_write) ? `OP_WR : `OP_RD;
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next_bank_st = `BANK_XFR;
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end // if (page_hit)
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else begin // page_miss
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b2r_ack = 1'b1;
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b2x_cmd_t = `OP_PRE;
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next_bank_st = `BANK_PRE; // bank was precharged on l_sdr_dma_last
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end // else: !if(page_hit)
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end else begin // ASIC
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if (~r2b_req) begin
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if (~r2b_req) begin
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bank_prech_page_closed = 1'b0;
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bank_prech_page_closed = 1'b0;
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b2x_req = 1'b0;
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b2x_req = 1'b0;
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b2x_cmd = 2'bx;
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b2x_cmd_t = 2'bx;
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b2r_ack = 1'b0;
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b2r_ack = 1'b0;
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b2x_addr = 12'bx;
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b2x_addr = 12'bx;
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next_bank_st = `BANK_IDLE;
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next_bank_st = `BANK_IDLE;
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end // if (~r2b_req)
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end // if (~r2b_req)
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else if (page_hit) begin
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else if (page_hit) begin
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b2x_req = (r2b_write) ? x2b_wrok & xfr_ok :
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b2x_req = (r2b_write) ? x2b_wrok_t & xfr_ok_t :
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x2b_rdok & xfr_ok;
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x2b_rdok_t & xfr_ok_t;
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b2x_cmd = (r2b_write) ? `OP_WR : `OP_RD;
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b2x_cmd_t = (r2b_write) ? `OP_WR : `OP_RD;
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b2r_ack = 1'b1;
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b2r_ack = 1'b1;
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b2x_addr = r2b_caddr;
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b2x_addr = r2b_caddr;
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next_bank_st = (x2b_ack) ? `BANK_IDLE : `BANK_XFR; // in case of hit, stay here till xfr sm acks
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next_bank_st = (x2b_ack) ? `BANK_IDLE : `BANK_XFR; // in case of hit, stay here till xfr sm acks
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end // if (page_hit)
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end // if (page_hit)
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else begin // page_miss
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else begin // page_miss
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b2x_req = tras_ok_internal & x2b_pre_ok;
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b2x_req = tras_ok & x2b_pre_ok_t;
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b2x_cmd = `OP_PRE;
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b2x_cmd_t = `OP_PRE;
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b2r_ack = 1'b1;
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b2r_ack = 1'b1;
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b2x_addr = r2b_raddr & 12'hBFF; // Dont want to pre all banks!
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b2x_addr = r2b_raddr & 12'hBFF; // Dont want to pre all banks!
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next_bank_st = (l_sdr_dma_last) ? `BANK_PRE : (x2b_ack) ? `BANK_ACT : `BANK_PRE; // bank was precharged on l_sdr_dma_last
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next_bank_st = (l_sdr_dma_last) ? `BANK_PRE : (x2b_ack) ? `BANK_ACT : `BANK_PRE; // bank was precharged on l_sdr_dma_last
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end // else: !if(page_hit)
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end // else: !if(page_hit)
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end
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end // case: `BANK_IDLE
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end // case: `BANK_IDLE
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`BANK_PRE : begin
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`BANK_PRE : begin
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b2x_req = tras_ok_internal & x2b_pre_ok;
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b2x_req = tras_ok & x2b_pre_ok_t;
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b2x_cmd = `OP_PRE;
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b2x_cmd_t = `OP_PRE;
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b2r_ack = 1'b0;
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b2r_ack = 1'b0;
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b2x_addr = l_raddr & 12'hBFF; // Dont want to pre all banks!
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b2x_addr = l_raddr & 12'hBFF; // Dont want to pre all banks!
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bank_prech_page_closed = 1'b0;
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bank_prech_page_closed = 1'b0;
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next_bank_st = (x2b_ack) ? `BANK_ACT : `BANK_PRE;
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next_bank_st = (x2b_ack) ? `BANK_ACT : `BANK_PRE;
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end // case: `BANK_PRE
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end // case: `BANK_PRE
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`BANK_ACT : begin
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`BANK_ACT : begin
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b2x_req = timer0_tc & x2b_act_ok;
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b2x_req = timer0_tc & x2b_act_ok_t;
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b2x_cmd = `OP_ACT;
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b2x_cmd_t = `OP_ACT;
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b2r_ack = 1'b0;
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b2r_ack = 1'b0;
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b2x_addr = l_raddr;
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b2x_addr = l_raddr;
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bank_prech_page_closed = 1'b0;
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bank_prech_page_closed = 1'b0;
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next_bank_st = (x2b_ack) ? `BANK_XFR : `BANK_ACT;
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next_bank_st = (x2b_ack) ? `BANK_XFR : `BANK_ACT;
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end // case: `BANK_ACT
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end // case: `BANK_ACT
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`BANK_XFR : begin
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`BANK_XFR : begin
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b2x_req = (l_write) ? timer0_tc & x2b_wrok & xfr_ok :
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b2x_req = (l_write) ? timer0_tc & x2b_wrok_t & xfr_ok_t :
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timer0_tc & x2b_rdok & xfr_ok;
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timer0_tc & x2b_rdok_t & xfr_ok_t;
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b2x_cmd = (l_write) ? `OP_WR : `OP_RD;
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b2x_cmd_t = (l_write) ? `OP_WR : `OP_RD;
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b2r_ack = 1'b0;
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b2r_ack = 1'b0;
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b2x_addr = l_caddr;
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b2x_addr = l_caddr;
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bank_prech_page_closed = 1'b0;
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bank_prech_page_closed = 1'b0;
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next_bank_st = (x2b_refresh) ? `BANK_ACT :
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next_bank_st = (x2b_refresh) ? `BANK_ACT :
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(x2b_ack & l_sdr_dma_last) ? `BANK_DMA_LAST_PRE :
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(x2b_ack & l_sdr_dma_last) ? `BANK_DMA_LAST_PRE :
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(x2b_ack) ? `BANK_IDLE : `BANK_XFR;
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(x2b_ack) ? `BANK_IDLE : `BANK_XFR;
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end // case: `BANK_XFR
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end // case: `BANK_XFR
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`BANK_DMA_LAST_PRE : begin
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`BANK_DMA_LAST_PRE : begin
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b2x_req = tras_ok_internal & x2b_pre_ok;
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b2x_req = tras_ok & x2b_pre_ok_t;
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b2x_cmd = `OP_PRE;
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b2x_cmd_t = `OP_PRE;
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b2r_ack = 1'b0;
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b2r_ack = 1'b0;
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b2x_addr = l_raddr & 12'hBFF; // Dont want to pre all banks!
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b2x_addr = l_raddr & 12'hBFF; // Dont want to pre all banks!
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bank_prech_page_closed = 1'b1;
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bank_prech_page_closed = 1'b1;
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next_bank_st = (x2b_ack) ? `BANK_IDLE : `BANK_DMA_LAST_PRE;
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next_bank_st = (x2b_ack) ? `BANK_IDLE : `BANK_DMA_LAST_PRE;
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end // case: `BANK_DMA_LAST_PRE
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end // case: `BANK_DMA_LAST_PRE
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