| Line 98... |
Line 98... |
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/* Req from bank_ctl */
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/* Req from bank_ctl */
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input r2b_req, r2b_start, r2b_last,
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input r2b_req, r2b_start, r2b_last,
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r2b_write, r2b_wrap;
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r2b_write, r2b_wrap;
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input [`SDR_REQ_ID_W-1:0] r2b_req_id;
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input [`SDR_REQ_ID_W-1:0] r2b_req_id;
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input [11:0] r2b_raddr;
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input [12:0] r2b_raddr;
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input [11:0] r2b_caddr;
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input [12:0] r2b_caddr;
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input [`REQ_BW-1:0] r2b_len;
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input [`REQ_BW-1:0] r2b_len;
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output b2r_ack;
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output b2r_ack;
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input sdr_dma_last;
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input sdr_dma_last;
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/* Req to xfr_ctl */
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/* Req to xfr_ctl */
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output b2x_req, b2x_start, b2x_last,
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output b2x_req, b2x_start, b2x_last,
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tras_ok, b2x_wrap;
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tras_ok, b2x_wrap;
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output [`SDR_REQ_ID_W-1:0] b2x_id;
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output [`SDR_REQ_ID_W-1:0] b2x_id;
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output [11:0] b2x_addr;
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output [12:0] b2x_addr;
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output [`REQ_BW-1:0] b2x_len;
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output [`REQ_BW-1:0] b2x_len;
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output [1:0] b2x_cmd;
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output [1:0] b2x_cmd;
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input x2b_ack;
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input x2b_ack;
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/* Status from xfr_ctl */
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/* Status from xfr_ctl */
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input x2b_refresh, x2b_act_ok, x2b_rdok,
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input x2b_refresh, x2b_act_ok, x2b_rdok,
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x2b_wrok, x2b_pre_ok, xfr_ok;
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x2b_wrok, x2b_pre_ok, xfr_ok;
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input [3:0] tras_delay, trp_delay, trcd_delay;
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input [3:0] tras_delay, trp_delay, trcd_delay;
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output [11:0] bank_row;
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output [12:0] bank_row;
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/****************************************************************************/
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/****************************************************************************/
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// Internal Nets
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// Internal Nets
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`define BANK_IDLE 3'b000
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`define BANK_IDLE 3'b000
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| Line 136... |
Line 136... |
wire b2x_start, b2x_last;
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wire b2x_start, b2x_last;
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reg l_start, l_last;
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reg l_start, l_last;
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reg b2x_req, b2r_ack;
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reg b2x_req, b2r_ack;
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wire [`SDR_REQ_ID_W-1:0] b2x_id;
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wire [`SDR_REQ_ID_W-1:0] b2x_id;
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reg [`SDR_REQ_ID_W-1:0] l_id;
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reg [`SDR_REQ_ID_W-1:0] l_id;
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reg [11:0] b2x_addr;
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reg [12:0] b2x_addr;
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reg [`REQ_BW-1:0] l_len;
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reg [`REQ_BW-1:0] l_len;
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wire [`REQ_BW-1:0] b2x_len;
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wire [`REQ_BW-1:0] b2x_len;
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reg [1:0] b2x_cmd_t;
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reg [1:0] b2x_cmd_t;
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reg bank_valid;
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reg bank_valid;
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reg [11:0] bank_row;
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reg [12:0] bank_row;
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reg [3:0] tras_cntr, timer0;
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reg [3:0] tras_cntr, timer0;
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reg l_wrap, l_write;
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reg l_wrap, l_write;
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wire b2x_wrap;
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wire b2x_wrap;
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reg [11:0] l_raddr;
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reg [12:0] l_raddr;
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reg [11:0] l_caddr;
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reg [12:0] l_caddr;
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reg l_sdr_dma_last;
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reg l_sdr_dma_last;
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reg bank_prech_page_closed;
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reg bank_prech_page_closed;
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wire tras_ok_internal, tras_ok, activate_bank;
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wire tras_ok_internal, tras_ok, activate_bank;
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| Line 266... |
Line 266... |
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bank_prech_page_closed = 1'b0;
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bank_prech_page_closed = 1'b0;
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b2x_req = 1'b0;
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b2x_req = 1'b0;
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b2x_cmd_t = 2'bx;
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b2x_cmd_t = 2'bx;
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b2r_ack = 1'b0;
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b2r_ack = 1'b0;
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b2x_addr = 12'bx;
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b2x_addr = 13'bx;
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next_bank_st = bank_st;
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next_bank_st = bank_st;
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case (bank_st)
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case (bank_st)
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`BANK_IDLE : begin
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`BANK_IDLE : begin
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| Line 292... |
Line 292... |
if (~r2b_req) begin
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if (~r2b_req) begin
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bank_prech_page_closed = 1'b0;
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bank_prech_page_closed = 1'b0;
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b2x_req = 1'b0;
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b2x_req = 1'b0;
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b2x_cmd_t = 2'bx;
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b2x_cmd_t = 2'bx;
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b2r_ack = 1'b0;
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b2r_ack = 1'b0;
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b2x_addr = 12'bx;
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b2x_addr = 13'bx;
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next_bank_st = `BANK_IDLE;
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next_bank_st = `BANK_IDLE;
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end // if (~r2b_req)
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end // if (~r2b_req)
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else if (page_hit) begin
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else if (page_hit) begin
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b2x_req = (r2b_write) ? x2b_wrok_t & xfr_ok_t :
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b2x_req = (r2b_write) ? x2b_wrok_t & xfr_ok_t :
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x2b_rdok_t & xfr_ok_t;
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x2b_rdok_t & xfr_ok_t;
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| Line 307... |
Line 307... |
end // if (page_hit)
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end // if (page_hit)
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else begin // page_miss
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else begin // page_miss
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b2x_req = tras_ok & x2b_pre_ok_t;
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b2x_req = tras_ok & x2b_pre_ok_t;
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b2x_cmd_t = `OP_PRE;
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b2x_cmd_t = `OP_PRE;
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b2r_ack = 1'b1;
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b2r_ack = 1'b1;
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b2x_addr = r2b_raddr & 12'hBFF; // Dont want to pre all banks!
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b2x_addr = r2b_raddr & 13'hBFF; // Dont want to pre all banks!
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next_bank_st = (l_sdr_dma_last) ? `BANK_PRE : (x2b_ack) ? `BANK_ACT : `BANK_PRE; // bank was precharged on l_sdr_dma_last
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next_bank_st = (l_sdr_dma_last) ? `BANK_PRE : (x2b_ack) ? `BANK_ACT : `BANK_PRE; // bank was precharged on l_sdr_dma_last
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end // else: !if(page_hit)
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end // else: !if(page_hit)
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end
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end
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end // case: `BANK_IDLE
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end // case: `BANK_IDLE
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`BANK_PRE : begin
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`BANK_PRE : begin
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b2x_req = tras_ok & x2b_pre_ok_t;
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b2x_req = tras_ok & x2b_pre_ok_t;
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b2x_cmd_t = `OP_PRE;
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b2x_cmd_t = `OP_PRE;
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b2r_ack = 1'b0;
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b2r_ack = 1'b0;
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b2x_addr = l_raddr & 12'hBFF; // Dont want to pre all banks!
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b2x_addr = l_raddr & 13'hBFF; // Dont want to pre all banks!
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bank_prech_page_closed = 1'b0;
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bank_prech_page_closed = 1'b0;
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next_bank_st = (x2b_ack) ? `BANK_ACT : `BANK_PRE;
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next_bank_st = (x2b_ack) ? `BANK_ACT : `BANK_PRE;
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end // case: `BANK_PRE
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end // case: `BANK_PRE
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`BANK_ACT : begin
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`BANK_ACT : begin
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| Line 347... |
Line 347... |
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`BANK_DMA_LAST_PRE : begin
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`BANK_DMA_LAST_PRE : begin
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b2x_req = tras_ok & x2b_pre_ok_t;
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b2x_req = tras_ok & x2b_pre_ok_t;
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b2x_cmd_t = `OP_PRE;
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b2x_cmd_t = `OP_PRE;
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b2r_ack = 1'b0;
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b2r_ack = 1'b0;
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b2x_addr = l_raddr & 12'hBFF; // Dont want to pre all banks!
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b2x_addr = l_raddr & 13'hBFF; // Dont want to pre all banks!
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bank_prech_page_closed = 1'b1;
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bank_prech_page_closed = 1'b1;
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next_bank_st = (x2b_ack) ? `BANK_IDLE : `BANK_DMA_LAST_PRE;
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next_bank_st = (x2b_ack) ? `BANK_IDLE : `BANK_DMA_LAST_PRE;
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end // case: `BANK_DMA_LAST_PRE
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end // case: `BANK_DMA_LAST_PRE
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endcase // case(bank_st)
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endcase // case(bank_st)
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