| Line 69... |
Line 69... |
(
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(
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clk,
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clk,
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pad_clk,
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pad_clk,
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reset_n,
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reset_n,
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sdr_width,
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sdr_width,
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cfg_colbits,
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/* Request from app */
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/* Request from app */
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app_req, // Transfer Request
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app_req, // Transfer Request
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app_req_addr, // SDRAM Address
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app_req_addr, // SDRAM Address
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app_req_addr_mask, // Address mask for queue wrap
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app_req_addr_mask, // Address mask for queue wrap
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| Line 131... |
Line 132... |
// ----------------------------------------------
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// ----------------------------------------------
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input clk ; // SDRAM Clock
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input clk ; // SDRAM Clock
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input pad_clk ; // SDRAM Clock from Pad, used for registering Read Data
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input pad_clk ; // SDRAM Clock from Pad, used for registering Read Data
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input reset_n ; // Reset Signal
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input reset_n ; // Reset Signal
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input sdr_width ; // 0 - 32 Bit SDR, 1 - 16 Bit SDR
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input sdr_width ; // 0 - 32 Bit SDR, 1 - 16 Bit SDR
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input [1:0] cfg_colbits ; // 2'b00 - 8 Bit column address, 2'b01 - 9 Bit, 10 - 10 bit, 11 - 11Bits
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//------------------------------------------------
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//------------------------------------------------
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// Request from app
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// Request from app
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//------------------------------------------------
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//------------------------------------------------
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input app_req ; // Application Request
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input app_req ; // Application Request
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| Line 167... |
Line 170... |
output [SDR_BW-1:0] sdr_den_n ; // SDRAM Data Output enable
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output [SDR_BW-1:0] sdr_den_n ; // SDRAM Data Output enable
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//------------------------------------------------
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//------------------------------------------------
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// Configuration Parameter
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// Configuration Parameter
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//------------------------------------------------
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//------------------------------------------------
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output sdr_init_done ;
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output sdr_init_done ; // Indicate SDRAM Initialisation Done
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input [3:0] cfg_sdr_tras_d ;
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input [3:0] cfg_sdr_tras_d ; // Active to precharge delay
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input [3:0] cfg_sdr_trp_d ;
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input [3:0] cfg_sdr_trp_d ; // Precharge to active delay
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input [3:0] cfg_sdr_trcd_d ;
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input [3:0] cfg_sdr_trcd_d ; // Active to R/W delay
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input cfg_sdr_en ;
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input cfg_sdr_en ; // Enable SDRAM controller
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input [1:0] cfg_sdr_dev_config ; // 2'b00 - 8 MB, 01 - 16 MB, 10 - 32 MB , 11 - 64 MB
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input [1:0] cfg_sdr_dev_config ; // 2'b00 - 8 MB, 01 - 16 MB, 10 - 32 MB , 11 - 64 MB
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input [1:0] cfg_req_depth ;
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input [1:0] cfg_req_depth ; // Maximum Request accepted by SDRAM controller
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input [APP_RW-1:0] app_req_len ;
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input [APP_RW-1:0] app_req_len ; // Application Burst Request length in 32 bit
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input [11:0] cfg_sdr_mode_reg ;
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input [11:0] cfg_sdr_mode_reg ;
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input [2:0] cfg_sdr_cas ;
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input [2:0] cfg_sdr_cas ; // SDRAM CAS Latency
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input [3:0] cfg_sdr_trcar_d ;
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input [3:0] cfg_sdr_trcar_d ; // Auto-refresh period
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input [3:0] cfg_sdr_twr_d ;
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input [3:0] cfg_sdr_twr_d ; // Write recovery delay
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input [`SDR_RFSH_TIMER_W-1 : 0] cfg_sdr_rfsh;
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input [`SDR_RFSH_TIMER_W-1 : 0] cfg_sdr_rfsh;
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input [`SDR_RFSH_ROW_CNT_W -1 : 0] cfg_sdr_rfmax;
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input [`SDR_RFSH_ROW_CNT_W -1 : 0] cfg_sdr_rfmax;
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input app_req_dma_last; // this signal should close the bank
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input app_req_dma_last; // this signal should close the bank
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/****************************************************************************/
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/****************************************************************************/
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| Line 267... |
Line 270... |
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sdrc_req_gen #(.SDR_DW(SDR_DW) , .SDR_BW(SDR_BW)) u_req_gen (
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sdrc_req_gen #(.SDR_DW(SDR_DW) , .SDR_BW(SDR_BW)) u_req_gen (
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.clk (clk ),
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.clk (clk ),
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.reset_n (reset_n ),
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.reset_n (reset_n ),
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.sdr_dev_config (cfg_sdr_dev_config ),
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.sdr_dev_config (cfg_sdr_dev_config ),
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.cfg_colbits (cfg_colbits ),
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/* Request from app */
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/* Request from app */
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.r2x_idle (r2x_idle ),
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.r2x_idle (r2x_idle ),
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.req (app_req_int ),
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.req (app_req_int ),
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.req_id (4'b0 ),
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.req_id (4'b0 ),
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