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[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] [sdrc_define.v] - Diff between revs 54 and 73
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Rev 54 |
Rev 73 |
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Line 23... |
`define SDR_REFRESH 4'b0001
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`define SDR_REFRESH 4'b0001
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`define SDR_MODE 4'b0000
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`define SDR_MODE 4'b0000
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`define ASIC 1'b1
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`define ASIC 1'b1
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`define FPGA 1'b0
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`define FPGA 1'b0
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`define TARGET_DESIGN `FPGA
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// Don't Enable FPGA mode, there is functional bug in handling Active to
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// Precharge timing
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`define TARGET_DESIGN `ASIC
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// 12 bit subtractor is not feasibile for FPGA, so changed to 6 bits
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// 12 bit subtractor is not feasibile for FPGA, so changed to 6 bits
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`define REQ_BW (`TARGET_DESIGN == `FPGA) ? 6 : 12 // Request Width
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`define REQ_BW (`TARGET_DESIGN == `FPGA) ? 6 : 12 // Request Width
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