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https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk
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Author(s): Dinesh Annayya, dinesha@opencores.org
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Author(s): Dinesh Annayya, dinesha@opencores.org
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Version : 0.0 - Initial Release
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Version : 0.0 - Initial Release
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0.1 - 2nd Feb 2012
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0.1 - 2nd Feb 2012
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Async Fifo towards the application layer is selected with Registered Full Generation
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Async Fifo towards the application layer is selected
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with Registered Full Generation
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0.2 - 2nd Feb 2012
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Pending Read generation bug fix done to handle backto back write
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followed by read request
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Copyright (C) 2000 Authors and OPENCORES.ORG
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Copyright (C) 2000 Authors and OPENCORES.ORG
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This source file may be used and distributed without
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This source file may be used and distributed without
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// ----------------------------------------------------------------------------
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// ----------------------------------------------------------------------------
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always @(posedge wb_rst_i or posedge wb_clk_i) begin
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always @(posedge wb_rst_i or posedge wb_clk_i) begin
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if(wb_rst_i) begin
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if(wb_rst_i) begin
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pending_read <= 1'b0;
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pending_read <= 1'b0;
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end else begin
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end else begin
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pending_read <= wb_stb_i & wb_cyc_i & !wb_we_i & !wb_ack_o;
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//pending_read <= wb_stb_i & wb_cyc_i & !wb_we_i & !wb_ack_o;
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pending_read <= (cmdfifo_wr && !wb_we_i) ? 1'b1:
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(wb_stb_i & wb_cyc_i & !wb_we_i & wb_ack_o) ? 1'b0: pending_read;
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end
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end
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end
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end
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//---------------------------------------------------------------------
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//---------------------------------------------------------------------
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// Async Command FIFO. This block handle the clock domain change from
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// Async Command FIFO. This block handle the clock domain change from
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