| Line 81... |
Line 81... |
);
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);
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|
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parameter dw = 32; // data width
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parameter dw = 32; // data width
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parameter tw = 8; // tag id width
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parameter tw = 8; // tag id width
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parameter bl = 9; // burst_lenght_width
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parameter bl = 9; // burst_lenght_width
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parameter APP_AW = 26; // Application Address Width
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//--------------------------------------
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//--------------------------------------
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// Wish Bone Interface
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// Wish Bone Interface
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// -------------------------------------
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// -------------------------------------
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input wb_rst_i ;
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input wb_rst_i ;
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input wb_clk_i ;
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input wb_clk_i ;
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input wb_stb_i ;
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input wb_stb_i ;
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output wb_ack_o ;
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output wb_ack_o ;
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input [24:0] wb_addr_i ;
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input [APP_AW-1:0] wb_addr_i ;
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input wb_we_i ; // 1 - Write , 0 - Read
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input wb_we_i ; // 1 - Write , 0 - Read
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input [dw-1:0] wb_dat_i ;
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input [dw-1:0] wb_dat_i ;
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input [dw/8-1:0] wb_sel_i ; // Byte enable
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input [dw/8-1:0] wb_sel_i ; // Byte enable
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output [dw-1:0] wb_dat_o ;
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output [dw-1:0] wb_dat_o ;
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input wb_cyc_i ;
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input wb_cyc_i ;
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| Line 118... |
Line 119... |
// SDRAM controller Interface
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// SDRAM controller Interface
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//--------------------------------------------
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//--------------------------------------------
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input sdram_clk ; // sdram clock
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input sdram_clk ; // sdram clock
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input sdram_resetn ; // sdram reset
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input sdram_resetn ; // sdram reset
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output sdr_req ; // SDRAM request
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output sdr_req ; // SDRAM request
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output [24:0] sdr_req_addr ; // SDRAM Request Address
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output [APP_AW-1:0] sdr_req_addr ; // SDRAM Request Address
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output [bl-1:0] sdr_req_len ;
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output [bl-1:0] sdr_req_len ;
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output sdr_req_wr_n ; // 0 - Write, 1 -> Read
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output sdr_req_wr_n ; // 0 - Write, 1 -> Read
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input sdr_req_ack ; // SDRAM request Accepted
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input sdr_req_ack ; // SDRAM request Accepted
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input sdr_busy_n ; // 0 -> sdr busy
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input sdr_busy_n ; // 0 -> sdr busy
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output [dw/8-1:0] sdr_wr_en_n ; // Active low sdr byte-wise write data valid
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output [dw/8-1:0] sdr_wr_en_n ; // Active low sdr byte-wise write data valid
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| Line 211... |
Line 212... |
//---------------------------------------------------------------------
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//---------------------------------------------------------------------
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// Async Command FIFO. This block handle the clock domain change from
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// Async Command FIFO. This block handle the clock domain change from
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// Application layer to SDRAM Controller
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// Application layer to SDRAM Controller
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// ------------------------------------------------------------------
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// ------------------------------------------------------------------
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// Address + Burst Length + W/R Request
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// Address + Burst Length + W/R Request
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async_fifo #(.W(25+bl+1),.DP(4),.WR_FAST(1'b0), .RD_FAST(1'b0)) u_cmdfifo (
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async_fifo #(.W(APP_AW+bl+1),.DP(4),.WR_FAST(1'b0), .RD_FAST(1'b0)) u_cmdfifo (
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// Write Path Sys CLock Domain
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// Write Path Sys CLock Domain
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.wr_clk (wb_clk_i ),
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.wr_clk (wb_clk_i ),
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.wr_reset_n (!wb_rst_i ),
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.wr_reset_n (!wb_rst_i ),
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.wr_en (cmdfifo_wr ),
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.wr_en (cmdfifo_wr ),
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.wr_data ({burst_length,
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.wr_data ({burst_length,
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