| Line 44... |
Line 44... |
# Loading work.sdrc_bank_ctl
|
# Loading work.sdrc_bank_ctl
|
# Loading work.sdrc_bank_fsm
|
# Loading work.sdrc_bank_fsm
|
# Loading work.sdrc_xfr_ctl
|
# Loading work.sdrc_xfr_ctl
|
# Loading work.sdrc_bs_convert
|
# Loading work.sdrc_bs_convert
|
# Loading work.mt48lc2m32b2
|
# Loading work.mt48lc2m32b2
|
|
# ** Warning: (vsim-3017) ../tb/tb_core.sv(180): [TFMPC] - Too few port connections. Expected 44, found 43.
|
|
# Region: /tb_core/u_dut
|
|
# ** Warning: (vsim-3722) ../tb/tb_core.sv(180): [TFMPC] - Missing connection for port 'app_last_wr'.
|
|
# ** Warning: (vsim-3015) ../../rtl/core/sdrc_core.v(302): [PCDPC] - Port size (31 or 31) does not match connection size (30) for port 'req_addr'. The port definition is at: ../../rtl/core/sdrc_req_gen.v(75).
|
|
# Region: /tb_core/u_dut/u_req_gen
|
# ** Warning: (vsim-3015) ../tb/tb_core.sv(199): [PCDPC] - Port size (11 or 11) does not match connection size (12) for port 'Addr'. The port definition is at: ../model/mt48lc2m32b2.v(42).
|
# ** Warning: (vsim-3015) ../tb/tb_core.sv(199): [PCDPC] - Port size (11 or 11) does not match connection size (12) for port 'Addr'. The port definition is at: ../model/mt48lc2m32b2.v(42).
|
# Region: /tb_core/u_sdram32
|
# Region: /tb_core/u_sdram32
|
# do run.do
|
# do run.do
|
# tb_core.u_sdram32 : at time 10157.0 ns AREF : Auto Refresh
|
# tb_core.u_sdram32 : at time 10157.0 ns AREF : Auto Refresh
|
# tb_core.u_sdram32 : at time 10247.0 ns AREF : Auto Refresh
|
# tb_core.u_sdram32 : at time 10247.0 ns AREF : Auto Refresh
|
| Line 1412... |
Line 1417... |
# tb_core.u_sdram32 : at time 26037.0 ns WRITE: Bank = 1 Row = 97, Col = 89, Data = 236afd46
|
# tb_core.u_sdram32 : at time 26037.0 ns WRITE: Bank = 1 Row = 97, Col = 89, Data = 236afd46
|
# Status: Burst-No: 61 Write Address: 00061472 WriteData: 236afd46
|
# Status: Burst-No: 61 Write Address: 00061472 WriteData: 236afd46
|
# tb_core.u_sdram32 : at time 26047.0 ns WRITE: Bank = 1 Row = 97, Col = 90, Data = c63a928c
|
# tb_core.u_sdram32 : at time 26047.0 ns WRITE: Bank = 1 Row = 97, Col = 90, Data = c63a928c
|
# Status: Burst-No: 62 Write Address: 00061472 WriteData: c63a928c
|
# Status: Burst-No: 62 Write Address: 00061472 WriteData: c63a928c
|
# tb_core.u_sdram32 : at time 26057.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 26057.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 26193.0 ns READ : Bank = 2 Row = 547, Col = 129, Data = cb5c8096
|
# tb_core.u_sdram32 : at time 26107.0 ns AREF : Auto Refresh
|
# tb_core.u_sdram32 : at time 26203.0 ns READ : Bank = 2 Row = 547, Col = 130, Data = 0a6e9314
|
# tb_core.u_sdram32 : at time 26197.0 ns AREF : Auto Refresh
|
|
# tb_core.u_sdram32 : at time 26287.0 ns AREF : Auto Refresh
|
|
# tb_core.u_sdram32 : at time 26377.0 ns AREF : Auto Refresh
|
|
# tb_core.u_sdram32 : at time 26467.0 ns AREF : Auto Refresh
|
|
# tb_core.u_sdram32 : at time 26557.0 ns AREF : Auto Refresh
|
|
# tb_core.u_sdram32 : at time 26677.0 ns ACT : Bank = 2 Row = 547
|
|
# tb_core.u_sdram32 : at time 26733.0 ns READ : Bank = 2 Row = 547, Col = 129, Data = cb5c8096
|
|
# tb_core.u_sdram32 : at time 26743.0 ns READ : Bank = 2 Row = 547, Col = 130, Data = 0a6e9314
|
# READ STATUS: Burst-No: 0 Addr: 00223a04 Rxd: cb5c8096
|
# READ STATUS: Burst-No: 0 Addr: 00223a04 Rxd: cb5c8096
|
# tb_core.u_sdram32 : at time 26213.0 ns READ : Bank = 2 Row = 547, Col = 131, Data = 8919b412
|
# tb_core.u_sdram32 : at time 26753.0 ns READ : Bank = 2 Row = 547, Col = 131, Data = 8919b412
|
# READ STATUS: Burst-No: 1 Addr: 00223a06 Rxd: 0a6e9314
|
# READ STATUS: Burst-No: 1 Addr: 00223a06 Rxd: 0a6e9314
|
# tb_core.u_sdram32 : at time 26223.0 ns READ : Bank = 2 Row = 547, Col = 132, Data = cb227096
|
# tb_core.u_sdram32 : at time 26763.0 ns READ : Bank = 2 Row = 547, Col = 132, Data = cb227096
|
# READ STATUS: Burst-No: 2 Addr: 00223a08 Rxd: 8919b412
|
# READ STATUS: Burst-No: 2 Addr: 00223a08 Rxd: 8919b412
|
# tb_core.u_sdram32 : at time 26233.0 ns READ : Bank = 2 Row = 547, Col = 133, Data = d8ace2b1
|
# tb_core.u_sdram32 : at time 26773.0 ns READ : Bank = 2 Row = 547, Col = 133, Data = d8ace2b1
|
# READ STATUS: Burst-No: 3 Addr: 00223a0a Rxd: cb227096
|
# READ STATUS: Burst-No: 3 Addr: 00223a0a Rxd: cb227096
|
# tb_core.u_sdram32 : at time 26243.0 ns READ : Bank = 2 Row = 547, Col = 134, Data = 2ac2d555
|
# tb_core.u_sdram32 : at time 26783.0 ns READ : Bank = 2 Row = 547, Col = 134, Data = 2ac2d555
|
# READ STATUS: Burst-No: 4 Addr: 00223a0c Rxd: d8ace2b1
|
# READ STATUS: Burst-No: 4 Addr: 00223a0c Rxd: d8ace2b1
|
# tb_core.u_sdram32 : at time 26253.0 ns READ : Bank = 2 Row = 547, Col = 135, Data = f6c38eed
|
# tb_core.u_sdram32 : at time 26793.0 ns READ : Bank = 2 Row = 547, Col = 135, Data = f6c38eed
|
# READ STATUS: Burst-No: 5 Addr: 00223a0e Rxd: 2ac2d555
|
# READ STATUS: Burst-No: 5 Addr: 00223a0e Rxd: 2ac2d555
|
# tb_core.u_sdram32 : at time 26263.0 ns READ : Bank = 2 Row = 547, Col = 136, Data = 158b2b2b
|
# tb_core.u_sdram32 : at time 26803.0 ns READ : Bank = 2 Row = 547, Col = 136, Data = 158b2b2b
|
# READ STATUS: Burst-No: 6 Addr: 00223a10 Rxd: f6c38eed
|
# READ STATUS: Burst-No: 6 Addr: 00223a10 Rxd: f6c38eed
|
# tb_core.u_sdram32 : at time 26273.0 ns READ : Bank = 2 Row = 547, Col = 137, Data = 7ab11bf5
|
# tb_core.u_sdram32 : at time 26813.0 ns READ : Bank = 2 Row = 547, Col = 137, Data = 7ab11bf5
|
# READ STATUS: Burst-No: 7 Addr: 00223a12 Rxd: 158b2b2b
|
# READ STATUS: Burst-No: 7 Addr: 00223a12 Rxd: 158b2b2b
|
# tb_core.u_sdram32 : at time 26283.0 ns READ : Bank = 2 Row = 547, Col = 138, Data = 56b403ad
|
# tb_core.u_sdram32 : at time 26823.0 ns READ : Bank = 2 Row = 547, Col = 138, Data = 56b403ad
|
# READ STATUS: Burst-No: 8 Addr: 00223a14 Rxd: 7ab11bf5
|
# READ STATUS: Burst-No: 8 Addr: 00223a14 Rxd: 7ab11bf5
|
# tb_core.u_sdram32 : at time 26293.0 ns READ : Bank = 2 Row = 547, Col = 139, Data = 93c12227
|
# tb_core.u_sdram32 : at time 26833.0 ns READ : Bank = 2 Row = 547, Col = 139, Data = 93c12227
|
# READ STATUS: Burst-No: 9 Addr: 00223a16 Rxd: 56b403ad
|
# READ STATUS: Burst-No: 9 Addr: 00223a16 Rxd: 56b403ad
|
# tb_core.u_sdram32 : at time 26303.0 ns READ : Bank = 2 Row = 547, Col = 140, Data = 4249ff84
|
# tb_core.u_sdram32 : at time 26843.0 ns READ : Bank = 2 Row = 547, Col = 140, Data = 4249ff84
|
# READ STATUS: Burst-No: 10 Addr: 00223a18 Rxd: 93c12227
|
# READ STATUS: Burst-No: 10 Addr: 00223a18 Rxd: 93c12227
|
# tb_core.u_sdram32 : at time 26313.0 ns READ : Bank = 2 Row = 547, Col = 141, Data = d3a8e4a7
|
# tb_core.u_sdram32 : at time 26853.0 ns READ : Bank = 2 Row = 547, Col = 141, Data = d3a8e4a7
|
# READ STATUS: Burst-No: 11 Addr: 00223a1a Rxd: 4249ff84
|
# READ STATUS: Burst-No: 11 Addr: 00223a1a Rxd: 4249ff84
|
# tb_core.u_sdram32 : at time 26323.0 ns READ : Bank = 2 Row = 547, Col = 142, Data = f3d7a6e7
|
# tb_core.u_sdram32 : at time 26863.0 ns READ : Bank = 2 Row = 547, Col = 142, Data = f3d7a6e7
|
# READ STATUS: Burst-No: 12 Addr: 00223a1c Rxd: d3a8e4a7
|
# READ STATUS: Burst-No: 12 Addr: 00223a1c Rxd: d3a8e4a7
|
# tb_core.u_sdram32 : at time 26333.0 ns READ : Bank = 2 Row = 547, Col = 143, Data = dcef90b9
|
# tb_core.u_sdram32 : at time 26873.0 ns READ : Bank = 2 Row = 547, Col = 143, Data = dcef90b9
|
# READ STATUS: Burst-No: 13 Addr: 00223a1e Rxd: f3d7a6e7
|
# READ STATUS: Burst-No: 13 Addr: 00223a1e Rxd: f3d7a6e7
|
# tb_core.u_sdram32 : at time 26343.0 ns READ : Bank = 2 Row = 547, Col = 144, Data = a4da5649
|
# tb_core.u_sdram32 : at time 26883.0 ns READ : Bank = 2 Row = 547, Col = 144, Data = a4da5649
|
# READ STATUS: Burst-No: 14 Addr: 00223a20 Rxd: dcef90b9
|
# READ STATUS: Burst-No: 14 Addr: 00223a20 Rxd: dcef90b9
|
# tb_core.u_sdram32 : at time 26353.0 ns READ : Bank = 2 Row = 547, Col = 145, Data = 6de5bbdb
|
# tb_core.u_sdram32 : at time 26893.0 ns READ : Bank = 2 Row = 547, Col = 145, Data = 6de5bbdb
|
# READ STATUS: Burst-No: 15 Addr: 00223a22 Rxd: a4da5649
|
# READ STATUS: Burst-No: 15 Addr: 00223a22 Rxd: a4da5649
|
# tb_core.u_sdram32 : at time 26363.0 ns READ : Bank = 2 Row = 547, Col = 146, Data = 64ba0fc9
|
# tb_core.u_sdram32 : at time 26903.0 ns READ : Bank = 2 Row = 547, Col = 146, Data = 64ba0fc9
|
# READ STATUS: Burst-No: 16 Addr: 00223a24 Rxd: 6de5bbdb
|
# READ STATUS: Burst-No: 16 Addr: 00223a24 Rxd: 6de5bbdb
|
# tb_core.u_sdram32 : at time 26373.0 ns READ : Bank = 2 Row = 547, Col = 147, Data = 2883b151
|
# tb_core.u_sdram32 : at time 26913.0 ns READ : Bank = 2 Row = 547, Col = 147, Data = 2883b151
|
# READ STATUS: Burst-No: 17 Addr: 00223a26 Rxd: 64ba0fc9
|
# READ STATUS: Burst-No: 17 Addr: 00223a26 Rxd: 64ba0fc9
|
# tb_core.u_sdram32 : at time 26383.0 ns READ : Bank = 2 Row = 547, Col = 148, Data = d0bc5ea1
|
# tb_core.u_sdram32 : at time 26923.0 ns READ : Bank = 2 Row = 547, Col = 148, Data = d0bc5ea1
|
# READ STATUS: Burst-No: 18 Addr: 00223a28 Rxd: 2883b151
|
# READ STATUS: Burst-No: 18 Addr: 00223a28 Rxd: 2883b151
|
# tb_core.u_sdram32 : at time 26393.0 ns READ : Bank = 2 Row = 547, Col = 149, Data = 1546dd2a
|
# tb_core.u_sdram32 : at time 26933.0 ns READ : Bank = 2 Row = 547, Col = 149, Data = 1546dd2a
|
# READ STATUS: Burst-No: 19 Addr: 00223a2a Rxd: d0bc5ea1
|
# READ STATUS: Burst-No: 19 Addr: 00223a2a Rxd: d0bc5ea1
|
# tb_core.u_sdram32 : at time 26403.0 ns READ : Bank = 2 Row = 547, Col = 150, Data = 7d2a45fa
|
# tb_core.u_sdram32 : at time 26943.0 ns READ : Bank = 2 Row = 547, Col = 150, Data = 7d2a45fa
|
# READ STATUS: Burst-No: 20 Addr: 00223a2c Rxd: 1546dd2a
|
# READ STATUS: Burst-No: 20 Addr: 00223a2c Rxd: 1546dd2a
|
# tb_core.u_sdram32 : at time 26413.0 ns READ : Bank = 2 Row = 547, Col = 151, Data = a2e62045
|
# tb_core.u_sdram32 : at time 26953.0 ns READ : Bank = 2 Row = 547, Col = 151, Data = a2e62045
|
# tb_core.u_sdram32 : at time 26417.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 26957.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 21 Addr: 00223a2e Rxd: 7d2a45fa
|
# READ STATUS: Burst-No: 21 Addr: 00223a2e Rxd: 7d2a45fa
|
# tb_core.u_sdram32 : at time 26423.0 ns READ : Bank = 2 Row = 547, Col = 152, Data = 41a10583
|
# tb_core.u_sdram32 : at time 26963.0 ns READ : Bank = 2 Row = 547, Col = 152, Data = 41a10583
|
# READ STATUS: Burst-No: 22 Addr: 00223a30 Rxd: a2e62045
|
# READ STATUS: Burst-No: 22 Addr: 00223a30 Rxd: a2e62045
|
# tb_core.u_sdram32 : at time 26433.0 ns READ : Bank = 2 Row = 547, Col = 153, Data = be75427c
|
# tb_core.u_sdram32 : at time 26973.0 ns READ : Bank = 2 Row = 547, Col = 153, Data = be75427c
|
# READ STATUS: Burst-No: 23 Addr: 00223a32 Rxd: 41a10583
|
# READ STATUS: Burst-No: 23 Addr: 00223a32 Rxd: 41a10583
|
# READ STATUS: Burst-No: 24 Addr: 00223a34 Rxd: be75427c
|
# READ STATUS: Burst-No: 24 Addr: 00223a34 Rxd: be75427c
|
# tb_core.u_sdram32 : at time 26603.0 ns READ : Bank = 1 Row = 97, Col = 28, Data = b455f268
|
# tb_core.u_sdram32 : at time 27147.0 ns ACT : Bank = 1 Row = 97
|
# tb_core.u_sdram32 : at time 26613.0 ns READ : Bank = 1 Row = 97, Col = 29, Data = b7dfaa6f
|
# tb_core.u_sdram32 : at time 27203.0 ns READ : Bank = 1 Row = 97, Col = 28, Data = b455f268
|
|
# tb_core.u_sdram32 : at time 27213.0 ns READ : Bank = 1 Row = 97, Col = 29, Data = b7dfaa6f
|
# READ STATUS: Burst-No: 0 Addr: 00061472 Rxd: b455f268
|
# READ STATUS: Burst-No: 0 Addr: 00061472 Rxd: b455f268
|
# tb_core.u_sdram32 : at time 26623.0 ns READ : Bank = 1 Row = 97, Col = 30, Data = 43460d86
|
# tb_core.u_sdram32 : at time 27223.0 ns READ : Bank = 1 Row = 97, Col = 30, Data = 43460d86
|
# READ STATUS: Burst-No: 1 Addr: 00061474 Rxd: b7dfaa6f
|
# READ STATUS: Burst-No: 1 Addr: 00061474 Rxd: b7dfaa6f
|
# tb_core.u_sdram32 : at time 26633.0 ns READ : Bank = 1 Row = 97, Col = 31, Data = 782321f0
|
# tb_core.u_sdram32 : at time 27233.0 ns READ : Bank = 1 Row = 97, Col = 31, Data = 782321f0
|
# READ STATUS: Burst-No: 2 Addr: 00061476 Rxd: 43460d86
|
# READ STATUS: Burst-No: 2 Addr: 00061476 Rxd: 43460d86
|
# tb_core.u_sdram32 : at time 26643.0 ns READ : Bank = 1 Row = 97, Col = 32, Data = 1c719738
|
# tb_core.u_sdram32 : at time 27243.0 ns READ : Bank = 1 Row = 97, Col = 32, Data = 1c719738
|
# READ STATUS: Burst-No: 3 Addr: 00061478 Rxd: 782321f0
|
# READ STATUS: Burst-No: 3 Addr: 00061478 Rxd: 782321f0
|
# tb_core.u_sdram32 : at time 26653.0 ns READ : Bank = 1 Row = 97, Col = 33, Data = 20769140
|
# tb_core.u_sdram32 : at time 27253.0 ns READ : Bank = 1 Row = 97, Col = 33, Data = 20769140
|
# READ STATUS: Burst-No: 4 Addr: 0006147a Rxd: 1c719738
|
# READ STATUS: Burst-No: 4 Addr: 0006147a Rxd: 1c719738
|
# tb_core.u_sdram32 : at time 26663.0 ns READ : Bank = 1 Row = 97, Col = 34, Data = 94097628
|
# tb_core.u_sdram32 : at time 27263.0 ns READ : Bank = 1 Row = 97, Col = 34, Data = 94097628
|
# READ STATUS: Burst-No: 5 Addr: 0006147c Rxd: 20769140
|
# READ STATUS: Burst-No: 5 Addr: 0006147c Rxd: 20769140
|
# tb_core.u_sdram32 : at time 26673.0 ns READ : Bank = 1 Row = 97, Col = 35, Data = 7b0da9f6
|
# tb_core.u_sdram32 : at time 27273.0 ns READ : Bank = 1 Row = 97, Col = 35, Data = 7b0da9f6
|
# READ STATUS: Burst-No: 6 Addr: 0006147e Rxd: 94097628
|
# READ STATUS: Burst-No: 6 Addr: 0006147e Rxd: 94097628
|
# tb_core.u_sdram32 : at time 26683.0 ns READ : Bank = 1 Row = 97, Col = 36, Data = e2bf1ac5
|
# tb_core.u_sdram32 : at time 27283.0 ns READ : Bank = 1 Row = 97, Col = 36, Data = e2bf1ac5
|
# READ STATUS: Burst-No: 7 Addr: 00061480 Rxd: 7b0da9f6
|
# READ STATUS: Burst-No: 7 Addr: 00061480 Rxd: 7b0da9f6
|
# tb_core.u_sdram32 : at time 26693.0 ns READ : Bank = 1 Row = 97, Col = 37, Data = 602831c0
|
# tb_core.u_sdram32 : at time 27293.0 ns READ : Bank = 1 Row = 97, Col = 37, Data = 602831c0
|
# READ STATUS: Burst-No: 8 Addr: 00061482 Rxd: e2bf1ac5
|
# READ STATUS: Burst-No: 8 Addr: 00061482 Rxd: e2bf1ac5
|
# tb_core.u_sdram32 : at time 26703.0 ns READ : Bank = 1 Row = 97, Col = 38, Data = 3a625f74
|
# tb_core.u_sdram32 : at time 27303.0 ns READ : Bank = 1 Row = 97, Col = 38, Data = 3a625f74
|
# READ STATUS: Burst-No: 9 Addr: 00061484 Rxd: 602831c0
|
# READ STATUS: Burst-No: 9 Addr: 00061484 Rxd: 602831c0
|
# tb_core.u_sdram32 : at time 26713.0 ns READ : Bank = 1 Row = 97, Col = 39, Data = 1cde7139
|
# tb_core.u_sdram32 : at time 27313.0 ns READ : Bank = 1 Row = 97, Col = 39, Data = 1cde7139
|
# READ STATUS: Burst-No: 10 Addr: 00061486 Rxd: 3a625f74
|
# READ STATUS: Burst-No: 10 Addr: 00061486 Rxd: 3a625f74
|
# tb_core.u_sdram32 : at time 26723.0 ns READ : Bank = 1 Row = 97, Col = 40, Data = d86a6ab0
|
# tb_core.u_sdram32 : at time 27323.0 ns READ : Bank = 1 Row = 97, Col = 40, Data = d86a6ab0
|
# READ STATUS: Burst-No: 11 Addr: 00061488 Rxd: 1cde7139
|
# READ STATUS: Burst-No: 11 Addr: 00061488 Rxd: 1cde7139
|
# tb_core.u_sdram32 : at time 26733.0 ns READ : Bank = 1 Row = 97, Col = 41, Data = 1e1c873c
|
# tb_core.u_sdram32 : at time 27333.0 ns READ : Bank = 1 Row = 97, Col = 41, Data = 1e1c873c
|
# READ STATUS: Burst-No: 12 Addr: 0006148a Rxd: d86a6ab0
|
# READ STATUS: Burst-No: 12 Addr: 0006148a Rxd: d86a6ab0
|
# tb_core.u_sdram32 : at time 26743.0 ns READ : Bank = 1 Row = 97, Col = 42, Data = 1521932a
|
# tb_core.u_sdram32 : at time 27343.0 ns READ : Bank = 1 Row = 97, Col = 42, Data = 1521932a
|
# READ STATUS: Burst-No: 13 Addr: 0006148c Rxd: 1e1c873c
|
# READ STATUS: Burst-No: 13 Addr: 0006148c Rxd: 1e1c873c
|
# tb_core.u_sdram32 : at time 26753.0 ns READ : Bank = 1 Row = 97, Col = 43, Data = 3124d362
|
# tb_core.u_sdram32 : at time 27353.0 ns READ : Bank = 1 Row = 97, Col = 43, Data = 3124d362
|
# READ STATUS: Burst-No: 14 Addr: 0006148e Rxd: 1521932a
|
# READ STATUS: Burst-No: 14 Addr: 0006148e Rxd: 1521932a
|
# tb_core.u_sdram32 : at time 26763.0 ns READ : Bank = 1 Row = 97, Col = 44, Data = 0aec3515
|
# tb_core.u_sdram32 : at time 27363.0 ns READ : Bank = 1 Row = 97, Col = 44, Data = 0aec3515
|
# READ STATUS: Burst-No: 15 Addr: 00061490 Rxd: 3124d362
|
# READ STATUS: Burst-No: 15 Addr: 00061490 Rxd: 3124d362
|
# tb_core.u_sdram32 : at time 26773.0 ns READ : Bank = 1 Row = 97, Col = 45, Data = f0b14ee1
|
# tb_core.u_sdram32 : at time 27373.0 ns READ : Bank = 1 Row = 97, Col = 45, Data = f0b14ee1
|
# READ STATUS: Burst-No: 16 Addr: 00061492 Rxd: 0aec3515
|
# READ STATUS: Burst-No: 16 Addr: 00061492 Rxd: 0aec3515
|
# tb_core.u_sdram32 : at time 26783.0 ns READ : Bank = 1 Row = 97, Col = 46, Data = 0be29d17
|
# tb_core.u_sdram32 : at time 27383.0 ns READ : Bank = 1 Row = 97, Col = 46, Data = 0be29d17
|
# READ STATUS: Burst-No: 17 Addr: 00061494 Rxd: f0b14ee1
|
# READ STATUS: Burst-No: 17 Addr: 00061494 Rxd: f0b14ee1
|
# tb_core.u_sdram32 : at time 26793.0 ns READ : Bank = 1 Row = 97, Col = 47, Data = a18bee43
|
# tb_core.u_sdram32 : at time 27393.0 ns READ : Bank = 1 Row = 97, Col = 47, Data = a18bee43
|
# READ STATUS: Burst-No: 18 Addr: 00061496 Rxd: 0be29d17
|
# READ STATUS: Burst-No: 18 Addr: 00061496 Rxd: 0be29d17
|
# tb_core.u_sdram32 : at time 26803.0 ns READ : Bank = 1 Row = 97, Col = 48, Data = 64b5e3c9
|
# tb_core.u_sdram32 : at time 27403.0 ns READ : Bank = 1 Row = 97, Col = 48, Data = 64b5e3c9
|
# READ STATUS: Burst-No: 19 Addr: 00061498 Rxd: a18bee43
|
# READ STATUS: Burst-No: 19 Addr: 00061498 Rxd: a18bee43
|
# tb_core.u_sdram32 : at time 26813.0 ns READ : Bank = 1 Row = 97, Col = 49, Data = c3360486
|
# tb_core.u_sdram32 : at time 27413.0 ns READ : Bank = 1 Row = 97, Col = 49, Data = c3360486
|
# READ STATUS: Burst-No: 20 Addr: 0006149a Rxd: 64b5e3c9
|
# READ STATUS: Burst-No: 20 Addr: 0006149a Rxd: 64b5e3c9
|
# tb_core.u_sdram32 : at time 26823.0 ns READ : Bank = 1 Row = 97, Col = 50, Data = 1297cb25
|
# tb_core.u_sdram32 : at time 27423.0 ns READ : Bank = 1 Row = 97, Col = 50, Data = 1297cb25
|
# READ STATUS: Burst-No: 21 Addr: 0006149c Rxd: c3360486
|
# READ STATUS: Burst-No: 21 Addr: 0006149c Rxd: c3360486
|
# tb_core.u_sdram32 : at time 26833.0 ns READ : Bank = 1 Row = 97, Col = 51, Data = 60f69dc1
|
# tb_core.u_sdram32 : at time 27433.0 ns READ : Bank = 1 Row = 97, Col = 51, Data = 60f69dc1
|
# READ STATUS: Burst-No: 22 Addr: 0006149e Rxd: 1297cb25
|
# READ STATUS: Burst-No: 22 Addr: 0006149e Rxd: 1297cb25
|
# tb_core.u_sdram32 : at time 26843.0 ns READ : Bank = 1 Row = 97, Col = 52, Data = c69da28d
|
# tb_core.u_sdram32 : at time 27443.0 ns READ : Bank = 1 Row = 97, Col = 52, Data = c69da28d
|
# READ STATUS: Burst-No: 23 Addr: 000614a0 Rxd: 60f69dc1
|
# READ STATUS: Burst-No: 23 Addr: 000614a0 Rxd: 60f69dc1
|
# tb_core.u_sdram32 : at time 26853.0 ns READ : Bank = 1 Row = 97, Col = 53, Data = ad67e25a
|
# tb_core.u_sdram32 : at time 27453.0 ns READ : Bank = 1 Row = 97, Col = 53, Data = ad67e25a
|
# READ STATUS: Burst-No: 24 Addr: 000614a2 Rxd: c69da28d
|
# READ STATUS: Burst-No: 24 Addr: 000614a2 Rxd: c69da28d
|
# tb_core.u_sdram32 : at time 26863.0 ns READ : Bank = 1 Row = 97, Col = 54, Data = 03d62707
|
# tb_core.u_sdram32 : at time 27463.0 ns READ : Bank = 1 Row = 97, Col = 54, Data = 03d62707
|
# READ STATUS: Burst-No: 25 Addr: 000614a4 Rxd: ad67e25a
|
# READ STATUS: Burst-No: 25 Addr: 000614a4 Rxd: ad67e25a
|
# tb_core.u_sdram32 : at time 26873.0 ns READ : Bank = 1 Row = 97, Col = 55, Data = 165b7b2c
|
# tb_core.u_sdram32 : at time 27473.0 ns READ : Bank = 1 Row = 97, Col = 55, Data = 165b7b2c
|
# READ STATUS: Burst-No: 26 Addr: 000614a6 Rxd: 03d62707
|
# READ STATUS: Burst-No: 26 Addr: 000614a6 Rxd: 03d62707
|
# tb_core.u_sdram32 : at time 26883.0 ns READ : Bank = 1 Row = 97, Col = 56, Data = 060a5d0c
|
# tb_core.u_sdram32 : at time 27483.0 ns READ : Bank = 1 Row = 97, Col = 56, Data = 060a5d0c
|
# READ STATUS: Burst-No: 27 Addr: 000614a8 Rxd: 165b7b2c
|
# READ STATUS: Burst-No: 27 Addr: 000614a8 Rxd: 165b7b2c
|
# tb_core.u_sdram32 : at time 26893.0 ns READ : Bank = 1 Row = 97, Col = 57, Data = b8ade671
|
# tb_core.u_sdram32 : at time 27493.0 ns READ : Bank = 1 Row = 97, Col = 57, Data = b8ade671
|
# READ STATUS: Burst-No: 28 Addr: 000614aa Rxd: 060a5d0c
|
# READ STATUS: Burst-No: 28 Addr: 000614aa Rxd: 060a5d0c
|
# tb_core.u_sdram32 : at time 26903.0 ns READ : Bank = 1 Row = 97, Col = 58, Data = 9de17c3b
|
# tb_core.u_sdram32 : at time 27503.0 ns READ : Bank = 1 Row = 97, Col = 58, Data = 9de17c3b
|
# READ STATUS: Burst-No: 29 Addr: 000614ac Rxd: b8ade671
|
# READ STATUS: Burst-No: 29 Addr: 000614ac Rxd: b8ade671
|
# tb_core.u_sdram32 : at time 26913.0 ns READ : Bank = 1 Row = 97, Col = 59, Data = 5b60e5b6
|
# tb_core.u_sdram32 : at time 27513.0 ns READ : Bank = 1 Row = 97, Col = 59, Data = 5b60e5b6
|
# READ STATUS: Burst-No: 30 Addr: 000614ae Rxd: 9de17c3b
|
# READ STATUS: Burst-No: 30 Addr: 000614ae Rxd: 9de17c3b
|
# tb_core.u_sdram32 : at time 26923.0 ns READ : Bank = 1 Row = 97, Col = 60, Data = fbdfc2f7
|
# tb_core.u_sdram32 : at time 27523.0 ns READ : Bank = 1 Row = 97, Col = 60, Data = fbdfc2f7
|
# READ STATUS: Burst-No: 31 Addr: 000614b0 Rxd: 5b60e5b6
|
# READ STATUS: Burst-No: 31 Addr: 000614b0 Rxd: 5b60e5b6
|
# tb_core.u_sdram32 : at time 26933.0 ns READ : Bank = 1 Row = 97, Col = 61, Data = cf14ce9e
|
# tb_core.u_sdram32 : at time 27533.0 ns READ : Bank = 1 Row = 97, Col = 61, Data = cf14ce9e
|
# READ STATUS: Burst-No: 32 Addr: 000614b2 Rxd: fbdfc2f7
|
# READ STATUS: Burst-No: 32 Addr: 000614b2 Rxd: fbdfc2f7
|
# tb_core.u_sdram32 : at time 26943.0 ns READ : Bank = 1 Row = 97, Col = 62, Data = ae78585c
|
# tb_core.u_sdram32 : at time 27543.0 ns READ : Bank = 1 Row = 97, Col = 62, Data = ae78585c
|
# READ STATUS: Burst-No: 33 Addr: 000614b4 Rxd: cf14ce9e
|
# READ STATUS: Burst-No: 33 Addr: 000614b4 Rxd: cf14ce9e
|
# tb_core.u_sdram32 : at time 26953.0 ns READ : Bank = 1 Row = 97, Col = 63, Data = 2ab8f755
|
# tb_core.u_sdram32 : at time 27553.0 ns READ : Bank = 1 Row = 97, Col = 63, Data = 2ab8f755
|
# READ STATUS: Burst-No: 34 Addr: 000614b6 Rxd: ae78585c
|
# READ STATUS: Burst-No: 34 Addr: 000614b6 Rxd: ae78585c
|
# tb_core.u_sdram32 : at time 26963.0 ns READ : Bank = 1 Row = 97, Col = 64, Data = 902a3a20
|
# tb_core.u_sdram32 : at time 27563.0 ns READ : Bank = 1 Row = 97, Col = 64, Data = 902a3a20
|
# READ STATUS: Burst-No: 35 Addr: 000614b8 Rxd: 2ab8f755
|
# READ STATUS: Burst-No: 35 Addr: 000614b8 Rxd: 2ab8f755
|
# tb_core.u_sdram32 : at time 26973.0 ns READ : Bank = 1 Row = 97, Col = 65, Data = d00b12a0
|
# tb_core.u_sdram32 : at time 27573.0 ns READ : Bank = 1 Row = 97, Col = 65, Data = d00b12a0
|
# READ STATUS: Burst-No: 36 Addr: 000614ba Rxd: 902a3a20
|
# READ STATUS: Burst-No: 36 Addr: 000614ba Rxd: 902a3a20
|
# tb_core.u_sdram32 : at time 26983.0 ns READ : Bank = 1 Row = 97, Col = 66, Data = 39600972
|
# tb_core.u_sdram32 : at time 27583.0 ns READ : Bank = 1 Row = 97, Col = 66, Data = 39600972
|
# READ STATUS: Burst-No: 37 Addr: 000614bc Rxd: d00b12a0
|
# READ STATUS: Burst-No: 37 Addr: 000614bc Rxd: d00b12a0
|
# tb_core.u_sdram32 : at time 26993.0 ns READ : Bank = 1 Row = 97, Col = 67, Data = da3d8cb4
|
# tb_core.u_sdram32 : at time 27593.0 ns READ : Bank = 1 Row = 97, Col = 67, Data = da3d8cb4
|
# READ STATUS: Burst-No: 38 Addr: 000614be Rxd: 39600972
|
# READ STATUS: Burst-No: 38 Addr: 000614be Rxd: 39600972
|
# tb_core.u_sdram32 : at time 27003.0 ns READ : Bank = 1 Row = 97, Col = 68, Data = 6e8af5dd
|
# tb_core.u_sdram32 : at time 27603.0 ns READ : Bank = 1 Row = 97, Col = 68, Data = 6e8af5dd
|
# READ STATUS: Burst-No: 39 Addr: 000614c0 Rxd: da3d8cb4
|
# READ STATUS: Burst-No: 39 Addr: 000614c0 Rxd: da3d8cb4
|
# tb_core.u_sdram32 : at time 27013.0 ns READ : Bank = 1 Row = 97, Col = 69, Data = 86dcf00d
|
# tb_core.u_sdram32 : at time 27613.0 ns READ : Bank = 1 Row = 97, Col = 69, Data = 86dcf00d
|
# READ STATUS: Burst-No: 40 Addr: 000614c2 Rxd: 6e8af5dd
|
# READ STATUS: Burst-No: 40 Addr: 000614c2 Rxd: 6e8af5dd
|
# tb_core.u_sdram32 : at time 27023.0 ns READ : Bank = 1 Row = 97, Col = 70, Data = 25b0994b
|
# tb_core.u_sdram32 : at time 27623.0 ns READ : Bank = 1 Row = 97, Col = 70, Data = 25b0994b
|
# READ STATUS: Burst-No: 41 Addr: 000614c4 Rxd: 86dcf00d
|
# READ STATUS: Burst-No: 41 Addr: 000614c4 Rxd: 86dcf00d
|
# tb_core.u_sdram32 : at time 27033.0 ns READ : Bank = 1 Row = 97, Col = 71, Data = bccc4279
|
# tb_core.u_sdram32 : at time 27633.0 ns READ : Bank = 1 Row = 97, Col = 71, Data = bccc4279
|
# READ STATUS: Burst-No: 42 Addr: 000614c6 Rxd: 25b0994b
|
# READ STATUS: Burst-No: 42 Addr: 000614c6 Rxd: 25b0994b
|
# tb_core.u_sdram32 : at time 27043.0 ns READ : Bank = 1 Row = 97, Col = 72, Data = cf63da9e
|
# tb_core.u_sdram32 : at time 27643.0 ns READ : Bank = 1 Row = 97, Col = 72, Data = cf63da9e
|
# READ STATUS: Burst-No: 43 Addr: 000614c8 Rxd: bccc4279
|
# READ STATUS: Burst-No: 43 Addr: 000614c8 Rxd: bccc4279
|
# tb_core.u_sdram32 : at time 27053.0 ns READ : Bank = 1 Row = 97, Col = 73, Data = fef064fd
|
# tb_core.u_sdram32 : at time 27653.0 ns READ : Bank = 1 Row = 97, Col = 73, Data = fef064fd
|
# READ STATUS: Burst-No: 44 Addr: 000614ca Rxd: cf63da9e
|
# READ STATUS: Burst-No: 44 Addr: 000614ca Rxd: cf63da9e
|
# tb_core.u_sdram32 : at time 27063.0 ns READ : Bank = 1 Row = 97, Col = 74, Data = bde0d27b
|
# tb_core.u_sdram32 : at time 27663.0 ns READ : Bank = 1 Row = 97, Col = 74, Data = bde0d27b
|
# READ STATUS: Burst-No: 45 Addr: 000614cc Rxd: fef064fd
|
# READ STATUS: Burst-No: 45 Addr: 000614cc Rxd: fef064fd
|
# tb_core.u_sdram32 : at time 27073.0 ns READ : Bank = 1 Row = 97, Col = 75, Data = 47e2738f
|
# tb_core.u_sdram32 : at time 27673.0 ns READ : Bank = 1 Row = 97, Col = 75, Data = 47e2738f
|
# READ STATUS: Burst-No: 46 Addr: 000614ce Rxd: bde0d27b
|
# READ STATUS: Burst-No: 46 Addr: 000614ce Rxd: bde0d27b
|
# tb_core.u_sdram32 : at time 27083.0 ns READ : Bank = 1 Row = 97, Col = 76, Data = 81c39a03
|
# tb_core.u_sdram32 : at time 27683.0 ns READ : Bank = 1 Row = 97, Col = 76, Data = 81c39a03
|
# READ STATUS: Burst-No: 47 Addr: 000614d0 Rxd: 47e2738f
|
# READ STATUS: Burst-No: 47 Addr: 000614d0 Rxd: 47e2738f
|
# tb_core.u_sdram32 : at time 27093.0 ns READ : Bank = 1 Row = 97, Col = 77, Data = 71c129e3
|
# tb_core.u_sdram32 : at time 27693.0 ns READ : Bank = 1 Row = 97, Col = 77, Data = 71c129e3
|
# READ STATUS: Burst-No: 48 Addr: 000614d2 Rxd: 81c39a03
|
# READ STATUS: Burst-No: 48 Addr: 000614d2 Rxd: 81c39a03
|
# tb_core.u_sdram32 : at time 27103.0 ns READ : Bank = 1 Row = 97, Col = 78, Data = 0e92431d
|
# tb_core.u_sdram32 : at time 27703.0 ns READ : Bank = 1 Row = 97, Col = 78, Data = 0e92431d
|
# READ STATUS: Burst-No: 49 Addr: 000614d4 Rxd: 71c129e3
|
# READ STATUS: Burst-No: 49 Addr: 000614d4 Rxd: 71c129e3
|
# tb_core.u_sdram32 : at time 27113.0 ns READ : Bank = 1 Row = 97, Col = 79, Data = 58f93db1
|
# tb_core.u_sdram32 : at time 27713.0 ns READ : Bank = 1 Row = 97, Col = 79, Data = 58f93db1
|
# READ STATUS: Burst-No: 50 Addr: 000614d6 Rxd: 0e92431d
|
# READ STATUS: Burst-No: 50 Addr: 000614d6 Rxd: 0e92431d
|
# tb_core.u_sdram32 : at time 27123.0 ns READ : Bank = 1 Row = 97, Col = 80, Data = 22119f44
|
# tb_core.u_sdram32 : at time 27723.0 ns READ : Bank = 1 Row = 97, Col = 80, Data = 22119f44
|
# READ STATUS: Burst-No: 51 Addr: 000614d8 Rxd: 58f93db1
|
# READ STATUS: Burst-No: 51 Addr: 000614d8 Rxd: 58f93db1
|
# tb_core.u_sdram32 : at time 27133.0 ns READ : Bank = 1 Row = 97, Col = 81, Data = ca9cbc95
|
# tb_core.u_sdram32 : at time 27733.0 ns READ : Bank = 1 Row = 97, Col = 81, Data = ca9cbc95
|
# READ STATUS: Burst-No: 52 Addr: 000614da Rxd: 22119f44
|
# READ STATUS: Burst-No: 52 Addr: 000614da Rxd: 22119f44
|
# tb_core.u_sdram32 : at time 27143.0 ns READ : Bank = 1 Row = 97, Col = 82, Data = f01d34e0
|
# tb_core.u_sdram32 : at time 27743.0 ns READ : Bank = 1 Row = 97, Col = 82, Data = f01d34e0
|
# READ STATUS: Burst-No: 53 Addr: 000614dc Rxd: ca9cbc95
|
# READ STATUS: Burst-No: 53 Addr: 000614dc Rxd: ca9cbc95
|
# tb_core.u_sdram32 : at time 27153.0 ns READ : Bank = 1 Row = 97, Col = 83, Data = f6a178ed
|
# tb_core.u_sdram32 : at time 27753.0 ns READ : Bank = 1 Row = 97, Col = 83, Data = f6a178ed
|
# READ STATUS: Burst-No: 54 Addr: 000614de Rxd: f01d34e0
|
# READ STATUS: Burst-No: 54 Addr: 000614de Rxd: f01d34e0
|
# tb_core.u_sdram32 : at time 27163.0 ns READ : Bank = 1 Row = 97, Col = 84, Data = 297a1552
|
# tb_core.u_sdram32 : at time 27763.0 ns READ : Bank = 1 Row = 97, Col = 84, Data = 297a1552
|
# READ STATUS: Burst-No: 55 Addr: 000614e0 Rxd: f6a178ed
|
# READ STATUS: Burst-No: 55 Addr: 000614e0 Rxd: f6a178ed
|
# tb_core.u_sdram32 : at time 27173.0 ns READ : Bank = 1 Row = 97, Col = 85, Data = 7c1e5bf8
|
# tb_core.u_sdram32 : at time 27773.0 ns READ : Bank = 1 Row = 97, Col = 85, Data = 7c1e5bf8
|
# READ STATUS: Burst-No: 56 Addr: 000614e2 Rxd: 297a1552
|
# READ STATUS: Burst-No: 56 Addr: 000614e2 Rxd: 297a1552
|
# tb_core.u_sdram32 : at time 27183.0 ns READ : Bank = 1 Row = 97, Col = 86, Data = 46dcb78d
|
# tb_core.u_sdram32 : at time 27783.0 ns READ : Bank = 1 Row = 97, Col = 86, Data = 46dcb78d
|
# READ STATUS: Burst-No: 57 Addr: 000614e4 Rxd: 7c1e5bf8
|
# READ STATUS: Burst-No: 57 Addr: 000614e4 Rxd: 7c1e5bf8
|
# tb_core.u_sdram32 : at time 27193.0 ns READ : Bank = 1 Row = 97, Col = 87, Data = a95fc452
|
# tb_core.u_sdram32 : at time 27793.0 ns READ : Bank = 1 Row = 97, Col = 87, Data = a95fc452
|
# READ STATUS: Burst-No: 58 Addr: 000614e6 Rxd: 46dcb78d
|
# READ STATUS: Burst-No: 58 Addr: 000614e6 Rxd: 46dcb78d
|
# tb_core.u_sdram32 : at time 27203.0 ns READ : Bank = 1 Row = 97, Col = 88, Data = 4219e784
|
# tb_core.u_sdram32 : at time 27803.0 ns READ : Bank = 1 Row = 97, Col = 88, Data = 4219e784
|
# tb_core.u_sdram32 : at time 27207.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 27807.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 59 Addr: 000614e8 Rxd: a95fc452
|
# READ STATUS: Burst-No: 59 Addr: 000614e8 Rxd: a95fc452
|
# tb_core.u_sdram32 : at time 27213.0 ns READ : Bank = 1 Row = 97, Col = 89, Data = 236afd46
|
# tb_core.u_sdram32 : at time 27813.0 ns READ : Bank = 1 Row = 97, Col = 89, Data = 236afd46
|
# READ STATUS: Burst-No: 60 Addr: 000614ea Rxd: 4219e784
|
# READ STATUS: Burst-No: 60 Addr: 000614ea Rxd: 4219e784
|
# tb_core.u_sdram32 : at time 27223.0 ns READ : Bank = 1 Row = 97, Col = 90, Data = c63a928c
|
# tb_core.u_sdram32 : at time 27823.0 ns READ : Bank = 1 Row = 97, Col = 90, Data = c63a928c
|
# READ STATUS: Burst-No: 61 Addr: 000614ec Rxd: 236afd46
|
# READ STATUS: Burst-No: 61 Addr: 000614ec Rxd: 236afd46
|
# READ STATUS: Burst-No: 62 Addr: 000614ee Rxd: c63a928c
|
# READ STATUS: Burst-No: 62 Addr: 000614ee Rxd: c63a928c
|
# Write Address: 00087d90, Burst Size: 24
|
# Write Address: 00087d90, Burst Size: 24
|
# tb_core.u_sdram32 : at time 27397.0 ns ACT : Bank = 3 Row = 135
|
# tb_core.u_sdram32 : at time 27997.0 ns ACT : Bank = 3 Row = 135
|
# tb_core.u_sdram32 : at time 27427.0 ns WRITE: Bank = 3 Row = 135, Col = 100, Data = 352d616a
|
# tb_core.u_sdram32 : at time 28027.0 ns WRITE: Bank = 3 Row = 135, Col = 100, Data = 352d616a
|
# Status: Burst-No: 0 Write Address: 00087d90 WriteData: 352d616a
|
# Status: Burst-No: 0 Write Address: 00087d90 WriteData: 352d616a
|
# tb_core.u_sdram32 : at time 27437.0 ns WRITE: Bank = 3 Row = 135, Col = 101, Data = 427b5784
|
# tb_core.u_sdram32 : at time 28037.0 ns WRITE: Bank = 3 Row = 135, Col = 101, Data = 427b5784
|
# Status: Burst-No: 1 Write Address: 00087d90 WriteData: 427b5784
|
# Status: Burst-No: 1 Write Address: 00087d90 WriteData: 427b5784
|
# tb_core.u_sdram32 : at time 27447.0 ns WRITE: Bank = 3 Row = 135, Col = 102, Data = d55bbcaa
|
# tb_core.u_sdram32 : at time 28047.0 ns WRITE: Bank = 3 Row = 135, Col = 102, Data = d55bbcaa
|
# Status: Burst-No: 2 Write Address: 00087d90 WriteData: d55bbcaa
|
# Status: Burst-No: 2 Write Address: 00087d90 WriteData: d55bbcaa
|
# tb_core.u_sdram32 : at time 27457.0 ns WRITE: Bank = 3 Row = 135, Col = 103, Data = 3e6f0f7c
|
# tb_core.u_sdram32 : at time 28057.0 ns WRITE: Bank = 3 Row = 135, Col = 103, Data = 3e6f0f7c
|
# Status: Burst-No: 3 Write Address: 00087d90 WriteData: 3e6f0f7c
|
# Status: Burst-No: 3 Write Address: 00087d90 WriteData: 3e6f0f7c
|
# tb_core.u_sdram32 : at time 27467.0 ns WRITE: Bank = 3 Row = 135, Col = 104, Data = b0520260
|
# tb_core.u_sdram32 : at time 28067.0 ns WRITE: Bank = 3 Row = 135, Col = 104, Data = b0520260
|
# Status: Burst-No: 4 Write Address: 00087d90 WriteData: b0520260
|
# Status: Burst-No: 4 Write Address: 00087d90 WriteData: b0520260
|
# tb_core.u_sdram32 : at time 27477.0 ns WRITE: Bank = 3 Row = 135, Col = 105, Data = 5d4a4dba
|
# tb_core.u_sdram32 : at time 28077.0 ns WRITE: Bank = 3 Row = 135, Col = 105, Data = 5d4a4dba
|
# Status: Burst-No: 5 Write Address: 00087d90 WriteData: 5d4a4dba
|
# Status: Burst-No: 5 Write Address: 00087d90 WriteData: 5d4a4dba
|
# tb_core.u_sdram32 : at time 27487.0 ns WRITE: Bank = 3 Row = 135, Col = 106, Data = c5a1608b
|
# tb_core.u_sdram32 : at time 28087.0 ns WRITE: Bank = 3 Row = 135, Col = 106, Data = c5a1608b
|
# Status: Burst-No: 6 Write Address: 00087d90 WriteData: c5a1608b
|
# Status: Burst-No: 6 Write Address: 00087d90 WriteData: c5a1608b
|
# tb_core.u_sdram32 : at time 27497.0 ns WRITE: Bank = 3 Row = 135, Col = 107, Data = d31dfea6
|
# tb_core.u_sdram32 : at time 28097.0 ns WRITE: Bank = 3 Row = 135, Col = 107, Data = d31dfea6
|
# Status: Burst-No: 7 Write Address: 00087d90 WriteData: d31dfea6
|
# Status: Burst-No: 7 Write Address: 00087d90 WriteData: d31dfea6
|
# tb_core.u_sdram32 : at time 27507.0 ns WRITE: Bank = 3 Row = 135, Col = 108, Data = 92831e25
|
# tb_core.u_sdram32 : at time 28107.0 ns WRITE: Bank = 3 Row = 135, Col = 108, Data = 92831e25
|
# Status: Burst-No: 8 Write Address: 00087d90 WriteData: 92831e25
|
# Status: Burst-No: 8 Write Address: 00087d90 WriteData: 92831e25
|
# tb_core.u_sdram32 : at time 27517.0 ns WRITE: Bank = 3 Row = 135, Col = 109, Data = 19058332
|
# tb_core.u_sdram32 : at time 28117.0 ns WRITE: Bank = 3 Row = 135, Col = 109, Data = 19058332
|
# Status: Burst-No: 9 Write Address: 00087d90 WriteData: 19058332
|
# Status: Burst-No: 9 Write Address: 00087d90 WriteData: 19058332
|
# tb_core.u_sdram32 : at time 27527.0 ns WRITE: Bank = 3 Row = 135, Col = 110, Data = d10504a2
|
# tb_core.u_sdram32 : at time 28127.0 ns WRITE: Bank = 3 Row = 135, Col = 110, Data = d10504a2
|
# Status: Burst-No: 10 Write Address: 00087d90 WriteData: d10504a2
|
# Status: Burst-No: 10 Write Address: 00087d90 WriteData: d10504a2
|
# tb_core.u_sdram32 : at time 27537.0 ns WRITE: Bank = 3 Row = 135, Col = 111, Data = a48f7c49
|
# tb_core.u_sdram32 : at time 28137.0 ns WRITE: Bank = 3 Row = 135, Col = 111, Data = a48f7c49
|
# Status: Burst-No: 11 Write Address: 00087d90 WriteData: a48f7c49
|
# Status: Burst-No: 11 Write Address: 00087d90 WriteData: a48f7c49
|
# tb_core.u_sdram32 : at time 27547.0 ns WRITE: Bank = 3 Row = 135, Col = 112, Data = 8a64b014
|
# tb_core.u_sdram32 : at time 28147.0 ns WRITE: Bank = 3 Row = 135, Col = 112, Data = 8a64b014
|
# Status: Burst-No: 12 Write Address: 00087d90 WriteData: 8a64b014
|
# Status: Burst-No: 12 Write Address: 00087d90 WriteData: 8a64b014
|
# tb_core.u_sdram32 : at time 27557.0 ns WRITE: Bank = 3 Row = 135, Col = 113, Data = 9ec9c03d
|
# tb_core.u_sdram32 : at time 28157.0 ns WRITE: Bank = 3 Row = 135, Col = 113, Data = 9ec9c03d
|
# Status: Burst-No: 13 Write Address: 00087d90 WriteData: 9ec9c03d
|
# Status: Burst-No: 13 Write Address: 00087d90 WriteData: 9ec9c03d
|
# tb_core.u_sdram32 : at time 27567.0 ns WRITE: Bank = 3 Row = 135, Col = 114, Data = 25f2034b
|
# tb_core.u_sdram32 : at time 28167.0 ns WRITE: Bank = 3 Row = 135, Col = 114, Data = 25f2034b
|
# Status: Burst-No: 14 Write Address: 00087d90 WriteData: 25f2034b
|
# Status: Burst-No: 14 Write Address: 00087d90 WriteData: 25f2034b
|
# tb_core.u_sdram32 : at time 27577.0 ns WRITE: Bank = 3 Row = 135, Col = 115, Data = ae68305c
|
# tb_core.u_sdram32 : at time 28177.0 ns WRITE: Bank = 3 Row = 135, Col = 115, Data = ae68305c
|
# Status: Burst-No: 15 Write Address: 00087d90 WriteData: ae68305c
|
# Status: Burst-No: 15 Write Address: 00087d90 WriteData: ae68305c
|
# tb_core.u_sdram32 : at time 27587.0 ns WRITE: Bank = 3 Row = 135, Col = 116, Data = 23907547
|
# tb_core.u_sdram32 : at time 28187.0 ns WRITE: Bank = 3 Row = 135, Col = 116, Data = 23907547
|
# Status: Burst-No: 16 Write Address: 00087d90 WriteData: 23907547
|
# Status: Burst-No: 16 Write Address: 00087d90 WriteData: 23907547
|
# tb_core.u_sdram32 : at time 27597.0 ns WRITE: Bank = 3 Row = 135, Col = 117, Data = 433e9786
|
# tb_core.u_sdram32 : at time 28197.0 ns WRITE: Bank = 3 Row = 135, Col = 117, Data = 433e9786
|
# Status: Burst-No: 17 Write Address: 00087d90 WriteData: 433e9786
|
# Status: Burst-No: 17 Write Address: 00087d90 WriteData: 433e9786
|
# tb_core.u_sdram32 : at time 27607.0 ns WRITE: Bank = 3 Row = 135, Col = 118, Data = 9caf7a39
|
# tb_core.u_sdram32 : at time 28207.0 ns WRITE: Bank = 3 Row = 135, Col = 118, Data = 9caf7a39
|
# Status: Burst-No: 18 Write Address: 00087d90 WriteData: 9caf7a39
|
# Status: Burst-No: 18 Write Address: 00087d90 WriteData: 9caf7a39
|
# tb_core.u_sdram32 : at time 27617.0 ns WRITE: Bank = 3 Row = 135, Col = 119, Data = da058ab4
|
# tb_core.u_sdram32 : at time 28217.0 ns WRITE: Bank = 3 Row = 135, Col = 119, Data = da058ab4
|
# Status: Burst-No: 19 Write Address: 00087d90 WriteData: da058ab4
|
# Status: Burst-No: 19 Write Address: 00087d90 WriteData: da058ab4
|
# tb_core.u_sdram32 : at time 27627.0 ns WRITE: Bank = 3 Row = 135, Col = 120, Data = 6851e5d0
|
# tb_core.u_sdram32 : at time 28227.0 ns WRITE: Bank = 3 Row = 135, Col = 120, Data = 6851e5d0
|
# Status: Burst-No: 20 Write Address: 00087d90 WriteData: 6851e5d0
|
# Status: Burst-No: 20 Write Address: 00087d90 WriteData: 6851e5d0
|
# tb_core.u_sdram32 : at time 27637.0 ns WRITE: Bank = 3 Row = 135, Col = 121, Data = 9622502c
|
# tb_core.u_sdram32 : at time 28237.0 ns WRITE: Bank = 3 Row = 135, Col = 121, Data = 9622502c
|
# Status: Burst-No: 21 Write Address: 00087d90 WriteData: 9622502c
|
# Status: Burst-No: 21 Write Address: 00087d90 WriteData: 9622502c
|
# tb_core.u_sdram32 : at time 27647.0 ns WRITE: Bank = 3 Row = 135, Col = 122, Data = 467c458c
|
# tb_core.u_sdram32 : at time 28247.0 ns WRITE: Bank = 3 Row = 135, Col = 122, Data = 467c458c
|
# Status: Burst-No: 22 Write Address: 00087d90 WriteData: 467c458c
|
# Status: Burst-No: 22 Write Address: 00087d90 WriteData: 467c458c
|
# tb_core.u_sdram32 : at time 27657.0 ns WRITE: Bank = 3 Row = 135, Col = 123, Data = 03e9b707
|
# tb_core.u_sdram32 : at time 28257.0 ns WRITE: Bank = 3 Row = 135, Col = 123, Data = 03e9b707
|
# Status: Burst-No: 23 Write Address: 00087d90 WriteData: 03e9b707
|
# Status: Burst-No: 23 Write Address: 00087d90 WriteData: 03e9b707
|
# tb_core.u_sdram32 : at time 27667.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 28267.0 ns BST : Burst Terminate
|
# Write Address: 0022406a, Burst Size: 18
|
# Write Address: 0022406a, Burst Size: 18
|
# tb_core.u_sdram32 : at time 27807.0 ns ACT : Bank = 0 Row = 548
|
# tb_core.u_sdram32 : at time 28407.0 ns ACT : Bank = 0 Row = 548
|
# tb_core.u_sdram32 : at time 27837.0 ns WRITE: Bank = 0 Row = 548, Col = 26, Data = 746affe8
|
# tb_core.u_sdram32 : at time 28437.0 ns WRITE: Bank = 0 Row = 548, Col = 26, Data = 746affe8
|
# Status: Burst-No: 0 Write Address: 0022406a WriteData: 746affe8
|
# Status: Burst-No: 0 Write Address: 0022406a WriteData: 746affe8
|
# tb_core.u_sdram32 : at time 27847.0 ns WRITE: Bank = 0 Row = 548, Col = 27, Data = a5e79e4b
|
# tb_core.u_sdram32 : at time 28447.0 ns WRITE: Bank = 0 Row = 548, Col = 27, Data = a5e79e4b
|
# Status: Burst-No: 1 Write Address: 0022406a WriteData: a5e79e4b
|
# Status: Burst-No: 1 Write Address: 0022406a WriteData: a5e79e4b
|
# tb_core.u_sdram32 : at time 27857.0 ns WRITE: Bank = 0 Row = 548, Col = 28, Data = 39e48173
|
# tb_core.u_sdram32 : at time 28457.0 ns WRITE: Bank = 0 Row = 548, Col = 28, Data = 39e48173
|
# Status: Burst-No: 2 Write Address: 0022406a WriteData: 39e48173
|
# Status: Burst-No: 2 Write Address: 0022406a WriteData: 39e48173
|
# tb_core.u_sdram32 : at time 27867.0 ns WRITE: Bank = 0 Row = 548, Col = 29, Data = 76295bec
|
# tb_core.u_sdram32 : at time 28467.0 ns WRITE: Bank = 0 Row = 548, Col = 29, Data = 76295bec
|
# Status: Burst-No: 3 Write Address: 0022406a WriteData: 76295bec
|
# Status: Burst-No: 3 Write Address: 0022406a WriteData: 76295bec
|
# tb_core.u_sdram32 : at time 27877.0 ns WRITE: Bank = 0 Row = 548, Col = 30, Data = 11fe0523
|
# tb_core.u_sdram32 : at time 28477.0 ns WRITE: Bank = 0 Row = 548, Col = 30, Data = 11fe0523
|
# Status: Burst-No: 4 Write Address: 0022406a WriteData: 11fe0523
|
# Status: Burst-No: 4 Write Address: 0022406a WriteData: 11fe0523
|
# tb_core.u_sdram32 : at time 27887.0 ns WRITE: Bank = 0 Row = 548, Col = 31, Data = 520eefa4
|
# tb_core.u_sdram32 : at time 28487.0 ns WRITE: Bank = 0 Row = 548, Col = 31, Data = 520eefa4
|
# Status: Burst-No: 5 Write Address: 0022406a WriteData: 520eefa4
|
# Status: Burst-No: 5 Write Address: 0022406a WriteData: 520eefa4
|
# tb_core.u_sdram32 : at time 27897.0 ns WRITE: Bank = 0 Row = 548, Col = 32, Data = 64e165c9
|
# tb_core.u_sdram32 : at time 28497.0 ns WRITE: Bank = 0 Row = 548, Col = 32, Data = 64e165c9
|
# Status: Burst-No: 6 Write Address: 0022406a WriteData: 64e165c9
|
# Status: Burst-No: 6 Write Address: 0022406a WriteData: 64e165c9
|
# tb_core.u_sdram32 : at time 27907.0 ns WRITE: Bank = 0 Row = 548, Col = 33, Data = 9ca70439
|
# tb_core.u_sdram32 : at time 28507.0 ns WRITE: Bank = 0 Row = 548, Col = 33, Data = 9ca70439
|
# Status: Burst-No: 7 Write Address: 0022406a WriteData: 9ca70439
|
# Status: Burst-No: 7 Write Address: 0022406a WriteData: 9ca70439
|
# tb_core.u_sdram32 : at time 27917.0 ns WRITE: Bank = 0 Row = 548, Col = 34, Data = ef8372df
|
# tb_core.u_sdram32 : at time 28517.0 ns WRITE: Bank = 0 Row = 548, Col = 34, Data = ef8372df
|
# Status: Burst-No: 8 Write Address: 0022406a WriteData: ef8372df
|
# Status: Burst-No: 8 Write Address: 0022406a WriteData: ef8372df
|
# tb_core.u_sdram32 : at time 27927.0 ns WRITE: Bank = 0 Row = 548, Col = 35, Data = ea5814d4
|
# tb_core.u_sdram32 : at time 28527.0 ns WRITE: Bank = 0 Row = 548, Col = 35, Data = ea5814d4
|
# Status: Burst-No: 9 Write Address: 0022406a WriteData: ea5814d4
|
# Status: Burst-No: 9 Write Address: 0022406a WriteData: ea5814d4
|
# tb_core.u_sdram32 : at time 27937.0 ns WRITE: Bank = 0 Row = 548, Col = 36, Data = 33836567
|
# tb_core.u_sdram32 : at time 28537.0 ns WRITE: Bank = 0 Row = 548, Col = 36, Data = 33836567
|
# Status: Burst-No: 10 Write Address: 0022406a WriteData: 33836567
|
# Status: Burst-No: 10 Write Address: 0022406a WriteData: 33836567
|
# tb_core.u_sdram32 : at time 27947.0 ns WRITE: Bank = 0 Row = 548, Col = 37, Data = 4ea0419d
|
# tb_core.u_sdram32 : at time 28547.0 ns WRITE: Bank = 0 Row = 548, Col = 37, Data = 4ea0419d
|
# Status: Burst-No: 11 Write Address: 0022406a WriteData: 4ea0419d
|
# Status: Burst-No: 11 Write Address: 0022406a WriteData: 4ea0419d
|
# tb_core.u_sdram32 : at time 27957.0 ns WRITE: Bank = 0 Row = 548, Col = 38, Data = 583125b0
|
# tb_core.u_sdram32 : at time 28557.0 ns WRITE: Bank = 0 Row = 548, Col = 38, Data = 583125b0
|
# Status: Burst-No: 12 Write Address: 0022406a WriteData: 583125b0
|
# Status: Burst-No: 12 Write Address: 0022406a WriteData: 583125b0
|
# tb_core.u_sdram32 : at time 27967.0 ns WRITE: Bank = 0 Row = 548, Col = 39, Data = 41103982
|
# tb_core.u_sdram32 : at time 28567.0 ns WRITE: Bank = 0 Row = 548, Col = 39, Data = 41103982
|
# Status: Burst-No: 13 Write Address: 0022406a WriteData: 41103982
|
# Status: Burst-No: 13 Write Address: 0022406a WriteData: 41103982
|
# tb_core.u_sdram32 : at time 27977.0 ns WRITE: Bank = 0 Row = 548, Col = 40, Data = 24d2bf49
|
# tb_core.u_sdram32 : at time 28577.0 ns WRITE: Bank = 0 Row = 548, Col = 40, Data = 24d2bf49
|
# Status: Burst-No: 14 Write Address: 0022406a WriteData: 24d2bf49
|
# Status: Burst-No: 14 Write Address: 0022406a WriteData: 24d2bf49
|
# tb_core.u_sdram32 : at time 27987.0 ns WRITE: Bank = 0 Row = 548, Col = 41, Data = ecb91ad9
|
# tb_core.u_sdram32 : at time 28587.0 ns WRITE: Bank = 0 Row = 548, Col = 41, Data = ecb91ad9
|
# Status: Burst-No: 15 Write Address: 0022406a WriteData: ecb91ad9
|
# Status: Burst-No: 15 Write Address: 0022406a WriteData: ecb91ad9
|
# tb_core.u_sdram32 : at time 27997.0 ns WRITE: Bank = 0 Row = 548, Col = 42, Data = 1000b720
|
# tb_core.u_sdram32 : at time 28597.0 ns WRITE: Bank = 0 Row = 548, Col = 42, Data = 1000b720
|
# Status: Burst-No: 16 Write Address: 0022406a WriteData: 1000b720
|
# Status: Burst-No: 16 Write Address: 0022406a WriteData: 1000b720
|
# tb_core.u_sdram32 : at time 28007.0 ns WRITE: Bank = 0 Row = 548, Col = 43, Data = 8e054c1c
|
# tb_core.u_sdram32 : at time 28607.0 ns WRITE: Bank = 0 Row = 548, Col = 43, Data = 8e054c1c
|
# Status: Burst-No: 17 Write Address: 0022406a WriteData: 8e054c1c
|
# Status: Burst-No: 17 Write Address: 0022406a WriteData: 8e054c1c
|
# tb_core.u_sdram32 : at time 28017.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 28617.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 28153.0 ns READ : Bank = 3 Row = 135, Col = 100, Data = 352d616a
|
# tb_core.u_sdram32 : at time 28753.0 ns READ : Bank = 3 Row = 135, Col = 100, Data = 352d616a
|
# tb_core.u_sdram32 : at time 28163.0 ns READ : Bank = 3 Row = 135, Col = 101, Data = 427b5784
|
# tb_core.u_sdram32 : at time 28763.0 ns READ : Bank = 3 Row = 135, Col = 101, Data = 427b5784
|
# READ STATUS: Burst-No: 0 Addr: 00087d90 Rxd: 352d616a
|
# READ STATUS: Burst-No: 0 Addr: 00087d90 Rxd: 352d616a
|
# tb_core.u_sdram32 : at time 28173.0 ns READ : Bank = 3 Row = 135, Col = 102, Data = d55bbcaa
|
# tb_core.u_sdram32 : at time 28773.0 ns READ : Bank = 3 Row = 135, Col = 102, Data = d55bbcaa
|
# READ STATUS: Burst-No: 1 Addr: 00087d92 Rxd: 427b5784
|
# READ STATUS: Burst-No: 1 Addr: 00087d92 Rxd: 427b5784
|
# tb_core.u_sdram32 : at time 28183.0 ns READ : Bank = 3 Row = 135, Col = 103, Data = 3e6f0f7c
|
# tb_core.u_sdram32 : at time 28783.0 ns READ : Bank = 3 Row = 135, Col = 103, Data = 3e6f0f7c
|
# READ STATUS: Burst-No: 2 Addr: 00087d94 Rxd: d55bbcaa
|
# READ STATUS: Burst-No: 2 Addr: 00087d94 Rxd: d55bbcaa
|
# tb_core.u_sdram32 : at time 28193.0 ns READ : Bank = 3 Row = 135, Col = 104, Data = b0520260
|
# tb_core.u_sdram32 : at time 28793.0 ns READ : Bank = 3 Row = 135, Col = 104, Data = b0520260
|
# READ STATUS: Burst-No: 3 Addr: 00087d96 Rxd: 3e6f0f7c
|
# READ STATUS: Burst-No: 3 Addr: 00087d96 Rxd: 3e6f0f7c
|
# tb_core.u_sdram32 : at time 28203.0 ns READ : Bank = 3 Row = 135, Col = 105, Data = 5d4a4dba
|
# tb_core.u_sdram32 : at time 28803.0 ns READ : Bank = 3 Row = 135, Col = 105, Data = 5d4a4dba
|
# READ STATUS: Burst-No: 4 Addr: 00087d98 Rxd: b0520260
|
# READ STATUS: Burst-No: 4 Addr: 00087d98 Rxd: b0520260
|
# tb_core.u_sdram32 : at time 28213.0 ns READ : Bank = 3 Row = 135, Col = 106, Data = c5a1608b
|
# tb_core.u_sdram32 : at time 28813.0 ns READ : Bank = 3 Row = 135, Col = 106, Data = c5a1608b
|
# READ STATUS: Burst-No: 5 Addr: 00087d9a Rxd: 5d4a4dba
|
# READ STATUS: Burst-No: 5 Addr: 00087d9a Rxd: 5d4a4dba
|
# tb_core.u_sdram32 : at time 28223.0 ns READ : Bank = 3 Row = 135, Col = 107, Data = d31dfea6
|
# tb_core.u_sdram32 : at time 28823.0 ns READ : Bank = 3 Row = 135, Col = 107, Data = d31dfea6
|
# READ STATUS: Burst-No: 6 Addr: 00087d9c Rxd: c5a1608b
|
# READ STATUS: Burst-No: 6 Addr: 00087d9c Rxd: c5a1608b
|
# tb_core.u_sdram32 : at time 28233.0 ns READ : Bank = 3 Row = 135, Col = 108, Data = 92831e25
|
# tb_core.u_sdram32 : at time 28833.0 ns READ : Bank = 3 Row = 135, Col = 108, Data = 92831e25
|
# READ STATUS: Burst-No: 7 Addr: 00087d9e Rxd: d31dfea6
|
# READ STATUS: Burst-No: 7 Addr: 00087d9e Rxd: d31dfea6
|
# tb_core.u_sdram32 : at time 28243.0 ns READ : Bank = 3 Row = 135, Col = 109, Data = 19058332
|
# tb_core.u_sdram32 : at time 28843.0 ns READ : Bank = 3 Row = 135, Col = 109, Data = 19058332
|
# READ STATUS: Burst-No: 8 Addr: 00087da0 Rxd: 92831e25
|
# READ STATUS: Burst-No: 8 Addr: 00087da0 Rxd: 92831e25
|
# tb_core.u_sdram32 : at time 28253.0 ns READ : Bank = 3 Row = 135, Col = 110, Data = d10504a2
|
# tb_core.u_sdram32 : at time 28853.0 ns READ : Bank = 3 Row = 135, Col = 110, Data = d10504a2
|
# READ STATUS: Burst-No: 9 Addr: 00087da2 Rxd: 19058332
|
# READ STATUS: Burst-No: 9 Addr: 00087da2 Rxd: 19058332
|
# tb_core.u_sdram32 : at time 28263.0 ns READ : Bank = 3 Row = 135, Col = 111, Data = a48f7c49
|
# tb_core.u_sdram32 : at time 28863.0 ns READ : Bank = 3 Row = 135, Col = 111, Data = a48f7c49
|
# READ STATUS: Burst-No: 10 Addr: 00087da4 Rxd: d10504a2
|
# READ STATUS: Burst-No: 10 Addr: 00087da4 Rxd: d10504a2
|
# tb_core.u_sdram32 : at time 28273.0 ns READ : Bank = 3 Row = 135, Col = 112, Data = 8a64b014
|
# tb_core.u_sdram32 : at time 28873.0 ns READ : Bank = 3 Row = 135, Col = 112, Data = 8a64b014
|
# READ STATUS: Burst-No: 11 Addr: 00087da6 Rxd: a48f7c49
|
# READ STATUS: Burst-No: 11 Addr: 00087da6 Rxd: a48f7c49
|
# tb_core.u_sdram32 : at time 28283.0 ns READ : Bank = 3 Row = 135, Col = 113, Data = 9ec9c03d
|
# tb_core.u_sdram32 : at time 28883.0 ns READ : Bank = 3 Row = 135, Col = 113, Data = 9ec9c03d
|
# READ STATUS: Burst-No: 12 Addr: 00087da8 Rxd: 8a64b014
|
# READ STATUS: Burst-No: 12 Addr: 00087da8 Rxd: 8a64b014
|
# tb_core.u_sdram32 : at time 28293.0 ns READ : Bank = 3 Row = 135, Col = 114, Data = 25f2034b
|
# tb_core.u_sdram32 : at time 28893.0 ns READ : Bank = 3 Row = 135, Col = 114, Data = 25f2034b
|
# READ STATUS: Burst-No: 13 Addr: 00087daa Rxd: 9ec9c03d
|
# READ STATUS: Burst-No: 13 Addr: 00087daa Rxd: 9ec9c03d
|
# tb_core.u_sdram32 : at time 28303.0 ns READ : Bank = 3 Row = 135, Col = 115, Data = ae68305c
|
# tb_core.u_sdram32 : at time 28903.0 ns READ : Bank = 3 Row = 135, Col = 115, Data = ae68305c
|
# READ STATUS: Burst-No: 14 Addr: 00087dac Rxd: 25f2034b
|
# READ STATUS: Burst-No: 14 Addr: 00087dac Rxd: 25f2034b
|
# tb_core.u_sdram32 : at time 28313.0 ns READ : Bank = 3 Row = 135, Col = 116, Data = 23907547
|
# tb_core.u_sdram32 : at time 28913.0 ns READ : Bank = 3 Row = 135, Col = 116, Data = 23907547
|
# READ STATUS: Burst-No: 15 Addr: 00087dae Rxd: ae68305c
|
# READ STATUS: Burst-No: 15 Addr: 00087dae Rxd: ae68305c
|
# tb_core.u_sdram32 : at time 28323.0 ns READ : Bank = 3 Row = 135, Col = 117, Data = 433e9786
|
# tb_core.u_sdram32 : at time 28923.0 ns READ : Bank = 3 Row = 135, Col = 117, Data = 433e9786
|
# READ STATUS: Burst-No: 16 Addr: 00087db0 Rxd: 23907547
|
# READ STATUS: Burst-No: 16 Addr: 00087db0 Rxd: 23907547
|
# tb_core.u_sdram32 : at time 28333.0 ns READ : Bank = 3 Row = 135, Col = 118, Data = 9caf7a39
|
# tb_core.u_sdram32 : at time 28933.0 ns READ : Bank = 3 Row = 135, Col = 118, Data = 9caf7a39
|
# READ STATUS: Burst-No: 17 Addr: 00087db2 Rxd: 433e9786
|
# READ STATUS: Burst-No: 17 Addr: 00087db2 Rxd: 433e9786
|
# tb_core.u_sdram32 : at time 28343.0 ns READ : Bank = 3 Row = 135, Col = 119, Data = da058ab4
|
# tb_core.u_sdram32 : at time 28943.0 ns READ : Bank = 3 Row = 135, Col = 119, Data = da058ab4
|
# READ STATUS: Burst-No: 18 Addr: 00087db4 Rxd: 9caf7a39
|
# READ STATUS: Burst-No: 18 Addr: 00087db4 Rxd: 9caf7a39
|
# tb_core.u_sdram32 : at time 28353.0 ns READ : Bank = 3 Row = 135, Col = 120, Data = 6851e5d0
|
# tb_core.u_sdram32 : at time 28953.0 ns READ : Bank = 3 Row = 135, Col = 120, Data = 6851e5d0
|
# READ STATUS: Burst-No: 19 Addr: 00087db6 Rxd: da058ab4
|
# READ STATUS: Burst-No: 19 Addr: 00087db6 Rxd: da058ab4
|
# tb_core.u_sdram32 : at time 28363.0 ns READ : Bank = 3 Row = 135, Col = 121, Data = 9622502c
|
# tb_core.u_sdram32 : at time 28963.0 ns READ : Bank = 3 Row = 135, Col = 121, Data = 9622502c
|
# tb_core.u_sdram32 : at time 28367.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 28967.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 20 Addr: 00087db8 Rxd: 6851e5d0
|
# READ STATUS: Burst-No: 20 Addr: 00087db8 Rxd: 6851e5d0
|
# tb_core.u_sdram32 : at time 28373.0 ns READ : Bank = 3 Row = 135, Col = 122, Data = 467c458c
|
# tb_core.u_sdram32 : at time 28973.0 ns READ : Bank = 3 Row = 135, Col = 122, Data = 467c458c
|
# READ STATUS: Burst-No: 21 Addr: 00087dba Rxd: 9622502c
|
# READ STATUS: Burst-No: 21 Addr: 00087dba Rxd: 9622502c
|
# tb_core.u_sdram32 : at time 28383.0 ns READ : Bank = 3 Row = 135, Col = 123, Data = 03e9b707
|
# tb_core.u_sdram32 : at time 28983.0 ns READ : Bank = 3 Row = 135, Col = 123, Data = 03e9b707
|
# READ STATUS: Burst-No: 22 Addr: 00087dbc Rxd: 467c458c
|
# READ STATUS: Burst-No: 22 Addr: 00087dbc Rxd: 467c458c
|
# READ STATUS: Burst-No: 23 Addr: 00087dbe Rxd: 03e9b707
|
# READ STATUS: Burst-No: 23 Addr: 00087dbe Rxd: 03e9b707
|
# tb_core.u_sdram32 : at time 28553.0 ns READ : Bank = 0 Row = 548, Col = 26, Data = 746affe8
|
# tb_core.u_sdram32 : at time 29153.0 ns READ : Bank = 0 Row = 548, Col = 26, Data = 746affe8
|
# tb_core.u_sdram32 : at time 28563.0 ns READ : Bank = 0 Row = 548, Col = 27, Data = a5e79e4b
|
# tb_core.u_sdram32 : at time 29163.0 ns READ : Bank = 0 Row = 548, Col = 27, Data = a5e79e4b
|
# READ STATUS: Burst-No: 0 Addr: 0022406a Rxd: 746affe8
|
# READ STATUS: Burst-No: 0 Addr: 0022406a Rxd: 746affe8
|
# tb_core.u_sdram32 : at time 28573.0 ns READ : Bank = 0 Row = 548, Col = 28, Data = 39e48173
|
# tb_core.u_sdram32 : at time 29173.0 ns READ : Bank = 0 Row = 548, Col = 28, Data = 39e48173
|
# READ STATUS: Burst-No: 1 Addr: 0022406c Rxd: a5e79e4b
|
# READ STATUS: Burst-No: 1 Addr: 0022406c Rxd: a5e79e4b
|
# tb_core.u_sdram32 : at time 28583.0 ns READ : Bank = 0 Row = 548, Col = 29, Data = 76295bec
|
# tb_core.u_sdram32 : at time 29183.0 ns READ : Bank = 0 Row = 548, Col = 29, Data = 76295bec
|
# READ STATUS: Burst-No: 2 Addr: 0022406e Rxd: 39e48173
|
# READ STATUS: Burst-No: 2 Addr: 0022406e Rxd: 39e48173
|
# tb_core.u_sdram32 : at time 28593.0 ns READ : Bank = 0 Row = 548, Col = 30, Data = 11fe0523
|
# tb_core.u_sdram32 : at time 29193.0 ns READ : Bank = 0 Row = 548, Col = 30, Data = 11fe0523
|
# READ STATUS: Burst-No: 3 Addr: 00224070 Rxd: 76295bec
|
# READ STATUS: Burst-No: 3 Addr: 00224070 Rxd: 76295bec
|
# tb_core.u_sdram32 : at time 28603.0 ns READ : Bank = 0 Row = 548, Col = 31, Data = 520eefa4
|
# tb_core.u_sdram32 : at time 29203.0 ns READ : Bank = 0 Row = 548, Col = 31, Data = 520eefa4
|
# READ STATUS: Burst-No: 4 Addr: 00224072 Rxd: 11fe0523
|
# READ STATUS: Burst-No: 4 Addr: 00224072 Rxd: 11fe0523
|
# tb_core.u_sdram32 : at time 28613.0 ns READ : Bank = 0 Row = 548, Col = 32, Data = 64e165c9
|
# tb_core.u_sdram32 : at time 29213.0 ns READ : Bank = 0 Row = 548, Col = 32, Data = 64e165c9
|
# READ STATUS: Burst-No: 5 Addr: 00224074 Rxd: 520eefa4
|
# READ STATUS: Burst-No: 5 Addr: 00224074 Rxd: 520eefa4
|
# tb_core.u_sdram32 : at time 28623.0 ns READ : Bank = 0 Row = 548, Col = 33, Data = 9ca70439
|
# tb_core.u_sdram32 : at time 29223.0 ns READ : Bank = 0 Row = 548, Col = 33, Data = 9ca70439
|
# READ STATUS: Burst-No: 6 Addr: 00224076 Rxd: 64e165c9
|
# READ STATUS: Burst-No: 6 Addr: 00224076 Rxd: 64e165c9
|
# tb_core.u_sdram32 : at time 28633.0 ns READ : Bank = 0 Row = 548, Col = 34, Data = ef8372df
|
# tb_core.u_sdram32 : at time 29233.0 ns READ : Bank = 0 Row = 548, Col = 34, Data = ef8372df
|
# READ STATUS: Burst-No: 7 Addr: 00224078 Rxd: 9ca70439
|
# READ STATUS: Burst-No: 7 Addr: 00224078 Rxd: 9ca70439
|
# tb_core.u_sdram32 : at time 28643.0 ns READ : Bank = 0 Row = 548, Col = 35, Data = ea5814d4
|
# tb_core.u_sdram32 : at time 29243.0 ns READ : Bank = 0 Row = 548, Col = 35, Data = ea5814d4
|
# READ STATUS: Burst-No: 8 Addr: 0022407a Rxd: ef8372df
|
# READ STATUS: Burst-No: 8 Addr: 0022407a Rxd: ef8372df
|
# tb_core.u_sdram32 : at time 28653.0 ns READ : Bank = 0 Row = 548, Col = 36, Data = 33836567
|
# tb_core.u_sdram32 : at time 29253.0 ns READ : Bank = 0 Row = 548, Col = 36, Data = 33836567
|
# READ STATUS: Burst-No: 9 Addr: 0022407c Rxd: ea5814d4
|
# READ STATUS: Burst-No: 9 Addr: 0022407c Rxd: ea5814d4
|
# tb_core.u_sdram32 : at time 28663.0 ns READ : Bank = 0 Row = 548, Col = 37, Data = 4ea0419d
|
# tb_core.u_sdram32 : at time 29263.0 ns READ : Bank = 0 Row = 548, Col = 37, Data = 4ea0419d
|
# READ STATUS: Burst-No: 10 Addr: 0022407e Rxd: 33836567
|
# READ STATUS: Burst-No: 10 Addr: 0022407e Rxd: 33836567
|
# tb_core.u_sdram32 : at time 28673.0 ns READ : Bank = 0 Row = 548, Col = 38, Data = 583125b0
|
# tb_core.u_sdram32 : at time 29273.0 ns READ : Bank = 0 Row = 548, Col = 38, Data = 583125b0
|
# READ STATUS: Burst-No: 11 Addr: 00224080 Rxd: 4ea0419d
|
# READ STATUS: Burst-No: 11 Addr: 00224080 Rxd: 4ea0419d
|
# tb_core.u_sdram32 : at time 28683.0 ns READ : Bank = 0 Row = 548, Col = 39, Data = 41103982
|
# tb_core.u_sdram32 : at time 29283.0 ns READ : Bank = 0 Row = 548, Col = 39, Data = 41103982
|
# READ STATUS: Burst-No: 12 Addr: 00224082 Rxd: 583125b0
|
# READ STATUS: Burst-No: 12 Addr: 00224082 Rxd: 583125b0
|
# tb_core.u_sdram32 : at time 28693.0 ns READ : Bank = 0 Row = 548, Col = 40, Data = 24d2bf49
|
# tb_core.u_sdram32 : at time 29293.0 ns READ : Bank = 0 Row = 548, Col = 40, Data = 24d2bf49
|
# READ STATUS: Burst-No: 13 Addr: 00224084 Rxd: 41103982
|
# READ STATUS: Burst-No: 13 Addr: 00224084 Rxd: 41103982
|
# tb_core.u_sdram32 : at time 28703.0 ns READ : Bank = 0 Row = 548, Col = 41, Data = ecb91ad9
|
# tb_core.u_sdram32 : at time 29303.0 ns READ : Bank = 0 Row = 548, Col = 41, Data = ecb91ad9
|
# tb_core.u_sdram32 : at time 28707.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 29307.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 14 Addr: 00224086 Rxd: 24d2bf49
|
# READ STATUS: Burst-No: 14 Addr: 00224086 Rxd: 24d2bf49
|
# tb_core.u_sdram32 : at time 28713.0 ns READ : Bank = 0 Row = 548, Col = 42, Data = 1000b720
|
# tb_core.u_sdram32 : at time 29313.0 ns READ : Bank = 0 Row = 548, Col = 42, Data = 1000b720
|
# READ STATUS: Burst-No: 15 Addr: 00224088 Rxd: ecb91ad9
|
# READ STATUS: Burst-No: 15 Addr: 00224088 Rxd: ecb91ad9
|
# tb_core.u_sdram32 : at time 28723.0 ns READ : Bank = 0 Row = 548, Col = 43, Data = 8e054c1c
|
# tb_core.u_sdram32 : at time 29323.0 ns READ : Bank = 0 Row = 548, Col = 43, Data = 8e054c1c
|
# READ STATUS: Burst-No: 16 Addr: 0022408a Rxd: 1000b720
|
# READ STATUS: Burst-No: 16 Addr: 0022408a Rxd: 1000b720
|
# READ STATUS: Burst-No: 17 Addr: 0022408c Rxd: 8e054c1c
|
# READ STATUS: Burst-No: 17 Addr: 0022408c Rxd: 8e054c1c
|
# Write Address: 00316f93, Burst Size: 36
|
# Write Address: 00316f93, Burst Size: 36
|
# tb_core.u_sdram32 : at time 28897.0 ns ACT : Bank = 3 Row = 790
|
# tb_core.u_sdram32 : at time 29497.0 ns ACT : Bank = 3 Row = 790
|
# tb_core.u_sdram32 : at time 28927.0 ns WRITE: Bank = 3 Row = 790, Col = 228, Data = 954b822a
|
# tb_core.u_sdram32 : at time 29527.0 ns WRITE: Bank = 3 Row = 790, Col = 228, Data = 954b822a
|
# Status: Burst-No: 0 Write Address: 00316f93 WriteData: 954b822a
|
# Status: Burst-No: 0 Write Address: 00316f93 WriteData: 954b822a
|
# tb_core.u_sdram32 : at time 28937.0 ns ACT : Bank = 0 Row = 791
|
# tb_core.u_sdram32 : at time 29537.0 ns ACT : Bank = 0 Row = 791
|
# tb_core.u_sdram32 : at time 28937.0 ns WRITE: Bank = 3 Row = 790, Col = 229, Data = e471f8c8
|
# tb_core.u_sdram32 : at time 29537.0 ns WRITE: Bank = 3 Row = 790, Col = 229, Data = e471f8c8
|
# Status: Burst-No: 1 Write Address: 00316f93 WriteData: e471f8c8
|
# Status: Burst-No: 1 Write Address: 00316f93 WriteData: e471f8c8
|
# tb_core.u_sdram32 : at time 28947.0 ns WRITE: Bank = 3 Row = 790, Col = 230, Data = aed72e5d
|
# tb_core.u_sdram32 : at time 29547.0 ns WRITE: Bank = 3 Row = 790, Col = 230, Data = aed72e5d
|
# Status: Burst-No: 2 Write Address: 00316f93 WriteData: aed72e5d
|
# Status: Burst-No: 2 Write Address: 00316f93 WriteData: aed72e5d
|
# tb_core.u_sdram32 : at time 28957.0 ns WRITE: Bank = 3 Row = 790, Col = 231, Data = 1d3f9d3a
|
# tb_core.u_sdram32 : at time 29557.0 ns WRITE: Bank = 3 Row = 790, Col = 231, Data = 1d3f9d3a
|
# Status: Burst-No: 3 Write Address: 00316f93 WriteData: 1d3f9d3a
|
# Status: Burst-No: 3 Write Address: 00316f93 WriteData: 1d3f9d3a
|
# tb_core.u_sdram32 : at time 28967.0 ns WRITE: Bank = 3 Row = 790, Col = 232, Data = 4226a984
|
# tb_core.u_sdram32 : at time 29567.0 ns WRITE: Bank = 3 Row = 790, Col = 232, Data = 4226a984
|
# Status: Burst-No: 4 Write Address: 00316f93 WriteData: 4226a984
|
# Status: Burst-No: 4 Write Address: 00316f93 WriteData: 4226a984
|
# tb_core.u_sdram32 : at time 28977.0 ns WRITE: Bank = 3 Row = 790, Col = 233, Data = 95a9a82b
|
# tb_core.u_sdram32 : at time 29577.0 ns WRITE: Bank = 3 Row = 790, Col = 233, Data = 95a9a82b
|
# Status: Burst-No: 5 Write Address: 00316f93 WriteData: 95a9a82b
|
# Status: Burst-No: 5 Write Address: 00316f93 WriteData: 95a9a82b
|
# tb_core.u_sdram32 : at time 28987.0 ns WRITE: Bank = 3 Row = 790, Col = 234, Data = 1c8d7f39
|
# tb_core.u_sdram32 : at time 29587.0 ns WRITE: Bank = 3 Row = 790, Col = 234, Data = 1c8d7f39
|
# Status: Burst-No: 6 Write Address: 00316f93 WriteData: 1c8d7f39
|
# Status: Burst-No: 6 Write Address: 00316f93 WriteData: 1c8d7f39
|
# tb_core.u_sdram32 : at time 28997.0 ns WRITE: Bank = 3 Row = 790, Col = 235, Data = 897f1c12
|
# tb_core.u_sdram32 : at time 29597.0 ns WRITE: Bank = 3 Row = 790, Col = 235, Data = 897f1c12
|
# Status: Burst-No: 7 Write Address: 00316f93 WriteData: 897f1c12
|
# Status: Burst-No: 7 Write Address: 00316f93 WriteData: 897f1c12
|
# tb_core.u_sdram32 : at time 29007.0 ns WRITE: Bank = 3 Row = 790, Col = 236, Data = a97f0052
|
# tb_core.u_sdram32 : at time 29607.0 ns WRITE: Bank = 3 Row = 790, Col = 236, Data = a97f0052
|
# Status: Burst-No: 8 Write Address: 00316f93 WriteData: a97f0052
|
# Status: Burst-No: 8 Write Address: 00316f93 WriteData: a97f0052
|
# tb_core.u_sdram32 : at time 29017.0 ns WRITE: Bank = 3 Row = 790, Col = 237, Data = 2c848959
|
# tb_core.u_sdram32 : at time 29617.0 ns WRITE: Bank = 3 Row = 790, Col = 237, Data = 2c848959
|
# Status: Burst-No: 9 Write Address: 00316f93 WriteData: 2c848959
|
# Status: Burst-No: 9 Write Address: 00316f93 WriteData: 2c848959
|
# tb_core.u_sdram32 : at time 29027.0 ns WRITE: Bank = 3 Row = 790, Col = 238, Data = e82b96d0
|
# tb_core.u_sdram32 : at time 29627.0 ns WRITE: Bank = 3 Row = 790, Col = 238, Data = e82b96d0
|
# Status: Burst-No: 10 Write Address: 00316f93 WriteData: e82b96d0
|
# Status: Burst-No: 10 Write Address: 00316f93 WriteData: e82b96d0
|
# tb_core.u_sdram32 : at time 29037.0 ns WRITE: Bank = 3 Row = 790, Col = 239, Data = b759ea6e
|
# tb_core.u_sdram32 : at time 29637.0 ns WRITE: Bank = 3 Row = 790, Col = 239, Data = b759ea6e
|
# Status: Burst-No: 11 Write Address: 00316f93 WriteData: b759ea6e
|
# Status: Burst-No: 11 Write Address: 00316f93 WriteData: b759ea6e
|
# tb_core.u_sdram32 : at time 29047.0 ns WRITE: Bank = 3 Row = 790, Col = 240, Data = 4bf52997
|
# tb_core.u_sdram32 : at time 29647.0 ns WRITE: Bank = 3 Row = 790, Col = 240, Data = 4bf52997
|
# Status: Burst-No: 12 Write Address: 00316f93 WriteData: 4bf52997
|
# Status: Burst-No: 12 Write Address: 00316f93 WriteData: 4bf52997
|
# tb_core.u_sdram32 : at time 29057.0 ns WRITE: Bank = 3 Row = 790, Col = 241, Data = 6d8b87db
|
# tb_core.u_sdram32 : at time 29657.0 ns WRITE: Bank = 3 Row = 790, Col = 241, Data = 6d8b87db
|
# Status: Burst-No: 13 Write Address: 00316f93 WriteData: 6d8b87db
|
# Status: Burst-No: 13 Write Address: 00316f93 WriteData: 6d8b87db
|
# tb_core.u_sdram32 : at time 29067.0 ns WRITE: Bank = 3 Row = 790, Col = 242, Data = 535277a6
|
# tb_core.u_sdram32 : at time 29667.0 ns WRITE: Bank = 3 Row = 790, Col = 242, Data = 535277a6
|
# Status: Burst-No: 14 Write Address: 00316f93 WriteData: 535277a6
|
# Status: Burst-No: 14 Write Address: 00316f93 WriteData: 535277a6
|
# tb_core.u_sdram32 : at time 29077.0 ns WRITE: Bank = 3 Row = 790, Col = 243, Data = 5d85d3bb
|
# tb_core.u_sdram32 : at time 29677.0 ns WRITE: Bank = 3 Row = 790, Col = 243, Data = 5d85d3bb
|
# Status: Burst-No: 15 Write Address: 00316f93 WriteData: 5d85d3bb
|
# Status: Burst-No: 15 Write Address: 00316f93 WriteData: 5d85d3bb
|
# tb_core.u_sdram32 : at time 29087.0 ns WRITE: Bank = 3 Row = 790, Col = 244, Data = 80797c00
|
# tb_core.u_sdram32 : at time 29687.0 ns WRITE: Bank = 3 Row = 790, Col = 244, Data = 80797c00
|
# Status: Burst-No: 16 Write Address: 00316f93 WriteData: 80797c00
|
# Status: Burst-No: 16 Write Address: 00316f93 WriteData: 80797c00
|
# tb_core.u_sdram32 : at time 29097.0 ns WRITE: Bank = 3 Row = 790, Col = 245, Data = 87e44c0f
|
# tb_core.u_sdram32 : at time 29697.0 ns WRITE: Bank = 3 Row = 790, Col = 245, Data = 87e44c0f
|
# Status: Burst-No: 17 Write Address: 00316f93 WriteData: 87e44c0f
|
# Status: Burst-No: 17 Write Address: 00316f93 WriteData: 87e44c0f
|
# tb_core.u_sdram32 : at time 29107.0 ns WRITE: Bank = 3 Row = 790, Col = 246, Data = b4e8d669
|
# tb_core.u_sdram32 : at time 29707.0 ns WRITE: Bank = 3 Row = 790, Col = 246, Data = b4e8d669
|
# Status: Burst-No: 18 Write Address: 00316f93 WriteData: b4e8d669
|
# Status: Burst-No: 18 Write Address: 00316f93 WriteData: b4e8d669
|
# tb_core.u_sdram32 : at time 29117.0 ns WRITE: Bank = 3 Row = 790, Col = 247, Data = 8653620c
|
# tb_core.u_sdram32 : at time 29717.0 ns WRITE: Bank = 3 Row = 790, Col = 247, Data = 8653620c
|
# Status: Burst-No: 19 Write Address: 00316f93 WriteData: 8653620c
|
# Status: Burst-No: 19 Write Address: 00316f93 WriteData: 8653620c
|
# tb_core.u_sdram32 : at time 29127.0 ns WRITE: Bank = 3 Row = 790, Col = 248, Data = 2ca81959
|
# tb_core.u_sdram32 : at time 29727.0 ns WRITE: Bank = 3 Row = 790, Col = 248, Data = 2ca81959
|
# Status: Burst-No: 20 Write Address: 00316f93 WriteData: 2ca81959
|
# Status: Burst-No: 20 Write Address: 00316f93 WriteData: 2ca81959
|
# tb_core.u_sdram32 : at time 29137.0 ns WRITE: Bank = 3 Row = 790, Col = 249, Data = 62fd49c5
|
# tb_core.u_sdram32 : at time 29737.0 ns WRITE: Bank = 3 Row = 790, Col = 249, Data = 62fd49c5
|
# Status: Burst-No: 21 Write Address: 00316f93 WriteData: 62fd49c5
|
# Status: Burst-No: 21 Write Address: 00316f93 WriteData: 62fd49c5
|
# tb_core.u_sdram32 : at time 29147.0 ns WRITE: Bank = 3 Row = 790, Col = 250, Data = 67d735cf
|
# tb_core.u_sdram32 : at time 29747.0 ns WRITE: Bank = 3 Row = 790, Col = 250, Data = 67d735cf
|
# Status: Burst-No: 22 Write Address: 00316f93 WriteData: 67d735cf
|
# Status: Burst-No: 22 Write Address: 00316f93 WriteData: 67d735cf
|
# tb_core.u_sdram32 : at time 29157.0 ns WRITE: Bank = 3 Row = 790, Col = 251, Data = 4839e590
|
# tb_core.u_sdram32 : at time 29757.0 ns WRITE: Bank = 3 Row = 790, Col = 251, Data = 4839e590
|
# Status: Burst-No: 23 Write Address: 00316f93 WriteData: 4839e590
|
# Status: Burst-No: 23 Write Address: 00316f93 WriteData: 4839e590
|
# tb_core.u_sdram32 : at time 29167.0 ns WRITE: Bank = 3 Row = 790, Col = 252, Data = a8e4d851
|
# tb_core.u_sdram32 : at time 29767.0 ns WRITE: Bank = 3 Row = 790, Col = 252, Data = a8e4d851
|
# Status: Burst-No: 24 Write Address: 00316f93 WriteData: a8e4d851
|
# Status: Burst-No: 24 Write Address: 00316f93 WriteData: a8e4d851
|
# tb_core.u_sdram32 : at time 29177.0 ns WRITE: Bank = 3 Row = 790, Col = 253, Data = b4f9a469
|
# tb_core.u_sdram32 : at time 29777.0 ns WRITE: Bank = 3 Row = 790, Col = 253, Data = b4f9a469
|
# Status: Burst-No: 25 Write Address: 00316f93 WriteData: b4f9a469
|
# Status: Burst-No: 25 Write Address: 00316f93 WriteData: b4f9a469
|
# tb_core.u_sdram32 : at time 29187.0 ns WRITE: Bank = 3 Row = 790, Col = 254, Data = 3b83cd77
|
# tb_core.u_sdram32 : at time 29787.0 ns WRITE: Bank = 3 Row = 790, Col = 254, Data = 3b83cd77
|
# Status: Burst-No: 26 Write Address: 00316f93 WriteData: 3b83cd77
|
# Status: Burst-No: 26 Write Address: 00316f93 WriteData: 3b83cd77
|
# tb_core.u_sdram32 : at time 29197.0 ns WRITE: Bank = 3 Row = 790, Col = 255, Data = 2523654a
|
# tb_core.u_sdram32 : at time 29797.0 ns WRITE: Bank = 3 Row = 790, Col = 255, Data = 2523654a
|
# Status: Burst-No: 27 Write Address: 00316f93 WriteData: 2523654a
|
# Status: Burst-No: 27 Write Address: 00316f93 WriteData: 2523654a
|
# tb_core.u_sdram32 : at time 29207.0 ns WRITE: Bank = 0 Row = 791, Col = 0, Data = ec3758d8
|
# tb_core.u_sdram32 : at time 29807.0 ns WRITE: Bank = 0 Row = 791, Col = 0, Data = ec3758d8
|
# Status: Burst-No: 28 Write Address: 00316f93 WriteData: ec3758d8
|
# Status: Burst-No: 28 Write Address: 00316f93 WriteData: ec3758d8
|
# tb_core.u_sdram32 : at time 29217.0 ns WRITE: Bank = 0 Row = 791, Col = 1, Data = 4ddd4d9b
|
# tb_core.u_sdram32 : at time 29817.0 ns WRITE: Bank = 0 Row = 791, Col = 1, Data = 4ddd4d9b
|
# Status: Burst-No: 29 Write Address: 00316f93 WriteData: 4ddd4d9b
|
# Status: Burst-No: 29 Write Address: 00316f93 WriteData: 4ddd4d9b
|
# tb_core.u_sdram32 : at time 29227.0 ns WRITE: Bank = 0 Row = 791, Col = 2, Data = e20e9ac4
|
# tb_core.u_sdram32 : at time 29827.0 ns WRITE: Bank = 0 Row = 791, Col = 2, Data = e20e9ac4
|
# Status: Burst-No: 30 Write Address: 00316f93 WriteData: e20e9ac4
|
# Status: Burst-No: 30 Write Address: 00316f93 WriteData: e20e9ac4
|
# tb_core.u_sdram32 : at time 29237.0 ns WRITE: Bank = 0 Row = 791, Col = 3, Data = 5c78b1b8
|
# tb_core.u_sdram32 : at time 29837.0 ns WRITE: Bank = 0 Row = 791, Col = 3, Data = 5c78b1b8
|
# Status: Burst-No: 31 Write Address: 00316f93 WriteData: 5c78b1b8
|
# Status: Burst-No: 31 Write Address: 00316f93 WriteData: 5c78b1b8
|
# tb_core.u_sdram32 : at time 29247.0 ns WRITE: Bank = 0 Row = 791, Col = 4, Data = dbe6f2b7
|
# tb_core.u_sdram32 : at time 29847.0 ns WRITE: Bank = 0 Row = 791, Col = 4, Data = dbe6f2b7
|
# Status: Burst-No: 32 Write Address: 00316f93 WriteData: dbe6f2b7
|
# Status: Burst-No: 32 Write Address: 00316f93 WriteData: dbe6f2b7
|
# tb_core.u_sdram32 : at time 29257.0 ns WRITE: Bank = 0 Row = 791, Col = 5, Data = c378ee86
|
# tb_core.u_sdram32 : at time 29857.0 ns WRITE: Bank = 0 Row = 791, Col = 5, Data = c378ee86
|
# Status: Burst-No: 33 Write Address: 00316f93 WriteData: c378ee86
|
# Status: Burst-No: 33 Write Address: 00316f93 WriteData: c378ee86
|
# tb_core.u_sdram32 : at time 29267.0 ns WRITE: Bank = 0 Row = 791, Col = 6, Data = 984d5a30
|
# tb_core.u_sdram32 : at time 29867.0 ns WRITE: Bank = 0 Row = 791, Col = 6, Data = 984d5a30
|
# Status: Burst-No: 34 Write Address: 00316f93 WriteData: 984d5a30
|
# Status: Burst-No: 34 Write Address: 00316f93 WriteData: 984d5a30
|
# tb_core.u_sdram32 : at time 29277.0 ns WRITE: Bank = 0 Row = 791, Col = 7, Data = 3bed5377
|
# tb_core.u_sdram32 : at time 29877.0 ns WRITE: Bank = 0 Row = 791, Col = 7, Data = 3bed5377
|
# Status: Burst-No: 35 Write Address: 00316f93 WriteData: 3bed5377
|
# Status: Burst-No: 35 Write Address: 00316f93 WriteData: 3bed5377
|
# tb_core.u_sdram32 : at time 29287.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 29887.0 ns BST : Burst Terminate
|
# Write Address: 0016c7b5, Burst Size: 21
|
# Write Address: 0016c7b5, Burst Size: 21
|
# tb_core.u_sdram32 : at time 29427.0 ns ACT : Bank = 1 Row = 364
|
# tb_core.u_sdram32 : at time 30027.0 ns ACT : Bank = 1 Row = 364
|
# tb_core.u_sdram32 : at time 29457.0 ns WRITE: Bank = 1 Row = 364, Col = 237, Data = 03878707
|
# tb_core.u_sdram32 : at time 30057.0 ns WRITE: Bank = 1 Row = 364, Col = 237, Data = 03878707
|
# Status: Burst-No: 0 Write Address: 0016c7b5 WriteData: 03878707
|
# Status: Burst-No: 0 Write Address: 0016c7b5 WriteData: 03878707
|
# tb_core.u_sdram32 : at time 29467.0 ns ACT : Bank = 2 Row = 364
|
# tb_core.u_sdram32 : at time 30067.0 ns ACT : Bank = 2 Row = 364
|
# tb_core.u_sdram32 : at time 29467.0 ns WRITE: Bank = 1 Row = 364, Col = 238, Data = 3b0b9776
|
# tb_core.u_sdram32 : at time 30067.0 ns WRITE: Bank = 1 Row = 364, Col = 238, Data = 3b0b9776
|
# Status: Burst-No: 1 Write Address: 0016c7b5 WriteData: 3b0b9776
|
# Status: Burst-No: 1 Write Address: 0016c7b5 WriteData: 3b0b9776
|
# tb_core.u_sdram32 : at time 29477.0 ns WRITE: Bank = 1 Row = 364, Col = 239, Data = 74a1ade9
|
# tb_core.u_sdram32 : at time 30077.0 ns WRITE: Bank = 1 Row = 364, Col = 239, Data = 74a1ade9
|
# Status: Burst-No: 2 Write Address: 0016c7b5 WriteData: 74a1ade9
|
# Status: Burst-No: 2 Write Address: 0016c7b5 WriteData: 74a1ade9
|
# tb_core.u_sdram32 : at time 29487.0 ns WRITE: Bank = 1 Row = 364, Col = 240, Data = 45e28b8b
|
# tb_core.u_sdram32 : at time 30087.0 ns WRITE: Bank = 1 Row = 364, Col = 240, Data = 45e28b8b
|
# Status: Burst-No: 3 Write Address: 0016c7b5 WriteData: 45e28b8b
|
# Status: Burst-No: 3 Write Address: 0016c7b5 WriteData: 45e28b8b
|
# tb_core.u_sdram32 : at time 29497.0 ns WRITE: Bank = 1 Row = 364, Col = 241, Data = 00f25f01
|
# tb_core.u_sdram32 : at time 30097.0 ns WRITE: Bank = 1 Row = 364, Col = 241, Data = 00f25f01
|
# Status: Burst-No: 4 Write Address: 0016c7b5 WriteData: 00f25f01
|
# Status: Burst-No: 4 Write Address: 0016c7b5 WriteData: 00f25f01
|
# tb_core.u_sdram32 : at time 29507.0 ns WRITE: Bank = 1 Row = 364, Col = 242, Data = 6d808bdb
|
# tb_core.u_sdram32 : at time 30107.0 ns WRITE: Bank = 1 Row = 364, Col = 242, Data = 6d808bdb
|
# Status: Burst-No: 5 Write Address: 0016c7b5 WriteData: 6d808bdb
|
# Status: Burst-No: 5 Write Address: 0016c7b5 WriteData: 6d808bdb
|
# tb_core.u_sdram32 : at time 29517.0 ns WRITE: Bank = 1 Row = 364, Col = 243, Data = c0764280
|
# tb_core.u_sdram32 : at time 30117.0 ns WRITE: Bank = 1 Row = 364, Col = 243, Data = c0764280
|
# Status: Burst-No: 6 Write Address: 0016c7b5 WriteData: c0764280
|
# Status: Burst-No: 6 Write Address: 0016c7b5 WriteData: c0764280
|
# tb_core.u_sdram32 : at time 29527.0 ns WRITE: Bank = 1 Row = 364, Col = 244, Data = 611d9fc2
|
# tb_core.u_sdram32 : at time 30127.0 ns WRITE: Bank = 1 Row = 364, Col = 244, Data = 611d9fc2
|
# Status: Burst-No: 7 Write Address: 0016c7b5 WriteData: 611d9fc2
|
# Status: Burst-No: 7 Write Address: 0016c7b5 WriteData: 611d9fc2
|
# tb_core.u_sdram32 : at time 29537.0 ns WRITE: Bank = 1 Row = 364, Col = 245, Data = e2ecdac5
|
# tb_core.u_sdram32 : at time 30137.0 ns WRITE: Bank = 1 Row = 364, Col = 245, Data = e2ecdac5
|
# Status: Burst-No: 8 Write Address: 0016c7b5 WriteData: e2ecdac5
|
# Status: Burst-No: 8 Write Address: 0016c7b5 WriteData: e2ecdac5
|
# tb_core.u_sdram32 : at time 29547.0 ns WRITE: Bank = 1 Row = 364, Col = 246, Data = 9827fa30
|
# tb_core.u_sdram32 : at time 30147.0 ns WRITE: Bank = 1 Row = 364, Col = 246, Data = 9827fa30
|
# Status: Burst-No: 9 Write Address: 0016c7b5 WriteData: 9827fa30
|
# Status: Burst-No: 9 Write Address: 0016c7b5 WriteData: 9827fa30
|
# tb_core.u_sdram32 : at time 29557.0 ns WRITE: Bank = 1 Row = 364, Col = 247, Data = d7b2e4af
|
# tb_core.u_sdram32 : at time 30157.0 ns WRITE: Bank = 1 Row = 364, Col = 247, Data = d7b2e4af
|
# Status: Burst-No: 10 Write Address: 0016c7b5 WriteData: d7b2e4af
|
# Status: Burst-No: 10 Write Address: 0016c7b5 WriteData: d7b2e4af
|
# tb_core.u_sdram32 : at time 29567.0 ns WRITE: Bank = 1 Row = 364, Col = 248, Data = b302da66
|
# tb_core.u_sdram32 : at time 30167.0 ns WRITE: Bank = 1 Row = 364, Col = 248, Data = b302da66
|
# Status: Burst-No: 11 Write Address: 0016c7b5 WriteData: b302da66
|
# Status: Burst-No: 11 Write Address: 0016c7b5 WriteData: b302da66
|
# tb_core.u_sdram32 : at time 29577.0 ns WRITE: Bank = 1 Row = 364, Col = 249, Data = 57fbb9af
|
# tb_core.u_sdram32 : at time 30177.0 ns WRITE: Bank = 1 Row = 364, Col = 249, Data = 57fbb9af
|
# Status: Burst-No: 12 Write Address: 0016c7b5 WriteData: 57fbb9af
|
# Status: Burst-No: 12 Write Address: 0016c7b5 WriteData: 57fbb9af
|
# tb_core.u_sdram32 : at time 29587.0 ns WRITE: Bank = 1 Row = 364, Col = 250, Data = f4d86ee9
|
# tb_core.u_sdram32 : at time 30187.0 ns WRITE: Bank = 1 Row = 364, Col = 250, Data = f4d86ee9
|
# Status: Burst-No: 13 Write Address: 0016c7b5 WriteData: f4d86ee9
|
# Status: Burst-No: 13 Write Address: 0016c7b5 WriteData: f4d86ee9
|
# tb_core.u_sdram32 : at time 29597.0 ns WRITE: Bank = 1 Row = 364, Col = 251, Data = 7c41aff8
|
# tb_core.u_sdram32 : at time 30197.0 ns WRITE: Bank = 1 Row = 364, Col = 251, Data = 7c41aff8
|
# Status: Burst-No: 14 Write Address: 0016c7b5 WriteData: 7c41aff8
|
# Status: Burst-No: 14 Write Address: 0016c7b5 WriteData: 7c41aff8
|
# tb_core.u_sdram32 : at time 29607.0 ns WRITE: Bank = 1 Row = 364, Col = 252, Data = 8376ac06
|
# tb_core.u_sdram32 : at time 30207.0 ns WRITE: Bank = 1 Row = 364, Col = 252, Data = 8376ac06
|
# Status: Burst-No: 15 Write Address: 0016c7b5 WriteData: 8376ac06
|
# Status: Burst-No: 15 Write Address: 0016c7b5 WriteData: 8376ac06
|
# tb_core.u_sdram32 : at time 29617.0 ns WRITE: Bank = 1 Row = 364, Col = 253, Data = f78576ef
|
# tb_core.u_sdram32 : at time 30217.0 ns WRITE: Bank = 1 Row = 364, Col = 253, Data = f78576ef
|
# Status: Burst-No: 16 Write Address: 0016c7b5 WriteData: f78576ef
|
# Status: Burst-No: 16 Write Address: 0016c7b5 WriteData: f78576ef
|
# tb_core.u_sdram32 : at time 29627.0 ns WRITE: Bank = 1 Row = 364, Col = 254, Data = 70ef37e1
|
# tb_core.u_sdram32 : at time 30227.0 ns WRITE: Bank = 1 Row = 364, Col = 254, Data = 70ef37e1
|
# Status: Burst-No: 17 Write Address: 0016c7b5 WriteData: 70ef37e1
|
# Status: Burst-No: 17 Write Address: 0016c7b5 WriteData: 70ef37e1
|
# tb_core.u_sdram32 : at time 29637.0 ns WRITE: Bank = 1 Row = 364, Col = 255, Data = cab47c95
|
# tb_core.u_sdram32 : at time 30237.0 ns WRITE: Bank = 1 Row = 364, Col = 255, Data = cab47c95
|
# Status: Burst-No: 18 Write Address: 0016c7b5 WriteData: cab47c95
|
# Status: Burst-No: 18 Write Address: 0016c7b5 WriteData: cab47c95
|
# tb_core.u_sdram32 : at time 29647.0 ns WRITE: Bank = 2 Row = 364, Col = 0, Data = f7723eee
|
# tb_core.u_sdram32 : at time 30247.0 ns WRITE: Bank = 2 Row = 364, Col = 0, Data = f7723eee
|
# Status: Burst-No: 19 Write Address: 0016c7b5 WriteData: f7723eee
|
# Status: Burst-No: 19 Write Address: 0016c7b5 WriteData: f7723eee
|
# tb_core.u_sdram32 : at time 29657.0 ns WRITE: Bank = 2 Row = 364, Col = 1, Data = 304e4d60
|
# tb_core.u_sdram32 : at time 30257.0 ns WRITE: Bank = 2 Row = 364, Col = 1, Data = 304e4d60
|
# Status: Burst-No: 20 Write Address: 0016c7b5 WriteData: 304e4d60
|
# Status: Burst-No: 20 Write Address: 0016c7b5 WriteData: 304e4d60
|
# tb_core.u_sdram32 : at time 29667.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 30267.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 29803.0 ns READ : Bank = 3 Row = 790, Col = 228, Data = 954b822a
|
# tb_core.u_sdram32 : at time 30403.0 ns READ : Bank = 3 Row = 790, Col = 228, Data = 954b822a
|
# tb_core.u_sdram32 : at time 29813.0 ns READ : Bank = 3 Row = 790, Col = 229, Data = e471f8c8
|
# tb_core.u_sdram32 : at time 30413.0 ns READ : Bank = 3 Row = 790, Col = 229, Data = e471f8c8
|
# READ STATUS: Burst-No: 0 Addr: 00316f93 Rxd: 954b822a
|
# READ STATUS: Burst-No: 0 Addr: 00316f93 Rxd: 954b822a
|
# tb_core.u_sdram32 : at time 29823.0 ns READ : Bank = 3 Row = 790, Col = 230, Data = aed72e5d
|
# tb_core.u_sdram32 : at time 30423.0 ns READ : Bank = 3 Row = 790, Col = 230, Data = aed72e5d
|
# READ STATUS: Burst-No: 1 Addr: 00316f95 Rxd: e471f8c8
|
# READ STATUS: Burst-No: 1 Addr: 00316f95 Rxd: e471f8c8
|
# tb_core.u_sdram32 : at time 29833.0 ns READ : Bank = 3 Row = 790, Col = 231, Data = 1d3f9d3a
|
# tb_core.u_sdram32 : at time 30433.0 ns READ : Bank = 3 Row = 790, Col = 231, Data = 1d3f9d3a
|
# READ STATUS: Burst-No: 2 Addr: 00316f97 Rxd: aed72e5d
|
# READ STATUS: Burst-No: 2 Addr: 00316f97 Rxd: aed72e5d
|
# tb_core.u_sdram32 : at time 29843.0 ns READ : Bank = 3 Row = 790, Col = 232, Data = 4226a984
|
# tb_core.u_sdram32 : at time 30443.0 ns READ : Bank = 3 Row = 790, Col = 232, Data = 4226a984
|
# READ STATUS: Burst-No: 3 Addr: 00316f99 Rxd: 1d3f9d3a
|
# READ STATUS: Burst-No: 3 Addr: 00316f99 Rxd: 1d3f9d3a
|
# tb_core.u_sdram32 : at time 29853.0 ns READ : Bank = 3 Row = 790, Col = 233, Data = 95a9a82b
|
# tb_core.u_sdram32 : at time 30453.0 ns READ : Bank = 3 Row = 790, Col = 233, Data = 95a9a82b
|
# READ STATUS: Burst-No: 4 Addr: 00316f9b Rxd: 4226a984
|
# READ STATUS: Burst-No: 4 Addr: 00316f9b Rxd: 4226a984
|
# tb_core.u_sdram32 : at time 29863.0 ns READ : Bank = 3 Row = 790, Col = 234, Data = 1c8d7f39
|
# tb_core.u_sdram32 : at time 30463.0 ns READ : Bank = 3 Row = 790, Col = 234, Data = 1c8d7f39
|
# READ STATUS: Burst-No: 5 Addr: 00316f9d Rxd: 95a9a82b
|
# READ STATUS: Burst-No: 5 Addr: 00316f9d Rxd: 95a9a82b
|
# tb_core.u_sdram32 : at time 29873.0 ns READ : Bank = 3 Row = 790, Col = 235, Data = 897f1c12
|
# tb_core.u_sdram32 : at time 30473.0 ns READ : Bank = 3 Row = 790, Col = 235, Data = 897f1c12
|
# READ STATUS: Burst-No: 6 Addr: 00316f9f Rxd: 1c8d7f39
|
# READ STATUS: Burst-No: 6 Addr: 00316f9f Rxd: 1c8d7f39
|
# tb_core.u_sdram32 : at time 29883.0 ns READ : Bank = 3 Row = 790, Col = 236, Data = a97f0052
|
# tb_core.u_sdram32 : at time 30483.0 ns READ : Bank = 3 Row = 790, Col = 236, Data = a97f0052
|
# READ STATUS: Burst-No: 7 Addr: 00316fa1 Rxd: 897f1c12
|
# READ STATUS: Burst-No: 7 Addr: 00316fa1 Rxd: 897f1c12
|
# tb_core.u_sdram32 : at time 29893.0 ns READ : Bank = 3 Row = 790, Col = 237, Data = 2c848959
|
# tb_core.u_sdram32 : at time 30493.0 ns READ : Bank = 3 Row = 790, Col = 237, Data = 2c848959
|
# READ STATUS: Burst-No: 8 Addr: 00316fa3 Rxd: a97f0052
|
# READ STATUS: Burst-No: 8 Addr: 00316fa3 Rxd: a97f0052
|
# tb_core.u_sdram32 : at time 29903.0 ns READ : Bank = 3 Row = 790, Col = 238, Data = e82b96d0
|
# tb_core.u_sdram32 : at time 30503.0 ns READ : Bank = 3 Row = 790, Col = 238, Data = e82b96d0
|
# READ STATUS: Burst-No: 9 Addr: 00316fa5 Rxd: 2c848959
|
# READ STATUS: Burst-No: 9 Addr: 00316fa5 Rxd: 2c848959
|
# tb_core.u_sdram32 : at time 29913.0 ns READ : Bank = 3 Row = 790, Col = 239, Data = b759ea6e
|
# tb_core.u_sdram32 : at time 30513.0 ns READ : Bank = 3 Row = 790, Col = 239, Data = b759ea6e
|
# READ STATUS: Burst-No: 10 Addr: 00316fa7 Rxd: e82b96d0
|
# READ STATUS: Burst-No: 10 Addr: 00316fa7 Rxd: e82b96d0
|
# tb_core.u_sdram32 : at time 29923.0 ns READ : Bank = 3 Row = 790, Col = 240, Data = 4bf52997
|
# tb_core.u_sdram32 : at time 30523.0 ns READ : Bank = 3 Row = 790, Col = 240, Data = 4bf52997
|
# READ STATUS: Burst-No: 11 Addr: 00316fa9 Rxd: b759ea6e
|
# READ STATUS: Burst-No: 11 Addr: 00316fa9 Rxd: b759ea6e
|
# tb_core.u_sdram32 : at time 29933.0 ns READ : Bank = 3 Row = 790, Col = 241, Data = 6d8b87db
|
# tb_core.u_sdram32 : at time 30533.0 ns READ : Bank = 3 Row = 790, Col = 241, Data = 6d8b87db
|
# READ STATUS: Burst-No: 12 Addr: 00316fab Rxd: 4bf52997
|
# READ STATUS: Burst-No: 12 Addr: 00316fab Rxd: 4bf52997
|
# tb_core.u_sdram32 : at time 29943.0 ns READ : Bank = 3 Row = 790, Col = 242, Data = 535277a6
|
# tb_core.u_sdram32 : at time 30543.0 ns READ : Bank = 3 Row = 790, Col = 242, Data = 535277a6
|
# READ STATUS: Burst-No: 13 Addr: 00316fad Rxd: 6d8b87db
|
# READ STATUS: Burst-No: 13 Addr: 00316fad Rxd: 6d8b87db
|
# tb_core.u_sdram32 : at time 29953.0 ns READ : Bank = 3 Row = 790, Col = 243, Data = 5d85d3bb
|
# tb_core.u_sdram32 : at time 30553.0 ns READ : Bank = 3 Row = 790, Col = 243, Data = 5d85d3bb
|
# READ STATUS: Burst-No: 14 Addr: 00316faf Rxd: 535277a6
|
# READ STATUS: Burst-No: 14 Addr: 00316faf Rxd: 535277a6
|
# tb_core.u_sdram32 : at time 29963.0 ns READ : Bank = 3 Row = 790, Col = 244, Data = 80797c00
|
# tb_core.u_sdram32 : at time 30563.0 ns READ : Bank = 3 Row = 790, Col = 244, Data = 80797c00
|
# READ STATUS: Burst-No: 15 Addr: 00316fb1 Rxd: 5d85d3bb
|
# READ STATUS: Burst-No: 15 Addr: 00316fb1 Rxd: 5d85d3bb
|
# tb_core.u_sdram32 : at time 29973.0 ns READ : Bank = 3 Row = 790, Col = 245, Data = 87e44c0f
|
# tb_core.u_sdram32 : at time 30573.0 ns READ : Bank = 3 Row = 790, Col = 245, Data = 87e44c0f
|
# READ STATUS: Burst-No: 16 Addr: 00316fb3 Rxd: 80797c00
|
# READ STATUS: Burst-No: 16 Addr: 00316fb3 Rxd: 80797c00
|
# tb_core.u_sdram32 : at time 29983.0 ns READ : Bank = 3 Row = 790, Col = 246, Data = b4e8d669
|
# tb_core.u_sdram32 : at time 30583.0 ns READ : Bank = 3 Row = 790, Col = 246, Data = b4e8d669
|
# READ STATUS: Burst-No: 17 Addr: 00316fb5 Rxd: 87e44c0f
|
# READ STATUS: Burst-No: 17 Addr: 00316fb5 Rxd: 87e44c0f
|
# tb_core.u_sdram32 : at time 29993.0 ns READ : Bank = 3 Row = 790, Col = 247, Data = 8653620c
|
# tb_core.u_sdram32 : at time 30593.0 ns READ : Bank = 3 Row = 790, Col = 247, Data = 8653620c
|
# READ STATUS: Burst-No: 18 Addr: 00316fb7 Rxd: b4e8d669
|
# READ STATUS: Burst-No: 18 Addr: 00316fb7 Rxd: b4e8d669
|
# tb_core.u_sdram32 : at time 30003.0 ns READ : Bank = 3 Row = 790, Col = 248, Data = 2ca81959
|
# tb_core.u_sdram32 : at time 30603.0 ns READ : Bank = 3 Row = 790, Col = 248, Data = 2ca81959
|
# READ STATUS: Burst-No: 19 Addr: 00316fb9 Rxd: 8653620c
|
# READ STATUS: Burst-No: 19 Addr: 00316fb9 Rxd: 8653620c
|
# tb_core.u_sdram32 : at time 30013.0 ns READ : Bank = 3 Row = 790, Col = 249, Data = 62fd49c5
|
# tb_core.u_sdram32 : at time 30613.0 ns READ : Bank = 3 Row = 790, Col = 249, Data = 62fd49c5
|
# READ STATUS: Burst-No: 20 Addr: 00316fbb Rxd: 2ca81959
|
# READ STATUS: Burst-No: 20 Addr: 00316fbb Rxd: 2ca81959
|
# tb_core.u_sdram32 : at time 30023.0 ns READ : Bank = 3 Row = 790, Col = 250, Data = 67d735cf
|
# tb_core.u_sdram32 : at time 30623.0 ns READ : Bank = 3 Row = 790, Col = 250, Data = 67d735cf
|
# READ STATUS: Burst-No: 21 Addr: 00316fbd Rxd: 62fd49c5
|
# READ STATUS: Burst-No: 21 Addr: 00316fbd Rxd: 62fd49c5
|
# tb_core.u_sdram32 : at time 30033.0 ns READ : Bank = 3 Row = 790, Col = 251, Data = 4839e590
|
# tb_core.u_sdram32 : at time 30633.0 ns READ : Bank = 3 Row = 790, Col = 251, Data = 4839e590
|
# READ STATUS: Burst-No: 22 Addr: 00316fbf Rxd: 67d735cf
|
# READ STATUS: Burst-No: 22 Addr: 00316fbf Rxd: 67d735cf
|
# tb_core.u_sdram32 : at time 30043.0 ns READ : Bank = 3 Row = 790, Col = 252, Data = a8e4d851
|
# tb_core.u_sdram32 : at time 30643.0 ns READ : Bank = 3 Row = 790, Col = 252, Data = a8e4d851
|
# READ STATUS: Burst-No: 23 Addr: 00316fc1 Rxd: 4839e590
|
# READ STATUS: Burst-No: 23 Addr: 00316fc1 Rxd: 4839e590
|
# tb_core.u_sdram32 : at time 30053.0 ns READ : Bank = 3 Row = 790, Col = 253, Data = b4f9a469
|
# tb_core.u_sdram32 : at time 30653.0 ns READ : Bank = 3 Row = 790, Col = 253, Data = b4f9a469
|
# READ STATUS: Burst-No: 24 Addr: 00316fc3 Rxd: a8e4d851
|
# READ STATUS: Burst-No: 24 Addr: 00316fc3 Rxd: a8e4d851
|
# tb_core.u_sdram32 : at time 30063.0 ns READ : Bank = 3 Row = 790, Col = 254, Data = 3b83cd77
|
# tb_core.u_sdram32 : at time 30663.0 ns READ : Bank = 3 Row = 790, Col = 254, Data = 3b83cd77
|
# READ STATUS: Burst-No: 25 Addr: 00316fc5 Rxd: b4f9a469
|
# READ STATUS: Burst-No: 25 Addr: 00316fc5 Rxd: b4f9a469
|
# tb_core.u_sdram32 : at time 30073.0 ns READ : Bank = 3 Row = 790, Col = 255, Data = 2523654a
|
# tb_core.u_sdram32 : at time 30673.0 ns READ : Bank = 3 Row = 790, Col = 255, Data = 2523654a
|
# READ STATUS: Burst-No: 26 Addr: 00316fc7 Rxd: 3b83cd77
|
# READ STATUS: Burst-No: 26 Addr: 00316fc7 Rxd: 3b83cd77
|
# tb_core.u_sdram32 : at time 30083.0 ns READ : Bank = 0 Row = 791, Col = 0, Data = ec3758d8
|
# tb_core.u_sdram32 : at time 30683.0 ns READ : Bank = 0 Row = 791, Col = 0, Data = ec3758d8
|
# READ STATUS: Burst-No: 27 Addr: 00316fc9 Rxd: 2523654a
|
# READ STATUS: Burst-No: 27 Addr: 00316fc9 Rxd: 2523654a
|
# tb_core.u_sdram32 : at time 30093.0 ns READ : Bank = 0 Row = 791, Col = 1, Data = 4ddd4d9b
|
# tb_core.u_sdram32 : at time 30693.0 ns READ : Bank = 0 Row = 791, Col = 1, Data = 4ddd4d9b
|
# READ STATUS: Burst-No: 28 Addr: 00316fcb Rxd: ec3758d8
|
# READ STATUS: Burst-No: 28 Addr: 00316fcb Rxd: ec3758d8
|
# tb_core.u_sdram32 : at time 30103.0 ns READ : Bank = 0 Row = 791, Col = 2, Data = e20e9ac4
|
# tb_core.u_sdram32 : at time 30703.0 ns READ : Bank = 0 Row = 791, Col = 2, Data = e20e9ac4
|
# READ STATUS: Burst-No: 29 Addr: 00316fcd Rxd: 4ddd4d9b
|
# READ STATUS: Burst-No: 29 Addr: 00316fcd Rxd: 4ddd4d9b
|
# tb_core.u_sdram32 : at time 30113.0 ns READ : Bank = 0 Row = 791, Col = 3, Data = 5c78b1b8
|
# tb_core.u_sdram32 : at time 30713.0 ns READ : Bank = 0 Row = 791, Col = 3, Data = 5c78b1b8
|
# READ STATUS: Burst-No: 30 Addr: 00316fcf Rxd: e20e9ac4
|
# READ STATUS: Burst-No: 30 Addr: 00316fcf Rxd: e20e9ac4
|
# tb_core.u_sdram32 : at time 30123.0 ns READ : Bank = 0 Row = 791, Col = 4, Data = dbe6f2b7
|
# tb_core.u_sdram32 : at time 30723.0 ns READ : Bank = 0 Row = 791, Col = 4, Data = dbe6f2b7
|
# READ STATUS: Burst-No: 31 Addr: 00316fd1 Rxd: 5c78b1b8
|
# READ STATUS: Burst-No: 31 Addr: 00316fd1 Rxd: 5c78b1b8
|
# tb_core.u_sdram32 : at time 30133.0 ns READ : Bank = 0 Row = 791, Col = 5, Data = c378ee86
|
# tb_core.u_sdram32 : at time 30733.0 ns READ : Bank = 0 Row = 791, Col = 5, Data = c378ee86
|
# tb_core.u_sdram32 : at time 30137.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 30737.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 32 Addr: 00316fd3 Rxd: dbe6f2b7
|
# READ STATUS: Burst-No: 32 Addr: 00316fd3 Rxd: dbe6f2b7
|
# tb_core.u_sdram32 : at time 30143.0 ns READ : Bank = 0 Row = 791, Col = 6, Data = 984d5a30
|
# tb_core.u_sdram32 : at time 30743.0 ns READ : Bank = 0 Row = 791, Col = 6, Data = 984d5a30
|
# READ STATUS: Burst-No: 33 Addr: 00316fd5 Rxd: c378ee86
|
# READ STATUS: Burst-No: 33 Addr: 00316fd5 Rxd: c378ee86
|
# tb_core.u_sdram32 : at time 30153.0 ns READ : Bank = 0 Row = 791, Col = 7, Data = 3bed5377
|
# tb_core.u_sdram32 : at time 30753.0 ns READ : Bank = 0 Row = 791, Col = 7, Data = 3bed5377
|
# READ STATUS: Burst-No: 34 Addr: 00316fd7 Rxd: 984d5a30
|
# READ STATUS: Burst-No: 34 Addr: 00316fd7 Rxd: 984d5a30
|
# READ STATUS: Burst-No: 35 Addr: 00316fd9 Rxd: 3bed5377
|
# READ STATUS: Burst-No: 35 Addr: 00316fd9 Rxd: 3bed5377
|
# tb_core.u_sdram32 : at time 30323.0 ns READ : Bank = 1 Row = 364, Col = 237, Data = 03878707
|
# tb_core.u_sdram32 : at time 30923.0 ns READ : Bank = 1 Row = 364, Col = 237, Data = 03878707
|
# tb_core.u_sdram32 : at time 30333.0 ns READ : Bank = 1 Row = 364, Col = 238, Data = 3b0b9776
|
# tb_core.u_sdram32 : at time 30933.0 ns READ : Bank = 1 Row = 364, Col = 238, Data = 3b0b9776
|
# READ STATUS: Burst-No: 0 Addr: 0016c7b5 Rxd: 03878707
|
# READ STATUS: Burst-No: 0 Addr: 0016c7b5 Rxd: 03878707
|
# tb_core.u_sdram32 : at time 30343.0 ns READ : Bank = 1 Row = 364, Col = 239, Data = 74a1ade9
|
# tb_core.u_sdram32 : at time 30943.0 ns READ : Bank = 1 Row = 364, Col = 239, Data = 74a1ade9
|
# READ STATUS: Burst-No: 1 Addr: 0016c7b7 Rxd: 3b0b9776
|
# READ STATUS: Burst-No: 1 Addr: 0016c7b7 Rxd: 3b0b9776
|
# tb_core.u_sdram32 : at time 30353.0 ns READ : Bank = 1 Row = 364, Col = 240, Data = 45e28b8b
|
# tb_core.u_sdram32 : at time 30953.0 ns READ : Bank = 1 Row = 364, Col = 240, Data = 45e28b8b
|
# READ STATUS: Burst-No: 2 Addr: 0016c7b9 Rxd: 74a1ade9
|
# READ STATUS: Burst-No: 2 Addr: 0016c7b9 Rxd: 74a1ade9
|
# tb_core.u_sdram32 : at time 30363.0 ns READ : Bank = 1 Row = 364, Col = 241, Data = 00f25f01
|
# tb_core.u_sdram32 : at time 30963.0 ns READ : Bank = 1 Row = 364, Col = 241, Data = 00f25f01
|
# READ STATUS: Burst-No: 3 Addr: 0016c7bb Rxd: 45e28b8b
|
# READ STATUS: Burst-No: 3 Addr: 0016c7bb Rxd: 45e28b8b
|
# tb_core.u_sdram32 : at time 30373.0 ns READ : Bank = 1 Row = 364, Col = 242, Data = 6d808bdb
|
# tb_core.u_sdram32 : at time 30973.0 ns READ : Bank = 1 Row = 364, Col = 242, Data = 6d808bdb
|
# READ STATUS: Burst-No: 4 Addr: 0016c7bd Rxd: 00f25f01
|
# READ STATUS: Burst-No: 4 Addr: 0016c7bd Rxd: 00f25f01
|
# tb_core.u_sdram32 : at time 30383.0 ns READ : Bank = 1 Row = 364, Col = 243, Data = c0764280
|
# tb_core.u_sdram32 : at time 30983.0 ns READ : Bank = 1 Row = 364, Col = 243, Data = c0764280
|
# READ STATUS: Burst-No: 5 Addr: 0016c7bf Rxd: 6d808bdb
|
# READ STATUS: Burst-No: 5 Addr: 0016c7bf Rxd: 6d808bdb
|
# tb_core.u_sdram32 : at time 30393.0 ns READ : Bank = 1 Row = 364, Col = 244, Data = 611d9fc2
|
# tb_core.u_sdram32 : at time 30993.0 ns READ : Bank = 1 Row = 364, Col = 244, Data = 611d9fc2
|
# READ STATUS: Burst-No: 6 Addr: 0016c7c1 Rxd: c0764280
|
# READ STATUS: Burst-No: 6 Addr: 0016c7c1 Rxd: c0764280
|
# tb_core.u_sdram32 : at time 30403.0 ns READ : Bank = 1 Row = 364, Col = 245, Data = e2ecdac5
|
# tb_core.u_sdram32 : at time 31003.0 ns READ : Bank = 1 Row = 364, Col = 245, Data = e2ecdac5
|
# READ STATUS: Burst-No: 7 Addr: 0016c7c3 Rxd: 611d9fc2
|
# READ STATUS: Burst-No: 7 Addr: 0016c7c3 Rxd: 611d9fc2
|
# tb_core.u_sdram32 : at time 30413.0 ns READ : Bank = 1 Row = 364, Col = 246, Data = 9827fa30
|
# tb_core.u_sdram32 : at time 31013.0 ns READ : Bank = 1 Row = 364, Col = 246, Data = 9827fa30
|
# READ STATUS: Burst-No: 8 Addr: 0016c7c5 Rxd: e2ecdac5
|
# READ STATUS: Burst-No: 8 Addr: 0016c7c5 Rxd: e2ecdac5
|
# tb_core.u_sdram32 : at time 30423.0 ns READ : Bank = 1 Row = 364, Col = 247, Data = d7b2e4af
|
# tb_core.u_sdram32 : at time 31023.0 ns READ : Bank = 1 Row = 364, Col = 247, Data = d7b2e4af
|
# READ STATUS: Burst-No: 9 Addr: 0016c7c7 Rxd: 9827fa30
|
# READ STATUS: Burst-No: 9 Addr: 0016c7c7 Rxd: 9827fa30
|
# tb_core.u_sdram32 : at time 30433.0 ns READ : Bank = 1 Row = 364, Col = 248, Data = b302da66
|
# tb_core.u_sdram32 : at time 31033.0 ns READ : Bank = 1 Row = 364, Col = 248, Data = b302da66
|
# READ STATUS: Burst-No: 10 Addr: 0016c7c9 Rxd: d7b2e4af
|
# READ STATUS: Burst-No: 10 Addr: 0016c7c9 Rxd: d7b2e4af
|
# tb_core.u_sdram32 : at time 30443.0 ns READ : Bank = 1 Row = 364, Col = 249, Data = 57fbb9af
|
# tb_core.u_sdram32 : at time 31043.0 ns READ : Bank = 1 Row = 364, Col = 249, Data = 57fbb9af
|
# READ STATUS: Burst-No: 11 Addr: 0016c7cb Rxd: b302da66
|
# READ STATUS: Burst-No: 11 Addr: 0016c7cb Rxd: b302da66
|
# tb_core.u_sdram32 : at time 30453.0 ns READ : Bank = 1 Row = 364, Col = 250, Data = f4d86ee9
|
# tb_core.u_sdram32 : at time 31053.0 ns READ : Bank = 1 Row = 364, Col = 250, Data = f4d86ee9
|
# READ STATUS: Burst-No: 12 Addr: 0016c7cd Rxd: 57fbb9af
|
# READ STATUS: Burst-No: 12 Addr: 0016c7cd Rxd: 57fbb9af
|
# tb_core.u_sdram32 : at time 30463.0 ns READ : Bank = 1 Row = 364, Col = 251, Data = 7c41aff8
|
# tb_core.u_sdram32 : at time 31063.0 ns READ : Bank = 1 Row = 364, Col = 251, Data = 7c41aff8
|
# READ STATUS: Burst-No: 13 Addr: 0016c7cf Rxd: f4d86ee9
|
# READ STATUS: Burst-No: 13 Addr: 0016c7cf Rxd: f4d86ee9
|
# tb_core.u_sdram32 : at time 30473.0 ns READ : Bank = 1 Row = 364, Col = 252, Data = 8376ac06
|
# tb_core.u_sdram32 : at time 31073.0 ns READ : Bank = 1 Row = 364, Col = 252, Data = 8376ac06
|
# READ STATUS: Burst-No: 14 Addr: 0016c7d1 Rxd: 7c41aff8
|
# READ STATUS: Burst-No: 14 Addr: 0016c7d1 Rxd: 7c41aff8
|
# tb_core.u_sdram32 : at time 30483.0 ns READ : Bank = 1 Row = 364, Col = 253, Data = f78576ef
|
# tb_core.u_sdram32 : at time 31083.0 ns READ : Bank = 1 Row = 364, Col = 253, Data = f78576ef
|
# READ STATUS: Burst-No: 15 Addr: 0016c7d3 Rxd: 8376ac06
|
# READ STATUS: Burst-No: 15 Addr: 0016c7d3 Rxd: 8376ac06
|
# tb_core.u_sdram32 : at time 30493.0 ns READ : Bank = 1 Row = 364, Col = 254, Data = 70ef37e1
|
# tb_core.u_sdram32 : at time 31093.0 ns READ : Bank = 1 Row = 364, Col = 254, Data = 70ef37e1
|
# READ STATUS: Burst-No: 16 Addr: 0016c7d5 Rxd: f78576ef
|
# READ STATUS: Burst-No: 16 Addr: 0016c7d5 Rxd: f78576ef
|
# tb_core.u_sdram32 : at time 30503.0 ns READ : Bank = 1 Row = 364, Col = 255, Data = cab47c95
|
# tb_core.u_sdram32 : at time 31103.0 ns READ : Bank = 1 Row = 364, Col = 255, Data = cab47c95
|
# tb_core.u_sdram32 : at time 30507.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 31107.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 17 Addr: 0016c7d7 Rxd: 70ef37e1
|
# READ STATUS: Burst-No: 17 Addr: 0016c7d7 Rxd: 70ef37e1
|
# tb_core.u_sdram32 : at time 30513.0 ns READ : Bank = 2 Row = 364, Col = 0, Data = f7723eee
|
# tb_core.u_sdram32 : at time 31113.0 ns READ : Bank = 2 Row = 364, Col = 0, Data = f7723eee
|
# READ STATUS: Burst-No: 18 Addr: 0016c7d9 Rxd: cab47c95
|
# READ STATUS: Burst-No: 18 Addr: 0016c7d9 Rxd: cab47c95
|
# tb_core.u_sdram32 : at time 30523.0 ns READ : Bank = 2 Row = 364, Col = 1, Data = 304e4d60
|
# tb_core.u_sdram32 : at time 31123.0 ns READ : Bank = 2 Row = 364, Col = 1, Data = 304e4d60
|
# READ STATUS: Burst-No: 19 Addr: 0016c7db Rxd: f7723eee
|
# READ STATUS: Burst-No: 19 Addr: 0016c7db Rxd: f7723eee
|
# READ STATUS: Burst-No: 20 Addr: 0016c7dd Rxd: 304e4d60
|
# READ STATUS: Burst-No: 20 Addr: 0016c7dd Rxd: 304e4d60
|
# Write Address: 001c5ee5, Burst Size: 41
|
# Write Address: 001c5ee5, Burst Size: 41
|
# tb_core.u_sdram32 : at time 30697.0 ns ACT : Bank = 3 Row = 453
|
# tb_core.u_sdram32 : at time 31297.0 ns ACT : Bank = 3 Row = 453
|
# tb_core.u_sdram32 : at time 30727.0 ns WRITE: Bank = 3 Row = 453, Col = 185, Data = 322f7d64
|
# tb_core.u_sdram32 : at time 31327.0 ns WRITE: Bank = 3 Row = 453, Col = 185, Data = 322f7d64
|
# Status: Burst-No: 0 Write Address: 001c5ee5 WriteData: 322f7d64
|
# Status: Burst-No: 0 Write Address: 001c5ee5 WriteData: 322f7d64
|
# tb_core.u_sdram32 : at time 30737.0 ns WRITE: Bank = 3 Row = 453, Col = 186, Data = 14b43729
|
# tb_core.u_sdram32 : at time 31337.0 ns WRITE: Bank = 3 Row = 453, Col = 186, Data = 14b43729
|
# Status: Burst-No: 1 Write Address: 001c5ee5 WriteData: 14b43729
|
# Status: Burst-No: 1 Write Address: 001c5ee5 WriteData: 14b43729
|
# tb_core.u_sdram32 : at time 30747.0 ns WRITE: Bank = 3 Row = 453, Col = 187, Data = f0eeaee1
|
# tb_core.u_sdram32 : at time 31347.0 ns WRITE: Bank = 3 Row = 453, Col = 187, Data = f0eeaee1
|
# Status: Burst-No: 2 Write Address: 001c5ee5 WriteData: f0eeaee1
|
# Status: Burst-No: 2 Write Address: 001c5ee5 WriteData: f0eeaee1
|
# tb_core.u_sdram32 : at time 30757.0 ns WRITE: Bank = 3 Row = 453, Col = 188, Data = bbbc5277
|
# tb_core.u_sdram32 : at time 31357.0 ns WRITE: Bank = 3 Row = 453, Col = 188, Data = bbbc5277
|
# Status: Burst-No: 3 Write Address: 001c5ee5 WriteData: bbbc5277
|
# Status: Burst-No: 3 Write Address: 001c5ee5 WriteData: bbbc5277
|
# tb_core.u_sdram32 : at time 30767.0 ns WRITE: Bank = 3 Row = 453, Col = 189, Data = 3715156e
|
# tb_core.u_sdram32 : at time 31367.0 ns WRITE: Bank = 3 Row = 453, Col = 189, Data = 3715156e
|
# Status: Burst-No: 4 Write Address: 001c5ee5 WriteData: 3715156e
|
# Status: Burst-No: 4 Write Address: 001c5ee5 WriteData: 3715156e
|
# tb_core.u_sdram32 : at time 30777.0 ns WRITE: Bank = 3 Row = 453, Col = 190, Data = 40aaf581
|
# tb_core.u_sdram32 : at time 31377.0 ns WRITE: Bank = 3 Row = 453, Col = 190, Data = 40aaf581
|
# Status: Burst-No: 5 Write Address: 001c5ee5 WriteData: 40aaf581
|
# Status: Burst-No: 5 Write Address: 001c5ee5 WriteData: 40aaf581
|
# tb_core.u_sdram32 : at time 30787.0 ns WRITE: Bank = 3 Row = 453, Col = 191, Data = 6a9fb9d5
|
# tb_core.u_sdram32 : at time 31387.0 ns WRITE: Bank = 3 Row = 453, Col = 191, Data = 6a9fb9d5
|
# Status: Burst-No: 6 Write Address: 001c5ee5 WriteData: 6a9fb9d5
|
# Status: Burst-No: 6 Write Address: 001c5ee5 WriteData: 6a9fb9d5
|
# tb_core.u_sdram32 : at time 30797.0 ns WRITE: Bank = 3 Row = 453, Col = 192, Data = 3437d568
|
# tb_core.u_sdram32 : at time 31397.0 ns WRITE: Bank = 3 Row = 453, Col = 192, Data = 3437d568
|
# Status: Burst-No: 7 Write Address: 001c5ee5 WriteData: 3437d568
|
# Status: Burst-No: 7 Write Address: 001c5ee5 WriteData: 3437d568
|
# tb_core.u_sdram32 : at time 30807.0 ns WRITE: Bank = 3 Row = 453, Col = 193, Data = 786271f0
|
# tb_core.u_sdram32 : at time 31407.0 ns WRITE: Bank = 3 Row = 453, Col = 193, Data = 786271f0
|
# Status: Burst-No: 8 Write Address: 001c5ee5 WriteData: 786271f0
|
# Status: Burst-No: 8 Write Address: 001c5ee5 WriteData: 786271f0
|
# tb_core.u_sdram32 : at time 30817.0 ns WRITE: Bank = 3 Row = 453, Col = 194, Data = d57800aa
|
# tb_core.u_sdram32 : at time 31417.0 ns WRITE: Bank = 3 Row = 453, Col = 194, Data = d57800aa
|
# Status: Burst-No: 9 Write Address: 001c5ee5 WriteData: d57800aa
|
# Status: Burst-No: 9 Write Address: 001c5ee5 WriteData: d57800aa
|
# tb_core.u_sdram32 : at time 30827.0 ns WRITE: Bank = 3 Row = 453, Col = 195, Data = 079fc30f
|
# tb_core.u_sdram32 : at time 31427.0 ns WRITE: Bank = 3 Row = 453, Col = 195, Data = 079fc30f
|
# Status: Burst-No: 10 Write Address: 001c5ee5 WriteData: 079fc30f
|
# Status: Burst-No: 10 Write Address: 001c5ee5 WriteData: 079fc30f
|
# tb_core.u_sdram32 : at time 30837.0 ns WRITE: Bank = 3 Row = 453, Col = 196, Data = f8dc48f1
|
# tb_core.u_sdram32 : at time 31437.0 ns WRITE: Bank = 3 Row = 453, Col = 196, Data = f8dc48f1
|
# Status: Burst-No: 11 Write Address: 001c5ee5 WriteData: f8dc48f1
|
# Status: Burst-No: 11 Write Address: 001c5ee5 WriteData: f8dc48f1
|
# tb_core.u_sdram32 : at time 30847.0 ns WRITE: Bank = 3 Row = 453, Col = 197, Data = be9bbc7d
|
# tb_core.u_sdram32 : at time 31447.0 ns WRITE: Bank = 3 Row = 453, Col = 197, Data = be9bbc7d
|
# Status: Burst-No: 12 Write Address: 001c5ee5 WriteData: be9bbc7d
|
# Status: Burst-No: 12 Write Address: 001c5ee5 WriteData: be9bbc7d
|
# tb_core.u_sdram32 : at time 30857.0 ns WRITE: Bank = 3 Row = 453, Col = 198, Data = 472e958e
|
# tb_core.u_sdram32 : at time 31457.0 ns WRITE: Bank = 3 Row = 453, Col = 198, Data = 472e958e
|
# Status: Burst-No: 13 Write Address: 001c5ee5 WriteData: 472e958e
|
# Status: Burst-No: 13 Write Address: 001c5ee5 WriteData: 472e958e
|
# tb_core.u_sdram32 : at time 30867.0 ns WRITE: Bank = 3 Row = 453, Col = 199, Data = f161dce2
|
# tb_core.u_sdram32 : at time 31467.0 ns WRITE: Bank = 3 Row = 453, Col = 199, Data = f161dce2
|
# Status: Burst-No: 14 Write Address: 001c5ee5 WriteData: f161dce2
|
# Status: Burst-No: 14 Write Address: 001c5ee5 WriteData: f161dce2
|
# tb_core.u_sdram32 : at time 30877.0 ns WRITE: Bank = 3 Row = 453, Col = 200, Data = 1e664d3c
|
# tb_core.u_sdram32 : at time 31477.0 ns WRITE: Bank = 3 Row = 453, Col = 200, Data = 1e664d3c
|
# Status: Burst-No: 15 Write Address: 001c5ee5 WriteData: 1e664d3c
|
# Status: Burst-No: 15 Write Address: 001c5ee5 WriteData: 1e664d3c
|
# tb_core.u_sdram32 : at time 30887.0 ns WRITE: Bank = 3 Row = 453, Col = 201, Data = d4b5e6a9
|
# tb_core.u_sdram32 : at time 31487.0 ns WRITE: Bank = 3 Row = 453, Col = 201, Data = d4b5e6a9
|
# Status: Burst-No: 16 Write Address: 001c5ee5 WriteData: d4b5e6a9
|
# Status: Burst-No: 16 Write Address: 001c5ee5 WriteData: d4b5e6a9
|
# tb_core.u_sdram32 : at time 30897.0 ns WRITE: Bank = 3 Row = 453, Col = 202, Data = 77ebb1ef
|
# tb_core.u_sdram32 : at time 31497.0 ns WRITE: Bank = 3 Row = 453, Col = 202, Data = 77ebb1ef
|
# Status: Burst-No: 17 Write Address: 001c5ee5 WriteData: 77ebb1ef
|
# Status: Burst-No: 17 Write Address: 001c5ee5 WriteData: 77ebb1ef
|
# tb_core.u_sdram32 : at time 30907.0 ns WRITE: Bank = 3 Row = 453, Col = 203, Data = ade7d05b
|
# tb_core.u_sdram32 : at time 31507.0 ns WRITE: Bank = 3 Row = 453, Col = 203, Data = ade7d05b
|
# Status: Burst-No: 18 Write Address: 001c5ee5 WriteData: ade7d05b
|
# Status: Burst-No: 18 Write Address: 001c5ee5 WriteData: ade7d05b
|
# tb_core.u_sdram32 : at time 30917.0 ns WRITE: Bank = 3 Row = 453, Col = 204, Data = d7a23caf
|
# tb_core.u_sdram32 : at time 31517.0 ns WRITE: Bank = 3 Row = 453, Col = 204, Data = d7a23caf
|
# Status: Burst-No: 19 Write Address: 001c5ee5 WriteData: d7a23caf
|
# Status: Burst-No: 19 Write Address: 001c5ee5 WriteData: d7a23caf
|
# tb_core.u_sdram32 : at time 30927.0 ns WRITE: Bank = 3 Row = 453, Col = 205, Data = 25029b4a
|
# tb_core.u_sdram32 : at time 31527.0 ns WRITE: Bank = 3 Row = 453, Col = 205, Data = 25029b4a
|
# Status: Burst-No: 20 Write Address: 001c5ee5 WriteData: 25029b4a
|
# Status: Burst-No: 20 Write Address: 001c5ee5 WriteData: 25029b4a
|
# tb_core.u_sdram32 : at time 30937.0 ns WRITE: Bank = 3 Row = 453, Col = 206, Data = 5cd20db9
|
# tb_core.u_sdram32 : at time 31537.0 ns WRITE: Bank = 3 Row = 453, Col = 206, Data = 5cd20db9
|
# Status: Burst-No: 21 Write Address: 001c5ee5 WriteData: 5cd20db9
|
# Status: Burst-No: 21 Write Address: 001c5ee5 WriteData: 5cd20db9
|
# tb_core.u_sdram32 : at time 30947.0 ns WRITE: Bank = 3 Row = 453, Col = 207, Data = 098e2d13
|
# tb_core.u_sdram32 : at time 31547.0 ns WRITE: Bank = 3 Row = 453, Col = 207, Data = 098e2d13
|
# Status: Burst-No: 22 Write Address: 001c5ee5 WriteData: 098e2d13
|
# Status: Burst-No: 22 Write Address: 001c5ee5 WriteData: 098e2d13
|
# tb_core.u_sdram32 : at time 30957.0 ns WRITE: Bank = 3 Row = 453, Col = 208, Data = 09c83513
|
# tb_core.u_sdram32 : at time 31557.0 ns WRITE: Bank = 3 Row = 453, Col = 208, Data = 09c83513
|
# Status: Burst-No: 23 Write Address: 001c5ee5 WriteData: 09c83513
|
# Status: Burst-No: 23 Write Address: 001c5ee5 WriteData: 09c83513
|
# tb_core.u_sdram32 : at time 30967.0 ns WRITE: Bank = 3 Row = 453, Col = 209, Data = 32dc4165
|
# tb_core.u_sdram32 : at time 31567.0 ns WRITE: Bank = 3 Row = 453, Col = 209, Data = 32dc4165
|
# Status: Burst-No: 24 Write Address: 001c5ee5 WriteData: 32dc4165
|
# Status: Burst-No: 24 Write Address: 001c5ee5 WriteData: 32dc4165
|
# tb_core.u_sdram32 : at time 30977.0 ns WRITE: Bank = 3 Row = 453, Col = 210, Data = 28c62751
|
# tb_core.u_sdram32 : at time 31577.0 ns WRITE: Bank = 3 Row = 453, Col = 210, Data = 28c62751
|
# Status: Burst-No: 25 Write Address: 001c5ee5 WriteData: 28c62751
|
# Status: Burst-No: 25 Write Address: 001c5ee5 WriteData: 28c62751
|
# tb_core.u_sdram32 : at time 30987.0 ns WRITE: Bank = 3 Row = 453, Col = 211, Data = db983ab7
|
# tb_core.u_sdram32 : at time 31587.0 ns WRITE: Bank = 3 Row = 453, Col = 211, Data = db983ab7
|
# Status: Burst-No: 26 Write Address: 001c5ee5 WriteData: db983ab7
|
# Status: Burst-No: 26 Write Address: 001c5ee5 WriteData: db983ab7
|
# tb_core.u_sdram32 : at time 30997.0 ns WRITE: Bank = 3 Row = 453, Col = 212, Data = cc981099
|
# tb_core.u_sdram32 : at time 31597.0 ns WRITE: Bank = 3 Row = 453, Col = 212, Data = cc981099
|
# Status: Burst-No: 27 Write Address: 001c5ee5 WriteData: cc981099
|
# Status: Burst-No: 27 Write Address: 001c5ee5 WriteData: cc981099
|
# tb_core.u_sdram32 : at time 31007.0 ns WRITE: Bank = 3 Row = 453, Col = 213, Data = 9d12083a
|
# tb_core.u_sdram32 : at time 31607.0 ns WRITE: Bank = 3 Row = 453, Col = 213, Data = 9d12083a
|
# Status: Burst-No: 28 Write Address: 001c5ee5 WriteData: 9d12083a
|
# Status: Burst-No: 28 Write Address: 001c5ee5 WriteData: 9d12083a
|
# tb_core.u_sdram32 : at time 31017.0 ns WRITE: Bank = 3 Row = 453, Col = 214, Data = b8ea3a71
|
# tb_core.u_sdram32 : at time 31617.0 ns WRITE: Bank = 3 Row = 453, Col = 214, Data = b8ea3a71
|
# Status: Burst-No: 29 Write Address: 001c5ee5 WriteData: b8ea3a71
|
# Status: Burst-No: 29 Write Address: 001c5ee5 WriteData: b8ea3a71
|
# tb_core.u_sdram32 : at time 31027.0 ns WRITE: Bank = 3 Row = 453, Col = 215, Data = 317c0762
|
# tb_core.u_sdram32 : at time 31627.0 ns WRITE: Bank = 3 Row = 453, Col = 215, Data = 317c0762
|
# Status: Burst-No: 30 Write Address: 001c5ee5 WriteData: 317c0762
|
# Status: Burst-No: 30 Write Address: 001c5ee5 WriteData: 317c0762
|
# tb_core.u_sdram32 : at time 31037.0 ns WRITE: Bank = 3 Row = 453, Col = 216, Data = f2356ae4
|
# tb_core.u_sdram32 : at time 31637.0 ns WRITE: Bank = 3 Row = 453, Col = 216, Data = f2356ae4
|
# Status: Burst-No: 31 Write Address: 001c5ee5 WriteData: f2356ae4
|
# Status: Burst-No: 31 Write Address: 001c5ee5 WriteData: f2356ae4
|
# tb_core.u_sdram32 : at time 31047.0 ns WRITE: Bank = 3 Row = 453, Col = 217, Data = 1513dd2a
|
# tb_core.u_sdram32 : at time 31647.0 ns WRITE: Bank = 3 Row = 453, Col = 217, Data = 1513dd2a
|
# Status: Burst-No: 32 Write Address: 001c5ee5 WriteData: 1513dd2a
|
# Status: Burst-No: 32 Write Address: 001c5ee5 WriteData: 1513dd2a
|
# tb_core.u_sdram32 : at time 31057.0 ns WRITE: Bank = 3 Row = 453, Col = 218, Data = beda447d
|
# tb_core.u_sdram32 : at time 31657.0 ns WRITE: Bank = 3 Row = 453, Col = 218, Data = beda447d
|
# Status: Burst-No: 33 Write Address: 001c5ee5 WriteData: beda447d
|
# Status: Burst-No: 33 Write Address: 001c5ee5 WriteData: beda447d
|
# tb_core.u_sdram32 : at time 31067.0 ns WRITE: Bank = 3 Row = 453, Col = 219, Data = 2cee5f59
|
# tb_core.u_sdram32 : at time 31667.0 ns WRITE: Bank = 3 Row = 453, Col = 219, Data = 2cee5f59
|
# Status: Burst-No: 34 Write Address: 001c5ee5 WriteData: 2cee5f59
|
# Status: Burst-No: 34 Write Address: 001c5ee5 WriteData: 2cee5f59
|
# tb_core.u_sdram32 : at time 31077.0 ns WRITE: Bank = 3 Row = 453, Col = 220, Data = 72c3a3e5
|
# tb_core.u_sdram32 : at time 31677.0 ns WRITE: Bank = 3 Row = 453, Col = 220, Data = 72c3a3e5
|
# Status: Burst-No: 35 Write Address: 001c5ee5 WriteData: 72c3a3e5
|
# Status: Burst-No: 35 Write Address: 001c5ee5 WriteData: 72c3a3e5
|
# tb_core.u_sdram32 : at time 31087.0 ns WRITE: Bank = 3 Row = 453, Col = 221, Data = 76de6bed
|
# tb_core.u_sdram32 : at time 31687.0 ns WRITE: Bank = 3 Row = 453, Col = 221, Data = 76de6bed
|
# Status: Burst-No: 36 Write Address: 001c5ee5 WriteData: 76de6bed
|
# Status: Burst-No: 36 Write Address: 001c5ee5 WriteData: 76de6bed
|
# tb_core.u_sdram32 : at time 31097.0 ns WRITE: Bank = 3 Row = 453, Col = 222, Data = e4a800c9
|
# tb_core.u_sdram32 : at time 31697.0 ns WRITE: Bank = 3 Row = 453, Col = 222, Data = e4a800c9
|
# Status: Burst-No: 37 Write Address: 001c5ee5 WriteData: e4a800c9
|
# Status: Burst-No: 37 Write Address: 001c5ee5 WriteData: e4a800c9
|
# tb_core.u_sdram32 : at time 31107.0 ns WRITE: Bank = 3 Row = 453, Col = 223, Data = a0aecc41
|
# tb_core.u_sdram32 : at time 31707.0 ns WRITE: Bank = 3 Row = 453, Col = 223, Data = a0aecc41
|
# Status: Burst-No: 38 Write Address: 001c5ee5 WriteData: a0aecc41
|
# Status: Burst-No: 38 Write Address: 001c5ee5 WriteData: a0aecc41
|
# tb_core.u_sdram32 : at time 31117.0 ns WRITE: Bank = 3 Row = 453, Col = 224, Data = 57c1d1af
|
# tb_core.u_sdram32 : at time 31717.0 ns WRITE: Bank = 3 Row = 453, Col = 224, Data = 57c1d1af
|
# Status: Burst-No: 39 Write Address: 001c5ee5 WriteData: 57c1d1af
|
# Status: Burst-No: 39 Write Address: 001c5ee5 WriteData: 57c1d1af
|
# tb_core.u_sdram32 : at time 31127.0 ns WRITE: Bank = 3 Row = 453, Col = 225, Data = eda71cdb
|
# tb_core.u_sdram32 : at time 31727.0 ns WRITE: Bank = 3 Row = 453, Col = 225, Data = eda71cdb
|
# Status: Burst-No: 40 Write Address: 001c5ee5 WriteData: eda71cdb
|
# Status: Burst-No: 40 Write Address: 001c5ee5 WriteData: eda71cdb
|
# tb_core.u_sdram32 : at time 31137.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 31737.0 ns BST : Burst Terminate
|
# Write Address: 0016e8cd, Burst Size: 49
|
# Write Address: 0016e8cd, Burst Size: 49
|
# tb_core.u_sdram32 : at time 31277.0 ns ACT : Bank = 2 Row = 366
|
# tb_core.u_sdram32 : at time 31877.0 ns ACT : Bank = 2 Row = 366
|
# tb_core.u_sdram32 : at time 31307.0 ns WRITE: Bank = 2 Row = 366, Col = 51, Data = 8326d406
|
# tb_core.u_sdram32 : at time 31907.0 ns WRITE: Bank = 2 Row = 366, Col = 51, Data = 8326d406
|
# Status: Burst-No: 0 Write Address: 0016e8cd WriteData: 8326d406
|
# Status: Burst-No: 0 Write Address: 0016e8cd WriteData: 8326d406
|
# tb_core.u_sdram32 : at time 31317.0 ns WRITE: Bank = 2 Row = 366, Col = 52, Data = d14820a2
|
# tb_core.u_sdram32 : at time 31917.0 ns WRITE: Bank = 2 Row = 366, Col = 52, Data = d14820a2
|
# Status: Burst-No: 1 Write Address: 0016e8cd WriteData: d14820a2
|
# Status: Burst-No: 1 Write Address: 0016e8cd WriteData: d14820a2
|
# tb_core.u_sdram32 : at time 31327.0 ns WRITE: Bank = 2 Row = 366, Col = 53, Data = 5e983dbd
|
# tb_core.u_sdram32 : at time 31927.0 ns WRITE: Bank = 2 Row = 366, Col = 53, Data = 5e983dbd
|
# Status: Burst-No: 2 Write Address: 0016e8cd WriteData: 5e983dbd
|
# Status: Burst-No: 2 Write Address: 0016e8cd WriteData: 5e983dbd
|
# tb_core.u_sdram32 : at time 31337.0 ns WRITE: Bank = 2 Row = 366, Col = 54, Data = b555de6a
|
# tb_core.u_sdram32 : at time 31937.0 ns WRITE: Bank = 2 Row = 366, Col = 54, Data = b555de6a
|
# Status: Burst-No: 3 Write Address: 0016e8cd WriteData: b555de6a
|
# Status: Burst-No: 3 Write Address: 0016e8cd WriteData: b555de6a
|
# tb_core.u_sdram32 : at time 31347.0 ns WRITE: Bank = 2 Row = 366, Col = 55, Data = 6e3d47dc
|
# tb_core.u_sdram32 : at time 31947.0 ns WRITE: Bank = 2 Row = 366, Col = 55, Data = 6e3d47dc
|
# Status: Burst-No: 4 Write Address: 0016e8cd WriteData: 6e3d47dc
|
# Status: Burst-No: 4 Write Address: 0016e8cd WriteData: 6e3d47dc
|
# tb_core.u_sdram32 : at time 31357.0 ns WRITE: Bank = 2 Row = 366, Col = 56, Data = a86c5e50
|
# tb_core.u_sdram32 : at time 31957.0 ns WRITE: Bank = 2 Row = 366, Col = 56, Data = a86c5e50
|
# Status: Burst-No: 5 Write Address: 0016e8cd WriteData: a86c5e50
|
# Status: Burst-No: 5 Write Address: 0016e8cd WriteData: a86c5e50
|
# tb_core.u_sdram32 : at time 31367.0 ns WRITE: Bank = 2 Row = 366, Col = 57, Data = bd86f47b
|
# tb_core.u_sdram32 : at time 31967.0 ns WRITE: Bank = 2 Row = 366, Col = 57, Data = bd86f47b
|
# Status: Burst-No: 6 Write Address: 0016e8cd WriteData: bd86f47b
|
# Status: Burst-No: 6 Write Address: 0016e8cd WriteData: bd86f47b
|
# tb_core.u_sdram32 : at time 31377.0 ns WRITE: Bank = 2 Row = 366, Col = 58, Data = 929d5825
|
# tb_core.u_sdram32 : at time 31977.0 ns WRITE: Bank = 2 Row = 366, Col = 58, Data = 929d5825
|
# Status: Burst-No: 7 Write Address: 0016e8cd WriteData: 929d5825
|
# Status: Burst-No: 7 Write Address: 0016e8cd WriteData: 929d5825
|
# tb_core.u_sdram32 : at time 31387.0 ns WRITE: Bank = 2 Row = 366, Col = 59, Data = bc3f8478
|
# tb_core.u_sdram32 : at time 31987.0 ns WRITE: Bank = 2 Row = 366, Col = 59, Data = bc3f8478
|
# Status: Burst-No: 8 Write Address: 0016e8cd WriteData: bc3f8478
|
# Status: Burst-No: 8 Write Address: 0016e8cd WriteData: bc3f8478
|
# tb_core.u_sdram32 : at time 31397.0 ns WRITE: Bank = 2 Row = 366, Col = 60, Data = 7b7b89f6
|
# tb_core.u_sdram32 : at time 31997.0 ns WRITE: Bank = 2 Row = 366, Col = 60, Data = 7b7b89f6
|
# Status: Burst-No: 9 Write Address: 0016e8cd WriteData: 7b7b89f6
|
# Status: Burst-No: 9 Write Address: 0016e8cd WriteData: 7b7b89f6
|
# tb_core.u_sdram32 : at time 31407.0 ns WRITE: Bank = 2 Row = 366, Col = 61, Data = ae23ce5c
|
# tb_core.u_sdram32 : at time 32007.0 ns WRITE: Bank = 2 Row = 366, Col = 61, Data = ae23ce5c
|
# Status: Burst-No: 10 Write Address: 0016e8cd WriteData: ae23ce5c
|
# Status: Burst-No: 10 Write Address: 0016e8cd WriteData: ae23ce5c
|
# tb_core.u_sdram32 : at time 31417.0 ns WRITE: Bank = 2 Row = 366, Col = 62, Data = 11cc9b23
|
# tb_core.u_sdram32 : at time 32017.0 ns WRITE: Bank = 2 Row = 366, Col = 62, Data = 11cc9b23
|
# Status: Burst-No: 11 Write Address: 0016e8cd WriteData: 11cc9b23
|
# Status: Burst-No: 11 Write Address: 0016e8cd WriteData: 11cc9b23
|
# tb_core.u_sdram32 : at time 31427.0 ns WRITE: Bank = 2 Row = 366, Col = 63, Data = 3cb3ab79
|
# tb_core.u_sdram32 : at time 32027.0 ns WRITE: Bank = 2 Row = 366, Col = 63, Data = 3cb3ab79
|
# Status: Burst-No: 12 Write Address: 0016e8cd WriteData: 3cb3ab79
|
# Status: Burst-No: 12 Write Address: 0016e8cd WriteData: 3cb3ab79
|
# tb_core.u_sdram32 : at time 31437.0 ns WRITE: Bank = 2 Row = 366, Col = 64, Data = 644605c8
|
# tb_core.u_sdram32 : at time 32037.0 ns WRITE: Bank = 2 Row = 366, Col = 64, Data = 644605c8
|
# Status: Burst-No: 13 Write Address: 0016e8cd WriteData: 644605c8
|
# Status: Burst-No: 13 Write Address: 0016e8cd WriteData: 644605c8
|
# tb_core.u_sdram32 : at time 31447.0 ns WRITE: Bank = 2 Row = 366, Col = 65, Data = ddd146bb
|
# tb_core.u_sdram32 : at time 32047.0 ns WRITE: Bank = 2 Row = 366, Col = 65, Data = ddd146bb
|
# Status: Burst-No: 14 Write Address: 0016e8cd WriteData: ddd146bb
|
# Status: Burst-No: 14 Write Address: 0016e8cd WriteData: ddd146bb
|
# tb_core.u_sdram32 : at time 31457.0 ns WRITE: Bank = 2 Row = 366, Col = 66, Data = 870cee0e
|
# tb_core.u_sdram32 : at time 32057.0 ns WRITE: Bank = 2 Row = 366, Col = 66, Data = 870cee0e
|
# Status: Burst-No: 15 Write Address: 0016e8cd WriteData: 870cee0e
|
# Status: Burst-No: 15 Write Address: 0016e8cd WriteData: 870cee0e
|
# tb_core.u_sdram32 : at time 31467.0 ns WRITE: Bank = 2 Row = 366, Col = 67, Data = b9879473
|
# tb_core.u_sdram32 : at time 32067.0 ns WRITE: Bank = 2 Row = 366, Col = 67, Data = b9879473
|
# Status: Burst-No: 16 Write Address: 0016e8cd WriteData: b9879473
|
# Status: Burst-No: 16 Write Address: 0016e8cd WriteData: b9879473
|
# tb_core.u_sdram32 : at time 31477.0 ns WRITE: Bank = 2 Row = 366, Col = 68, Data = 0671030c
|
# tb_core.u_sdram32 : at time 32077.0 ns WRITE: Bank = 2 Row = 366, Col = 68, Data = 0671030c
|
# Status: Burst-No: 17 Write Address: 0016e8cd WriteData: 0671030c
|
# Status: Burst-No: 17 Write Address: 0016e8cd WriteData: 0671030c
|
# tb_core.u_sdram32 : at time 31487.0 ns WRITE: Bank = 2 Row = 366, Col = 69, Data = e70f98ce
|
# tb_core.u_sdram32 : at time 32087.0 ns WRITE: Bank = 2 Row = 366, Col = 69, Data = e70f98ce
|
# Status: Burst-No: 18 Write Address: 0016e8cd WriteData: e70f98ce
|
# Status: Burst-No: 18 Write Address: 0016e8cd WriteData: e70f98ce
|
# tb_core.u_sdram32 : at time 31497.0 ns WRITE: Bank = 2 Row = 366, Col = 70, Data = 6a1a61d4
|
# tb_core.u_sdram32 : at time 32097.0 ns WRITE: Bank = 2 Row = 366, Col = 70, Data = 6a1a61d4
|
# Status: Burst-No: 19 Write Address: 0016e8cd WriteData: 6a1a61d4
|
# Status: Burst-No: 19 Write Address: 0016e8cd WriteData: 6a1a61d4
|
# tb_core.u_sdram32 : at time 31507.0 ns WRITE: Bank = 2 Row = 366, Col = 71, Data = acecdc59
|
# tb_core.u_sdram32 : at time 32107.0 ns WRITE: Bank = 2 Row = 366, Col = 71, Data = acecdc59
|
# Status: Burst-No: 20 Write Address: 0016e8cd WriteData: acecdc59
|
# Status: Burst-No: 20 Write Address: 0016e8cd WriteData: acecdc59
|
# tb_core.u_sdram32 : at time 31517.0 ns WRITE: Bank = 2 Row = 366, Col = 72, Data = 5ca26fb9
|
# tb_core.u_sdram32 : at time 32117.0 ns WRITE: Bank = 2 Row = 366, Col = 72, Data = 5ca26fb9
|
# Status: Burst-No: 21 Write Address: 0016e8cd WriteData: 5ca26fb9
|
# Status: Burst-No: 21 Write Address: 0016e8cd WriteData: 5ca26fb9
|
# tb_core.u_sdram32 : at time 31527.0 ns WRITE: Bank = 2 Row = 366, Col = 73, Data = d9b8c0b3
|
# tb_core.u_sdram32 : at time 32127.0 ns WRITE: Bank = 2 Row = 366, Col = 73, Data = d9b8c0b3
|
# Status: Burst-No: 22 Write Address: 0016e8cd WriteData: d9b8c0b3
|
# Status: Burst-No: 22 Write Address: 0016e8cd WriteData: d9b8c0b3
|
# tb_core.u_sdram32 : at time 31537.0 ns WRITE: Bank = 2 Row = 366, Col = 74, Data = 7a4fbff4
|
# tb_core.u_sdram32 : at time 32137.0 ns WRITE: Bank = 2 Row = 366, Col = 74, Data = 7a4fbff4
|
# Status: Burst-No: 23 Write Address: 0016e8cd WriteData: 7a4fbff4
|
# Status: Burst-No: 23 Write Address: 0016e8cd WriteData: 7a4fbff4
|
# tb_core.u_sdram32 : at time 31547.0 ns WRITE: Bank = 2 Row = 366, Col = 75, Data = baf4e275
|
# tb_core.u_sdram32 : at time 32147.0 ns WRITE: Bank = 2 Row = 366, Col = 75, Data = baf4e275
|
# Status: Burst-No: 24 Write Address: 0016e8cd WriteData: baf4e275
|
# Status: Burst-No: 24 Write Address: 0016e8cd WriteData: baf4e275
|
# tb_core.u_sdram32 : at time 31557.0 ns WRITE: Bank = 2 Row = 366, Col = 76, Data = 066cf10c
|
# tb_core.u_sdram32 : at time 32157.0 ns WRITE: Bank = 2 Row = 366, Col = 76, Data = 066cf10c
|
# Status: Burst-No: 25 Write Address: 0016e8cd WriteData: 066cf10c
|
# Status: Burst-No: 25 Write Address: 0016e8cd WriteData: 066cf10c
|
# tb_core.u_sdram32 : at time 31567.0 ns WRITE: Bank = 2 Row = 366, Col = 77, Data = 9cfc7a39
|
# tb_core.u_sdram32 : at time 32167.0 ns WRITE: Bank = 2 Row = 366, Col = 77, Data = 9cfc7a39
|
# Status: Burst-No: 26 Write Address: 0016e8cd WriteData: 9cfc7a39
|
# Status: Burst-No: 26 Write Address: 0016e8cd WriteData: 9cfc7a39
|
# tb_core.u_sdram32 : at time 31577.0 ns WRITE: Bank = 2 Row = 366, Col = 78, Data = 01729302
|
# tb_core.u_sdram32 : at time 32177.0 ns WRITE: Bank = 2 Row = 366, Col = 78, Data = 01729302
|
# Status: Burst-No: 27 Write Address: 0016e8cd WriteData: 01729302
|
# Status: Burst-No: 27 Write Address: 0016e8cd WriteData: 01729302
|
# tb_core.u_sdram32 : at time 31587.0 ns WRITE: Bank = 2 Row = 366, Col = 79, Data = 8aecbe15
|
# tb_core.u_sdram32 : at time 32187.0 ns WRITE: Bank = 2 Row = 366, Col = 79, Data = 8aecbe15
|
# Status: Burst-No: 28 Write Address: 0016e8cd WriteData: 8aecbe15
|
# Status: Burst-No: 28 Write Address: 0016e8cd WriteData: 8aecbe15
|
# tb_core.u_sdram32 : at time 31597.0 ns WRITE: Bank = 2 Row = 366, Col = 80, Data = 02fbf905
|
# tb_core.u_sdram32 : at time 32197.0 ns WRITE: Bank = 2 Row = 366, Col = 80, Data = 02fbf905
|
# Status: Burst-No: 29 Write Address: 0016e8cd WriteData: 02fbf905
|
# Status: Burst-No: 29 Write Address: 0016e8cd WriteData: 02fbf905
|
# tb_core.u_sdram32 : at time 31607.0 ns WRITE: Bank = 2 Row = 366, Col = 81, Data = 271c434e
|
# tb_core.u_sdram32 : at time 32207.0 ns WRITE: Bank = 2 Row = 366, Col = 81, Data = 271c434e
|
# Status: Burst-No: 30 Write Address: 0016e8cd WriteData: 271c434e
|
# Status: Burst-No: 30 Write Address: 0016e8cd WriteData: 271c434e
|
# tb_core.u_sdram32 : at time 31617.0 ns WRITE: Bank = 2 Row = 366, Col = 82, Data = 013f2902
|
# tb_core.u_sdram32 : at time 32217.0 ns WRITE: Bank = 2 Row = 366, Col = 82, Data = 013f2902
|
# Status: Burst-No: 31 Write Address: 0016e8cd WriteData: 013f2902
|
# Status: Burst-No: 31 Write Address: 0016e8cd WriteData: 013f2902
|
# tb_core.u_sdram32 : at time 31627.0 ns WRITE: Bank = 2 Row = 366, Col = 83, Data = 5c7951b8
|
# tb_core.u_sdram32 : at time 32227.0 ns WRITE: Bank = 2 Row = 366, Col = 83, Data = 5c7951b8
|
# Status: Burst-No: 32 Write Address: 0016e8cd WriteData: 5c7951b8
|
# Status: Burst-No: 32 Write Address: 0016e8cd WriteData: 5c7951b8
|
# tb_core.u_sdram32 : at time 31637.0 ns WRITE: Bank = 2 Row = 366, Col = 84, Data = 847fb208
|
# tb_core.u_sdram32 : at time 32237.0 ns WRITE: Bank = 2 Row = 366, Col = 84, Data = 847fb208
|
# Status: Burst-No: 33 Write Address: 0016e8cd WriteData: 847fb208
|
# Status: Burst-No: 33 Write Address: 0016e8cd WriteData: 847fb208
|
# tb_core.u_sdram32 : at time 31647.0 ns WRITE: Bank = 2 Row = 366, Col = 85, Data = 46e7538d
|
# tb_core.u_sdram32 : at time 32247.0 ns WRITE: Bank = 2 Row = 366, Col = 85, Data = 46e7538d
|
# Status: Burst-No: 34 Write Address: 0016e8cd WriteData: 46e7538d
|
# Status: Burst-No: 34 Write Address: 0016e8cd WriteData: 46e7538d
|
# tb_core.u_sdram32 : at time 31657.0 ns WRITE: Bank = 2 Row = 366, Col = 86, Data = d7b48eaf
|
# tb_core.u_sdram32 : at time 32257.0 ns WRITE: Bank = 2 Row = 366, Col = 86, Data = d7b48eaf
|
# Status: Burst-No: 35 Write Address: 0016e8cd WriteData: d7b48eaf
|
# Status: Burst-No: 35 Write Address: 0016e8cd WriteData: d7b48eaf
|
# tb_core.u_sdram32 : at time 31667.0 ns WRITE: Bank = 2 Row = 366, Col = 87, Data = 747331e8
|
# tb_core.u_sdram32 : at time 32267.0 ns WRITE: Bank = 2 Row = 366, Col = 87, Data = 747331e8
|
# Status: Burst-No: 36 Write Address: 0016e8cd WriteData: 747331e8
|
# Status: Burst-No: 36 Write Address: 0016e8cd WriteData: 747331e8
|
# tb_core.u_sdram32 : at time 31677.0 ns WRITE: Bank = 2 Row = 366, Col = 88, Data = 48590990
|
# tb_core.u_sdram32 : at time 32277.0 ns WRITE: Bank = 2 Row = 366, Col = 88, Data = 48590990
|
# Status: Burst-No: 37 Write Address: 0016e8cd WriteData: 48590990
|
# Status: Burst-No: 37 Write Address: 0016e8cd WriteData: 48590990
|
# tb_core.u_sdram32 : at time 31687.0 ns WRITE: Bank = 2 Row = 366, Col = 89, Data = 7af6abf5
|
# tb_core.u_sdram32 : at time 32287.0 ns WRITE: Bank = 2 Row = 366, Col = 89, Data = 7af6abf5
|
# Status: Burst-No: 38 Write Address: 0016e8cd WriteData: 7af6abf5
|
# Status: Burst-No: 38 Write Address: 0016e8cd WriteData: 7af6abf5
|
# tb_core.u_sdram32 : at time 31697.0 ns WRITE: Bank = 2 Row = 366, Col = 90, Data = a620904c
|
# tb_core.u_sdram32 : at time 32297.0 ns WRITE: Bank = 2 Row = 366, Col = 90, Data = a620904c
|
# Status: Burst-No: 39 Write Address: 0016e8cd WriteData: a620904c
|
# Status: Burst-No: 39 Write Address: 0016e8cd WriteData: a620904c
|
# tb_core.u_sdram32 : at time 31707.0 ns WRITE: Bank = 2 Row = 366, Col = 91, Data = 3d82bd7b
|
# tb_core.u_sdram32 : at time 32307.0 ns WRITE: Bank = 2 Row = 366, Col = 91, Data = 3d82bd7b
|
# Status: Burst-No: 40 Write Address: 0016e8cd WriteData: 3d82bd7b
|
# Status: Burst-No: 40 Write Address: 0016e8cd WriteData: 3d82bd7b
|
# tb_core.u_sdram32 : at time 31717.0 ns WRITE: Bank = 2 Row = 366, Col = 92, Data = a005a640
|
# tb_core.u_sdram32 : at time 32317.0 ns WRITE: Bank = 2 Row = 366, Col = 92, Data = a005a640
|
# Status: Burst-No: 41 Write Address: 0016e8cd WriteData: a005a640
|
# Status: Burst-No: 41 Write Address: 0016e8cd WriteData: a005a640
|
# tb_core.u_sdram32 : at time 31727.0 ns WRITE: Bank = 2 Row = 366, Col = 93, Data = 12a90325
|
# tb_core.u_sdram32 : at time 32327.0 ns WRITE: Bank = 2 Row = 366, Col = 93, Data = 12a90325
|
# Status: Burst-No: 42 Write Address: 0016e8cd WriteData: 12a90325
|
# Status: Burst-No: 42 Write Address: 0016e8cd WriteData: 12a90325
|
# tb_core.u_sdram32 : at time 31737.0 ns WRITE: Bank = 2 Row = 366, Col = 94, Data = 86ebb60d
|
# tb_core.u_sdram32 : at time 32337.0 ns WRITE: Bank = 2 Row = 366, Col = 94, Data = 86ebb60d
|
# Status: Burst-No: 43 Write Address: 0016e8cd WriteData: 86ebb60d
|
# Status: Burst-No: 43 Write Address: 0016e8cd WriteData: 86ebb60d
|
# tb_core.u_sdram32 : at time 31747.0 ns WRITE: Bank = 2 Row = 366, Col = 95, Data = b87c1070
|
# tb_core.u_sdram32 : at time 32347.0 ns WRITE: Bank = 2 Row = 366, Col = 95, Data = b87c1070
|
# Status: Burst-No: 44 Write Address: 0016e8cd WriteData: b87c1070
|
# Status: Burst-No: 44 Write Address: 0016e8cd WriteData: b87c1070
|
# tb_core.u_sdram32 : at time 31757.0 ns WRITE: Bank = 2 Row = 366, Col = 96, Data = 16cbf92d
|
# tb_core.u_sdram32 : at time 32357.0 ns WRITE: Bank = 2 Row = 366, Col = 96, Data = 16cbf92d
|
# Status: Burst-No: 45 Write Address: 0016e8cd WriteData: 16cbf92d
|
# Status: Burst-No: 45 Write Address: 0016e8cd WriteData: 16cbf92d
|
# tb_core.u_sdram32 : at time 31767.0 ns WRITE: Bank = 2 Row = 366, Col = 97, Data = 94ded829
|
# tb_core.u_sdram32 : at time 32367.0 ns WRITE: Bank = 2 Row = 366, Col = 97, Data = 94ded829
|
# Status: Burst-No: 46 Write Address: 0016e8cd WriteData: 94ded829
|
# Status: Burst-No: 46 Write Address: 0016e8cd WriteData: 94ded829
|
# tb_core.u_sdram32 : at time 31777.0 ns WRITE: Bank = 2 Row = 366, Col = 98, Data = 5e2551bc
|
# tb_core.u_sdram32 : at time 32377.0 ns WRITE: Bank = 2 Row = 366, Col = 98, Data = 5e2551bc
|
# Status: Burst-No: 47 Write Address: 0016e8cd WriteData: 5e2551bc
|
# Status: Burst-No: 47 Write Address: 0016e8cd WriteData: 5e2551bc
|
# tb_core.u_sdram32 : at time 31787.0 ns WRITE: Bank = 2 Row = 366, Col = 99, Data = 987b0830
|
# tb_core.u_sdram32 : at time 32387.0 ns WRITE: Bank = 2 Row = 366, Col = 99, Data = 987b0830
|
# Status: Burst-No: 48 Write Address: 0016e8cd WriteData: 987b0830
|
# Status: Burst-No: 48 Write Address: 0016e8cd WriteData: 987b0830
|
# tb_core.u_sdram32 : at time 31797.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 32397.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 31933.0 ns READ : Bank = 3 Row = 453, Col = 185, Data = 322f7d64
|
# tb_core.u_sdram32 : at time 32533.0 ns READ : Bank = 3 Row = 453, Col = 185, Data = 322f7d64
|
# tb_core.u_sdram32 : at time 31943.0 ns READ : Bank = 3 Row = 453, Col = 186, Data = 14b43729
|
# tb_core.u_sdram32 : at time 32543.0 ns READ : Bank = 3 Row = 453, Col = 186, Data = 14b43729
|
# READ STATUS: Burst-No: 0 Addr: 001c5ee5 Rxd: 322f7d64
|
# READ STATUS: Burst-No: 0 Addr: 001c5ee5 Rxd: 322f7d64
|
# tb_core.u_sdram32 : at time 31953.0 ns READ : Bank = 3 Row = 453, Col = 187, Data = f0eeaee1
|
# tb_core.u_sdram32 : at time 32553.0 ns READ : Bank = 3 Row = 453, Col = 187, Data = f0eeaee1
|
# READ STATUS: Burst-No: 1 Addr: 001c5ee7 Rxd: 14b43729
|
# READ STATUS: Burst-No: 1 Addr: 001c5ee7 Rxd: 14b43729
|
# tb_core.u_sdram32 : at time 31963.0 ns READ : Bank = 3 Row = 453, Col = 188, Data = bbbc5277
|
# tb_core.u_sdram32 : at time 32563.0 ns READ : Bank = 3 Row = 453, Col = 188, Data = bbbc5277
|
# READ STATUS: Burst-No: 2 Addr: 001c5ee9 Rxd: f0eeaee1
|
# READ STATUS: Burst-No: 2 Addr: 001c5ee9 Rxd: f0eeaee1
|
# tb_core.u_sdram32 : at time 31973.0 ns READ : Bank = 3 Row = 453, Col = 189, Data = 3715156e
|
# tb_core.u_sdram32 : at time 32573.0 ns READ : Bank = 3 Row = 453, Col = 189, Data = 3715156e
|
# READ STATUS: Burst-No: 3 Addr: 001c5eeb Rxd: bbbc5277
|
# READ STATUS: Burst-No: 3 Addr: 001c5eeb Rxd: bbbc5277
|
# tb_core.u_sdram32 : at time 31983.0 ns READ : Bank = 3 Row = 453, Col = 190, Data = 40aaf581
|
# tb_core.u_sdram32 : at time 32583.0 ns READ : Bank = 3 Row = 453, Col = 190, Data = 40aaf581
|
# READ STATUS: Burst-No: 4 Addr: 001c5eed Rxd: 3715156e
|
# READ STATUS: Burst-No: 4 Addr: 001c5eed Rxd: 3715156e
|
# tb_core.u_sdram32 : at time 31993.0 ns READ : Bank = 3 Row = 453, Col = 191, Data = 6a9fb9d5
|
# tb_core.u_sdram32 : at time 32593.0 ns READ : Bank = 3 Row = 453, Col = 191, Data = 6a9fb9d5
|
# READ STATUS: Burst-No: 5 Addr: 001c5eef Rxd: 40aaf581
|
# READ STATUS: Burst-No: 5 Addr: 001c5eef Rxd: 40aaf581
|
# tb_core.u_sdram32 : at time 32003.0 ns READ : Bank = 3 Row = 453, Col = 192, Data = 3437d568
|
# tb_core.u_sdram32 : at time 32603.0 ns READ : Bank = 3 Row = 453, Col = 192, Data = 3437d568
|
# READ STATUS: Burst-No: 6 Addr: 001c5ef1 Rxd: 6a9fb9d5
|
# READ STATUS: Burst-No: 6 Addr: 001c5ef1 Rxd: 6a9fb9d5
|
# tb_core.u_sdram32 : at time 32013.0 ns READ : Bank = 3 Row = 453, Col = 193, Data = 786271f0
|
# tb_core.u_sdram32 : at time 32613.0 ns READ : Bank = 3 Row = 453, Col = 193, Data = 786271f0
|
# READ STATUS: Burst-No: 7 Addr: 001c5ef3 Rxd: 3437d568
|
# READ STATUS: Burst-No: 7 Addr: 001c5ef3 Rxd: 3437d568
|
# tb_core.u_sdram32 : at time 32023.0 ns READ : Bank = 3 Row = 453, Col = 194, Data = d57800aa
|
# tb_core.u_sdram32 : at time 32623.0 ns READ : Bank = 3 Row = 453, Col = 194, Data = d57800aa
|
# READ STATUS: Burst-No: 8 Addr: 001c5ef5 Rxd: 786271f0
|
# READ STATUS: Burst-No: 8 Addr: 001c5ef5 Rxd: 786271f0
|
# tb_core.u_sdram32 : at time 32033.0 ns READ : Bank = 3 Row = 453, Col = 195, Data = 079fc30f
|
# tb_core.u_sdram32 : at time 32633.0 ns READ : Bank = 3 Row = 453, Col = 195, Data = 079fc30f
|
# READ STATUS: Burst-No: 9 Addr: 001c5ef7 Rxd: d57800aa
|
# READ STATUS: Burst-No: 9 Addr: 001c5ef7 Rxd: d57800aa
|
# tb_core.u_sdram32 : at time 32043.0 ns READ : Bank = 3 Row = 453, Col = 196, Data = f8dc48f1
|
# tb_core.u_sdram32 : at time 32643.0 ns READ : Bank = 3 Row = 453, Col = 196, Data = f8dc48f1
|
# READ STATUS: Burst-No: 10 Addr: 001c5ef9 Rxd: 079fc30f
|
# READ STATUS: Burst-No: 10 Addr: 001c5ef9 Rxd: 079fc30f
|
# tb_core.u_sdram32 : at time 32053.0 ns READ : Bank = 3 Row = 453, Col = 197, Data = be9bbc7d
|
# tb_core.u_sdram32 : at time 32653.0 ns READ : Bank = 3 Row = 453, Col = 197, Data = be9bbc7d
|
# READ STATUS: Burst-No: 11 Addr: 001c5efb Rxd: f8dc48f1
|
# READ STATUS: Burst-No: 11 Addr: 001c5efb Rxd: f8dc48f1
|
# tb_core.u_sdram32 : at time 32063.0 ns READ : Bank = 3 Row = 453, Col = 198, Data = 472e958e
|
# tb_core.u_sdram32 : at time 32663.0 ns READ : Bank = 3 Row = 453, Col = 198, Data = 472e958e
|
# READ STATUS: Burst-No: 12 Addr: 001c5efd Rxd: be9bbc7d
|
# READ STATUS: Burst-No: 12 Addr: 001c5efd Rxd: be9bbc7d
|
# tb_core.u_sdram32 : at time 32073.0 ns READ : Bank = 3 Row = 453, Col = 199, Data = f161dce2
|
# tb_core.u_sdram32 : at time 32673.0 ns READ : Bank = 3 Row = 453, Col = 199, Data = f161dce2
|
# READ STATUS: Burst-No: 13 Addr: 001c5eff Rxd: 472e958e
|
# READ STATUS: Burst-No: 13 Addr: 001c5eff Rxd: 472e958e
|
# tb_core.u_sdram32 : at time 32083.0 ns READ : Bank = 3 Row = 453, Col = 200, Data = 1e664d3c
|
# tb_core.u_sdram32 : at time 32683.0 ns READ : Bank = 3 Row = 453, Col = 200, Data = 1e664d3c
|
# READ STATUS: Burst-No: 14 Addr: 001c5f01 Rxd: f161dce2
|
# READ STATUS: Burst-No: 14 Addr: 001c5f01 Rxd: f161dce2
|
# tb_core.u_sdram32 : at time 32093.0 ns READ : Bank = 3 Row = 453, Col = 201, Data = d4b5e6a9
|
# tb_core.u_sdram32 : at time 32693.0 ns READ : Bank = 3 Row = 453, Col = 201, Data = d4b5e6a9
|
# READ STATUS: Burst-No: 15 Addr: 001c5f03 Rxd: 1e664d3c
|
# READ STATUS: Burst-No: 15 Addr: 001c5f03 Rxd: 1e664d3c
|
# tb_core.u_sdram32 : at time 32103.0 ns READ : Bank = 3 Row = 453, Col = 202, Data = 77ebb1ef
|
# tb_core.u_sdram32 : at time 32703.0 ns READ : Bank = 3 Row = 453, Col = 202, Data = 77ebb1ef
|
# READ STATUS: Burst-No: 16 Addr: 001c5f05 Rxd: d4b5e6a9
|
# READ STATUS: Burst-No: 16 Addr: 001c5f05 Rxd: d4b5e6a9
|
# tb_core.u_sdram32 : at time 32113.0 ns READ : Bank = 3 Row = 453, Col = 203, Data = ade7d05b
|
# tb_core.u_sdram32 : at time 32713.0 ns READ : Bank = 3 Row = 453, Col = 203, Data = ade7d05b
|
# READ STATUS: Burst-No: 17 Addr: 001c5f07 Rxd: 77ebb1ef
|
# READ STATUS: Burst-No: 17 Addr: 001c5f07 Rxd: 77ebb1ef
|
# tb_core.u_sdram32 : at time 32123.0 ns READ : Bank = 3 Row = 453, Col = 204, Data = d7a23caf
|
# tb_core.u_sdram32 : at time 32723.0 ns READ : Bank = 3 Row = 453, Col = 204, Data = d7a23caf
|
# READ STATUS: Burst-No: 18 Addr: 001c5f09 Rxd: ade7d05b
|
# READ STATUS: Burst-No: 18 Addr: 001c5f09 Rxd: ade7d05b
|
# tb_core.u_sdram32 : at time 32133.0 ns READ : Bank = 3 Row = 453, Col = 205, Data = 25029b4a
|
# tb_core.u_sdram32 : at time 32733.0 ns READ : Bank = 3 Row = 453, Col = 205, Data = 25029b4a
|
# READ STATUS: Burst-No: 19 Addr: 001c5f0b Rxd: d7a23caf
|
# READ STATUS: Burst-No: 19 Addr: 001c5f0b Rxd: d7a23caf
|
# tb_core.u_sdram32 : at time 32143.0 ns READ : Bank = 3 Row = 453, Col = 206, Data = 5cd20db9
|
# tb_core.u_sdram32 : at time 32743.0 ns READ : Bank = 3 Row = 453, Col = 206, Data = 5cd20db9
|
# READ STATUS: Burst-No: 20 Addr: 001c5f0d Rxd: 25029b4a
|
# READ STATUS: Burst-No: 20 Addr: 001c5f0d Rxd: 25029b4a
|
# tb_core.u_sdram32 : at time 32153.0 ns READ : Bank = 3 Row = 453, Col = 207, Data = 098e2d13
|
# tb_core.u_sdram32 : at time 32753.0 ns READ : Bank = 3 Row = 453, Col = 207, Data = 098e2d13
|
# READ STATUS: Burst-No: 21 Addr: 001c5f0f Rxd: 5cd20db9
|
# READ STATUS: Burst-No: 21 Addr: 001c5f0f Rxd: 5cd20db9
|
# tb_core.u_sdram32 : at time 32163.0 ns READ : Bank = 3 Row = 453, Col = 208, Data = 09c83513
|
# tb_core.u_sdram32 : at time 32763.0 ns READ : Bank = 3 Row = 453, Col = 208, Data = 09c83513
|
# READ STATUS: Burst-No: 22 Addr: 001c5f11 Rxd: 098e2d13
|
# READ STATUS: Burst-No: 22 Addr: 001c5f11 Rxd: 098e2d13
|
# tb_core.u_sdram32 : at time 32173.0 ns READ : Bank = 3 Row = 453, Col = 209, Data = 32dc4165
|
# tb_core.u_sdram32 : at time 32773.0 ns READ : Bank = 3 Row = 453, Col = 209, Data = 32dc4165
|
# READ STATUS: Burst-No: 23 Addr: 001c5f13 Rxd: 09c83513
|
# READ STATUS: Burst-No: 23 Addr: 001c5f13 Rxd: 09c83513
|
# tb_core.u_sdram32 : at time 32183.0 ns READ : Bank = 3 Row = 453, Col = 210, Data = 28c62751
|
# tb_core.u_sdram32 : at time 32783.0 ns READ : Bank = 3 Row = 453, Col = 210, Data = 28c62751
|
# READ STATUS: Burst-No: 24 Addr: 001c5f15 Rxd: 32dc4165
|
# READ STATUS: Burst-No: 24 Addr: 001c5f15 Rxd: 32dc4165
|
# tb_core.u_sdram32 : at time 32193.0 ns READ : Bank = 3 Row = 453, Col = 211, Data = db983ab7
|
# tb_core.u_sdram32 : at time 32793.0 ns READ : Bank = 3 Row = 453, Col = 211, Data = db983ab7
|
# READ STATUS: Burst-No: 25 Addr: 001c5f17 Rxd: 28c62751
|
# READ STATUS: Burst-No: 25 Addr: 001c5f17 Rxd: 28c62751
|
# tb_core.u_sdram32 : at time 32203.0 ns READ : Bank = 3 Row = 453, Col = 212, Data = cc981099
|
# tb_core.u_sdram32 : at time 32803.0 ns READ : Bank = 3 Row = 453, Col = 212, Data = cc981099
|
# READ STATUS: Burst-No: 26 Addr: 001c5f19 Rxd: db983ab7
|
# READ STATUS: Burst-No: 26 Addr: 001c5f19 Rxd: db983ab7
|
# tb_core.u_sdram32 : at time 32213.0 ns READ : Bank = 3 Row = 453, Col = 213, Data = 9d12083a
|
# tb_core.u_sdram32 : at time 32813.0 ns READ : Bank = 3 Row = 453, Col = 213, Data = 9d12083a
|
# READ STATUS: Burst-No: 27 Addr: 001c5f1b Rxd: cc981099
|
# READ STATUS: Burst-No: 27 Addr: 001c5f1b Rxd: cc981099
|
# tb_core.u_sdram32 : at time 32223.0 ns READ : Bank = 3 Row = 453, Col = 214, Data = b8ea3a71
|
# tb_core.u_sdram32 : at time 32823.0 ns READ : Bank = 3 Row = 453, Col = 214, Data = b8ea3a71
|
# READ STATUS: Burst-No: 28 Addr: 001c5f1d Rxd: 9d12083a
|
# READ STATUS: Burst-No: 28 Addr: 001c5f1d Rxd: 9d12083a
|
# tb_core.u_sdram32 : at time 32233.0 ns READ : Bank = 3 Row = 453, Col = 215, Data = 317c0762
|
# tb_core.u_sdram32 : at time 32833.0 ns READ : Bank = 3 Row = 453, Col = 215, Data = 317c0762
|
# READ STATUS: Burst-No: 29 Addr: 001c5f1f Rxd: b8ea3a71
|
# READ STATUS: Burst-No: 29 Addr: 001c5f1f Rxd: b8ea3a71
|
# tb_core.u_sdram32 : at time 32243.0 ns READ : Bank = 3 Row = 453, Col = 216, Data = f2356ae4
|
# tb_core.u_sdram32 : at time 32843.0 ns READ : Bank = 3 Row = 453, Col = 216, Data = f2356ae4
|
# READ STATUS: Burst-No: 30 Addr: 001c5f21 Rxd: 317c0762
|
# READ STATUS: Burst-No: 30 Addr: 001c5f21 Rxd: 317c0762
|
# tb_core.u_sdram32 : at time 32253.0 ns READ : Bank = 3 Row = 453, Col = 217, Data = 1513dd2a
|
# tb_core.u_sdram32 : at time 32853.0 ns READ : Bank = 3 Row = 453, Col = 217, Data = 1513dd2a
|
# READ STATUS: Burst-No: 31 Addr: 001c5f23 Rxd: f2356ae4
|
# READ STATUS: Burst-No: 31 Addr: 001c5f23 Rxd: f2356ae4
|
# tb_core.u_sdram32 : at time 32263.0 ns READ : Bank = 3 Row = 453, Col = 218, Data = beda447d
|
# tb_core.u_sdram32 : at time 32863.0 ns READ : Bank = 3 Row = 453, Col = 218, Data = beda447d
|
# READ STATUS: Burst-No: 32 Addr: 001c5f25 Rxd: 1513dd2a
|
# READ STATUS: Burst-No: 32 Addr: 001c5f25 Rxd: 1513dd2a
|
# tb_core.u_sdram32 : at time 32273.0 ns READ : Bank = 3 Row = 453, Col = 219, Data = 2cee5f59
|
# tb_core.u_sdram32 : at time 32873.0 ns READ : Bank = 3 Row = 453, Col = 219, Data = 2cee5f59
|
# READ STATUS: Burst-No: 33 Addr: 001c5f27 Rxd: beda447d
|
# READ STATUS: Burst-No: 33 Addr: 001c5f27 Rxd: beda447d
|
# tb_core.u_sdram32 : at time 32283.0 ns READ : Bank = 3 Row = 453, Col = 220, Data = 72c3a3e5
|
# tb_core.u_sdram32 : at time 32883.0 ns READ : Bank = 3 Row = 453, Col = 220, Data = 72c3a3e5
|
# READ STATUS: Burst-No: 34 Addr: 001c5f29 Rxd: 2cee5f59
|
# READ STATUS: Burst-No: 34 Addr: 001c5f29 Rxd: 2cee5f59
|
# tb_core.u_sdram32 : at time 32293.0 ns READ : Bank = 3 Row = 453, Col = 221, Data = 76de6bed
|
# tb_core.u_sdram32 : at time 32893.0 ns READ : Bank = 3 Row = 453, Col = 221, Data = 76de6bed
|
# READ STATUS: Burst-No: 35 Addr: 001c5f2b Rxd: 72c3a3e5
|
# READ STATUS: Burst-No: 35 Addr: 001c5f2b Rxd: 72c3a3e5
|
# tb_core.u_sdram32 : at time 32303.0 ns READ : Bank = 3 Row = 453, Col = 222, Data = e4a800c9
|
# tb_core.u_sdram32 : at time 32903.0 ns READ : Bank = 3 Row = 453, Col = 222, Data = e4a800c9
|
# READ STATUS: Burst-No: 36 Addr: 001c5f2d Rxd: 76de6bed
|
# READ STATUS: Burst-No: 36 Addr: 001c5f2d Rxd: 76de6bed
|
# tb_core.u_sdram32 : at time 32313.0 ns READ : Bank = 3 Row = 453, Col = 223, Data = a0aecc41
|
# tb_core.u_sdram32 : at time 32913.0 ns READ : Bank = 3 Row = 453, Col = 223, Data = a0aecc41
|
# tb_core.u_sdram32 : at time 32317.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 32917.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 37 Addr: 001c5f2f Rxd: e4a800c9
|
# READ STATUS: Burst-No: 37 Addr: 001c5f2f Rxd: e4a800c9
|
# tb_core.u_sdram32 : at time 32323.0 ns READ : Bank = 3 Row = 453, Col = 224, Data = 57c1d1af
|
# tb_core.u_sdram32 : at time 32923.0 ns READ : Bank = 3 Row = 453, Col = 224, Data = 57c1d1af
|
# READ STATUS: Burst-No: 38 Addr: 001c5f31 Rxd: a0aecc41
|
# READ STATUS: Burst-No: 38 Addr: 001c5f31 Rxd: a0aecc41
|
# tb_core.u_sdram32 : at time 32333.0 ns READ : Bank = 3 Row = 453, Col = 225, Data = eda71cdb
|
# tb_core.u_sdram32 : at time 32933.0 ns READ : Bank = 3 Row = 453, Col = 225, Data = eda71cdb
|
# READ STATUS: Burst-No: 39 Addr: 001c5f33 Rxd: 57c1d1af
|
# READ STATUS: Burst-No: 39 Addr: 001c5f33 Rxd: 57c1d1af
|
# READ STATUS: Burst-No: 40 Addr: 001c5f35 Rxd: eda71cdb
|
# READ STATUS: Burst-No: 40 Addr: 001c5f35 Rxd: eda71cdb
|
# tb_core.u_sdram32 : at time 32503.0 ns READ : Bank = 2 Row = 366, Col = 51, Data = 8326d406
|
# tb_core.u_sdram32 : at time 33103.0 ns READ : Bank = 2 Row = 366, Col = 51, Data = 8326d406
|
# tb_core.u_sdram32 : at time 32513.0 ns READ : Bank = 2 Row = 366, Col = 52, Data = d14820a2
|
# tb_core.u_sdram32 : at time 33113.0 ns READ : Bank = 2 Row = 366, Col = 52, Data = d14820a2
|
# READ STATUS: Burst-No: 0 Addr: 0016e8cd Rxd: 8326d406
|
# READ STATUS: Burst-No: 0 Addr: 0016e8cd Rxd: 8326d406
|
# tb_core.u_sdram32 : at time 32523.0 ns READ : Bank = 2 Row = 366, Col = 53, Data = 5e983dbd
|
# tb_core.u_sdram32 : at time 33123.0 ns READ : Bank = 2 Row = 366, Col = 53, Data = 5e983dbd
|
# READ STATUS: Burst-No: 1 Addr: 0016e8cf Rxd: d14820a2
|
# READ STATUS: Burst-No: 1 Addr: 0016e8cf Rxd: d14820a2
|
# tb_core.u_sdram32 : at time 32533.0 ns READ : Bank = 2 Row = 366, Col = 54, Data = b555de6a
|
# tb_core.u_sdram32 : at time 33133.0 ns READ : Bank = 2 Row = 366, Col = 54, Data = b555de6a
|
# READ STATUS: Burst-No: 2 Addr: 0016e8d1 Rxd: 5e983dbd
|
# READ STATUS: Burst-No: 2 Addr: 0016e8d1 Rxd: 5e983dbd
|
# tb_core.u_sdram32 : at time 32543.0 ns READ : Bank = 2 Row = 366, Col = 55, Data = 6e3d47dc
|
# tb_core.u_sdram32 : at time 33143.0 ns READ : Bank = 2 Row = 366, Col = 55, Data = 6e3d47dc
|
# READ STATUS: Burst-No: 3 Addr: 0016e8d3 Rxd: b555de6a
|
# READ STATUS: Burst-No: 3 Addr: 0016e8d3 Rxd: b555de6a
|
# tb_core.u_sdram32 : at time 32553.0 ns READ : Bank = 2 Row = 366, Col = 56, Data = a86c5e50
|
# tb_core.u_sdram32 : at time 33153.0 ns READ : Bank = 2 Row = 366, Col = 56, Data = a86c5e50
|
# READ STATUS: Burst-No: 4 Addr: 0016e8d5 Rxd: 6e3d47dc
|
# READ STATUS: Burst-No: 4 Addr: 0016e8d5 Rxd: 6e3d47dc
|
# tb_core.u_sdram32 : at time 32563.0 ns READ : Bank = 2 Row = 366, Col = 57, Data = bd86f47b
|
# tb_core.u_sdram32 : at time 33163.0 ns READ : Bank = 2 Row = 366, Col = 57, Data = bd86f47b
|
# READ STATUS: Burst-No: 5 Addr: 0016e8d7 Rxd: a86c5e50
|
# READ STATUS: Burst-No: 5 Addr: 0016e8d7 Rxd: a86c5e50
|
# tb_core.u_sdram32 : at time 32573.0 ns READ : Bank = 2 Row = 366, Col = 58, Data = 929d5825
|
# tb_core.u_sdram32 : at time 33173.0 ns READ : Bank = 2 Row = 366, Col = 58, Data = 929d5825
|
# READ STATUS: Burst-No: 6 Addr: 0016e8d9 Rxd: bd86f47b
|
# READ STATUS: Burst-No: 6 Addr: 0016e8d9 Rxd: bd86f47b
|
# tb_core.u_sdram32 : at time 32583.0 ns READ : Bank = 2 Row = 366, Col = 59, Data = bc3f8478
|
# tb_core.u_sdram32 : at time 33183.0 ns READ : Bank = 2 Row = 366, Col = 59, Data = bc3f8478
|
# READ STATUS: Burst-No: 7 Addr: 0016e8db Rxd: 929d5825
|
# READ STATUS: Burst-No: 7 Addr: 0016e8db Rxd: 929d5825
|
# tb_core.u_sdram32 : at time 32593.0 ns READ : Bank = 2 Row = 366, Col = 60, Data = 7b7b89f6
|
# tb_core.u_sdram32 : at time 33193.0 ns READ : Bank = 2 Row = 366, Col = 60, Data = 7b7b89f6
|
# READ STATUS: Burst-No: 8 Addr: 0016e8dd Rxd: bc3f8478
|
# READ STATUS: Burst-No: 8 Addr: 0016e8dd Rxd: bc3f8478
|
# tb_core.u_sdram32 : at time 32603.0 ns READ : Bank = 2 Row = 366, Col = 61, Data = ae23ce5c
|
# tb_core.u_sdram32 : at time 33203.0 ns READ : Bank = 2 Row = 366, Col = 61, Data = ae23ce5c
|
# READ STATUS: Burst-No: 9 Addr: 0016e8df Rxd: 7b7b89f6
|
# READ STATUS: Burst-No: 9 Addr: 0016e8df Rxd: 7b7b89f6
|
# tb_core.u_sdram32 : at time 32613.0 ns READ : Bank = 2 Row = 366, Col = 62, Data = 11cc9b23
|
# tb_core.u_sdram32 : at time 33213.0 ns READ : Bank = 2 Row = 366, Col = 62, Data = 11cc9b23
|
# READ STATUS: Burst-No: 10 Addr: 0016e8e1 Rxd: ae23ce5c
|
# READ STATUS: Burst-No: 10 Addr: 0016e8e1 Rxd: ae23ce5c
|
# tb_core.u_sdram32 : at time 32623.0 ns READ : Bank = 2 Row = 366, Col = 63, Data = 3cb3ab79
|
# tb_core.u_sdram32 : at time 33223.0 ns READ : Bank = 2 Row = 366, Col = 63, Data = 3cb3ab79
|
# READ STATUS: Burst-No: 11 Addr: 0016e8e3 Rxd: 11cc9b23
|
# READ STATUS: Burst-No: 11 Addr: 0016e8e3 Rxd: 11cc9b23
|
# tb_core.u_sdram32 : at time 32633.0 ns READ : Bank = 2 Row = 366, Col = 64, Data = 644605c8
|
# tb_core.u_sdram32 : at time 33233.0 ns READ : Bank = 2 Row = 366, Col = 64, Data = 644605c8
|
# READ STATUS: Burst-No: 12 Addr: 0016e8e5 Rxd: 3cb3ab79
|
# READ STATUS: Burst-No: 12 Addr: 0016e8e5 Rxd: 3cb3ab79
|
# tb_core.u_sdram32 : at time 32643.0 ns READ : Bank = 2 Row = 366, Col = 65, Data = ddd146bb
|
# tb_core.u_sdram32 : at time 33243.0 ns READ : Bank = 2 Row = 366, Col = 65, Data = ddd146bb
|
# READ STATUS: Burst-No: 13 Addr: 0016e8e7 Rxd: 644605c8
|
# READ STATUS: Burst-No: 13 Addr: 0016e8e7 Rxd: 644605c8
|
# tb_core.u_sdram32 : at time 32653.0 ns READ : Bank = 2 Row = 366, Col = 66, Data = 870cee0e
|
# tb_core.u_sdram32 : at time 33253.0 ns READ : Bank = 2 Row = 366, Col = 66, Data = 870cee0e
|
# READ STATUS: Burst-No: 14 Addr: 0016e8e9 Rxd: ddd146bb
|
# READ STATUS: Burst-No: 14 Addr: 0016e8e9 Rxd: ddd146bb
|
# tb_core.u_sdram32 : at time 32663.0 ns READ : Bank = 2 Row = 366, Col = 67, Data = b9879473
|
# tb_core.u_sdram32 : at time 33263.0 ns READ : Bank = 2 Row = 366, Col = 67, Data = b9879473
|
# READ STATUS: Burst-No: 15 Addr: 0016e8eb Rxd: 870cee0e
|
# READ STATUS: Burst-No: 15 Addr: 0016e8eb Rxd: 870cee0e
|
# tb_core.u_sdram32 : at time 32673.0 ns READ : Bank = 2 Row = 366, Col = 68, Data = 0671030c
|
# tb_core.u_sdram32 : at time 33273.0 ns READ : Bank = 2 Row = 366, Col = 68, Data = 0671030c
|
# READ STATUS: Burst-No: 16 Addr: 0016e8ed Rxd: b9879473
|
# READ STATUS: Burst-No: 16 Addr: 0016e8ed Rxd: b9879473
|
# tb_core.u_sdram32 : at time 32683.0 ns READ : Bank = 2 Row = 366, Col = 69, Data = e70f98ce
|
# tb_core.u_sdram32 : at time 33283.0 ns READ : Bank = 2 Row = 366, Col = 69, Data = e70f98ce
|
# READ STATUS: Burst-No: 17 Addr: 0016e8ef Rxd: 0671030c
|
# READ STATUS: Burst-No: 17 Addr: 0016e8ef Rxd: 0671030c
|
# tb_core.u_sdram32 : at time 32693.0 ns READ : Bank = 2 Row = 366, Col = 70, Data = 6a1a61d4
|
# tb_core.u_sdram32 : at time 33293.0 ns READ : Bank = 2 Row = 366, Col = 70, Data = 6a1a61d4
|
# READ STATUS: Burst-No: 18 Addr: 0016e8f1 Rxd: e70f98ce
|
# READ STATUS: Burst-No: 18 Addr: 0016e8f1 Rxd: e70f98ce
|
# tb_core.u_sdram32 : at time 32703.0 ns READ : Bank = 2 Row = 366, Col = 71, Data = acecdc59
|
# tb_core.u_sdram32 : at time 33303.0 ns READ : Bank = 2 Row = 366, Col = 71, Data = acecdc59
|
# READ STATUS: Burst-No: 19 Addr: 0016e8f3 Rxd: 6a1a61d4
|
# READ STATUS: Burst-No: 19 Addr: 0016e8f3 Rxd: 6a1a61d4
|
# tb_core.u_sdram32 : at time 32713.0 ns READ : Bank = 2 Row = 366, Col = 72, Data = 5ca26fb9
|
# tb_core.u_sdram32 : at time 33313.0 ns READ : Bank = 2 Row = 366, Col = 72, Data = 5ca26fb9
|
# READ STATUS: Burst-No: 20 Addr: 0016e8f5 Rxd: acecdc59
|
# READ STATUS: Burst-No: 20 Addr: 0016e8f5 Rxd: acecdc59
|
# tb_core.u_sdram32 : at time 32723.0 ns READ : Bank = 2 Row = 366, Col = 73, Data = d9b8c0b3
|
# tb_core.u_sdram32 : at time 33323.0 ns READ : Bank = 2 Row = 366, Col = 73, Data = d9b8c0b3
|
# READ STATUS: Burst-No: 21 Addr: 0016e8f7 Rxd: 5ca26fb9
|
# READ STATUS: Burst-No: 21 Addr: 0016e8f7 Rxd: 5ca26fb9
|
# tb_core.u_sdram32 : at time 32733.0 ns READ : Bank = 2 Row = 366, Col = 74, Data = 7a4fbff4
|
# tb_core.u_sdram32 : at time 33333.0 ns READ : Bank = 2 Row = 366, Col = 74, Data = 7a4fbff4
|
# READ STATUS: Burst-No: 22 Addr: 0016e8f9 Rxd: d9b8c0b3
|
# READ STATUS: Burst-No: 22 Addr: 0016e8f9 Rxd: d9b8c0b3
|
# tb_core.u_sdram32 : at time 32743.0 ns READ : Bank = 2 Row = 366, Col = 75, Data = baf4e275
|
# tb_core.u_sdram32 : at time 33343.0 ns READ : Bank = 2 Row = 366, Col = 75, Data = baf4e275
|
# READ STATUS: Burst-No: 23 Addr: 0016e8fb Rxd: 7a4fbff4
|
# READ STATUS: Burst-No: 23 Addr: 0016e8fb Rxd: 7a4fbff4
|
# tb_core.u_sdram32 : at time 32753.0 ns READ : Bank = 2 Row = 366, Col = 76, Data = 066cf10c
|
# tb_core.u_sdram32 : at time 33353.0 ns READ : Bank = 2 Row = 366, Col = 76, Data = 066cf10c
|
# READ STATUS: Burst-No: 24 Addr: 0016e8fd Rxd: baf4e275
|
# READ STATUS: Burst-No: 24 Addr: 0016e8fd Rxd: baf4e275
|
# tb_core.u_sdram32 : at time 32763.0 ns READ : Bank = 2 Row = 366, Col = 77, Data = 9cfc7a39
|
# tb_core.u_sdram32 : at time 33363.0 ns READ : Bank = 2 Row = 366, Col = 77, Data = 9cfc7a39
|
# READ STATUS: Burst-No: 25 Addr: 0016e8ff Rxd: 066cf10c
|
# READ STATUS: Burst-No: 25 Addr: 0016e8ff Rxd: 066cf10c
|
# tb_core.u_sdram32 : at time 32773.0 ns READ : Bank = 2 Row = 366, Col = 78, Data = 01729302
|
# tb_core.u_sdram32 : at time 33373.0 ns READ : Bank = 2 Row = 366, Col = 78, Data = 01729302
|
# READ STATUS: Burst-No: 26 Addr: 0016e901 Rxd: 9cfc7a39
|
# READ STATUS: Burst-No: 26 Addr: 0016e901 Rxd: 9cfc7a39
|
# tb_core.u_sdram32 : at time 32783.0 ns READ : Bank = 2 Row = 366, Col = 79, Data = 8aecbe15
|
# tb_core.u_sdram32 : at time 33383.0 ns READ : Bank = 2 Row = 366, Col = 79, Data = 8aecbe15
|
# READ STATUS: Burst-No: 27 Addr: 0016e903 Rxd: 01729302
|
# READ STATUS: Burst-No: 27 Addr: 0016e903 Rxd: 01729302
|
# tb_core.u_sdram32 : at time 32793.0 ns READ : Bank = 2 Row = 366, Col = 80, Data = 02fbf905
|
# tb_core.u_sdram32 : at time 33393.0 ns READ : Bank = 2 Row = 366, Col = 80, Data = 02fbf905
|
# READ STATUS: Burst-No: 28 Addr: 0016e905 Rxd: 8aecbe15
|
# READ STATUS: Burst-No: 28 Addr: 0016e905 Rxd: 8aecbe15
|
# tb_core.u_sdram32 : at time 32803.0 ns READ : Bank = 2 Row = 366, Col = 81, Data = 271c434e
|
# tb_core.u_sdram32 : at time 33403.0 ns READ : Bank = 2 Row = 366, Col = 81, Data = 271c434e
|
# READ STATUS: Burst-No: 29 Addr: 0016e907 Rxd: 02fbf905
|
# READ STATUS: Burst-No: 29 Addr: 0016e907 Rxd: 02fbf905
|
# tb_core.u_sdram32 : at time 32813.0 ns READ : Bank = 2 Row = 366, Col = 82, Data = 013f2902
|
# tb_core.u_sdram32 : at time 33413.0 ns READ : Bank = 2 Row = 366, Col = 82, Data = 013f2902
|
# READ STATUS: Burst-No: 30 Addr: 0016e909 Rxd: 271c434e
|
# READ STATUS: Burst-No: 30 Addr: 0016e909 Rxd: 271c434e
|
# tb_core.u_sdram32 : at time 32823.0 ns READ : Bank = 2 Row = 366, Col = 83, Data = 5c7951b8
|
# tb_core.u_sdram32 : at time 33423.0 ns READ : Bank = 2 Row = 366, Col = 83, Data = 5c7951b8
|
# READ STATUS: Burst-No: 31 Addr: 0016e90b Rxd: 013f2902
|
# READ STATUS: Burst-No: 31 Addr: 0016e90b Rxd: 013f2902
|
# tb_core.u_sdram32 : at time 32833.0 ns READ : Bank = 2 Row = 366, Col = 84, Data = 847fb208
|
# tb_core.u_sdram32 : at time 33433.0 ns READ : Bank = 2 Row = 366, Col = 84, Data = 847fb208
|
# READ STATUS: Burst-No: 32 Addr: 0016e90d Rxd: 5c7951b8
|
# READ STATUS: Burst-No: 32 Addr: 0016e90d Rxd: 5c7951b8
|
# tb_core.u_sdram32 : at time 32843.0 ns READ : Bank = 2 Row = 366, Col = 85, Data = 46e7538d
|
# tb_core.u_sdram32 : at time 33443.0 ns READ : Bank = 2 Row = 366, Col = 85, Data = 46e7538d
|
# READ STATUS: Burst-No: 33 Addr: 0016e90f Rxd: 847fb208
|
# READ STATUS: Burst-No: 33 Addr: 0016e90f Rxd: 847fb208
|
# tb_core.u_sdram32 : at time 32853.0 ns READ : Bank = 2 Row = 366, Col = 86, Data = d7b48eaf
|
# tb_core.u_sdram32 : at time 33453.0 ns READ : Bank = 2 Row = 366, Col = 86, Data = d7b48eaf
|
# READ STATUS: Burst-No: 34 Addr: 0016e911 Rxd: 46e7538d
|
# READ STATUS: Burst-No: 34 Addr: 0016e911 Rxd: 46e7538d
|
# tb_core.u_sdram32 : at time 32863.0 ns READ : Bank = 2 Row = 366, Col = 87, Data = 747331e8
|
# tb_core.u_sdram32 : at time 33463.0 ns READ : Bank = 2 Row = 366, Col = 87, Data = 747331e8
|
# READ STATUS: Burst-No: 35 Addr: 0016e913 Rxd: d7b48eaf
|
# READ STATUS: Burst-No: 35 Addr: 0016e913 Rxd: d7b48eaf
|
# tb_core.u_sdram32 : at time 32873.0 ns READ : Bank = 2 Row = 366, Col = 88, Data = 48590990
|
# tb_core.u_sdram32 : at time 33473.0 ns READ : Bank = 2 Row = 366, Col = 88, Data = 48590990
|
# READ STATUS: Burst-No: 36 Addr: 0016e915 Rxd: 747331e8
|
# READ STATUS: Burst-No: 36 Addr: 0016e915 Rxd: 747331e8
|
# tb_core.u_sdram32 : at time 32883.0 ns READ : Bank = 2 Row = 366, Col = 89, Data = 7af6abf5
|
# tb_core.u_sdram32 : at time 33483.0 ns READ : Bank = 2 Row = 366, Col = 89, Data = 7af6abf5
|
# READ STATUS: Burst-No: 37 Addr: 0016e917 Rxd: 48590990
|
# READ STATUS: Burst-No: 37 Addr: 0016e917 Rxd: 48590990
|
# tb_core.u_sdram32 : at time 32893.0 ns READ : Bank = 2 Row = 366, Col = 90, Data = a620904c
|
# tb_core.u_sdram32 : at time 33493.0 ns READ : Bank = 2 Row = 366, Col = 90, Data = a620904c
|
# READ STATUS: Burst-No: 38 Addr: 0016e919 Rxd: 7af6abf5
|
# READ STATUS: Burst-No: 38 Addr: 0016e919 Rxd: 7af6abf5
|
# tb_core.u_sdram32 : at time 32903.0 ns READ : Bank = 2 Row = 366, Col = 91, Data = 3d82bd7b
|
# tb_core.u_sdram32 : at time 33503.0 ns READ : Bank = 2 Row = 366, Col = 91, Data = 3d82bd7b
|
# READ STATUS: Burst-No: 39 Addr: 0016e91b Rxd: a620904c
|
# READ STATUS: Burst-No: 39 Addr: 0016e91b Rxd: a620904c
|
# tb_core.u_sdram32 : at time 32913.0 ns READ : Bank = 2 Row = 366, Col = 92, Data = a005a640
|
# tb_core.u_sdram32 : at time 33513.0 ns READ : Bank = 2 Row = 366, Col = 92, Data = a005a640
|
# READ STATUS: Burst-No: 40 Addr: 0016e91d Rxd: 3d82bd7b
|
# READ STATUS: Burst-No: 40 Addr: 0016e91d Rxd: 3d82bd7b
|
# tb_core.u_sdram32 : at time 32923.0 ns READ : Bank = 2 Row = 366, Col = 93, Data = 12a90325
|
# tb_core.u_sdram32 : at time 33523.0 ns READ : Bank = 2 Row = 366, Col = 93, Data = 12a90325
|
# READ STATUS: Burst-No: 41 Addr: 0016e91f Rxd: a005a640
|
# READ STATUS: Burst-No: 41 Addr: 0016e91f Rxd: a005a640
|
# tb_core.u_sdram32 : at time 32933.0 ns READ : Bank = 2 Row = 366, Col = 94, Data = 86ebb60d
|
# tb_core.u_sdram32 : at time 33533.0 ns READ : Bank = 2 Row = 366, Col = 94, Data = 86ebb60d
|
# READ STATUS: Burst-No: 42 Addr: 0016e921 Rxd: 12a90325
|
# READ STATUS: Burst-No: 42 Addr: 0016e921 Rxd: 12a90325
|
# tb_core.u_sdram32 : at time 32943.0 ns READ : Bank = 2 Row = 366, Col = 95, Data = b87c1070
|
# tb_core.u_sdram32 : at time 33543.0 ns READ : Bank = 2 Row = 366, Col = 95, Data = b87c1070
|
# READ STATUS: Burst-No: 43 Addr: 0016e923 Rxd: 86ebb60d
|
# READ STATUS: Burst-No: 43 Addr: 0016e923 Rxd: 86ebb60d
|
# tb_core.u_sdram32 : at time 32953.0 ns READ : Bank = 2 Row = 366, Col = 96, Data = 16cbf92d
|
# tb_core.u_sdram32 : at time 33553.0 ns READ : Bank = 2 Row = 366, Col = 96, Data = 16cbf92d
|
# READ STATUS: Burst-No: 44 Addr: 0016e925 Rxd: b87c1070
|
# READ STATUS: Burst-No: 44 Addr: 0016e925 Rxd: b87c1070
|
# tb_core.u_sdram32 : at time 32963.0 ns READ : Bank = 2 Row = 366, Col = 97, Data = 94ded829
|
# tb_core.u_sdram32 : at time 33563.0 ns READ : Bank = 2 Row = 366, Col = 97, Data = 94ded829
|
# tb_core.u_sdram32 : at time 32967.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 33567.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 45 Addr: 0016e927 Rxd: 16cbf92d
|
# READ STATUS: Burst-No: 45 Addr: 0016e927 Rxd: 16cbf92d
|
# tb_core.u_sdram32 : at time 32973.0 ns READ : Bank = 2 Row = 366, Col = 98, Data = 5e2551bc
|
# tb_core.u_sdram32 : at time 33573.0 ns READ : Bank = 2 Row = 366, Col = 98, Data = 5e2551bc
|
# READ STATUS: Burst-No: 46 Addr: 0016e929 Rxd: 94ded829
|
# READ STATUS: Burst-No: 46 Addr: 0016e929 Rxd: 94ded829
|
# tb_core.u_sdram32 : at time 32983.0 ns READ : Bank = 2 Row = 366, Col = 99, Data = 987b0830
|
# tb_core.u_sdram32 : at time 33583.0 ns READ : Bank = 2 Row = 366, Col = 99, Data = 987b0830
|
# READ STATUS: Burst-No: 47 Addr: 0016e92b Rxd: 5e2551bc
|
# READ STATUS: Burst-No: 47 Addr: 0016e92b Rxd: 5e2551bc
|
# READ STATUS: Burst-No: 48 Addr: 0016e92d Rxd: 987b0830
|
# READ STATUS: Burst-No: 48 Addr: 0016e92d Rxd: 987b0830
|
# Write Address: 00272dc0, Burst Size: 17
|
# Write Address: 00272dc0, Burst Size: 17
|
# tb_core.u_sdram32 : at time 33157.0 ns ACT : Bank = 3 Row = 626
|
# tb_core.u_sdram32 : at time 33757.0 ns ACT : Bank = 3 Row = 626
|
# tb_core.u_sdram32 : at time 33187.0 ns WRITE: Bank = 3 Row = 626, Col = 112, Data = d0cf6aa1
|
# tb_core.u_sdram32 : at time 33787.0 ns WRITE: Bank = 3 Row = 626, Col = 112, Data = d0cf6aa1
|
# Status: Burst-No: 0 Write Address: 00272dc0 WriteData: d0cf6aa1
|
# Status: Burst-No: 0 Write Address: 00272dc0 WriteData: d0cf6aa1
|
# tb_core.u_sdram32 : at time 33197.0 ns WRITE: Bank = 3 Row = 626, Col = 113, Data = 26bf3f4d
|
# tb_core.u_sdram32 : at time 33797.0 ns WRITE: Bank = 3 Row = 626, Col = 113, Data = 26bf3f4d
|
# Status: Burst-No: 1 Write Address: 00272dc0 WriteData: 26bf3f4d
|
# Status: Burst-No: 1 Write Address: 00272dc0 WriteData: 26bf3f4d
|
# tb_core.u_sdram32 : at time 33207.0 ns WRITE: Bank = 3 Row = 626, Col = 114, Data = faf32ef5
|
# tb_core.u_sdram32 : at time 33807.0 ns WRITE: Bank = 3 Row = 626, Col = 114, Data = faf32ef5
|
# Status: Burst-No: 2 Write Address: 00272dc0 WriteData: faf32ef5
|
# Status: Burst-No: 2 Write Address: 00272dc0 WriteData: faf32ef5
|
# tb_core.u_sdram32 : at time 33217.0 ns WRITE: Bank = 3 Row = 626, Col = 115, Data = 7a87aff5
|
# tb_core.u_sdram32 : at time 33817.0 ns WRITE: Bank = 3 Row = 626, Col = 115, Data = 7a87aff5
|
# Status: Burst-No: 3 Write Address: 00272dc0 WriteData: 7a87aff5
|
# Status: Burst-No: 3 Write Address: 00272dc0 WriteData: 7a87aff5
|
# tb_core.u_sdram32 : at time 33227.0 ns WRITE: Bank = 3 Row = 626, Col = 116, Data = aeeacc5d
|
# tb_core.u_sdram32 : at time 33827.0 ns WRITE: Bank = 3 Row = 626, Col = 116, Data = aeeacc5d
|
# Status: Burst-No: 4 Write Address: 00272dc0 WriteData: aeeacc5d
|
# Status: Burst-No: 4 Write Address: 00272dc0 WriteData: aeeacc5d
|
# tb_core.u_sdram32 : at time 33237.0 ns WRITE: Bank = 3 Row = 626, Col = 117, Data = ca481294
|
# tb_core.u_sdram32 : at time 33837.0 ns WRITE: Bank = 3 Row = 626, Col = 117, Data = ca481294
|
# Status: Burst-No: 5 Write Address: 00272dc0 WriteData: ca481294
|
# Status: Burst-No: 5 Write Address: 00272dc0 WriteData: ca481294
|
# tb_core.u_sdram32 : at time 33247.0 ns WRITE: Bank = 3 Row = 626, Col = 118, Data = b558a66a
|
# tb_core.u_sdram32 : at time 33847.0 ns WRITE: Bank = 3 Row = 626, Col = 118, Data = b558a66a
|
# Status: Burst-No: 6 Write Address: 00272dc0 WriteData: b558a66a
|
# Status: Burst-No: 6 Write Address: 00272dc0 WriteData: b558a66a
|
# tb_core.u_sdram32 : at time 33257.0 ns WRITE: Bank = 3 Row = 626, Col = 119, Data = 5e6065bc
|
# tb_core.u_sdram32 : at time 33857.0 ns WRITE: Bank = 3 Row = 626, Col = 119, Data = 5e6065bc
|
# Status: Burst-No: 7 Write Address: 00272dc0 WriteData: 5e6065bc
|
# Status: Burst-No: 7 Write Address: 00272dc0 WriteData: 5e6065bc
|
# tb_core.u_sdram32 : at time 33267.0 ns WRITE: Bank = 3 Row = 626, Col = 120, Data = dc4308b8
|
# tb_core.u_sdram32 : at time 33867.0 ns WRITE: Bank = 3 Row = 626, Col = 120, Data = dc4308b8
|
# Status: Burst-No: 8 Write Address: 00272dc0 WriteData: dc4308b8
|
# Status: Burst-No: 8 Write Address: 00272dc0 WriteData: dc4308b8
|
# tb_core.u_sdram32 : at time 33277.0 ns WRITE: Bank = 3 Row = 626, Col = 121, Data = cf309c9e
|
# tb_core.u_sdram32 : at time 33877.0 ns WRITE: Bank = 3 Row = 626, Col = 121, Data = cf309c9e
|
# Status: Burst-No: 9 Write Address: 00272dc0 WriteData: cf309c9e
|
# Status: Burst-No: 9 Write Address: 00272dc0 WriteData: cf309c9e
|
# tb_core.u_sdram32 : at time 33287.0 ns WRITE: Bank = 3 Row = 626, Col = 122, Data = fd7906fa
|
# tb_core.u_sdram32 : at time 33887.0 ns WRITE: Bank = 3 Row = 626, Col = 122, Data = fd7906fa
|
# Status: Burst-No: 10 Write Address: 00272dc0 WriteData: fd7906fa
|
# Status: Burst-No: 10 Write Address: 00272dc0 WriteData: fd7906fa
|
# tb_core.u_sdram32 : at time 33297.0 ns WRITE: Bank = 3 Row = 626, Col = 123, Data = 23400b46
|
# tb_core.u_sdram32 : at time 33897.0 ns WRITE: Bank = 3 Row = 626, Col = 123, Data = 23400b46
|
# Status: Burst-No: 11 Write Address: 00272dc0 WriteData: 23400b46
|
# Status: Burst-No: 11 Write Address: 00272dc0 WriteData: 23400b46
|
# tb_core.u_sdram32 : at time 33307.0 ns WRITE: Bank = 3 Row = 626, Col = 124, Data = 83fa6407
|
# tb_core.u_sdram32 : at time 33907.0 ns WRITE: Bank = 3 Row = 626, Col = 124, Data = 83fa6407
|
# Status: Burst-No: 12 Write Address: 00272dc0 WriteData: 83fa6407
|
# Status: Burst-No: 12 Write Address: 00272dc0 WriteData: 83fa6407
|
# tb_core.u_sdram32 : at time 33317.0 ns WRITE: Bank = 3 Row = 626, Col = 125, Data = c9cbbc93
|
# tb_core.u_sdram32 : at time 33917.0 ns WRITE: Bank = 3 Row = 626, Col = 125, Data = c9cbbc93
|
# Status: Burst-No: 13 Write Address: 00272dc0 WriteData: c9cbbc93
|
# Status: Burst-No: 13 Write Address: 00272dc0 WriteData: c9cbbc93
|
# tb_core.u_sdram32 : at time 33327.0 ns WRITE: Bank = 3 Row = 626, Col = 126, Data = aada7455
|
# tb_core.u_sdram32 : at time 33927.0 ns WRITE: Bank = 3 Row = 626, Col = 126, Data = aada7455
|
# Status: Burst-No: 14 Write Address: 00272dc0 WriteData: aada7455
|
# Status: Burst-No: 14 Write Address: 00272dc0 WriteData: aada7455
|
# tb_core.u_sdram32 : at time 33337.0 ns WRITE: Bank = 3 Row = 626, Col = 127, Data = 5bd3dbb7
|
# tb_core.u_sdram32 : at time 33937.0 ns WRITE: Bank = 3 Row = 626, Col = 127, Data = 5bd3dbb7
|
# Status: Burst-No: 15 Write Address: 00272dc0 WriteData: 5bd3dbb7
|
# Status: Burst-No: 15 Write Address: 00272dc0 WriteData: 5bd3dbb7
|
# tb_core.u_sdram32 : at time 33347.0 ns WRITE: Bank = 3 Row = 626, Col = 128, Data = 22d5f145
|
# tb_core.u_sdram32 : at time 33947.0 ns WRITE: Bank = 3 Row = 626, Col = 128, Data = 22d5f145
|
# Status: Burst-No: 16 Write Address: 00272dc0 WriteData: 22d5f145
|
# Status: Burst-No: 16 Write Address: 00272dc0 WriteData: 22d5f145
|
# tb_core.u_sdram32 : at time 33357.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 33957.0 ns BST : Burst Terminate
|
# Write Address: 00000a63, Burst Size: 26
|
# Write Address: 00000a63, Burst Size: 26
|
# tb_core.u_sdram32 : at time 33497.0 ns ACT : Bank = 2 Row = 0
|
# tb_core.u_sdram32 : at time 34097.0 ns ACT : Bank = 2 Row = 0
|
# tb_core.u_sdram32 : at time 33527.0 ns WRITE: Bank = 2 Row = 0, Col = 152, Data = 9372ce26
|
# tb_core.u_sdram32 : at time 34127.0 ns WRITE: Bank = 2 Row = 0, Col = 152, Data = 9372ce26
|
# Status: Burst-No: 0 Write Address: 00000a63 WriteData: 9372ce26
|
# Status: Burst-No: 0 Write Address: 00000a63 WriteData: 9372ce26
|
# tb_core.u_sdram32 : at time 33537.0 ns WRITE: Bank = 2 Row = 0, Col = 153, Data = b4497668
|
# tb_core.u_sdram32 : at time 34137.0 ns WRITE: Bank = 2 Row = 0, Col = 153, Data = b4497668
|
# Status: Burst-No: 1 Write Address: 00000a63 WriteData: b4497668
|
# Status: Burst-No: 1 Write Address: 00000a63 WriteData: b4497668
|
# tb_core.u_sdram32 : at time 33547.0 ns WRITE: Bank = 2 Row = 0, Col = 154, Data = 8f63e41e
|
# tb_core.u_sdram32 : at time 34147.0 ns WRITE: Bank = 2 Row = 0, Col = 154, Data = 8f63e41e
|
# Status: Burst-No: 2 Write Address: 00000a63 WriteData: 8f63e41e
|
# Status: Burst-No: 2 Write Address: 00000a63 WriteData: 8f63e41e
|
# tb_core.u_sdram32 : at time 33557.0 ns WRITE: Bank = 2 Row = 0, Col = 155, Data = c838f490
|
# tb_core.u_sdram32 : at time 34157.0 ns WRITE: Bank = 2 Row = 0, Col = 155, Data = c838f490
|
# Status: Burst-No: 3 Write Address: 00000a63 WriteData: c838f490
|
# Status: Burst-No: 3 Write Address: 00000a63 WriteData: c838f490
|
# tb_core.u_sdram32 : at time 33567.0 ns WRITE: Bank = 2 Row = 0, Col = 156, Data = 2d19a55a
|
# tb_core.u_sdram32 : at time 34167.0 ns WRITE: Bank = 2 Row = 0, Col = 156, Data = 2d19a55a
|
# Status: Burst-No: 4 Write Address: 00000a63 WriteData: 2d19a55a
|
# Status: Burst-No: 4 Write Address: 00000a63 WriteData: 2d19a55a
|
# tb_core.u_sdram32 : at time 33577.0 ns WRITE: Bank = 2 Row = 0, Col = 157, Data = 0e43851c
|
# tb_core.u_sdram32 : at time 34177.0 ns WRITE: Bank = 2 Row = 0, Col = 157, Data = 0e43851c
|
# Status: Burst-No: 5 Write Address: 00000a63 WriteData: 0e43851c
|
# Status: Burst-No: 5 Write Address: 00000a63 WriteData: 0e43851c
|
# tb_core.u_sdram32 : at time 33587.0 ns WRITE: Bank = 2 Row = 0, Col = 158, Data = 5c9967b9
|
# tb_core.u_sdram32 : at time 34187.0 ns WRITE: Bank = 2 Row = 0, Col = 158, Data = 5c9967b9
|
# Status: Burst-No: 6 Write Address: 00000a63 WriteData: 5c9967b9
|
# Status: Burst-No: 6 Write Address: 00000a63 WriteData: 5c9967b9
|
# tb_core.u_sdram32 : at time 33597.0 ns WRITE: Bank = 2 Row = 0, Col = 159, Data = 55861fab
|
# tb_core.u_sdram32 : at time 34197.0 ns WRITE: Bank = 2 Row = 0, Col = 159, Data = 55861fab
|
# Status: Burst-No: 7 Write Address: 00000a63 WriteData: 55861fab
|
# Status: Burst-No: 7 Write Address: 00000a63 WriteData: 55861fab
|
# tb_core.u_sdram32 : at time 33607.0 ns WRITE: Bank = 2 Row = 0, Col = 160, Data = 6826d9d0
|
# tb_core.u_sdram32 : at time 34207.0 ns WRITE: Bank = 2 Row = 0, Col = 160, Data = 6826d9d0
|
# Status: Burst-No: 8 Write Address: 00000a63 WriteData: 6826d9d0
|
# Status: Burst-No: 8 Write Address: 00000a63 WriteData: 6826d9d0
|
# tb_core.u_sdram32 : at time 33617.0 ns WRITE: Bank = 2 Row = 0, Col = 161, Data = 37b9656f
|
# tb_core.u_sdram32 : at time 34217.0 ns WRITE: Bank = 2 Row = 0, Col = 161, Data = 37b9656f
|
# Status: Burst-No: 9 Write Address: 00000a63 WriteData: 37b9656f
|
# Status: Burst-No: 9 Write Address: 00000a63 WriteData: 37b9656f
|
# tb_core.u_sdram32 : at time 33627.0 ns WRITE: Bank = 2 Row = 0, Col = 162, Data = 6c6a6dd8
|
# tb_core.u_sdram32 : at time 34227.0 ns WRITE: Bank = 2 Row = 0, Col = 162, Data = 6c6a6dd8
|
# Status: Burst-No: 10 Write Address: 00000a63 WriteData: 6c6a6dd8
|
# Status: Burst-No: 10 Write Address: 00000a63 WriteData: 6c6a6dd8
|
# tb_core.u_sdram32 : at time 33637.0 ns WRITE: Bank = 2 Row = 0, Col = 163, Data = a2cc8845
|
# tb_core.u_sdram32 : at time 34237.0 ns WRITE: Bank = 2 Row = 0, Col = 163, Data = a2cc8845
|
# Status: Burst-No: 11 Write Address: 00000a63 WriteData: a2cc8845
|
# Status: Burst-No: 11 Write Address: 00000a63 WriteData: a2cc8845
|
# tb_core.u_sdram32 : at time 33647.0 ns WRITE: Bank = 2 Row = 0, Col = 164, Data = 46d6a78d
|
# tb_core.u_sdram32 : at time 34247.0 ns WRITE: Bank = 2 Row = 0, Col = 164, Data = 46d6a78d
|
# Status: Burst-No: 12 Write Address: 00000a63 WriteData: 46d6a78d
|
# Status: Burst-No: 12 Write Address: 00000a63 WriteData: 46d6a78d
|
# tb_core.u_sdram32 : at time 33657.0 ns WRITE: Bank = 2 Row = 0, Col = 165, Data = 45f3238b
|
# tb_core.u_sdram32 : at time 34257.0 ns WRITE: Bank = 2 Row = 0, Col = 165, Data = 45f3238b
|
# Status: Burst-No: 13 Write Address: 00000a63 WriteData: 45f3238b
|
# Status: Burst-No: 13 Write Address: 00000a63 WriteData: 45f3238b
|
# tb_core.u_sdram32 : at time 33667.0 ns WRITE: Bank = 2 Row = 0, Col = 166, Data = 7e2491fc
|
# tb_core.u_sdram32 : at time 34267.0 ns WRITE: Bank = 2 Row = 0, Col = 166, Data = 7e2491fc
|
# Status: Burst-No: 14 Write Address: 00000a63 WriteData: 7e2491fc
|
# Status: Burst-No: 14 Write Address: 00000a63 WriteData: 7e2491fc
|
# tb_core.u_sdram32 : at time 33677.0 ns WRITE: Bank = 2 Row = 0, Col = 167, Data = 6e1e1fdc
|
# tb_core.u_sdram32 : at time 34277.0 ns WRITE: Bank = 2 Row = 0, Col = 167, Data = 6e1e1fdc
|
# Status: Burst-No: 15 Write Address: 00000a63 WriteData: 6e1e1fdc
|
# Status: Burst-No: 15 Write Address: 00000a63 WriteData: 6e1e1fdc
|
# tb_core.u_sdram32 : at time 33687.0 ns WRITE: Bank = 2 Row = 0, Col = 168, Data = d27f0aa4
|
# tb_core.u_sdram32 : at time 34287.0 ns WRITE: Bank = 2 Row = 0, Col = 168, Data = d27f0aa4
|
# Status: Burst-No: 16 Write Address: 00000a63 WriteData: d27f0aa4
|
# Status: Burst-No: 16 Write Address: 00000a63 WriteData: d27f0aa4
|
# tb_core.u_sdram32 : at time 33697.0 ns WRITE: Bank = 2 Row = 0, Col = 169, Data = 0c978d19
|
# tb_core.u_sdram32 : at time 34297.0 ns WRITE: Bank = 2 Row = 0, Col = 169, Data = 0c978d19
|
# Status: Burst-No: 17 Write Address: 00000a63 WriteData: 0c978d19
|
# Status: Burst-No: 17 Write Address: 00000a63 WriteData: 0c978d19
|
# tb_core.u_sdram32 : at time 33707.0 ns WRITE: Bank = 2 Row = 0, Col = 170, Data = 52b533a5
|
# tb_core.u_sdram32 : at time 34307.0 ns WRITE: Bank = 2 Row = 0, Col = 170, Data = 52b533a5
|
# Status: Burst-No: 18 Write Address: 00000a63 WriteData: 52b533a5
|
# Status: Burst-No: 18 Write Address: 00000a63 WriteData: 52b533a5
|
# tb_core.u_sdram32 : at time 33717.0 ns WRITE: Bank = 2 Row = 0, Col = 171, Data = 9f398e3e
|
# tb_core.u_sdram32 : at time 34317.0 ns WRITE: Bank = 2 Row = 0, Col = 171, Data = 9f398e3e
|
# Status: Burst-No: 19 Write Address: 00000a63 WriteData: 9f398e3e
|
# Status: Burst-No: 19 Write Address: 00000a63 WriteData: 9f398e3e
|
# tb_core.u_sdram32 : at time 33727.0 ns WRITE: Bank = 2 Row = 0, Col = 172, Data = f98bc0f3
|
# tb_core.u_sdram32 : at time 34327.0 ns WRITE: Bank = 2 Row = 0, Col = 172, Data = f98bc0f3
|
# Status: Burst-No: 20 Write Address: 00000a63 WriteData: f98bc0f3
|
# Status: Burst-No: 20 Write Address: 00000a63 WriteData: f98bc0f3
|
# tb_core.u_sdram32 : at time 33737.0 ns WRITE: Bank = 2 Row = 0, Col = 173, Data = ac782c58
|
# tb_core.u_sdram32 : at time 34337.0 ns WRITE: Bank = 2 Row = 0, Col = 173, Data = ac782c58
|
# Status: Burst-No: 21 Write Address: 00000a63 WriteData: ac782c58
|
# Status: Burst-No: 21 Write Address: 00000a63 WriteData: ac782c58
|
# tb_core.u_sdram32 : at time 33747.0 ns WRITE: Bank = 2 Row = 0, Col = 174, Data = 62056bc4
|
# tb_core.u_sdram32 : at time 34347.0 ns WRITE: Bank = 2 Row = 0, Col = 174, Data = 62056bc4
|
# Status: Burst-No: 22 Write Address: 00000a63 WriteData: 62056bc4
|
# Status: Burst-No: 22 Write Address: 00000a63 WriteData: 62056bc4
|
# tb_core.u_sdram32 : at time 33757.0 ns WRITE: Bank = 2 Row = 0, Col = 175, Data = 2e36435c
|
# tb_core.u_sdram32 : at time 34357.0 ns WRITE: Bank = 2 Row = 0, Col = 175, Data = 2e36435c
|
# Status: Burst-No: 23 Write Address: 00000a63 WriteData: 2e36435c
|
# Status: Burst-No: 23 Write Address: 00000a63 WriteData: 2e36435c
|
# tb_core.u_sdram32 : at time 33767.0 ns WRITE: Bank = 2 Row = 0, Col = 176, Data = 033a4506
|
# tb_core.u_sdram32 : at time 34367.0 ns WRITE: Bank = 2 Row = 0, Col = 176, Data = 033a4506
|
# Status: Burst-No: 24 Write Address: 00000a63 WriteData: 033a4506
|
# Status: Burst-No: 24 Write Address: 00000a63 WriteData: 033a4506
|
# tb_core.u_sdram32 : at time 33777.0 ns WRITE: Bank = 2 Row = 0, Col = 177, Data = cd1d509a
|
# tb_core.u_sdram32 : at time 34377.0 ns WRITE: Bank = 2 Row = 0, Col = 177, Data = cd1d509a
|
# Status: Burst-No: 25 Write Address: 00000a63 WriteData: cd1d509a
|
# Status: Burst-No: 25 Write Address: 00000a63 WriteData: cd1d509a
|
# tb_core.u_sdram32 : at time 33787.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 34387.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 33923.0 ns READ : Bank = 3 Row = 626, Col = 112, Data = d0cf6aa1
|
# tb_core.u_sdram32 : at time 34523.0 ns READ : Bank = 3 Row = 626, Col = 112, Data = d0cf6aa1
|
# tb_core.u_sdram32 : at time 33933.0 ns READ : Bank = 3 Row = 626, Col = 113, Data = 26bf3f4d
|
# tb_core.u_sdram32 : at time 34533.0 ns READ : Bank = 3 Row = 626, Col = 113, Data = 26bf3f4d
|
# READ STATUS: Burst-No: 0 Addr: 00272dc0 Rxd: d0cf6aa1
|
# READ STATUS: Burst-No: 0 Addr: 00272dc0 Rxd: d0cf6aa1
|
# tb_core.u_sdram32 : at time 33943.0 ns READ : Bank = 3 Row = 626, Col = 114, Data = faf32ef5
|
# tb_core.u_sdram32 : at time 34543.0 ns READ : Bank = 3 Row = 626, Col = 114, Data = faf32ef5
|
# READ STATUS: Burst-No: 1 Addr: 00272dc2 Rxd: 26bf3f4d
|
# READ STATUS: Burst-No: 1 Addr: 00272dc2 Rxd: 26bf3f4d
|
# tb_core.u_sdram32 : at time 33953.0 ns READ : Bank = 3 Row = 626, Col = 115, Data = 7a87aff5
|
# tb_core.u_sdram32 : at time 34553.0 ns READ : Bank = 3 Row = 626, Col = 115, Data = 7a87aff5
|
# READ STATUS: Burst-No: 2 Addr: 00272dc4 Rxd: faf32ef5
|
# READ STATUS: Burst-No: 2 Addr: 00272dc4 Rxd: faf32ef5
|
# tb_core.u_sdram32 : at time 33963.0 ns READ : Bank = 3 Row = 626, Col = 116, Data = aeeacc5d
|
# tb_core.u_sdram32 : at time 34563.0 ns READ : Bank = 3 Row = 626, Col = 116, Data = aeeacc5d
|
# READ STATUS: Burst-No: 3 Addr: 00272dc6 Rxd: 7a87aff5
|
# READ STATUS: Burst-No: 3 Addr: 00272dc6 Rxd: 7a87aff5
|
# tb_core.u_sdram32 : at time 33973.0 ns READ : Bank = 3 Row = 626, Col = 117, Data = ca481294
|
# tb_core.u_sdram32 : at time 34573.0 ns READ : Bank = 3 Row = 626, Col = 117, Data = ca481294
|
# READ STATUS: Burst-No: 4 Addr: 00272dc8 Rxd: aeeacc5d
|
# READ STATUS: Burst-No: 4 Addr: 00272dc8 Rxd: aeeacc5d
|
# tb_core.u_sdram32 : at time 33983.0 ns READ : Bank = 3 Row = 626, Col = 118, Data = b558a66a
|
# tb_core.u_sdram32 : at time 34583.0 ns READ : Bank = 3 Row = 626, Col = 118, Data = b558a66a
|
# READ STATUS: Burst-No: 5 Addr: 00272dca Rxd: ca481294
|
# READ STATUS: Burst-No: 5 Addr: 00272dca Rxd: ca481294
|
# tb_core.u_sdram32 : at time 33993.0 ns READ : Bank = 3 Row = 626, Col = 119, Data = 5e6065bc
|
# tb_core.u_sdram32 : at time 34593.0 ns READ : Bank = 3 Row = 626, Col = 119, Data = 5e6065bc
|
# READ STATUS: Burst-No: 6 Addr: 00272dcc Rxd: b558a66a
|
# READ STATUS: Burst-No: 6 Addr: 00272dcc Rxd: b558a66a
|
# tb_core.u_sdram32 : at time 34003.0 ns READ : Bank = 3 Row = 626, Col = 120, Data = dc4308b8
|
# tb_core.u_sdram32 : at time 34603.0 ns READ : Bank = 3 Row = 626, Col = 120, Data = dc4308b8
|
# READ STATUS: Burst-No: 7 Addr: 00272dce Rxd: 5e6065bc
|
# READ STATUS: Burst-No: 7 Addr: 00272dce Rxd: 5e6065bc
|
# tb_core.u_sdram32 : at time 34013.0 ns READ : Bank = 3 Row = 626, Col = 121, Data = cf309c9e
|
# tb_core.u_sdram32 : at time 34613.0 ns READ : Bank = 3 Row = 626, Col = 121, Data = cf309c9e
|
# READ STATUS: Burst-No: 8 Addr: 00272dd0 Rxd: dc4308b8
|
# READ STATUS: Burst-No: 8 Addr: 00272dd0 Rxd: dc4308b8
|
# tb_core.u_sdram32 : at time 34023.0 ns READ : Bank = 3 Row = 626, Col = 122, Data = fd7906fa
|
# tb_core.u_sdram32 : at time 34623.0 ns READ : Bank = 3 Row = 626, Col = 122, Data = fd7906fa
|
# READ STATUS: Burst-No: 9 Addr: 00272dd2 Rxd: cf309c9e
|
# READ STATUS: Burst-No: 9 Addr: 00272dd2 Rxd: cf309c9e
|
# tb_core.u_sdram32 : at time 34033.0 ns READ : Bank = 3 Row = 626, Col = 123, Data = 23400b46
|
# tb_core.u_sdram32 : at time 34633.0 ns READ : Bank = 3 Row = 626, Col = 123, Data = 23400b46
|
# READ STATUS: Burst-No: 10 Addr: 00272dd4 Rxd: fd7906fa
|
# READ STATUS: Burst-No: 10 Addr: 00272dd4 Rxd: fd7906fa
|
# tb_core.u_sdram32 : at time 34043.0 ns READ : Bank = 3 Row = 626, Col = 124, Data = 83fa6407
|
# tb_core.u_sdram32 : at time 34643.0 ns READ : Bank = 3 Row = 626, Col = 124, Data = 83fa6407
|
# READ STATUS: Burst-No: 11 Addr: 00272dd6 Rxd: 23400b46
|
# READ STATUS: Burst-No: 11 Addr: 00272dd6 Rxd: 23400b46
|
# tb_core.u_sdram32 : at time 34053.0 ns READ : Bank = 3 Row = 626, Col = 125, Data = c9cbbc93
|
# tb_core.u_sdram32 : at time 34653.0 ns READ : Bank = 3 Row = 626, Col = 125, Data = c9cbbc93
|
# READ STATUS: Burst-No: 12 Addr: 00272dd8 Rxd: 83fa6407
|
# READ STATUS: Burst-No: 12 Addr: 00272dd8 Rxd: 83fa6407
|
# tb_core.u_sdram32 : at time 34063.0 ns READ : Bank = 3 Row = 626, Col = 126, Data = aada7455
|
# tb_core.u_sdram32 : at time 34663.0 ns READ : Bank = 3 Row = 626, Col = 126, Data = aada7455
|
# tb_core.u_sdram32 : at time 34067.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 34667.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 13 Addr: 00272dda Rxd: c9cbbc93
|
# READ STATUS: Burst-No: 13 Addr: 00272dda Rxd: c9cbbc93
|
# tb_core.u_sdram32 : at time 34073.0 ns READ : Bank = 3 Row = 626, Col = 127, Data = 5bd3dbb7
|
# tb_core.u_sdram32 : at time 34673.0 ns READ : Bank = 3 Row = 626, Col = 127, Data = 5bd3dbb7
|
# READ STATUS: Burst-No: 14 Addr: 00272ddc Rxd: aada7455
|
# READ STATUS: Burst-No: 14 Addr: 00272ddc Rxd: aada7455
|
# tb_core.u_sdram32 : at time 34083.0 ns READ : Bank = 3 Row = 626, Col = 128, Data = 22d5f145
|
# tb_core.u_sdram32 : at time 34683.0 ns READ : Bank = 3 Row = 626, Col = 128, Data = 22d5f145
|
# READ STATUS: Burst-No: 15 Addr: 00272dde Rxd: 5bd3dbb7
|
# READ STATUS: Burst-No: 15 Addr: 00272dde Rxd: 5bd3dbb7
|
# READ STATUS: Burst-No: 16 Addr: 00272de0 Rxd: 22d5f145
|
# READ STATUS: Burst-No: 16 Addr: 00272de0 Rxd: 22d5f145
|
# tb_core.u_sdram32 : at time 34253.0 ns READ : Bank = 2 Row = 0, Col = 152, Data = 9372ce26
|
# tb_core.u_sdram32 : at time 34853.0 ns READ : Bank = 2 Row = 0, Col = 152, Data = 9372ce26
|
# tb_core.u_sdram32 : at time 34263.0 ns READ : Bank = 2 Row = 0, Col = 153, Data = b4497668
|
# tb_core.u_sdram32 : at time 34863.0 ns READ : Bank = 2 Row = 0, Col = 153, Data = b4497668
|
# READ STATUS: Burst-No: 0 Addr: 00000a63 Rxd: 9372ce26
|
# READ STATUS: Burst-No: 0 Addr: 00000a63 Rxd: 9372ce26
|
# tb_core.u_sdram32 : at time 34273.0 ns READ : Bank = 2 Row = 0, Col = 154, Data = 8f63e41e
|
# tb_core.u_sdram32 : at time 34873.0 ns READ : Bank = 2 Row = 0, Col = 154, Data = 8f63e41e
|
# READ STATUS: Burst-No: 1 Addr: 00000a65 Rxd: b4497668
|
# READ STATUS: Burst-No: 1 Addr: 00000a65 Rxd: b4497668
|
# tb_core.u_sdram32 : at time 34283.0 ns READ : Bank = 2 Row = 0, Col = 155, Data = c838f490
|
# tb_core.u_sdram32 : at time 34883.0 ns READ : Bank = 2 Row = 0, Col = 155, Data = c838f490
|
# READ STATUS: Burst-No: 2 Addr: 00000a67 Rxd: 8f63e41e
|
# READ STATUS: Burst-No: 2 Addr: 00000a67 Rxd: 8f63e41e
|
# tb_core.u_sdram32 : at time 34293.0 ns READ : Bank = 2 Row = 0, Col = 156, Data = 2d19a55a
|
# tb_core.u_sdram32 : at time 34893.0 ns READ : Bank = 2 Row = 0, Col = 156, Data = 2d19a55a
|
# READ STATUS: Burst-No: 3 Addr: 00000a69 Rxd: c838f490
|
# READ STATUS: Burst-No: 3 Addr: 00000a69 Rxd: c838f490
|
# tb_core.u_sdram32 : at time 34303.0 ns READ : Bank = 2 Row = 0, Col = 157, Data = 0e43851c
|
# tb_core.u_sdram32 : at time 34903.0 ns READ : Bank = 2 Row = 0, Col = 157, Data = 0e43851c
|
# READ STATUS: Burst-No: 4 Addr: 00000a6b Rxd: 2d19a55a
|
# READ STATUS: Burst-No: 4 Addr: 00000a6b Rxd: 2d19a55a
|
# tb_core.u_sdram32 : at time 34313.0 ns READ : Bank = 2 Row = 0, Col = 158, Data = 5c9967b9
|
# tb_core.u_sdram32 : at time 34913.0 ns READ : Bank = 2 Row = 0, Col = 158, Data = 5c9967b9
|
# READ STATUS: Burst-No: 5 Addr: 00000a6d Rxd: 0e43851c
|
# READ STATUS: Burst-No: 5 Addr: 00000a6d Rxd: 0e43851c
|
# tb_core.u_sdram32 : at time 34323.0 ns READ : Bank = 2 Row = 0, Col = 159, Data = 55861fab
|
# tb_core.u_sdram32 : at time 34923.0 ns READ : Bank = 2 Row = 0, Col = 159, Data = 55861fab
|
# READ STATUS: Burst-No: 6 Addr: 00000a6f Rxd: 5c9967b9
|
# READ STATUS: Burst-No: 6 Addr: 00000a6f Rxd: 5c9967b9
|
# tb_core.u_sdram32 : at time 34333.0 ns READ : Bank = 2 Row = 0, Col = 160, Data = 6826d9d0
|
# tb_core.u_sdram32 : at time 34933.0 ns READ : Bank = 2 Row = 0, Col = 160, Data = 6826d9d0
|
# READ STATUS: Burst-No: 7 Addr: 00000a71 Rxd: 55861fab
|
# READ STATUS: Burst-No: 7 Addr: 00000a71 Rxd: 55861fab
|
# tb_core.u_sdram32 : at time 34343.0 ns READ : Bank = 2 Row = 0, Col = 161, Data = 37b9656f
|
# tb_core.u_sdram32 : at time 34943.0 ns READ : Bank = 2 Row = 0, Col = 161, Data = 37b9656f
|
# READ STATUS: Burst-No: 8 Addr: 00000a73 Rxd: 6826d9d0
|
# READ STATUS: Burst-No: 8 Addr: 00000a73 Rxd: 6826d9d0
|
# tb_core.u_sdram32 : at time 34353.0 ns READ : Bank = 2 Row = 0, Col = 162, Data = 6c6a6dd8
|
# tb_core.u_sdram32 : at time 34953.0 ns READ : Bank = 2 Row = 0, Col = 162, Data = 6c6a6dd8
|
# READ STATUS: Burst-No: 9 Addr: 00000a75 Rxd: 37b9656f
|
# READ STATUS: Burst-No: 9 Addr: 00000a75 Rxd: 37b9656f
|
# tb_core.u_sdram32 : at time 34363.0 ns READ : Bank = 2 Row = 0, Col = 163, Data = a2cc8845
|
# tb_core.u_sdram32 : at time 34963.0 ns READ : Bank = 2 Row = 0, Col = 163, Data = a2cc8845
|
# READ STATUS: Burst-No: 10 Addr: 00000a77 Rxd: 6c6a6dd8
|
# READ STATUS: Burst-No: 10 Addr: 00000a77 Rxd: 6c6a6dd8
|
# tb_core.u_sdram32 : at time 34373.0 ns READ : Bank = 2 Row = 0, Col = 164, Data = 46d6a78d
|
# tb_core.u_sdram32 : at time 34973.0 ns READ : Bank = 2 Row = 0, Col = 164, Data = 46d6a78d
|
# READ STATUS: Burst-No: 11 Addr: 00000a79 Rxd: a2cc8845
|
# READ STATUS: Burst-No: 11 Addr: 00000a79 Rxd: a2cc8845
|
# tb_core.u_sdram32 : at time 34383.0 ns READ : Bank = 2 Row = 0, Col = 165, Data = 45f3238b
|
# tb_core.u_sdram32 : at time 34983.0 ns READ : Bank = 2 Row = 0, Col = 165, Data = 45f3238b
|
# READ STATUS: Burst-No: 12 Addr: 00000a7b Rxd: 46d6a78d
|
# READ STATUS: Burst-No: 12 Addr: 00000a7b Rxd: 46d6a78d
|
# tb_core.u_sdram32 : at time 34393.0 ns READ : Bank = 2 Row = 0, Col = 166, Data = 7e2491fc
|
# tb_core.u_sdram32 : at time 34993.0 ns READ : Bank = 2 Row = 0, Col = 166, Data = 7e2491fc
|
# READ STATUS: Burst-No: 13 Addr: 00000a7d Rxd: 45f3238b
|
# READ STATUS: Burst-No: 13 Addr: 00000a7d Rxd: 45f3238b
|
# tb_core.u_sdram32 : at time 34403.0 ns READ : Bank = 2 Row = 0, Col = 167, Data = 6e1e1fdc
|
# tb_core.u_sdram32 : at time 35003.0 ns READ : Bank = 2 Row = 0, Col = 167, Data = 6e1e1fdc
|
# READ STATUS: Burst-No: 14 Addr: 00000a7f Rxd: 7e2491fc
|
# READ STATUS: Burst-No: 14 Addr: 00000a7f Rxd: 7e2491fc
|
# tb_core.u_sdram32 : at time 34413.0 ns READ : Bank = 2 Row = 0, Col = 168, Data = d27f0aa4
|
# tb_core.u_sdram32 : at time 35013.0 ns READ : Bank = 2 Row = 0, Col = 168, Data = d27f0aa4
|
# READ STATUS: Burst-No: 15 Addr: 00000a81 Rxd: 6e1e1fdc
|
# READ STATUS: Burst-No: 15 Addr: 00000a81 Rxd: 6e1e1fdc
|
# tb_core.u_sdram32 : at time 34423.0 ns READ : Bank = 2 Row = 0, Col = 169, Data = 0c978d19
|
# tb_core.u_sdram32 : at time 35023.0 ns READ : Bank = 2 Row = 0, Col = 169, Data = 0c978d19
|
# READ STATUS: Burst-No: 16 Addr: 00000a83 Rxd: d27f0aa4
|
# READ STATUS: Burst-No: 16 Addr: 00000a83 Rxd: d27f0aa4
|
# tb_core.u_sdram32 : at time 34433.0 ns READ : Bank = 2 Row = 0, Col = 170, Data = 52b533a5
|
# tb_core.u_sdram32 : at time 35033.0 ns READ : Bank = 2 Row = 0, Col = 170, Data = 52b533a5
|
# READ STATUS: Burst-No: 17 Addr: 00000a85 Rxd: 0c978d19
|
# READ STATUS: Burst-No: 17 Addr: 00000a85 Rxd: 0c978d19
|
# tb_core.u_sdram32 : at time 34443.0 ns READ : Bank = 2 Row = 0, Col = 171, Data = 9f398e3e
|
# tb_core.u_sdram32 : at time 35043.0 ns READ : Bank = 2 Row = 0, Col = 171, Data = 9f398e3e
|
# READ STATUS: Burst-No: 18 Addr: 00000a87 Rxd: 52b533a5
|
# READ STATUS: Burst-No: 18 Addr: 00000a87 Rxd: 52b533a5
|
# tb_core.u_sdram32 : at time 34453.0 ns READ : Bank = 2 Row = 0, Col = 172, Data = f98bc0f3
|
# tb_core.u_sdram32 : at time 35053.0 ns READ : Bank = 2 Row = 0, Col = 172, Data = f98bc0f3
|
# READ STATUS: Burst-No: 19 Addr: 00000a89 Rxd: 9f398e3e
|
# READ STATUS: Burst-No: 19 Addr: 00000a89 Rxd: 9f398e3e
|
# tb_core.u_sdram32 : at time 34463.0 ns READ : Bank = 2 Row = 0, Col = 173, Data = ac782c58
|
# tb_core.u_sdram32 : at time 35063.0 ns READ : Bank = 2 Row = 0, Col = 173, Data = ac782c58
|
# READ STATUS: Burst-No: 20 Addr: 00000a8b Rxd: f98bc0f3
|
# READ STATUS: Burst-No: 20 Addr: 00000a8b Rxd: f98bc0f3
|
# tb_core.u_sdram32 : at time 34473.0 ns READ : Bank = 2 Row = 0, Col = 174, Data = 62056bc4
|
# tb_core.u_sdram32 : at time 35073.0 ns READ : Bank = 2 Row = 0, Col = 174, Data = 62056bc4
|
# READ STATUS: Burst-No: 21 Addr: 00000a8d Rxd: ac782c58
|
# READ STATUS: Burst-No: 21 Addr: 00000a8d Rxd: ac782c58
|
# tb_core.u_sdram32 : at time 34483.0 ns READ : Bank = 2 Row = 0, Col = 175, Data = 2e36435c
|
# tb_core.u_sdram32 : at time 35083.0 ns READ : Bank = 2 Row = 0, Col = 175, Data = 2e36435c
|
# tb_core.u_sdram32 : at time 34487.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 35087.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 22 Addr: 00000a8f Rxd: 62056bc4
|
# READ STATUS: Burst-No: 22 Addr: 00000a8f Rxd: 62056bc4
|
# tb_core.u_sdram32 : at time 34493.0 ns READ : Bank = 2 Row = 0, Col = 176, Data = 033a4506
|
# tb_core.u_sdram32 : at time 35093.0 ns READ : Bank = 2 Row = 0, Col = 176, Data = 033a4506
|
# READ STATUS: Burst-No: 23 Addr: 00000a91 Rxd: 2e36435c
|
# READ STATUS: Burst-No: 23 Addr: 00000a91 Rxd: 2e36435c
|
# tb_core.u_sdram32 : at time 34503.0 ns READ : Bank = 2 Row = 0, Col = 177, Data = cd1d509a
|
# tb_core.u_sdram32 : at time 35103.0 ns READ : Bank = 2 Row = 0, Col = 177, Data = cd1d509a
|
# READ STATUS: Burst-No: 24 Addr: 00000a93 Rxd: 033a4506
|
# READ STATUS: Burst-No: 24 Addr: 00000a93 Rxd: 033a4506
|
# READ STATUS: Burst-No: 25 Addr: 00000a95 Rxd: cd1d509a
|
# READ STATUS: Burst-No: 25 Addr: 00000a95 Rxd: cd1d509a
|
# Write Address: 00161918, Burst Size: 6
|
# Write Address: 00161918, Burst Size: 6
|
# tb_core.u_sdram32 : at time 34677.0 ns ACT : Bank = 2 Row = 353
|
# tb_core.u_sdram32 : at time 35277.0 ns ACT : Bank = 2 Row = 353
|
# tb_core.u_sdram32 : at time 34707.0 ns WRITE: Bank = 2 Row = 353, Col = 70, Data = 5515d1aa
|
# tb_core.u_sdram32 : at time 35307.0 ns WRITE: Bank = 2 Row = 353, Col = 70, Data = 5515d1aa
|
# Status: Burst-No: 0 Write Address: 00161918 WriteData: 5515d1aa
|
# Status: Burst-No: 0 Write Address: 00161918 WriteData: 5515d1aa
|
# tb_core.u_sdram32 : at time 34717.0 ns WRITE: Bank = 2 Row = 353, Col = 71, Data = 0d12031a
|
# tb_core.u_sdram32 : at time 35317.0 ns WRITE: Bank = 2 Row = 353, Col = 71, Data = 0d12031a
|
# Status: Burst-No: 1 Write Address: 00161918 WriteData: 0d12031a
|
# Status: Burst-No: 1 Write Address: 00161918 WriteData: 0d12031a
|
# tb_core.u_sdram32 : at time 34727.0 ns WRITE: Bank = 2 Row = 353, Col = 72, Data = 61dbd5c3
|
# tb_core.u_sdram32 : at time 35327.0 ns WRITE: Bank = 2 Row = 353, Col = 72, Data = 61dbd5c3
|
# Status: Burst-No: 2 Write Address: 00161918 WriteData: 61dbd5c3
|
# Status: Burst-No: 2 Write Address: 00161918 WriteData: 61dbd5c3
|
# tb_core.u_sdram32 : at time 34737.0 ns WRITE: Bank = 2 Row = 353, Col = 73, Data = 5934e9b2
|
# tb_core.u_sdram32 : at time 35337.0 ns WRITE: Bank = 2 Row = 353, Col = 73, Data = 5934e9b2
|
# Status: Burst-No: 3 Write Address: 00161918 WriteData: 5934e9b2
|
# Status: Burst-No: 3 Write Address: 00161918 WriteData: 5934e9b2
|
# tb_core.u_sdram32 : at time 34747.0 ns WRITE: Bank = 2 Row = 353, Col = 74, Data = 0633630c
|
# tb_core.u_sdram32 : at time 35347.0 ns WRITE: Bank = 2 Row = 353, Col = 74, Data = 0633630c
|
# Status: Burst-No: 4 Write Address: 00161918 WriteData: 0633630c
|
# Status: Burst-No: 4 Write Address: 00161918 WriteData: 0633630c
|
# tb_core.u_sdram32 : at time 34757.0 ns WRITE: Bank = 2 Row = 353, Col = 75, Data = f4f00ee9
|
# tb_core.u_sdram32 : at time 35357.0 ns WRITE: Bank = 2 Row = 353, Col = 75, Data = f4f00ee9
|
# Status: Burst-No: 5 Write Address: 00161918 WriteData: f4f00ee9
|
# Status: Burst-No: 5 Write Address: 00161918 WriteData: f4f00ee9
|
# tb_core.u_sdram32 : at time 34767.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 35367.0 ns BST : Burst Terminate
|
# Write Address: 001afdc3, Burst Size: 44
|
# Write Address: 001afdc3, Burst Size: 44
|
# tb_core.u_sdram32 : at time 34907.0 ns ACT : Bank = 3 Row = 431
|
# tb_core.u_sdram32 : at time 35507.0 ns ACT : Bank = 3 Row = 431
|
# tb_core.u_sdram32 : at time 34937.0 ns WRITE: Bank = 3 Row = 431, Col = 112, Data = 7c2db9f8
|
# tb_core.u_sdram32 : at time 35537.0 ns WRITE: Bank = 3 Row = 431, Col = 112, Data = 7c2db9f8
|
# Status: Burst-No: 0 Write Address: 001afdc3 WriteData: 7c2db9f8
|
# Status: Burst-No: 0 Write Address: 001afdc3 WriteData: 7c2db9f8
|
# tb_core.u_sdram32 : at time 34947.0 ns WRITE: Bank = 3 Row = 431, Col = 113, Data = 792c03f2
|
# tb_core.u_sdram32 : at time 35547.0 ns WRITE: Bank = 3 Row = 431, Col = 113, Data = 792c03f2
|
# Status: Burst-No: 1 Write Address: 001afdc3 WriteData: 792c03f2
|
# Status: Burst-No: 1 Write Address: 001afdc3 WriteData: 792c03f2
|
# tb_core.u_sdram32 : at time 34957.0 ns WRITE: Bank = 3 Row = 431, Col = 114, Data = 4483ad89
|
# tb_core.u_sdram32 : at time 35557.0 ns WRITE: Bank = 3 Row = 431, Col = 114, Data = 4483ad89
|
# Status: Burst-No: 2 Write Address: 001afdc3 WriteData: 4483ad89
|
# Status: Burst-No: 2 Write Address: 001afdc3 WriteData: 4483ad89
|
# tb_core.u_sdram32 : at time 34967.0 ns WRITE: Bank = 3 Row = 431, Col = 115, Data = 378c736f
|
# tb_core.u_sdram32 : at time 35567.0 ns WRITE: Bank = 3 Row = 431, Col = 115, Data = 378c736f
|
# Status: Burst-No: 3 Write Address: 001afdc3 WriteData: 378c736f
|
# Status: Burst-No: 3 Write Address: 001afdc3 WriteData: 378c736f
|
# tb_core.u_sdram32 : at time 34977.0 ns WRITE: Bank = 3 Row = 431, Col = 116, Data = 0de14b1b
|
# tb_core.u_sdram32 : at time 35577.0 ns WRITE: Bank = 3 Row = 431, Col = 116, Data = 0de14b1b
|
# Status: Burst-No: 4 Write Address: 001afdc3 WriteData: 0de14b1b
|
# Status: Burst-No: 4 Write Address: 001afdc3 WriteData: 0de14b1b
|
# tb_core.u_sdram32 : at time 34987.0 ns WRITE: Bank = 3 Row = 431, Col = 117, Data = d6a128ad
|
# tb_core.u_sdram32 : at time 35587.0 ns WRITE: Bank = 3 Row = 431, Col = 117, Data = d6a128ad
|
# Status: Burst-No: 5 Write Address: 001afdc3 WriteData: d6a128ad
|
# Status: Burst-No: 5 Write Address: 001afdc3 WriteData: d6a128ad
|
# tb_core.u_sdram32 : at time 34997.0 ns WRITE: Bank = 3 Row = 431, Col = 118, Data = 344dc168
|
# tb_core.u_sdram32 : at time 35597.0 ns WRITE: Bank = 3 Row = 431, Col = 118, Data = 344dc168
|
# Status: Burst-No: 6 Write Address: 001afdc3 WriteData: 344dc168
|
# Status: Burst-No: 6 Write Address: 001afdc3 WriteData: 344dc168
|
# tb_core.u_sdram32 : at time 35007.0 ns WRITE: Bank = 3 Row = 431, Col = 119, Data = 92f91225
|
# tb_core.u_sdram32 : at time 35607.0 ns WRITE: Bank = 3 Row = 431, Col = 119, Data = 92f91225
|
# Status: Burst-No: 7 Write Address: 001afdc3 WriteData: 92f91225
|
# Status: Burst-No: 7 Write Address: 001afdc3 WriteData: 92f91225
|
# tb_core.u_sdram32 : at time 35017.0 ns WRITE: Bank = 3 Row = 431, Col = 120, Data = 67e857cf
|
# tb_core.u_sdram32 : at time 35617.0 ns WRITE: Bank = 3 Row = 431, Col = 120, Data = 67e857cf
|
# Status: Burst-No: 8 Write Address: 001afdc3 WriteData: 67e857cf
|
# Status: Burst-No: 8 Write Address: 001afdc3 WriteData: 67e857cf
|
# tb_core.u_sdram32 : at time 35027.0 ns WRITE: Bank = 3 Row = 431, Col = 121, Data = 55dd8dab
|
# tb_core.u_sdram32 : at time 35627.0 ns WRITE: Bank = 3 Row = 431, Col = 121, Data = 55dd8dab
|
# Status: Burst-No: 9 Write Address: 001afdc3 WriteData: 55dd8dab
|
# Status: Burst-No: 9 Write Address: 001afdc3 WriteData: 55dd8dab
|
# tb_core.u_sdram32 : at time 35037.0 ns WRITE: Bank = 3 Row = 431, Col = 122, Data = 8d94d21b
|
# tb_core.u_sdram32 : at time 35637.0 ns WRITE: Bank = 3 Row = 431, Col = 122, Data = 8d94d21b
|
# Status: Burst-No: 10 Write Address: 001afdc3 WriteData: 8d94d21b
|
# Status: Burst-No: 10 Write Address: 001afdc3 WriteData: 8d94d21b
|
# tb_core.u_sdram32 : at time 35047.0 ns WRITE: Bank = 3 Row = 431, Col = 123, Data = c03b3e80
|
# tb_core.u_sdram32 : at time 35647.0 ns WRITE: Bank = 3 Row = 431, Col = 123, Data = c03b3e80
|
# Status: Burst-No: 11 Write Address: 001afdc3 WriteData: c03b3e80
|
# Status: Burst-No: 11 Write Address: 001afdc3 WriteData: c03b3e80
|
# tb_core.u_sdram32 : at time 35057.0 ns WRITE: Bank = 3 Row = 431, Col = 124, Data = 2ed6d95d
|
# tb_core.u_sdram32 : at time 35657.0 ns WRITE: Bank = 3 Row = 431, Col = 124, Data = 2ed6d95d
|
# Status: Burst-No: 12 Write Address: 001afdc3 WriteData: 2ed6d95d
|
# Status: Burst-No: 12 Write Address: 001afdc3 WriteData: 2ed6d95d
|
# tb_core.u_sdram32 : at time 35067.0 ns WRITE: Bank = 3 Row = 431, Col = 125, Data = 412dfd82
|
# tb_core.u_sdram32 : at time 35667.0 ns WRITE: Bank = 3 Row = 431, Col = 125, Data = 412dfd82
|
# Status: Burst-No: 13 Write Address: 001afdc3 WriteData: 412dfd82
|
# Status: Burst-No: 13 Write Address: 001afdc3 WriteData: 412dfd82
|
# tb_core.u_sdram32 : at time 35077.0 ns WRITE: Bank = 3 Row = 431, Col = 126, Data = 82344204
|
# tb_core.u_sdram32 : at time 35677.0 ns WRITE: Bank = 3 Row = 431, Col = 126, Data = 82344204
|
# Status: Burst-No: 14 Write Address: 001afdc3 WriteData: 82344204
|
# Status: Burst-No: 14 Write Address: 001afdc3 WriteData: 82344204
|
# tb_core.u_sdram32 : at time 35087.0 ns WRITE: Bank = 3 Row = 431, Col = 127, Data = 2ba7a557
|
# tb_core.u_sdram32 : at time 35687.0 ns WRITE: Bank = 3 Row = 431, Col = 127, Data = 2ba7a557
|
# Status: Burst-No: 15 Write Address: 001afdc3 WriteData: 2ba7a557
|
# Status: Burst-No: 15 Write Address: 001afdc3 WriteData: 2ba7a557
|
# tb_core.u_sdram32 : at time 35097.0 ns WRITE: Bank = 3 Row = 431, Col = 128, Data = 1b368b36
|
# tb_core.u_sdram32 : at time 35697.0 ns WRITE: Bank = 3 Row = 431, Col = 128, Data = 1b368b36
|
# Status: Burst-No: 16 Write Address: 001afdc3 WriteData: 1b368b36
|
# Status: Burst-No: 16 Write Address: 001afdc3 WriteData: 1b368b36
|
# tb_core.u_sdram32 : at time 35107.0 ns WRITE: Bank = 3 Row = 431, Col = 129, Data = 196a0332
|
# tb_core.u_sdram32 : at time 35707.0 ns WRITE: Bank = 3 Row = 431, Col = 129, Data = 196a0332
|
# Status: Burst-No: 17 Write Address: 001afdc3 WriteData: 196a0332
|
# Status: Burst-No: 17 Write Address: 001afdc3 WriteData: 196a0332
|
# tb_core.u_sdram32 : at time 35117.0 ns WRITE: Bank = 3 Row = 431, Col = 130, Data = bce32879
|
# tb_core.u_sdram32 : at time 35717.0 ns WRITE: Bank = 3 Row = 431, Col = 130, Data = bce32879
|
# Status: Burst-No: 18 Write Address: 001afdc3 WriteData: bce32879
|
# Status: Burst-No: 18 Write Address: 001afdc3 WriteData: bce32879
|
# tb_core.u_sdram32 : at time 35127.0 ns WRITE: Bank = 3 Row = 431, Col = 131, Data = f24baee4
|
# tb_core.u_sdram32 : at time 35727.0 ns WRITE: Bank = 3 Row = 431, Col = 131, Data = f24baee4
|
# Status: Burst-No: 19 Write Address: 001afdc3 WriteData: f24baee4
|
# Status: Burst-No: 19 Write Address: 001afdc3 WriteData: f24baee4
|
# tb_core.u_sdram32 : at time 35137.0 ns WRITE: Bank = 3 Row = 431, Col = 132, Data = 8b42ec16
|
# tb_core.u_sdram32 : at time 35737.0 ns WRITE: Bank = 3 Row = 431, Col = 132, Data = 8b42ec16
|
# Status: Burst-No: 20 Write Address: 001afdc3 WriteData: 8b42ec16
|
# Status: Burst-No: 20 Write Address: 001afdc3 WriteData: 8b42ec16
|
# tb_core.u_sdram32 : at time 35147.0 ns WRITE: Bank = 3 Row = 431, Col = 133, Data = d57fecaa
|
# tb_core.u_sdram32 : at time 35747.0 ns WRITE: Bank = 3 Row = 431, Col = 133, Data = d57fecaa
|
# Status: Burst-No: 21 Write Address: 001afdc3 WriteData: d57fecaa
|
# Status: Burst-No: 21 Write Address: 001afdc3 WriteData: d57fecaa
|
# tb_core.u_sdram32 : at time 35157.0 ns WRITE: Bank = 3 Row = 431, Col = 134, Data = 605065c0
|
# tb_core.u_sdram32 : at time 35757.0 ns WRITE: Bank = 3 Row = 431, Col = 134, Data = 605065c0
|
# Status: Burst-No: 22 Write Address: 001afdc3 WriteData: 605065c0
|
# Status: Burst-No: 22 Write Address: 001afdc3 WriteData: 605065c0
|
# tb_core.u_sdram32 : at time 35167.0 ns WRITE: Bank = 3 Row = 431, Col = 135, Data = 9759882e
|
# tb_core.u_sdram32 : at time 35767.0 ns WRITE: Bank = 3 Row = 431, Col = 135, Data = 9759882e
|
# Status: Burst-No: 23 Write Address: 001afdc3 WriteData: 9759882e
|
# Status: Burst-No: 23 Write Address: 001afdc3 WriteData: 9759882e
|
# tb_core.u_sdram32 : at time 35177.0 ns WRITE: Bank = 3 Row = 431, Col = 136, Data = 4665378c
|
# tb_core.u_sdram32 : at time 35777.0 ns WRITE: Bank = 3 Row = 431, Col = 136, Data = 4665378c
|
# Status: Burst-No: 24 Write Address: 001afdc3 WriteData: 4665378c
|
# Status: Burst-No: 24 Write Address: 001afdc3 WriteData: 4665378c
|
# tb_core.u_sdram32 : at time 35187.0 ns WRITE: Bank = 3 Row = 431, Col = 137, Data = b8c0c271
|
# tb_core.u_sdram32 : at time 35787.0 ns WRITE: Bank = 3 Row = 431, Col = 137, Data = b8c0c271
|
# Status: Burst-No: 25 Write Address: 001afdc3 WriteData: b8c0c271
|
# Status: Burst-No: 25 Write Address: 001afdc3 WriteData: b8c0c271
|
# tb_core.u_sdram32 : at time 35197.0 ns WRITE: Bank = 3 Row = 431, Col = 138, Data = 7dfe8ffb
|
# tb_core.u_sdram32 : at time 35797.0 ns WRITE: Bank = 3 Row = 431, Col = 138, Data = 7dfe8ffb
|
# Status: Burst-No: 26 Write Address: 001afdc3 WriteData: 7dfe8ffb
|
# Status: Burst-No: 26 Write Address: 001afdc3 WriteData: 7dfe8ffb
|
# tb_core.u_sdram32 : at time 35207.0 ns WRITE: Bank = 3 Row = 431, Col = 139, Data = 5e5421bc
|
# tb_core.u_sdram32 : at time 35807.0 ns WRITE: Bank = 3 Row = 431, Col = 139, Data = 5e5421bc
|
# Status: Burst-No: 27 Write Address: 001afdc3 WriteData: 5e5421bc
|
# Status: Burst-No: 27 Write Address: 001afdc3 WriteData: 5e5421bc
|
# tb_core.u_sdram32 : at time 35217.0 ns WRITE: Bank = 3 Row = 431, Col = 140, Data = ee7068dc
|
# tb_core.u_sdram32 : at time 35817.0 ns WRITE: Bank = 3 Row = 431, Col = 140, Data = ee7068dc
|
# Status: Burst-No: 28 Write Address: 001afdc3 WriteData: ee7068dc
|
# Status: Burst-No: 28 Write Address: 001afdc3 WriteData: ee7068dc
|
# tb_core.u_sdram32 : at time 35227.0 ns WRITE: Bank = 3 Row = 431, Col = 141, Data = 0bec5717
|
# tb_core.u_sdram32 : at time 35827.0 ns WRITE: Bank = 3 Row = 431, Col = 141, Data = 0bec5717
|
# Status: Burst-No: 29 Write Address: 001afdc3 WriteData: 0bec5717
|
# Status: Burst-No: 29 Write Address: 001afdc3 WriteData: 0bec5717
|
# tb_core.u_sdram32 : at time 35237.0 ns WRITE: Bank = 3 Row = 431, Col = 142, Data = e0e004c1
|
# tb_core.u_sdram32 : at time 35837.0 ns WRITE: Bank = 3 Row = 431, Col = 142, Data = e0e004c1
|
# Status: Burst-No: 30 Write Address: 001afdc3 WriteData: e0e004c1
|
# Status: Burst-No: 30 Write Address: 001afdc3 WriteData: e0e004c1
|
# tb_core.u_sdram32 : at time 35247.0 ns WRITE: Bank = 3 Row = 431, Col = 143, Data = 75fb21eb
|
# tb_core.u_sdram32 : at time 35847.0 ns WRITE: Bank = 3 Row = 431, Col = 143, Data = 75fb21eb
|
# Status: Burst-No: 31 Write Address: 001afdc3 WriteData: 75fb21eb
|
# Status: Burst-No: 31 Write Address: 001afdc3 WriteData: 75fb21eb
|
# tb_core.u_sdram32 : at time 35257.0 ns WRITE: Bank = 3 Row = 431, Col = 144, Data = 5a9d3bb5
|
# tb_core.u_sdram32 : at time 35857.0 ns WRITE: Bank = 3 Row = 431, Col = 144, Data = 5a9d3bb5
|
# Status: Burst-No: 32 Write Address: 001afdc3 WriteData: 5a9d3bb5
|
# Status: Burst-No: 32 Write Address: 001afdc3 WriteData: 5a9d3bb5
|
# tb_core.u_sdram32 : at time 35267.0 ns WRITE: Bank = 3 Row = 431, Col = 145, Data = c4fd2e89
|
# tb_core.u_sdram32 : at time 35867.0 ns WRITE: Bank = 3 Row = 431, Col = 145, Data = c4fd2e89
|
# Status: Burst-No: 33 Write Address: 001afdc3 WriteData: c4fd2e89
|
# Status: Burst-No: 33 Write Address: 001afdc3 WriteData: c4fd2e89
|
# tb_core.u_sdram32 : at time 35277.0 ns WRITE: Bank = 3 Row = 431, Col = 146, Data = c7b2e28f
|
# tb_core.u_sdram32 : at time 35877.0 ns WRITE: Bank = 3 Row = 431, Col = 146, Data = c7b2e28f
|
# Status: Burst-No: 34 Write Address: 001afdc3 WriteData: c7b2e28f
|
# Status: Burst-No: 34 Write Address: 001afdc3 WriteData: c7b2e28f
|
# tb_core.u_sdram32 : at time 35287.0 ns WRITE: Bank = 3 Row = 431, Col = 147, Data = dff6f6bf
|
# tb_core.u_sdram32 : at time 35887.0 ns WRITE: Bank = 3 Row = 431, Col = 147, Data = dff6f6bf
|
# Status: Burst-No: 35 Write Address: 001afdc3 WriteData: dff6f6bf
|
# Status: Burst-No: 35 Write Address: 001afdc3 WriteData: dff6f6bf
|
# tb_core.u_sdram32 : at time 35297.0 ns WRITE: Bank = 3 Row = 431, Col = 148, Data = d8462ab0
|
# tb_core.u_sdram32 : at time 35897.0 ns WRITE: Bank = 3 Row = 431, Col = 148, Data = d8462ab0
|
# Status: Burst-No: 36 Write Address: 001afdc3 WriteData: d8462ab0
|
# Status: Burst-No: 36 Write Address: 001afdc3 WriteData: d8462ab0
|
# tb_core.u_sdram32 : at time 35307.0 ns WRITE: Bank = 3 Row = 431, Col = 149, Data = e9b49ad3
|
# tb_core.u_sdram32 : at time 35907.0 ns WRITE: Bank = 3 Row = 431, Col = 149, Data = e9b49ad3
|
# Status: Burst-No: 37 Write Address: 001afdc3 WriteData: e9b49ad3
|
# Status: Burst-No: 37 Write Address: 001afdc3 WriteData: e9b49ad3
|
# tb_core.u_sdram32 : at time 35317.0 ns WRITE: Bank = 3 Row = 431, Col = 150, Data = eb1d02d6
|
# tb_core.u_sdram32 : at time 35917.0 ns WRITE: Bank = 3 Row = 431, Col = 150, Data = eb1d02d6
|
# Status: Burst-No: 38 Write Address: 001afdc3 WriteData: eb1d02d6
|
# Status: Burst-No: 38 Write Address: 001afdc3 WriteData: eb1d02d6
|
# tb_core.u_sdram32 : at time 35327.0 ns WRITE: Bank = 3 Row = 431, Col = 151, Data = c144cc82
|
# tb_core.u_sdram32 : at time 35927.0 ns WRITE: Bank = 3 Row = 431, Col = 151, Data = c144cc82
|
# Status: Burst-No: 39 Write Address: 001afdc3 WriteData: c144cc82
|
# Status: Burst-No: 39 Write Address: 001afdc3 WriteData: c144cc82
|
# tb_core.u_sdram32 : at time 35337.0 ns WRITE: Bank = 3 Row = 431, Col = 152, Data = 0d63751a
|
# tb_core.u_sdram32 : at time 35937.0 ns WRITE: Bank = 3 Row = 431, Col = 152, Data = 0d63751a
|
# Status: Burst-No: 40 Write Address: 001afdc3 WriteData: 0d63751a
|
# Status: Burst-No: 40 Write Address: 001afdc3 WriteData: 0d63751a
|
# tb_core.u_sdram32 : at time 35347.0 ns WRITE: Bank = 3 Row = 431, Col = 153, Data = 38e6a771
|
# tb_core.u_sdram32 : at time 35947.0 ns WRITE: Bank = 3 Row = 431, Col = 153, Data = 38e6a771
|
# Status: Burst-No: 41 Write Address: 001afdc3 WriteData: 38e6a771
|
# Status: Burst-No: 41 Write Address: 001afdc3 WriteData: 38e6a771
|
# tb_core.u_sdram32 : at time 35357.0 ns WRITE: Bank = 3 Row = 431, Col = 154, Data = eb8804d7
|
# tb_core.u_sdram32 : at time 35957.0 ns WRITE: Bank = 3 Row = 431, Col = 154, Data = eb8804d7
|
# Status: Burst-No: 42 Write Address: 001afdc3 WriteData: eb8804d7
|
# Status: Burst-No: 42 Write Address: 001afdc3 WriteData: eb8804d7
|
# tb_core.u_sdram32 : at time 35367.0 ns WRITE: Bank = 3 Row = 431, Col = 155, Data = 87628e0e
|
# tb_core.u_sdram32 : at time 35967.0 ns WRITE: Bank = 3 Row = 431, Col = 155, Data = 87628e0e
|
# Status: Burst-No: 43 Write Address: 001afdc3 WriteData: 87628e0e
|
# Status: Burst-No: 43 Write Address: 001afdc3 WriteData: 87628e0e
|
# tb_core.u_sdram32 : at time 35377.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 35977.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 35513.0 ns READ : Bank = 2 Row = 353, Col = 70, Data = 5515d1aa
|
# tb_core.u_sdram32 : at time 36113.0 ns READ : Bank = 2 Row = 353, Col = 70, Data = 5515d1aa
|
# tb_core.u_sdram32 : at time 35523.0 ns READ : Bank = 2 Row = 353, Col = 71, Data = 0d12031a
|
# tb_core.u_sdram32 : at time 36123.0 ns READ : Bank = 2 Row = 353, Col = 71, Data = 0d12031a
|
# READ STATUS: Burst-No: 0 Addr: 00161918 Rxd: 5515d1aa
|
# READ STATUS: Burst-No: 0 Addr: 00161918 Rxd: 5515d1aa
|
# tb_core.u_sdram32 : at time 35533.0 ns READ : Bank = 2 Row = 353, Col = 72, Data = 61dbd5c3
|
# tb_core.u_sdram32 : at time 36133.0 ns READ : Bank = 2 Row = 353, Col = 72, Data = 61dbd5c3
|
# READ STATUS: Burst-No: 1 Addr: 0016191a Rxd: 0d12031a
|
# READ STATUS: Burst-No: 1 Addr: 0016191a Rxd: 0d12031a
|
# tb_core.u_sdram32 : at time 35543.0 ns READ : Bank = 2 Row = 353, Col = 73, Data = 5934e9b2
|
# tb_core.u_sdram32 : at time 36143.0 ns READ : Bank = 2 Row = 353, Col = 73, Data = 5934e9b2
|
# tb_core.u_sdram32 : at time 35547.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 36147.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 2 Addr: 0016191c Rxd: 61dbd5c3
|
# READ STATUS: Burst-No: 2 Addr: 0016191c Rxd: 61dbd5c3
|
# tb_core.u_sdram32 : at time 35553.0 ns READ : Bank = 2 Row = 353, Col = 74, Data = 0633630c
|
# tb_core.u_sdram32 : at time 36153.0 ns READ : Bank = 2 Row = 353, Col = 74, Data = 0633630c
|
# READ STATUS: Burst-No: 3 Addr: 0016191e Rxd: 5934e9b2
|
# READ STATUS: Burst-No: 3 Addr: 0016191e Rxd: 5934e9b2
|
# tb_core.u_sdram32 : at time 35563.0 ns READ : Bank = 2 Row = 353, Col = 75, Data = f4f00ee9
|
# tb_core.u_sdram32 : at time 36163.0 ns READ : Bank = 2 Row = 353, Col = 75, Data = f4f00ee9
|
# READ STATUS: Burst-No: 4 Addr: 00161920 Rxd: 0633630c
|
# READ STATUS: Burst-No: 4 Addr: 00161920 Rxd: 0633630c
|
# READ STATUS: Burst-No: 5 Addr: 00161922 Rxd: f4f00ee9
|
# READ STATUS: Burst-No: 5 Addr: 00161922 Rxd: f4f00ee9
|
# tb_core.u_sdram32 : at time 35733.0 ns READ : Bank = 3 Row = 431, Col = 112, Data = 7c2db9f8
|
# tb_core.u_sdram32 : at time 36333.0 ns READ : Bank = 3 Row = 431, Col = 112, Data = 7c2db9f8
|
# tb_core.u_sdram32 : at time 35743.0 ns READ : Bank = 3 Row = 431, Col = 113, Data = 792c03f2
|
# tb_core.u_sdram32 : at time 36343.0 ns READ : Bank = 3 Row = 431, Col = 113, Data = 792c03f2
|
# READ STATUS: Burst-No: 0 Addr: 001afdc3 Rxd: 7c2db9f8
|
# READ STATUS: Burst-No: 0 Addr: 001afdc3 Rxd: 7c2db9f8
|
# tb_core.u_sdram32 : at time 35753.0 ns READ : Bank = 3 Row = 431, Col = 114, Data = 4483ad89
|
# tb_core.u_sdram32 : at time 36353.0 ns READ : Bank = 3 Row = 431, Col = 114, Data = 4483ad89
|
# READ STATUS: Burst-No: 1 Addr: 001afdc5 Rxd: 792c03f2
|
# READ STATUS: Burst-No: 1 Addr: 001afdc5 Rxd: 792c03f2
|
# tb_core.u_sdram32 : at time 35763.0 ns READ : Bank = 3 Row = 431, Col = 115, Data = 378c736f
|
# tb_core.u_sdram32 : at time 36363.0 ns READ : Bank = 3 Row = 431, Col = 115, Data = 378c736f
|
# READ STATUS: Burst-No: 2 Addr: 001afdc7 Rxd: 4483ad89
|
# READ STATUS: Burst-No: 2 Addr: 001afdc7 Rxd: 4483ad89
|
# tb_core.u_sdram32 : at time 35773.0 ns READ : Bank = 3 Row = 431, Col = 116, Data = 0de14b1b
|
# tb_core.u_sdram32 : at time 36373.0 ns READ : Bank = 3 Row = 431, Col = 116, Data = 0de14b1b
|
# READ STATUS: Burst-No: 3 Addr: 001afdc9 Rxd: 378c736f
|
# READ STATUS: Burst-No: 3 Addr: 001afdc9 Rxd: 378c736f
|
# tb_core.u_sdram32 : at time 35783.0 ns READ : Bank = 3 Row = 431, Col = 117, Data = d6a128ad
|
# tb_core.u_sdram32 : at time 36383.0 ns READ : Bank = 3 Row = 431, Col = 117, Data = d6a128ad
|
# READ STATUS: Burst-No: 4 Addr: 001afdcb Rxd: 0de14b1b
|
# READ STATUS: Burst-No: 4 Addr: 001afdcb Rxd: 0de14b1b
|
# tb_core.u_sdram32 : at time 35793.0 ns READ : Bank = 3 Row = 431, Col = 118, Data = 344dc168
|
# tb_core.u_sdram32 : at time 36393.0 ns READ : Bank = 3 Row = 431, Col = 118, Data = 344dc168
|
# READ STATUS: Burst-No: 5 Addr: 001afdcd Rxd: d6a128ad
|
# READ STATUS: Burst-No: 5 Addr: 001afdcd Rxd: d6a128ad
|
# tb_core.u_sdram32 : at time 35803.0 ns READ : Bank = 3 Row = 431, Col = 119, Data = 92f91225
|
# tb_core.u_sdram32 : at time 36403.0 ns READ : Bank = 3 Row = 431, Col = 119, Data = 92f91225
|
# READ STATUS: Burst-No: 6 Addr: 001afdcf Rxd: 344dc168
|
# READ STATUS: Burst-No: 6 Addr: 001afdcf Rxd: 344dc168
|
# tb_core.u_sdram32 : at time 35813.0 ns READ : Bank = 3 Row = 431, Col = 120, Data = 67e857cf
|
# tb_core.u_sdram32 : at time 36413.0 ns READ : Bank = 3 Row = 431, Col = 120, Data = 67e857cf
|
# READ STATUS: Burst-No: 7 Addr: 001afdd1 Rxd: 92f91225
|
# READ STATUS: Burst-No: 7 Addr: 001afdd1 Rxd: 92f91225
|
# tb_core.u_sdram32 : at time 35823.0 ns READ : Bank = 3 Row = 431, Col = 121, Data = 55dd8dab
|
# tb_core.u_sdram32 : at time 36423.0 ns READ : Bank = 3 Row = 431, Col = 121, Data = 55dd8dab
|
# READ STATUS: Burst-No: 8 Addr: 001afdd3 Rxd: 67e857cf
|
# READ STATUS: Burst-No: 8 Addr: 001afdd3 Rxd: 67e857cf
|
# tb_core.u_sdram32 : at time 35833.0 ns READ : Bank = 3 Row = 431, Col = 122, Data = 8d94d21b
|
# tb_core.u_sdram32 : at time 36433.0 ns READ : Bank = 3 Row = 431, Col = 122, Data = 8d94d21b
|
# READ STATUS: Burst-No: 9 Addr: 001afdd5 Rxd: 55dd8dab
|
# READ STATUS: Burst-No: 9 Addr: 001afdd5 Rxd: 55dd8dab
|
# tb_core.u_sdram32 : at time 35843.0 ns READ : Bank = 3 Row = 431, Col = 123, Data = c03b3e80
|
# tb_core.u_sdram32 : at time 36443.0 ns READ : Bank = 3 Row = 431, Col = 123, Data = c03b3e80
|
# READ STATUS: Burst-No: 10 Addr: 001afdd7 Rxd: 8d94d21b
|
# READ STATUS: Burst-No: 10 Addr: 001afdd7 Rxd: 8d94d21b
|
# tb_core.u_sdram32 : at time 35853.0 ns READ : Bank = 3 Row = 431, Col = 124, Data = 2ed6d95d
|
# tb_core.u_sdram32 : at time 36453.0 ns READ : Bank = 3 Row = 431, Col = 124, Data = 2ed6d95d
|
# READ STATUS: Burst-No: 11 Addr: 001afdd9 Rxd: c03b3e80
|
# READ STATUS: Burst-No: 11 Addr: 001afdd9 Rxd: c03b3e80
|
# tb_core.u_sdram32 : at time 35863.0 ns READ : Bank = 3 Row = 431, Col = 125, Data = 412dfd82
|
# tb_core.u_sdram32 : at time 36463.0 ns READ : Bank = 3 Row = 431, Col = 125, Data = 412dfd82
|
# READ STATUS: Burst-No: 12 Addr: 001afddb Rxd: 2ed6d95d
|
# READ STATUS: Burst-No: 12 Addr: 001afddb Rxd: 2ed6d95d
|
# tb_core.u_sdram32 : at time 35873.0 ns READ : Bank = 3 Row = 431, Col = 126, Data = 82344204
|
# tb_core.u_sdram32 : at time 36473.0 ns READ : Bank = 3 Row = 431, Col = 126, Data = 82344204
|
# READ STATUS: Burst-No: 13 Addr: 001afddd Rxd: 412dfd82
|
# READ STATUS: Burst-No: 13 Addr: 001afddd Rxd: 412dfd82
|
# tb_core.u_sdram32 : at time 35883.0 ns READ : Bank = 3 Row = 431, Col = 127, Data = 2ba7a557
|
# tb_core.u_sdram32 : at time 36483.0 ns READ : Bank = 3 Row = 431, Col = 127, Data = 2ba7a557
|
# READ STATUS: Burst-No: 14 Addr: 001afddf Rxd: 82344204
|
# READ STATUS: Burst-No: 14 Addr: 001afddf Rxd: 82344204
|
# tb_core.u_sdram32 : at time 35893.0 ns READ : Bank = 3 Row = 431, Col = 128, Data = 1b368b36
|
# tb_core.u_sdram32 : at time 36493.0 ns READ : Bank = 3 Row = 431, Col = 128, Data = 1b368b36
|
# READ STATUS: Burst-No: 15 Addr: 001afde1 Rxd: 2ba7a557
|
# READ STATUS: Burst-No: 15 Addr: 001afde1 Rxd: 2ba7a557
|
# tb_core.u_sdram32 : at time 35903.0 ns READ : Bank = 3 Row = 431, Col = 129, Data = 196a0332
|
# tb_core.u_sdram32 : at time 36503.0 ns READ : Bank = 3 Row = 431, Col = 129, Data = 196a0332
|
# READ STATUS: Burst-No: 16 Addr: 001afde3 Rxd: 1b368b36
|
# READ STATUS: Burst-No: 16 Addr: 001afde3 Rxd: 1b368b36
|
# tb_core.u_sdram32 : at time 35913.0 ns READ : Bank = 3 Row = 431, Col = 130, Data = bce32879
|
# tb_core.u_sdram32 : at time 36513.0 ns READ : Bank = 3 Row = 431, Col = 130, Data = bce32879
|
# READ STATUS: Burst-No: 17 Addr: 001afde5 Rxd: 196a0332
|
# READ STATUS: Burst-No: 17 Addr: 001afde5 Rxd: 196a0332
|
# tb_core.u_sdram32 : at time 35923.0 ns READ : Bank = 3 Row = 431, Col = 131, Data = f24baee4
|
# tb_core.u_sdram32 : at time 36523.0 ns READ : Bank = 3 Row = 431, Col = 131, Data = f24baee4
|
# READ STATUS: Burst-No: 18 Addr: 001afde7 Rxd: bce32879
|
# READ STATUS: Burst-No: 18 Addr: 001afde7 Rxd: bce32879
|
# tb_core.u_sdram32 : at time 35933.0 ns READ : Bank = 3 Row = 431, Col = 132, Data = 8b42ec16
|
# tb_core.u_sdram32 : at time 36533.0 ns READ : Bank = 3 Row = 431, Col = 132, Data = 8b42ec16
|
# READ STATUS: Burst-No: 19 Addr: 001afde9 Rxd: f24baee4
|
# READ STATUS: Burst-No: 19 Addr: 001afde9 Rxd: f24baee4
|
# tb_core.u_sdram32 : at time 35943.0 ns READ : Bank = 3 Row = 431, Col = 133, Data = d57fecaa
|
# tb_core.u_sdram32 : at time 36543.0 ns READ : Bank = 3 Row = 431, Col = 133, Data = d57fecaa
|
# READ STATUS: Burst-No: 20 Addr: 001afdeb Rxd: 8b42ec16
|
# READ STATUS: Burst-No: 20 Addr: 001afdeb Rxd: 8b42ec16
|
# tb_core.u_sdram32 : at time 35953.0 ns READ : Bank = 3 Row = 431, Col = 134, Data = 605065c0
|
# tb_core.u_sdram32 : at time 36553.0 ns READ : Bank = 3 Row = 431, Col = 134, Data = 605065c0
|
# READ STATUS: Burst-No: 21 Addr: 001afded Rxd: d57fecaa
|
# READ STATUS: Burst-No: 21 Addr: 001afded Rxd: d57fecaa
|
# tb_core.u_sdram32 : at time 35963.0 ns READ : Bank = 3 Row = 431, Col = 135, Data = 9759882e
|
# tb_core.u_sdram32 : at time 36563.0 ns READ : Bank = 3 Row = 431, Col = 135, Data = 9759882e
|
# READ STATUS: Burst-No: 22 Addr: 001afdef Rxd: 605065c0
|
# READ STATUS: Burst-No: 22 Addr: 001afdef Rxd: 605065c0
|
# tb_core.u_sdram32 : at time 35973.0 ns READ : Bank = 3 Row = 431, Col = 136, Data = 4665378c
|
# tb_core.u_sdram32 : at time 36573.0 ns READ : Bank = 3 Row = 431, Col = 136, Data = 4665378c
|
# READ STATUS: Burst-No: 23 Addr: 001afdf1 Rxd: 9759882e
|
# READ STATUS: Burst-No: 23 Addr: 001afdf1 Rxd: 9759882e
|
# tb_core.u_sdram32 : at time 35983.0 ns READ : Bank = 3 Row = 431, Col = 137, Data = b8c0c271
|
# tb_core.u_sdram32 : at time 36583.0 ns READ : Bank = 3 Row = 431, Col = 137, Data = b8c0c271
|
# READ STATUS: Burst-No: 24 Addr: 001afdf3 Rxd: 4665378c
|
# READ STATUS: Burst-No: 24 Addr: 001afdf3 Rxd: 4665378c
|
# tb_core.u_sdram32 : at time 35993.0 ns READ : Bank = 3 Row = 431, Col = 138, Data = 7dfe8ffb
|
# tb_core.u_sdram32 : at time 36593.0 ns READ : Bank = 3 Row = 431, Col = 138, Data = 7dfe8ffb
|
# READ STATUS: Burst-No: 25 Addr: 001afdf5 Rxd: b8c0c271
|
# READ STATUS: Burst-No: 25 Addr: 001afdf5 Rxd: b8c0c271
|
# tb_core.u_sdram32 : at time 36003.0 ns READ : Bank = 3 Row = 431, Col = 139, Data = 5e5421bc
|
# tb_core.u_sdram32 : at time 36603.0 ns READ : Bank = 3 Row = 431, Col = 139, Data = 5e5421bc
|
# READ STATUS: Burst-No: 26 Addr: 001afdf7 Rxd: 7dfe8ffb
|
# READ STATUS: Burst-No: 26 Addr: 001afdf7 Rxd: 7dfe8ffb
|
# tb_core.u_sdram32 : at time 36013.0 ns READ : Bank = 3 Row = 431, Col = 140, Data = ee7068dc
|
# tb_core.u_sdram32 : at time 36613.0 ns READ : Bank = 3 Row = 431, Col = 140, Data = ee7068dc
|
# READ STATUS: Burst-No: 27 Addr: 001afdf9 Rxd: 5e5421bc
|
# READ STATUS: Burst-No: 27 Addr: 001afdf9 Rxd: 5e5421bc
|
# tb_core.u_sdram32 : at time 36023.0 ns READ : Bank = 3 Row = 431, Col = 141, Data = 0bec5717
|
# tb_core.u_sdram32 : at time 36623.0 ns READ : Bank = 3 Row = 431, Col = 141, Data = 0bec5717
|
# READ STATUS: Burst-No: 28 Addr: 001afdfb Rxd: ee7068dc
|
# READ STATUS: Burst-No: 28 Addr: 001afdfb Rxd: ee7068dc
|
# tb_core.u_sdram32 : at time 36033.0 ns READ : Bank = 3 Row = 431, Col = 142, Data = e0e004c1
|
# tb_core.u_sdram32 : at time 36633.0 ns READ : Bank = 3 Row = 431, Col = 142, Data = e0e004c1
|
# READ STATUS: Burst-No: 29 Addr: 001afdfd Rxd: 0bec5717
|
# READ STATUS: Burst-No: 29 Addr: 001afdfd Rxd: 0bec5717
|
# tb_core.u_sdram32 : at time 36043.0 ns READ : Bank = 3 Row = 431, Col = 143, Data = 75fb21eb
|
# tb_core.u_sdram32 : at time 36643.0 ns READ : Bank = 3 Row = 431, Col = 143, Data = 75fb21eb
|
# READ STATUS: Burst-No: 30 Addr: 001afdff Rxd: e0e004c1
|
# READ STATUS: Burst-No: 30 Addr: 001afdff Rxd: e0e004c1
|
# tb_core.u_sdram32 : at time 36053.0 ns READ : Bank = 3 Row = 431, Col = 144, Data = 5a9d3bb5
|
# tb_core.u_sdram32 : at time 36653.0 ns READ : Bank = 3 Row = 431, Col = 144, Data = 5a9d3bb5
|
# READ STATUS: Burst-No: 31 Addr: 001afe01 Rxd: 75fb21eb
|
# READ STATUS: Burst-No: 31 Addr: 001afe01 Rxd: 75fb21eb
|
# tb_core.u_sdram32 : at time 36063.0 ns READ : Bank = 3 Row = 431, Col = 145, Data = c4fd2e89
|
# tb_core.u_sdram32 : at time 36663.0 ns READ : Bank = 3 Row = 431, Col = 145, Data = c4fd2e89
|
# READ STATUS: Burst-No: 32 Addr: 001afe03 Rxd: 5a9d3bb5
|
# READ STATUS: Burst-No: 32 Addr: 001afe03 Rxd: 5a9d3bb5
|
# tb_core.u_sdram32 : at time 36073.0 ns READ : Bank = 3 Row = 431, Col = 146, Data = c7b2e28f
|
# tb_core.u_sdram32 : at time 36673.0 ns READ : Bank = 3 Row = 431, Col = 146, Data = c7b2e28f
|
# READ STATUS: Burst-No: 33 Addr: 001afe05 Rxd: c4fd2e89
|
# READ STATUS: Burst-No: 33 Addr: 001afe05 Rxd: c4fd2e89
|
# tb_core.u_sdram32 : at time 36083.0 ns READ : Bank = 3 Row = 431, Col = 147, Data = dff6f6bf
|
# tb_core.u_sdram32 : at time 36683.0 ns READ : Bank = 3 Row = 431, Col = 147, Data = dff6f6bf
|
# READ STATUS: Burst-No: 34 Addr: 001afe07 Rxd: c7b2e28f
|
# READ STATUS: Burst-No: 34 Addr: 001afe07 Rxd: c7b2e28f
|
# tb_core.u_sdram32 : at time 36093.0 ns READ : Bank = 3 Row = 431, Col = 148, Data = d8462ab0
|
# tb_core.u_sdram32 : at time 36693.0 ns READ : Bank = 3 Row = 431, Col = 148, Data = d8462ab0
|
# READ STATUS: Burst-No: 35 Addr: 001afe09 Rxd: dff6f6bf
|
# READ STATUS: Burst-No: 35 Addr: 001afe09 Rxd: dff6f6bf
|
# tb_core.u_sdram32 : at time 36103.0 ns READ : Bank = 3 Row = 431, Col = 149, Data = e9b49ad3
|
# tb_core.u_sdram32 : at time 36703.0 ns READ : Bank = 3 Row = 431, Col = 149, Data = e9b49ad3
|
# READ STATUS: Burst-No: 36 Addr: 001afe0b Rxd: d8462ab0
|
# READ STATUS: Burst-No: 36 Addr: 001afe0b Rxd: d8462ab0
|
# tb_core.u_sdram32 : at time 36113.0 ns READ : Bank = 3 Row = 431, Col = 150, Data = eb1d02d6
|
# tb_core.u_sdram32 : at time 36713.0 ns READ : Bank = 3 Row = 431, Col = 150, Data = eb1d02d6
|
# READ STATUS: Burst-No: 37 Addr: 001afe0d Rxd: e9b49ad3
|
# READ STATUS: Burst-No: 37 Addr: 001afe0d Rxd: e9b49ad3
|
# tb_core.u_sdram32 : at time 36123.0 ns READ : Bank = 3 Row = 431, Col = 151, Data = c144cc82
|
# tb_core.u_sdram32 : at time 36723.0 ns READ : Bank = 3 Row = 431, Col = 151, Data = c144cc82
|
# READ STATUS: Burst-No: 38 Addr: 001afe0f Rxd: eb1d02d6
|
# READ STATUS: Burst-No: 38 Addr: 001afe0f Rxd: eb1d02d6
|
# tb_core.u_sdram32 : at time 36133.0 ns READ : Bank = 3 Row = 431, Col = 152, Data = 0d63751a
|
# tb_core.u_sdram32 : at time 36733.0 ns READ : Bank = 3 Row = 431, Col = 152, Data = 0d63751a
|
# READ STATUS: Burst-No: 39 Addr: 001afe11 Rxd: c144cc82
|
# READ STATUS: Burst-No: 39 Addr: 001afe11 Rxd: c144cc82
|
# tb_core.u_sdram32 : at time 36143.0 ns READ : Bank = 3 Row = 431, Col = 153, Data = 38e6a771
|
# tb_core.u_sdram32 : at time 36743.0 ns READ : Bank = 3 Row = 431, Col = 153, Data = 38e6a771
|
# tb_core.u_sdram32 : at time 36147.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 36747.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 40 Addr: 001afe13 Rxd: 0d63751a
|
# READ STATUS: Burst-No: 40 Addr: 001afe13 Rxd: 0d63751a
|
# tb_core.u_sdram32 : at time 36153.0 ns READ : Bank = 3 Row = 431, Col = 154, Data = eb8804d7
|
# tb_core.u_sdram32 : at time 36753.0 ns READ : Bank = 3 Row = 431, Col = 154, Data = eb8804d7
|
# READ STATUS: Burst-No: 41 Addr: 001afe15 Rxd: 38e6a771
|
# READ STATUS: Burst-No: 41 Addr: 001afe15 Rxd: 38e6a771
|
# tb_core.u_sdram32 : at time 36163.0 ns READ : Bank = 3 Row = 431, Col = 155, Data = 87628e0e
|
# tb_core.u_sdram32 : at time 36763.0 ns READ : Bank = 3 Row = 431, Col = 155, Data = 87628e0e
|
# READ STATUS: Burst-No: 42 Addr: 001afe17 Rxd: eb8804d7
|
# READ STATUS: Burst-No: 42 Addr: 001afe17 Rxd: eb8804d7
|
# READ STATUS: Burst-No: 43 Addr: 001afe19 Rxd: 87628e0e
|
# READ STATUS: Burst-No: 43 Addr: 001afe19 Rxd: 87628e0e
|
# Write Address: 000714f1, Burst Size: 14
|
# Write Address: 000714f1, Burst Size: 14
|
# tb_core.u_sdram32 : at time 36337.0 ns ACT : Bank = 1 Row = 113
|
# tb_core.u_sdram32 : at time 36937.0 ns ACT : Bank = 1 Row = 113
|
# tb_core.u_sdram32 : at time 36367.0 ns WRITE: Bank = 1 Row = 113, Col = 60, Data = 02bd4305
|
# tb_core.u_sdram32 : at time 36967.0 ns WRITE: Bank = 1 Row = 113, Col = 60, Data = 02bd4305
|
# Status: Burst-No: 0 Write Address: 000714f1 WriteData: 02bd4305
|
# Status: Burst-No: 0 Write Address: 000714f1 WriteData: 02bd4305
|
# tb_core.u_sdram32 : at time 36377.0 ns WRITE: Bank = 1 Row = 113, Col = 61, Data = 0e3aeb1c
|
# tb_core.u_sdram32 : at time 36977.0 ns WRITE: Bank = 1 Row = 113, Col = 61, Data = 0e3aeb1c
|
# Status: Burst-No: 1 Write Address: 000714f1 WriteData: 0e3aeb1c
|
# Status: Burst-No: 1 Write Address: 000714f1 WriteData: 0e3aeb1c
|
# tb_core.u_sdram32 : at time 36387.0 ns WRITE: Bank = 1 Row = 113, Col = 62, Data = 4c18c798
|
# tb_core.u_sdram32 : at time 36987.0 ns WRITE: Bank = 1 Row = 113, Col = 62, Data = 4c18c798
|
# Status: Burst-No: 2 Write Address: 000714f1 WriteData: 4c18c798
|
# Status: Burst-No: 2 Write Address: 000714f1 WriteData: 4c18c798
|
# tb_core.u_sdram32 : at time 36397.0 ns WRITE: Bank = 1 Row = 113, Col = 63, Data = f67088ec
|
# tb_core.u_sdram32 : at time 36997.0 ns WRITE: Bank = 1 Row = 113, Col = 63, Data = f67088ec
|
# Status: Burst-No: 3 Write Address: 000714f1 WriteData: f67088ec
|
# Status: Burst-No: 3 Write Address: 000714f1 WriteData: f67088ec
|
# tb_core.u_sdram32 : at time 36407.0 ns WRITE: Bank = 1 Row = 113, Col = 64, Data = 9541d62a
|
# tb_core.u_sdram32 : at time 37007.0 ns WRITE: Bank = 1 Row = 113, Col = 64, Data = 9541d62a
|
# Status: Burst-No: 4 Write Address: 000714f1 WriteData: 9541d62a
|
# Status: Burst-No: 4 Write Address: 000714f1 WriteData: 9541d62a
|
# tb_core.u_sdram32 : at time 36417.0 ns WRITE: Bank = 1 Row = 113, Col = 65, Data = b2d14a65
|
# tb_core.u_sdram32 : at time 37017.0 ns WRITE: Bank = 1 Row = 113, Col = 65, Data = b2d14a65
|
# Status: Burst-No: 5 Write Address: 000714f1 WriteData: b2d14a65
|
# Status: Burst-No: 5 Write Address: 000714f1 WriteData: b2d14a65
|
# tb_core.u_sdram32 : at time 36427.0 ns WRITE: Bank = 1 Row = 113, Col = 66, Data = 1b920537
|
# tb_core.u_sdram32 : at time 37027.0 ns WRITE: Bank = 1 Row = 113, Col = 66, Data = 1b920537
|
# Status: Burst-No: 6 Write Address: 000714f1 WriteData: 1b920537
|
# Status: Burst-No: 6 Write Address: 000714f1 WriteData: 1b920537
|
# tb_core.u_sdram32 : at time 36437.0 ns WRITE: Bank = 1 Row = 113, Col = 67, Data = 81fa3603
|
# tb_core.u_sdram32 : at time 37037.0 ns WRITE: Bank = 1 Row = 113, Col = 67, Data = 81fa3603
|
# Status: Burst-No: 7 Write Address: 000714f1 WriteData: 81fa3603
|
# Status: Burst-No: 7 Write Address: 000714f1 WriteData: 81fa3603
|
# tb_core.u_sdram32 : at time 36447.0 ns WRITE: Bank = 1 Row = 113, Col = 68, Data = ff729efe
|
# tb_core.u_sdram32 : at time 37047.0 ns WRITE: Bank = 1 Row = 113, Col = 68, Data = ff729efe
|
# Status: Burst-No: 8 Write Address: 000714f1 WriteData: ff729efe
|
# Status: Burst-No: 8 Write Address: 000714f1 WriteData: ff729efe
|
# tb_core.u_sdram32 : at time 36457.0 ns WRITE: Bank = 1 Row = 113, Col = 69, Data = feaddcfd
|
# tb_core.u_sdram32 : at time 37057.0 ns WRITE: Bank = 1 Row = 113, Col = 69, Data = feaddcfd
|
# Status: Burst-No: 9 Write Address: 000714f1 WriteData: feaddcfd
|
# Status: Burst-No: 9 Write Address: 000714f1 WriteData: feaddcfd
|
# tb_core.u_sdram32 : at time 36467.0 ns WRITE: Bank = 1 Row = 113, Col = 70, Data = 9f7a0e3e
|
# tb_core.u_sdram32 : at time 37067.0 ns WRITE: Bank = 1 Row = 113, Col = 70, Data = 9f7a0e3e
|
# Status: Burst-No: 10 Write Address: 000714f1 WriteData: 9f7a0e3e
|
# Status: Burst-No: 10 Write Address: 000714f1 WriteData: 9f7a0e3e
|
# tb_core.u_sdram32 : at time 36477.0 ns WRITE: Bank = 1 Row = 113, Col = 71, Data = f43a34e8
|
# tb_core.u_sdram32 : at time 37077.0 ns WRITE: Bank = 1 Row = 113, Col = 71, Data = f43a34e8
|
# Status: Burst-No: 11 Write Address: 000714f1 WriteData: f43a34e8
|
# Status: Burst-No: 11 Write Address: 000714f1 WriteData: f43a34e8
|
# tb_core.u_sdram32 : at time 36487.0 ns WRITE: Bank = 1 Row = 113, Col = 72, Data = ba603874
|
# tb_core.u_sdram32 : at time 37087.0 ns WRITE: Bank = 1 Row = 113, Col = 72, Data = ba603874
|
# Status: Burst-No: 12 Write Address: 000714f1 WriteData: ba603874
|
# Status: Burst-No: 12 Write Address: 000714f1 WriteData: ba603874
|
# tb_core.u_sdram32 : at time 36497.0 ns WRITE: Bank = 1 Row = 113, Col = 73, Data = 580989b0
|
# tb_core.u_sdram32 : at time 37097.0 ns WRITE: Bank = 1 Row = 113, Col = 73, Data = 580989b0
|
# Status: Burst-No: 13 Write Address: 000714f1 WriteData: 580989b0
|
# Status: Burst-No: 13 Write Address: 000714f1 WriteData: 580989b0
|
# tb_core.u_sdram32 : at time 36507.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 37107.0 ns BST : Burst Terminate
|
# Write Address: 0021dc06, Burst Size: 19
|
# Write Address: 0021dc06, Burst Size: 19
|
# tb_core.u_sdram32 : at time 36647.0 ns ACT : Bank = 3 Row = 541
|
# tb_core.u_sdram32 : at time 37247.0 ns ACT : Bank = 3 Row = 541
|
# tb_core.u_sdram32 : at time 36677.0 ns WRITE: Bank = 3 Row = 541, Col = 1, Data = b46afc68
|
# tb_core.u_sdram32 : at time 37277.0 ns WRITE: Bank = 3 Row = 541, Col = 1, Data = b46afc68
|
# Status: Burst-No: 0 Write Address: 0021dc06 WriteData: b46afc68
|
# Status: Burst-No: 0 Write Address: 0021dc06 WriteData: b46afc68
|
# tb_core.u_sdram32 : at time 36687.0 ns WRITE: Bank = 3 Row = 541, Col = 2, Data = e2ba00c5
|
# tb_core.u_sdram32 : at time 37287.0 ns WRITE: Bank = 3 Row = 541, Col = 2, Data = e2ba00c5
|
# Status: Burst-No: 1 Write Address: 0021dc06 WriteData: e2ba00c5
|
# Status: Burst-No: 1 Write Address: 0021dc06 WriteData: e2ba00c5
|
# tb_core.u_sdram32 : at time 36697.0 ns WRITE: Bank = 3 Row = 541, Col = 3, Data = ff202efe
|
# tb_core.u_sdram32 : at time 37297.0 ns WRITE: Bank = 3 Row = 541, Col = 3, Data = ff202efe
|
# Status: Burst-No: 2 Write Address: 0021dc06 WriteData: ff202efe
|
# Status: Burst-No: 2 Write Address: 0021dc06 WriteData: ff202efe
|
# tb_core.u_sdram32 : at time 36707.0 ns WRITE: Bank = 3 Row = 541, Col = 4, Data = 1b0f0d36
|
# tb_core.u_sdram32 : at time 37307.0 ns WRITE: Bank = 3 Row = 541, Col = 4, Data = 1b0f0d36
|
# Status: Burst-No: 3 Write Address: 0021dc06 WriteData: 1b0f0d36
|
# Status: Burst-No: 3 Write Address: 0021dc06 WriteData: 1b0f0d36
|
# tb_core.u_sdram32 : at time 36717.0 ns WRITE: Bank = 3 Row = 541, Col = 5, Data = 799f09f3
|
# tb_core.u_sdram32 : at time 37317.0 ns WRITE: Bank = 3 Row = 541, Col = 5, Data = 799f09f3
|
# Status: Burst-No: 4 Write Address: 0021dc06 WriteData: 799f09f3
|
# Status: Burst-No: 4 Write Address: 0021dc06 WriteData: 799f09f3
|
# tb_core.u_sdram32 : at time 36727.0 ns WRITE: Bank = 3 Row = 541, Col = 6, Data = 7dddabfb
|
# tb_core.u_sdram32 : at time 37327.0 ns WRITE: Bank = 3 Row = 541, Col = 6, Data = 7dddabfb
|
# Status: Burst-No: 5 Write Address: 0021dc06 WriteData: 7dddabfb
|
# Status: Burst-No: 5 Write Address: 0021dc06 WriteData: 7dddabfb
|
# tb_core.u_sdram32 : at time 36737.0 ns WRITE: Bank = 3 Row = 541, Col = 7, Data = b58d7c6b
|
# tb_core.u_sdram32 : at time 37337.0 ns WRITE: Bank = 3 Row = 541, Col = 7, Data = b58d7c6b
|
# Status: Burst-No: 6 Write Address: 0021dc06 WriteData: b58d7c6b
|
# Status: Burst-No: 6 Write Address: 0021dc06 WriteData: b58d7c6b
|
# tb_core.u_sdram32 : at time 36747.0 ns WRITE: Bank = 3 Row = 541, Col = 8, Data = 0bcbbf17
|
# tb_core.u_sdram32 : at time 37347.0 ns WRITE: Bank = 3 Row = 541, Col = 8, Data = 0bcbbf17
|
# Status: Burst-No: 7 Write Address: 0021dc06 WriteData: 0bcbbf17
|
# Status: Burst-No: 7 Write Address: 0021dc06 WriteData: 0bcbbf17
|
# tb_core.u_sdram32 : at time 36757.0 ns WRITE: Bank = 3 Row = 541, Col = 9, Data = 87d0360f
|
# tb_core.u_sdram32 : at time 37357.0 ns WRITE: Bank = 3 Row = 541, Col = 9, Data = 87d0360f
|
# Status: Burst-No: 8 Write Address: 0021dc06 WriteData: 87d0360f
|
# Status: Burst-No: 8 Write Address: 0021dc06 WriteData: 87d0360f
|
# tb_core.u_sdram32 : at time 36767.0 ns WRITE: Bank = 3 Row = 541, Col = 10, Data = 8a47b614
|
# tb_core.u_sdram32 : at time 37367.0 ns WRITE: Bank = 3 Row = 541, Col = 10, Data = 8a47b614
|
# Status: Burst-No: 9 Write Address: 0021dc06 WriteData: 8a47b614
|
# Status: Burst-No: 9 Write Address: 0021dc06 WriteData: 8a47b614
|
# tb_core.u_sdram32 : at time 36777.0 ns WRITE: Bank = 3 Row = 541, Col = 11, Data = 1500052a
|
# tb_core.u_sdram32 : at time 37377.0 ns WRITE: Bank = 3 Row = 541, Col = 11, Data = 1500052a
|
# Status: Burst-No: 10 Write Address: 0021dc06 WriteData: 1500052a
|
# Status: Burst-No: 10 Write Address: 0021dc06 WriteData: 1500052a
|
# tb_core.u_sdram32 : at time 36787.0 ns WRITE: Bank = 3 Row = 541, Col = 12, Data = d3666ea6
|
# tb_core.u_sdram32 : at time 37387.0 ns WRITE: Bank = 3 Row = 541, Col = 12, Data = d3666ea6
|
# Status: Burst-No: 11 Write Address: 0021dc06 WriteData: d3666ea6
|
# Status: Burst-No: 11 Write Address: 0021dc06 WriteData: d3666ea6
|
# tb_core.u_sdram32 : at time 36797.0 ns WRITE: Bank = 3 Row = 541, Col = 13, Data = ea7626d4
|
# tb_core.u_sdram32 : at time 37397.0 ns WRITE: Bank = 3 Row = 541, Col = 13, Data = ea7626d4
|
# Status: Burst-No: 12 Write Address: 0021dc06 WriteData: ea7626d4
|
# Status: Burst-No: 12 Write Address: 0021dc06 WriteData: ea7626d4
|
# tb_core.u_sdram32 : at time 36807.0 ns WRITE: Bank = 3 Row = 541, Col = 14, Data = e5ac10cb
|
# tb_core.u_sdram32 : at time 37407.0 ns WRITE: Bank = 3 Row = 541, Col = 14, Data = e5ac10cb
|
# Status: Burst-No: 13 Write Address: 0021dc06 WriteData: e5ac10cb
|
# Status: Burst-No: 13 Write Address: 0021dc06 WriteData: e5ac10cb
|
# tb_core.u_sdram32 : at time 36817.0 ns WRITE: Bank = 3 Row = 541, Col = 15, Data = b587c26b
|
# tb_core.u_sdram32 : at time 37417.0 ns WRITE: Bank = 3 Row = 541, Col = 15, Data = b587c26b
|
# Status: Burst-No: 14 Write Address: 0021dc06 WriteData: b587c26b
|
# Status: Burst-No: 14 Write Address: 0021dc06 WriteData: b587c26b
|
# tb_core.u_sdram32 : at time 36827.0 ns WRITE: Bank = 3 Row = 541, Col = 16, Data = 0277eb04
|
# tb_core.u_sdram32 : at time 37427.0 ns WRITE: Bank = 3 Row = 541, Col = 16, Data = 0277eb04
|
# Status: Burst-No: 15 Write Address: 0021dc06 WriteData: 0277eb04
|
# Status: Burst-No: 15 Write Address: 0021dc06 WriteData: 0277eb04
|
# tb_core.u_sdram32 : at time 36837.0 ns WRITE: Bank = 3 Row = 541, Col = 17, Data = fa4832f4
|
# tb_core.u_sdram32 : at time 37437.0 ns WRITE: Bank = 3 Row = 541, Col = 17, Data = fa4832f4
|
# Status: Burst-No: 16 Write Address: 0021dc06 WriteData: fa4832f4
|
# Status: Burst-No: 16 Write Address: 0021dc06 WriteData: fa4832f4
|
# tb_core.u_sdram32 : at time 36847.0 ns WRITE: Bank = 3 Row = 541, Col = 18, Data = 468b618d
|
# tb_core.u_sdram32 : at time 37447.0 ns WRITE: Bank = 3 Row = 541, Col = 18, Data = 468b618d
|
# Status: Burst-No: 17 Write Address: 0021dc06 WriteData: 468b618d
|
# Status: Burst-No: 17 Write Address: 0021dc06 WriteData: 468b618d
|
# tb_core.u_sdram32 : at time 36857.0 ns WRITE: Bank = 3 Row = 541, Col = 19, Data = f0ea70e1
|
# tb_core.u_sdram32 : at time 37457.0 ns WRITE: Bank = 3 Row = 541, Col = 19, Data = f0ea70e1
|
# Status: Burst-No: 18 Write Address: 0021dc06 WriteData: f0ea70e1
|
# Status: Burst-No: 18 Write Address: 0021dc06 WriteData: f0ea70e1
|
# tb_core.u_sdram32 : at time 36867.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 37467.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 37003.0 ns READ : Bank = 1 Row = 113, Col = 60, Data = 02bd4305
|
# tb_core.u_sdram32 : at time 37603.0 ns READ : Bank = 1 Row = 113, Col = 60, Data = 02bd4305
|
# tb_core.u_sdram32 : at time 37013.0 ns READ : Bank = 1 Row = 113, Col = 61, Data = 0e3aeb1c
|
# tb_core.u_sdram32 : at time 37613.0 ns READ : Bank = 1 Row = 113, Col = 61, Data = 0e3aeb1c
|
# READ STATUS: Burst-No: 0 Addr: 000714f1 Rxd: 02bd4305
|
# READ STATUS: Burst-No: 0 Addr: 000714f1 Rxd: 02bd4305
|
# tb_core.u_sdram32 : at time 37023.0 ns READ : Bank = 1 Row = 113, Col = 62, Data = 4c18c798
|
# tb_core.u_sdram32 : at time 37623.0 ns READ : Bank = 1 Row = 113, Col = 62, Data = 4c18c798
|
# READ STATUS: Burst-No: 1 Addr: 000714f3 Rxd: 0e3aeb1c
|
# READ STATUS: Burst-No: 1 Addr: 000714f3 Rxd: 0e3aeb1c
|
# tb_core.u_sdram32 : at time 37033.0 ns READ : Bank = 1 Row = 113, Col = 63, Data = f67088ec
|
# tb_core.u_sdram32 : at time 37633.0 ns READ : Bank = 1 Row = 113, Col = 63, Data = f67088ec
|
# READ STATUS: Burst-No: 2 Addr: 000714f5 Rxd: 4c18c798
|
# READ STATUS: Burst-No: 2 Addr: 000714f5 Rxd: 4c18c798
|
# tb_core.u_sdram32 : at time 37043.0 ns READ : Bank = 1 Row = 113, Col = 64, Data = 9541d62a
|
# tb_core.u_sdram32 : at time 37643.0 ns READ : Bank = 1 Row = 113, Col = 64, Data = 9541d62a
|
# READ STATUS: Burst-No: 3 Addr: 000714f7 Rxd: f67088ec
|
# READ STATUS: Burst-No: 3 Addr: 000714f7 Rxd: f67088ec
|
# tb_core.u_sdram32 : at time 37053.0 ns READ : Bank = 1 Row = 113, Col = 65, Data = b2d14a65
|
# tb_core.u_sdram32 : at time 37653.0 ns READ : Bank = 1 Row = 113, Col = 65, Data = b2d14a65
|
# READ STATUS: Burst-No: 4 Addr: 000714f9 Rxd: 9541d62a
|
# READ STATUS: Burst-No: 4 Addr: 000714f9 Rxd: 9541d62a
|
# tb_core.u_sdram32 : at time 37063.0 ns READ : Bank = 1 Row = 113, Col = 66, Data = 1b920537
|
# tb_core.u_sdram32 : at time 37663.0 ns READ : Bank = 1 Row = 113, Col = 66, Data = 1b920537
|
# READ STATUS: Burst-No: 5 Addr: 000714fb Rxd: b2d14a65
|
# READ STATUS: Burst-No: 5 Addr: 000714fb Rxd: b2d14a65
|
# tb_core.u_sdram32 : at time 37073.0 ns READ : Bank = 1 Row = 113, Col = 67, Data = 81fa3603
|
# tb_core.u_sdram32 : at time 37673.0 ns READ : Bank = 1 Row = 113, Col = 67, Data = 81fa3603
|
# READ STATUS: Burst-No: 6 Addr: 000714fd Rxd: 1b920537
|
# READ STATUS: Burst-No: 6 Addr: 000714fd Rxd: 1b920537
|
# tb_core.u_sdram32 : at time 37083.0 ns READ : Bank = 1 Row = 113, Col = 68, Data = ff729efe
|
# tb_core.u_sdram32 : at time 37683.0 ns READ : Bank = 1 Row = 113, Col = 68, Data = ff729efe
|
# READ STATUS: Burst-No: 7 Addr: 000714ff Rxd: 81fa3603
|
# READ STATUS: Burst-No: 7 Addr: 000714ff Rxd: 81fa3603
|
# tb_core.u_sdram32 : at time 37093.0 ns READ : Bank = 1 Row = 113, Col = 69, Data = feaddcfd
|
# tb_core.u_sdram32 : at time 37693.0 ns READ : Bank = 1 Row = 113, Col = 69, Data = feaddcfd
|
# READ STATUS: Burst-No: 8 Addr: 00071501 Rxd: ff729efe
|
# READ STATUS: Burst-No: 8 Addr: 00071501 Rxd: ff729efe
|
# tb_core.u_sdram32 : at time 37103.0 ns READ : Bank = 1 Row = 113, Col = 70, Data = 9f7a0e3e
|
# tb_core.u_sdram32 : at time 37703.0 ns READ : Bank = 1 Row = 113, Col = 70, Data = 9f7a0e3e
|
# READ STATUS: Burst-No: 9 Addr: 00071503 Rxd: feaddcfd
|
# READ STATUS: Burst-No: 9 Addr: 00071503 Rxd: feaddcfd
|
# tb_core.u_sdram32 : at time 37113.0 ns READ : Bank = 1 Row = 113, Col = 71, Data = f43a34e8
|
# tb_core.u_sdram32 : at time 37713.0 ns READ : Bank = 1 Row = 113, Col = 71, Data = f43a34e8
|
# tb_core.u_sdram32 : at time 37117.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 37717.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 10 Addr: 00071505 Rxd: 9f7a0e3e
|
# READ STATUS: Burst-No: 10 Addr: 00071505 Rxd: 9f7a0e3e
|
# tb_core.u_sdram32 : at time 37123.0 ns READ : Bank = 1 Row = 113, Col = 72, Data = ba603874
|
# tb_core.u_sdram32 : at time 37723.0 ns READ : Bank = 1 Row = 113, Col = 72, Data = ba603874
|
# READ STATUS: Burst-No: 11 Addr: 00071507 Rxd: f43a34e8
|
# READ STATUS: Burst-No: 11 Addr: 00071507 Rxd: f43a34e8
|
# tb_core.u_sdram32 : at time 37133.0 ns READ : Bank = 1 Row = 113, Col = 73, Data = 580989b0
|
# tb_core.u_sdram32 : at time 37733.0 ns READ : Bank = 1 Row = 113, Col = 73, Data = 580989b0
|
# READ STATUS: Burst-No: 12 Addr: 00071509 Rxd: ba603874
|
# READ STATUS: Burst-No: 12 Addr: 00071509 Rxd: ba603874
|
# READ STATUS: Burst-No: 13 Addr: 0007150b Rxd: 580989b0
|
# READ STATUS: Burst-No: 13 Addr: 0007150b Rxd: 580989b0
|
# tb_core.u_sdram32 : at time 37303.0 ns READ : Bank = 3 Row = 541, Col = 1, Data = b46afc68
|
# tb_core.u_sdram32 : at time 37903.0 ns READ : Bank = 3 Row = 541, Col = 1, Data = b46afc68
|
# tb_core.u_sdram32 : at time 37313.0 ns READ : Bank = 3 Row = 541, Col = 2, Data = e2ba00c5
|
# tb_core.u_sdram32 : at time 37913.0 ns READ : Bank = 3 Row = 541, Col = 2, Data = e2ba00c5
|
# READ STATUS: Burst-No: 0 Addr: 0021dc06 Rxd: b46afc68
|
# READ STATUS: Burst-No: 0 Addr: 0021dc06 Rxd: b46afc68
|
# tb_core.u_sdram32 : at time 37323.0 ns READ : Bank = 3 Row = 541, Col = 3, Data = ff202efe
|
# tb_core.u_sdram32 : at time 37923.0 ns READ : Bank = 3 Row = 541, Col = 3, Data = ff202efe
|
# READ STATUS: Burst-No: 1 Addr: 0021dc08 Rxd: e2ba00c5
|
# READ STATUS: Burst-No: 1 Addr: 0021dc08 Rxd: e2ba00c5
|
# tb_core.u_sdram32 : at time 37333.0 ns READ : Bank = 3 Row = 541, Col = 4, Data = 1b0f0d36
|
# tb_core.u_sdram32 : at time 37933.0 ns READ : Bank = 3 Row = 541, Col = 4, Data = 1b0f0d36
|
# READ STATUS: Burst-No: 2 Addr: 0021dc0a Rxd: ff202efe
|
# READ STATUS: Burst-No: 2 Addr: 0021dc0a Rxd: ff202efe
|
# tb_core.u_sdram32 : at time 37343.0 ns READ : Bank = 3 Row = 541, Col = 5, Data = 799f09f3
|
# tb_core.u_sdram32 : at time 37943.0 ns READ : Bank = 3 Row = 541, Col = 5, Data = 799f09f3
|
# READ STATUS: Burst-No: 3 Addr: 0021dc0c Rxd: 1b0f0d36
|
# READ STATUS: Burst-No: 3 Addr: 0021dc0c Rxd: 1b0f0d36
|
# tb_core.u_sdram32 : at time 37353.0 ns READ : Bank = 3 Row = 541, Col = 6, Data = 7dddabfb
|
# tb_core.u_sdram32 : at time 37953.0 ns READ : Bank = 3 Row = 541, Col = 6, Data = 7dddabfb
|
# READ STATUS: Burst-No: 4 Addr: 0021dc0e Rxd: 799f09f3
|
# READ STATUS: Burst-No: 4 Addr: 0021dc0e Rxd: 799f09f3
|
# tb_core.u_sdram32 : at time 37363.0 ns READ : Bank = 3 Row = 541, Col = 7, Data = b58d7c6b
|
# tb_core.u_sdram32 : at time 37963.0 ns READ : Bank = 3 Row = 541, Col = 7, Data = b58d7c6b
|
# READ STATUS: Burst-No: 5 Addr: 0021dc10 Rxd: 7dddabfb
|
# READ STATUS: Burst-No: 5 Addr: 0021dc10 Rxd: 7dddabfb
|
# tb_core.u_sdram32 : at time 37373.0 ns READ : Bank = 3 Row = 541, Col = 8, Data = 0bcbbf17
|
# tb_core.u_sdram32 : at time 37973.0 ns READ : Bank = 3 Row = 541, Col = 8, Data = 0bcbbf17
|
# READ STATUS: Burst-No: 6 Addr: 0021dc12 Rxd: b58d7c6b
|
# READ STATUS: Burst-No: 6 Addr: 0021dc12 Rxd: b58d7c6b
|
# tb_core.u_sdram32 : at time 37383.0 ns READ : Bank = 3 Row = 541, Col = 9, Data = 87d0360f
|
# tb_core.u_sdram32 : at time 37983.0 ns READ : Bank = 3 Row = 541, Col = 9, Data = 87d0360f
|
# READ STATUS: Burst-No: 7 Addr: 0021dc14 Rxd: 0bcbbf17
|
# READ STATUS: Burst-No: 7 Addr: 0021dc14 Rxd: 0bcbbf17
|
# tb_core.u_sdram32 : at time 37393.0 ns READ : Bank = 3 Row = 541, Col = 10, Data = 8a47b614
|
# tb_core.u_sdram32 : at time 37993.0 ns READ : Bank = 3 Row = 541, Col = 10, Data = 8a47b614
|
# READ STATUS: Burst-No: 8 Addr: 0021dc16 Rxd: 87d0360f
|
# READ STATUS: Burst-No: 8 Addr: 0021dc16 Rxd: 87d0360f
|
# tb_core.u_sdram32 : at time 37403.0 ns READ : Bank = 3 Row = 541, Col = 11, Data = 1500052a
|
# tb_core.u_sdram32 : at time 38003.0 ns READ : Bank = 3 Row = 541, Col = 11, Data = 1500052a
|
# READ STATUS: Burst-No: 9 Addr: 0021dc18 Rxd: 8a47b614
|
# READ STATUS: Burst-No: 9 Addr: 0021dc18 Rxd: 8a47b614
|
# tb_core.u_sdram32 : at time 37413.0 ns READ : Bank = 3 Row = 541, Col = 12, Data = d3666ea6
|
# tb_core.u_sdram32 : at time 38013.0 ns READ : Bank = 3 Row = 541, Col = 12, Data = d3666ea6
|
# READ STATUS: Burst-No: 10 Addr: 0021dc1a Rxd: 1500052a
|
# READ STATUS: Burst-No: 10 Addr: 0021dc1a Rxd: 1500052a
|
# tb_core.u_sdram32 : at time 37423.0 ns READ : Bank = 3 Row = 541, Col = 13, Data = ea7626d4
|
# tb_core.u_sdram32 : at time 38023.0 ns READ : Bank = 3 Row = 541, Col = 13, Data = ea7626d4
|
# READ STATUS: Burst-No: 11 Addr: 0021dc1c Rxd: d3666ea6
|
# READ STATUS: Burst-No: 11 Addr: 0021dc1c Rxd: d3666ea6
|
# tb_core.u_sdram32 : at time 37433.0 ns READ : Bank = 3 Row = 541, Col = 14, Data = e5ac10cb
|
# tb_core.u_sdram32 : at time 38033.0 ns READ : Bank = 3 Row = 541, Col = 14, Data = e5ac10cb
|
# READ STATUS: Burst-No: 12 Addr: 0021dc1e Rxd: ea7626d4
|
# READ STATUS: Burst-No: 12 Addr: 0021dc1e Rxd: ea7626d4
|
# tb_core.u_sdram32 : at time 37443.0 ns READ : Bank = 3 Row = 541, Col = 15, Data = b587c26b
|
# tb_core.u_sdram32 : at time 38043.0 ns READ : Bank = 3 Row = 541, Col = 15, Data = b587c26b
|
# READ STATUS: Burst-No: 13 Addr: 0021dc20 Rxd: e5ac10cb
|
# READ STATUS: Burst-No: 13 Addr: 0021dc20 Rxd: e5ac10cb
|
# tb_core.u_sdram32 : at time 37453.0 ns READ : Bank = 3 Row = 541, Col = 16, Data = 0277eb04
|
# tb_core.u_sdram32 : at time 38053.0 ns READ : Bank = 3 Row = 541, Col = 16, Data = 0277eb04
|
# READ STATUS: Burst-No: 14 Addr: 0021dc22 Rxd: b587c26b
|
# READ STATUS: Burst-No: 14 Addr: 0021dc22 Rxd: b587c26b
|
# tb_core.u_sdram32 : at time 37463.0 ns READ : Bank = 3 Row = 541, Col = 17, Data = fa4832f4
|
# tb_core.u_sdram32 : at time 38063.0 ns READ : Bank = 3 Row = 541, Col = 17, Data = fa4832f4
|
# tb_core.u_sdram32 : at time 37467.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 38067.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 15 Addr: 0021dc24 Rxd: 0277eb04
|
# READ STATUS: Burst-No: 15 Addr: 0021dc24 Rxd: 0277eb04
|
# tb_core.u_sdram32 : at time 37473.0 ns READ : Bank = 3 Row = 541, Col = 18, Data = 468b618d
|
# tb_core.u_sdram32 : at time 38073.0 ns READ : Bank = 3 Row = 541, Col = 18, Data = 468b618d
|
# READ STATUS: Burst-No: 16 Addr: 0021dc26 Rxd: fa4832f4
|
# READ STATUS: Burst-No: 16 Addr: 0021dc26 Rxd: fa4832f4
|
# tb_core.u_sdram32 : at time 37483.0 ns READ : Bank = 3 Row = 541, Col = 19, Data = f0ea70e1
|
# tb_core.u_sdram32 : at time 38083.0 ns READ : Bank = 3 Row = 541, Col = 19, Data = f0ea70e1
|
# READ STATUS: Burst-No: 17 Addr: 0021dc28 Rxd: 468b618d
|
# READ STATUS: Burst-No: 17 Addr: 0021dc28 Rxd: 468b618d
|
# READ STATUS: Burst-No: 18 Addr: 0021dc2a Rxd: f0ea70e1
|
# READ STATUS: Burst-No: 18 Addr: 0021dc2a Rxd: f0ea70e1
|
# Write Address: 0023bd85, Burst Size: 58
|
# Write Address: 0023bd85, Burst Size: 58
|
# tb_core.u_sdram32 : at time 37657.0 ns ACT : Bank = 3 Row = 571
|
# tb_core.u_sdram32 : at time 38257.0 ns ACT : Bank = 3 Row = 571
|
# tb_core.u_sdram32 : at time 37687.0 ns WRITE: Bank = 3 Row = 571, Col = 97, Data = e4df16c9
|
# tb_core.u_sdram32 : at time 38287.0 ns WRITE: Bank = 3 Row = 571, Col = 97, Data = e4df16c9
|
# Status: Burst-No: 0 Write Address: 0023bd85 WriteData: e4df16c9
|
# Status: Burst-No: 0 Write Address: 0023bd85 WriteData: e4df16c9
|
# tb_core.u_sdram32 : at time 37697.0 ns WRITE: Bank = 3 Row = 571, Col = 98, Data = b05f8e60
|
# tb_core.u_sdram32 : at time 38297.0 ns WRITE: Bank = 3 Row = 571, Col = 98, Data = b05f8e60
|
# Status: Burst-No: 1 Write Address: 0023bd85 WriteData: b05f8e60
|
# Status: Burst-No: 1 Write Address: 0023bd85 WriteData: b05f8e60
|
# tb_core.u_sdram32 : at time 37707.0 ns WRITE: Bank = 3 Row = 571, Col = 99, Data = a3643246
|
# tb_core.u_sdram32 : at time 38307.0 ns WRITE: Bank = 3 Row = 571, Col = 99, Data = a3643246
|
# Status: Burst-No: 2 Write Address: 0023bd85 WriteData: a3643246
|
# Status: Burst-No: 2 Write Address: 0023bd85 WriteData: a3643246
|
# tb_core.u_sdram32 : at time 37717.0 ns WRITE: Bank = 3 Row = 571, Col = 100, Data = 1e74cb3c
|
# tb_core.u_sdram32 : at time 38317.0 ns WRITE: Bank = 3 Row = 571, Col = 100, Data = 1e74cb3c
|
# Status: Burst-No: 3 Write Address: 0023bd85 WriteData: 1e74cb3c
|
# Status: Burst-No: 3 Write Address: 0023bd85 WriteData: 1e74cb3c
|
# tb_core.u_sdram32 : at time 37727.0 ns WRITE: Bank = 3 Row = 571, Col = 101, Data = 1b855f37
|
# tb_core.u_sdram32 : at time 38327.0 ns WRITE: Bank = 3 Row = 571, Col = 101, Data = 1b855f37
|
# Status: Burst-No: 4 Write Address: 0023bd85 WriteData: 1b855f37
|
# Status: Burst-No: 4 Write Address: 0023bd85 WriteData: 1b855f37
|
# tb_core.u_sdram32 : at time 37737.0 ns WRITE: Bank = 3 Row = 571, Col = 102, Data = 2c0c5558
|
# tb_core.u_sdram32 : at time 38337.0 ns WRITE: Bank = 3 Row = 571, Col = 102, Data = 2c0c5558
|
# Status: Burst-No: 5 Write Address: 0023bd85 WriteData: 2c0c5558
|
# Status: Burst-No: 5 Write Address: 0023bd85 WriteData: 2c0c5558
|
# tb_core.u_sdram32 : at time 37747.0 ns WRITE: Bank = 3 Row = 571, Col = 103, Data = 39d65773
|
# tb_core.u_sdram32 : at time 38347.0 ns WRITE: Bank = 3 Row = 571, Col = 103, Data = 39d65773
|
# Status: Burst-No: 6 Write Address: 0023bd85 WriteData: 39d65773
|
# Status: Burst-No: 6 Write Address: 0023bd85 WriteData: 39d65773
|
# tb_core.u_sdram32 : at time 37757.0 ns WRITE: Bank = 3 Row = 571, Col = 104, Data = 8778d20e
|
# tb_core.u_sdram32 : at time 38357.0 ns WRITE: Bank = 3 Row = 571, Col = 104, Data = 8778d20e
|
# Status: Burst-No: 7 Write Address: 0023bd85 WriteData: 8778d20e
|
# Status: Burst-No: 7 Write Address: 0023bd85 WriteData: 8778d20e
|
# tb_core.u_sdram32 : at time 37767.0 ns WRITE: Bank = 3 Row = 571, Col = 105, Data = 6e6d23dc
|
# tb_core.u_sdram32 : at time 38367.0 ns WRITE: Bank = 3 Row = 571, Col = 105, Data = 6e6d23dc
|
# Status: Burst-No: 8 Write Address: 0023bd85 WriteData: 6e6d23dc
|
# Status: Burst-No: 8 Write Address: 0023bd85 WriteData: 6e6d23dc
|
# tb_core.u_sdram32 : at time 37777.0 ns WRITE: Bank = 3 Row = 571, Col = 106, Data = 183fc330
|
# tb_core.u_sdram32 : at time 38377.0 ns WRITE: Bank = 3 Row = 571, Col = 106, Data = 183fc330
|
# Status: Burst-No: 9 Write Address: 0023bd85 WriteData: 183fc330
|
# Status: Burst-No: 9 Write Address: 0023bd85 WriteData: 183fc330
|
# tb_core.u_sdram32 : at time 37787.0 ns WRITE: Bank = 3 Row = 571, Col = 107, Data = 6845f5d0
|
# tb_core.u_sdram32 : at time 38387.0 ns WRITE: Bank = 3 Row = 571, Col = 107, Data = 6845f5d0
|
# Status: Burst-No: 10 Write Address: 0023bd85 WriteData: 6845f5d0
|
# Status: Burst-No: 10 Write Address: 0023bd85 WriteData: 6845f5d0
|
# tb_core.u_sdram32 : at time 37797.0 ns WRITE: Bank = 3 Row = 571, Col = 108, Data = 0073e500
|
# tb_core.u_sdram32 : at time 38397.0 ns WRITE: Bank = 3 Row = 571, Col = 108, Data = 0073e500
|
# Status: Burst-No: 11 Write Address: 0023bd85 WriteData: 0073e500
|
# Status: Burst-No: 11 Write Address: 0023bd85 WriteData: 0073e500
|
# tb_core.u_sdram32 : at time 37807.0 ns WRITE: Bank = 3 Row = 571, Col = 109, Data = 21820f43
|
# tb_core.u_sdram32 : at time 38407.0 ns WRITE: Bank = 3 Row = 571, Col = 109, Data = 21820f43
|
# Status: Burst-No: 12 Write Address: 0023bd85 WriteData: 21820f43
|
# Status: Burst-No: 12 Write Address: 0023bd85 WriteData: 21820f43
|
# tb_core.u_sdram32 : at time 37817.0 ns WRITE: Bank = 3 Row = 571, Col = 110, Data = 7c6e91f8
|
# tb_core.u_sdram32 : at time 38417.0 ns WRITE: Bank = 3 Row = 571, Col = 110, Data = 7c6e91f8
|
# Status: Burst-No: 13 Write Address: 0023bd85 WriteData: 7c6e91f8
|
# Status: Burst-No: 13 Write Address: 0023bd85 WriteData: 7c6e91f8
|
# tb_core.u_sdram32 : at time 37827.0 ns WRITE: Bank = 3 Row = 571, Col = 111, Data = d0b99aa1
|
# tb_core.u_sdram32 : at time 38427.0 ns WRITE: Bank = 3 Row = 571, Col = 111, Data = d0b99aa1
|
# Status: Burst-No: 14 Write Address: 0023bd85 WriteData: d0b99aa1
|
# Status: Burst-No: 14 Write Address: 0023bd85 WriteData: d0b99aa1
|
# tb_core.u_sdram32 : at time 37837.0 ns WRITE: Bank = 3 Row = 571, Col = 112, Data = 29c01f53
|
# tb_core.u_sdram32 : at time 38437.0 ns WRITE: Bank = 3 Row = 571, Col = 112, Data = 29c01f53
|
# Status: Burst-No: 15 Write Address: 0023bd85 WriteData: 29c01f53
|
# Status: Burst-No: 15 Write Address: 0023bd85 WriteData: 29c01f53
|
# tb_core.u_sdram32 : at time 37847.0 ns WRITE: Bank = 3 Row = 571, Col = 113, Data = 4c588f98
|
# tb_core.u_sdram32 : at time 38447.0 ns WRITE: Bank = 3 Row = 571, Col = 113, Data = 4c588f98
|
# Status: Burst-No: 16 Write Address: 0023bd85 WriteData: 4c588f98
|
# Status: Burst-No: 16 Write Address: 0023bd85 WriteData: 4c588f98
|
# tb_core.u_sdram32 : at time 37857.0 ns WRITE: Bank = 3 Row = 571, Col = 114, Data = 2fef3d5f
|
# tb_core.u_sdram32 : at time 38457.0 ns WRITE: Bank = 3 Row = 571, Col = 114, Data = 2fef3d5f
|
# Status: Burst-No: 17 Write Address: 0023bd85 WriteData: 2fef3d5f
|
# Status: Burst-No: 17 Write Address: 0023bd85 WriteData: 2fef3d5f
|
# tb_core.u_sdram32 : at time 37867.0 ns WRITE: Bank = 3 Row = 571, Col = 115, Data = c3be9287
|
# tb_core.u_sdram32 : at time 38467.0 ns WRITE: Bank = 3 Row = 571, Col = 115, Data = c3be9287
|
# Status: Burst-No: 18 Write Address: 0023bd85 WriteData: c3be9287
|
# Status: Burst-No: 18 Write Address: 0023bd85 WriteData: c3be9287
|
# tb_core.u_sdram32 : at time 37877.0 ns WRITE: Bank = 3 Row = 571, Col = 116, Data = fd5f5afa
|
# tb_core.u_sdram32 : at time 38477.0 ns WRITE: Bank = 3 Row = 571, Col = 116, Data = fd5f5afa
|
# Status: Burst-No: 19 Write Address: 0023bd85 WriteData: fd5f5afa
|
# Status: Burst-No: 19 Write Address: 0023bd85 WriteData: fd5f5afa
|
# tb_core.u_sdram32 : at time 37887.0 ns WRITE: Bank = 3 Row = 571, Col = 117, Data = 1699d12d
|
# tb_core.u_sdram32 : at time 38487.0 ns WRITE: Bank = 3 Row = 571, Col = 117, Data = 1699d12d
|
# Status: Burst-No: 20 Write Address: 0023bd85 WriteData: 1699d12d
|
# Status: Burst-No: 20 Write Address: 0023bd85 WriteData: 1699d12d
|
# tb_core.u_sdram32 : at time 37897.0 ns WRITE: Bank = 3 Row = 571, Col = 118, Data = b8760270
|
# tb_core.u_sdram32 : at time 38497.0 ns WRITE: Bank = 3 Row = 571, Col = 118, Data = b8760270
|
# Status: Burst-No: 21 Write Address: 0023bd85 WriteData: b8760270
|
# Status: Burst-No: 21 Write Address: 0023bd85 WriteData: b8760270
|
# tb_core.u_sdram32 : at time 37907.0 ns WRITE: Bank = 3 Row = 571, Col = 119, Data = b5b4e86b
|
# tb_core.u_sdram32 : at time 38507.0 ns WRITE: Bank = 3 Row = 571, Col = 119, Data = b5b4e86b
|
# Status: Burst-No: 22 Write Address: 0023bd85 WriteData: b5b4e86b
|
# Status: Burst-No: 22 Write Address: 0023bd85 WriteData: b5b4e86b
|
# tb_core.u_sdram32 : at time 37917.0 ns WRITE: Bank = 3 Row = 571, Col = 120, Data = 98d73831
|
# tb_core.u_sdram32 : at time 38517.0 ns WRITE: Bank = 3 Row = 571, Col = 120, Data = 98d73831
|
# Status: Burst-No: 23 Write Address: 0023bd85 WriteData: 98d73831
|
# Status: Burst-No: 23 Write Address: 0023bd85 WriteData: 98d73831
|
# tb_core.u_sdram32 : at time 37927.0 ns WRITE: Bank = 3 Row = 571, Col = 121, Data = 892fc012
|
# tb_core.u_sdram32 : at time 38527.0 ns WRITE: Bank = 3 Row = 571, Col = 121, Data = 892fc012
|
# Status: Burst-No: 24 Write Address: 0023bd85 WriteData: 892fc012
|
# Status: Burst-No: 24 Write Address: 0023bd85 WriteData: 892fc012
|
# tb_core.u_sdram32 : at time 37937.0 ns WRITE: Bank = 3 Row = 571, Col = 122, Data = 0650df0c
|
# tb_core.u_sdram32 : at time 38537.0 ns WRITE: Bank = 3 Row = 571, Col = 122, Data = 0650df0c
|
# Status: Burst-No: 25 Write Address: 0023bd85 WriteData: 0650df0c
|
# Status: Burst-No: 25 Write Address: 0023bd85 WriteData: 0650df0c
|
# tb_core.u_sdram32 : at time 37947.0 ns WRITE: Bank = 3 Row = 571, Col = 123, Data = 06db6b0d
|
# tb_core.u_sdram32 : at time 38547.0 ns WRITE: Bank = 3 Row = 571, Col = 123, Data = 06db6b0d
|
# Status: Burst-No: 26 Write Address: 0023bd85 WriteData: 06db6b0d
|
# Status: Burst-No: 26 Write Address: 0023bd85 WriteData: 06db6b0d
|
# tb_core.u_sdram32 : at time 37957.0 ns WRITE: Bank = 3 Row = 571, Col = 124, Data = 0acd1315
|
# tb_core.u_sdram32 : at time 38557.0 ns WRITE: Bank = 3 Row = 571, Col = 124, Data = 0acd1315
|
# Status: Burst-No: 27 Write Address: 0023bd85 WriteData: 0acd1315
|
# Status: Burst-No: 27 Write Address: 0023bd85 WriteData: 0acd1315
|
# tb_core.u_sdram32 : at time 37967.0 ns WRITE: Bank = 3 Row = 571, Col = 125, Data = 20310740
|
# tb_core.u_sdram32 : at time 38567.0 ns WRITE: Bank = 3 Row = 571, Col = 125, Data = 20310740
|
# Status: Burst-No: 28 Write Address: 0023bd85 WriteData: 20310740
|
# Status: Burst-No: 28 Write Address: 0023bd85 WriteData: 20310740
|
# tb_core.u_sdram32 : at time 37977.0 ns WRITE: Bank = 3 Row = 571, Col = 126, Data = 4a638d94
|
# tb_core.u_sdram32 : at time 38577.0 ns WRITE: Bank = 3 Row = 571, Col = 126, Data = 4a638d94
|
# Status: Burst-No: 29 Write Address: 0023bd85 WriteData: 4a638d94
|
# Status: Burst-No: 29 Write Address: 0023bd85 WriteData: 4a638d94
|
# tb_core.u_sdram32 : at time 37987.0 ns WRITE: Bank = 3 Row = 571, Col = 127, Data = 2a1ba354
|
# tb_core.u_sdram32 : at time 38587.0 ns WRITE: Bank = 3 Row = 571, Col = 127, Data = 2a1ba354
|
# Status: Burst-No: 30 Write Address: 0023bd85 WriteData: 2a1ba354
|
# Status: Burst-No: 30 Write Address: 0023bd85 WriteData: 2a1ba354
|
# tb_core.u_sdram32 : at time 37997.0 ns WRITE: Bank = 3 Row = 571, Col = 128, Data = c0620280
|
# tb_core.u_sdram32 : at time 38597.0 ns WRITE: Bank = 3 Row = 571, Col = 128, Data = c0620280
|
# Status: Burst-No: 31 Write Address: 0023bd85 WriteData: c0620280
|
# Status: Burst-No: 31 Write Address: 0023bd85 WriteData: c0620280
|
# tb_core.u_sdram32 : at time 38007.0 ns WRITE: Bank = 3 Row = 571, Col = 129, Data = 098d1513
|
# tb_core.u_sdram32 : at time 38607.0 ns WRITE: Bank = 3 Row = 571, Col = 129, Data = 098d1513
|
# Status: Burst-No: 32 Write Address: 0023bd85 WriteData: 098d1513
|
# Status: Burst-No: 32 Write Address: 0023bd85 WriteData: 098d1513
|
# tb_core.u_sdram32 : at time 38017.0 ns WRITE: Bank = 3 Row = 571, Col = 130, Data = e1e386c3
|
# tb_core.u_sdram32 : at time 38617.0 ns WRITE: Bank = 3 Row = 571, Col = 130, Data = e1e386c3
|
# Status: Burst-No: 33 Write Address: 0023bd85 WriteData: e1e386c3
|
# Status: Burst-No: 33 Write Address: 0023bd85 WriteData: e1e386c3
|
# tb_core.u_sdram32 : at time 38027.0 ns WRITE: Bank = 3 Row = 571, Col = 131, Data = f695deed
|
# tb_core.u_sdram32 : at time 38627.0 ns WRITE: Bank = 3 Row = 571, Col = 131, Data = f695deed
|
# Status: Burst-No: 34 Write Address: 0023bd85 WriteData: f695deed
|
# Status: Burst-No: 34 Write Address: 0023bd85 WriteData: f695deed
|
# tb_core.u_sdram32 : at time 38037.0 ns WRITE: Bank = 3 Row = 571, Col = 132, Data = ee4ee6dc
|
# tb_core.u_sdram32 : at time 38637.0 ns WRITE: Bank = 3 Row = 571, Col = 132, Data = ee4ee6dc
|
# Status: Burst-No: 35 Write Address: 0023bd85 WriteData: ee4ee6dc
|
# Status: Burst-No: 35 Write Address: 0023bd85 WriteData: ee4ee6dc
|
# tb_core.u_sdram32 : at time 38047.0 ns WRITE: Bank = 3 Row = 571, Col = 133, Data = bc781078
|
# tb_core.u_sdram32 : at time 38647.0 ns WRITE: Bank = 3 Row = 571, Col = 133, Data = bc781078
|
# Status: Burst-No: 36 Write Address: 0023bd85 WriteData: bc781078
|
# Status: Burst-No: 36 Write Address: 0023bd85 WriteData: bc781078
|
# tb_core.u_sdram32 : at time 38057.0 ns WRITE: Bank = 3 Row = 571, Col = 134, Data = 13d40d27
|
# tb_core.u_sdram32 : at time 38657.0 ns WRITE: Bank = 3 Row = 571, Col = 134, Data = 13d40d27
|
# Status: Burst-No: 37 Write Address: 0023bd85 WriteData: 13d40d27
|
# Status: Burst-No: 37 Write Address: 0023bd85 WriteData: 13d40d27
|
# tb_core.u_sdram32 : at time 38067.0 ns WRITE: Bank = 3 Row = 571, Col = 135, Data = afed265f
|
# tb_core.u_sdram32 : at time 38667.0 ns WRITE: Bank = 3 Row = 571, Col = 135, Data = afed265f
|
# Status: Burst-No: 38 Write Address: 0023bd85 WriteData: afed265f
|
# Status: Burst-No: 38 Write Address: 0023bd85 WriteData: afed265f
|
# tb_core.u_sdram32 : at time 38077.0 ns WRITE: Bank = 3 Row = 571, Col = 136, Data = 11c05b23
|
# tb_core.u_sdram32 : at time 38677.0 ns WRITE: Bank = 3 Row = 571, Col = 136, Data = 11c05b23
|
# Status: Burst-No: 39 Write Address: 0023bd85 WriteData: 11c05b23
|
# Status: Burst-No: 39 Write Address: 0023bd85 WriteData: 11c05b23
|
# tb_core.u_sdram32 : at time 38087.0 ns WRITE: Bank = 3 Row = 571, Col = 137, Data = 5596ebab
|
# tb_core.u_sdram32 : at time 38687.0 ns WRITE: Bank = 3 Row = 571, Col = 137, Data = 5596ebab
|
# Status: Burst-No: 40 Write Address: 0023bd85 WriteData: 5596ebab
|
# Status: Burst-No: 40 Write Address: 0023bd85 WriteData: 5596ebab
|
# tb_core.u_sdram32 : at time 38097.0 ns WRITE: Bank = 3 Row = 571, Col = 138, Data = 1c421738
|
# tb_core.u_sdram32 : at time 38697.0 ns WRITE: Bank = 3 Row = 571, Col = 138, Data = 1c421738
|
# Status: Burst-No: 41 Write Address: 0023bd85 WriteData: 1c421738
|
# Status: Burst-No: 41 Write Address: 0023bd85 WriteData: 1c421738
|
# tb_core.u_sdram32 : at time 38107.0 ns WRITE: Bank = 3 Row = 571, Col = 139, Data = 11534d22
|
# tb_core.u_sdram32 : at time 38707.0 ns WRITE: Bank = 3 Row = 571, Col = 139, Data = 11534d22
|
# Status: Burst-No: 42 Write Address: 0023bd85 WriteData: 11534d22
|
# Status: Burst-No: 42 Write Address: 0023bd85 WriteData: 11534d22
|
# tb_core.u_sdram32 : at time 38117.0 ns WRITE: Bank = 3 Row = 571, Col = 140, Data = 64f2bdc9
|
# tb_core.u_sdram32 : at time 38717.0 ns WRITE: Bank = 3 Row = 571, Col = 140, Data = 64f2bdc9
|
# Status: Burst-No: 43 Write Address: 0023bd85 WriteData: 64f2bdc9
|
# Status: Burst-No: 43 Write Address: 0023bd85 WriteData: 64f2bdc9
|
# tb_core.u_sdram32 : at time 38127.0 ns WRITE: Bank = 3 Row = 571, Col = 141, Data = e3eb4cc7
|
# tb_core.u_sdram32 : at time 38727.0 ns WRITE: Bank = 3 Row = 571, Col = 141, Data = e3eb4cc7
|
# Status: Burst-No: 44 Write Address: 0023bd85 WriteData: e3eb4cc7
|
# Status: Burst-No: 44 Write Address: 0023bd85 WriteData: e3eb4cc7
|
# tb_core.u_sdram32 : at time 38137.0 ns WRITE: Bank = 3 Row = 571, Col = 142, Data = c1406282
|
# tb_core.u_sdram32 : at time 38737.0 ns WRITE: Bank = 3 Row = 571, Col = 142, Data = c1406282
|
# Status: Burst-No: 45 Write Address: 0023bd85 WriteData: c1406282
|
# Status: Burst-No: 45 Write Address: 0023bd85 WriteData: c1406282
|
# tb_core.u_sdram32 : at time 38147.0 ns WRITE: Bank = 3 Row = 571, Col = 143, Data = 6754d7ce
|
# tb_core.u_sdram32 : at time 38747.0 ns WRITE: Bank = 3 Row = 571, Col = 143, Data = 6754d7ce
|
# Status: Burst-No: 46 Write Address: 0023bd85 WriteData: 6754d7ce
|
# Status: Burst-No: 46 Write Address: 0023bd85 WriteData: 6754d7ce
|
# tb_core.u_sdram32 : at time 38157.0 ns WRITE: Bank = 3 Row = 571, Col = 144, Data = e38e22c7
|
# tb_core.u_sdram32 : at time 38757.0 ns WRITE: Bank = 3 Row = 571, Col = 144, Data = e38e22c7
|
# Status: Burst-No: 47 Write Address: 0023bd85 WriteData: e38e22c7
|
# Status: Burst-No: 47 Write Address: 0023bd85 WriteData: e38e22c7
|
# tb_core.u_sdram32 : at time 38167.0 ns WRITE: Bank = 3 Row = 571, Col = 145, Data = 927fa424
|
# tb_core.u_sdram32 : at time 38767.0 ns WRITE: Bank = 3 Row = 571, Col = 145, Data = 927fa424
|
# Status: Burst-No: 48 Write Address: 0023bd85 WriteData: 927fa424
|
# Status: Burst-No: 48 Write Address: 0023bd85 WriteData: 927fa424
|
# tb_core.u_sdram32 : at time 38177.0 ns WRITE: Bank = 3 Row = 571, Col = 146, Data = 6da36fdb
|
# tb_core.u_sdram32 : at time 38777.0 ns WRITE: Bank = 3 Row = 571, Col = 146, Data = 6da36fdb
|
# Status: Burst-No: 49 Write Address: 0023bd85 WriteData: 6da36fdb
|
# Status: Burst-No: 49 Write Address: 0023bd85 WriteData: 6da36fdb
|
# tb_core.u_sdram32 : at time 38187.0 ns WRITE: Bank = 3 Row = 571, Col = 147, Data = 84651408
|
# tb_core.u_sdram32 : at time 38787.0 ns WRITE: Bank = 3 Row = 571, Col = 147, Data = 84651408
|
# Status: Burst-No: 50 Write Address: 0023bd85 WriteData: 84651408
|
# Status: Burst-No: 50 Write Address: 0023bd85 WriteData: 84651408
|
# tb_core.u_sdram32 : at time 38197.0 ns WRITE: Bank = 3 Row = 571, Col = 148, Data = 3ac26f75
|
# tb_core.u_sdram32 : at time 38797.0 ns WRITE: Bank = 3 Row = 571, Col = 148, Data = 3ac26f75
|
# Status: Burst-No: 51 Write Address: 0023bd85 WriteData: 3ac26f75
|
# Status: Burst-No: 51 Write Address: 0023bd85 WriteData: 3ac26f75
|
# tb_core.u_sdram32 : at time 38207.0 ns WRITE: Bank = 3 Row = 571, Col = 149, Data = 5ad31db5
|
# tb_core.u_sdram32 : at time 38807.0 ns WRITE: Bank = 3 Row = 571, Col = 149, Data = 5ad31db5
|
# Status: Burst-No: 52 Write Address: 0023bd85 WriteData: 5ad31db5
|
# Status: Burst-No: 52 Write Address: 0023bd85 WriteData: 5ad31db5
|
# tb_core.u_sdram32 : at time 38217.0 ns WRITE: Bank = 3 Row = 571, Col = 150, Data = 8d7d721a
|
# tb_core.u_sdram32 : at time 38817.0 ns WRITE: Bank = 3 Row = 571, Col = 150, Data = 8d7d721a
|
# Status: Burst-No: 53 Write Address: 0023bd85 WriteData: 8d7d721a
|
# Status: Burst-No: 53 Write Address: 0023bd85 WriteData: 8d7d721a
|
# tb_core.u_sdram32 : at time 38227.0 ns WRITE: Bank = 3 Row = 571, Col = 151, Data = 1c2a1338
|
# tb_core.u_sdram32 : at time 38827.0 ns WRITE: Bank = 3 Row = 571, Col = 151, Data = 1c2a1338
|
# Status: Burst-No: 54 Write Address: 0023bd85 WriteData: 1c2a1338
|
# Status: Burst-No: 54 Write Address: 0023bd85 WriteData: 1c2a1338
|
# tb_core.u_sdram32 : at time 38237.0 ns WRITE: Bank = 3 Row = 571, Col = 152, Data = c1233a82
|
# tb_core.u_sdram32 : at time 38837.0 ns WRITE: Bank = 3 Row = 571, Col = 152, Data = c1233a82
|
# Status: Burst-No: 55 Write Address: 0023bd85 WriteData: c1233a82
|
# Status: Burst-No: 55 Write Address: 0023bd85 WriteData: c1233a82
|
# tb_core.u_sdram32 : at time 38247.0 ns WRITE: Bank = 3 Row = 571, Col = 153, Data = ac05a058
|
# tb_core.u_sdram32 : at time 38847.0 ns WRITE: Bank = 3 Row = 571, Col = 153, Data = ac05a058
|
# Status: Burst-No: 56 Write Address: 0023bd85 WriteData: ac05a058
|
# Status: Burst-No: 56 Write Address: 0023bd85 WriteData: ac05a058
|
# tb_core.u_sdram32 : at time 38257.0 ns WRITE: Bank = 3 Row = 571, Col = 154, Data = a85a6a50
|
# tb_core.u_sdram32 : at time 38857.0 ns WRITE: Bank = 3 Row = 571, Col = 154, Data = a85a6a50
|
# Status: Burst-No: 57 Write Address: 0023bd85 WriteData: a85a6a50
|
# Status: Burst-No: 57 Write Address: 0023bd85 WriteData: a85a6a50
|
# tb_core.u_sdram32 : at time 38267.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 38867.0 ns BST : Burst Terminate
|
# Write Address: 00089aa3, Burst Size: 37
|
# Write Address: 00089aa3, Burst Size: 37
|
# tb_core.u_sdram32 : at time 38407.0 ns ACT : Bank = 2 Row = 137
|
# tb_core.u_sdram32 : at time 39007.0 ns ACT : Bank = 2 Row = 137
|
# tb_core.u_sdram32 : at time 38437.0 ns WRITE: Bank = 2 Row = 137, Col = 168, Data = 32c3df65
|
# tb_core.u_sdram32 : at time 39037.0 ns WRITE: Bank = 2 Row = 137, Col = 168, Data = 32c3df65
|
# Status: Burst-No: 0 Write Address: 00089aa3 WriteData: 32c3df65
|
# Status: Burst-No: 0 Write Address: 00089aa3 WriteData: 32c3df65
|
# tb_core.u_sdram32 : at time 38447.0 ns WRITE: Bank = 2 Row = 137, Col = 169, Data = 753c17ea
|
# tb_core.u_sdram32 : at time 39047.0 ns WRITE: Bank = 2 Row = 137, Col = 169, Data = 753c17ea
|
# Status: Burst-No: 1 Write Address: 00089aa3 WriteData: 753c17ea
|
# Status: Burst-No: 1 Write Address: 00089aa3 WriteData: 753c17ea
|
# tb_core.u_sdram32 : at time 38457.0 ns WRITE: Bank = 2 Row = 137, Col = 170, Data = 03703906
|
# tb_core.u_sdram32 : at time 39057.0 ns WRITE: Bank = 2 Row = 137, Col = 170, Data = 03703906
|
# Status: Burst-No: 2 Write Address: 00089aa3 WriteData: 03703906
|
# Status: Burst-No: 2 Write Address: 00089aa3 WriteData: 03703906
|
# tb_core.u_sdram32 : at time 38467.0 ns WRITE: Bank = 2 Row = 137, Col = 171, Data = aa138054
|
# tb_core.u_sdram32 : at time 39067.0 ns WRITE: Bank = 2 Row = 137, Col = 171, Data = aa138054
|
# Status: Burst-No: 3 Write Address: 00089aa3 WriteData: aa138054
|
# Status: Burst-No: 3 Write Address: 00089aa3 WriteData: aa138054
|
# tb_core.u_sdram32 : at time 38477.0 ns WRITE: Bank = 2 Row = 137, Col = 172, Data = adf3405b
|
# tb_core.u_sdram32 : at time 39077.0 ns WRITE: Bank = 2 Row = 137, Col = 172, Data = adf3405b
|
# Status: Burst-No: 4 Write Address: 00089aa3 WriteData: adf3405b
|
# Status: Burst-No: 4 Write Address: 00089aa3 WriteData: adf3405b
|
# tb_core.u_sdram32 : at time 38487.0 ns WRITE: Bank = 2 Row = 137, Col = 173, Data = e455f0c8
|
# tb_core.u_sdram32 : at time 39087.0 ns WRITE: Bank = 2 Row = 137, Col = 173, Data = e455f0c8
|
# Status: Burst-No: 5 Write Address: 00089aa3 WriteData: e455f0c8
|
# Status: Burst-No: 5 Write Address: 00089aa3 WriteData: e455f0c8
|
# tb_core.u_sdram32 : at time 38497.0 ns WRITE: Bank = 2 Row = 137, Col = 174, Data = 24673948
|
# tb_core.u_sdram32 : at time 39097.0 ns WRITE: Bank = 2 Row = 137, Col = 174, Data = 24673948
|
# Status: Burst-No: 6 Write Address: 00089aa3 WriteData: 24673948
|
# Status: Burst-No: 6 Write Address: 00089aa3 WriteData: 24673948
|
# tb_core.u_sdram32 : at time 38507.0 ns WRITE: Bank = 2 Row = 137, Col = 175, Data = 9bf8f237
|
# tb_core.u_sdram32 : at time 39107.0 ns WRITE: Bank = 2 Row = 137, Col = 175, Data = 9bf8f237
|
# Status: Burst-No: 7 Write Address: 00089aa3 WriteData: 9bf8f237
|
# Status: Burst-No: 7 Write Address: 00089aa3 WriteData: 9bf8f237
|
# tb_core.u_sdram32 : at time 38517.0 ns WRITE: Bank = 2 Row = 137, Col = 176, Data = 7c1df3f8
|
# tb_core.u_sdram32 : at time 39117.0 ns WRITE: Bank = 2 Row = 137, Col = 176, Data = 7c1df3f8
|
# Status: Burst-No: 8 Write Address: 00089aa3 WriteData: 7c1df3f8
|
# Status: Burst-No: 8 Write Address: 00089aa3 WriteData: 7c1df3f8
|
# tb_core.u_sdram32 : at time 38527.0 ns WRITE: Bank = 2 Row = 137, Col = 177, Data = da8932b5
|
# tb_core.u_sdram32 : at time 39127.0 ns WRITE: Bank = 2 Row = 137, Col = 177, Data = da8932b5
|
# Status: Burst-No: 9 Write Address: 00089aa3 WriteData: da8932b5
|
# Status: Burst-No: 9 Write Address: 00089aa3 WriteData: da8932b5
|
# tb_core.u_sdram32 : at time 38537.0 ns WRITE: Bank = 2 Row = 137, Col = 178, Data = 28d6a951
|
# tb_core.u_sdram32 : at time 39137.0 ns WRITE: Bank = 2 Row = 137, Col = 178, Data = 28d6a951
|
# Status: Burst-No: 10 Write Address: 00089aa3 WriteData: 28d6a951
|
# Status: Burst-No: 10 Write Address: 00089aa3 WriteData: 28d6a951
|
# tb_core.u_sdram32 : at time 38547.0 ns WRITE: Bank = 2 Row = 137, Col = 179, Data = 41aed583
|
# tb_core.u_sdram32 : at time 39147.0 ns WRITE: Bank = 2 Row = 137, Col = 179, Data = 41aed583
|
# Status: Burst-No: 11 Write Address: 00089aa3 WriteData: 41aed583
|
# Status: Burst-No: 11 Write Address: 00089aa3 WriteData: 41aed583
|
# tb_core.u_sdram32 : at time 38557.0 ns WRITE: Bank = 2 Row = 137, Col = 180, Data = 4d9ee39b
|
# tb_core.u_sdram32 : at time 39157.0 ns WRITE: Bank = 2 Row = 137, Col = 180, Data = 4d9ee39b
|
# Status: Burst-No: 12 Write Address: 00089aa3 WriteData: 4d9ee39b
|
# Status: Burst-No: 12 Write Address: 00089aa3 WriteData: 4d9ee39b
|
# tb_core.u_sdram32 : at time 38567.0 ns WRITE: Bank = 2 Row = 137, Col = 181, Data = 1aa0dd35
|
# tb_core.u_sdram32 : at time 39167.0 ns WRITE: Bank = 2 Row = 137, Col = 181, Data = 1aa0dd35
|
# Status: Burst-No: 13 Write Address: 00089aa3 WriteData: 1aa0dd35
|
# Status: Burst-No: 13 Write Address: 00089aa3 WriteData: 1aa0dd35
|
# tb_core.u_sdram32 : at time 38577.0 ns WRITE: Bank = 2 Row = 137, Col = 182, Data = 581653b0
|
# tb_core.u_sdram32 : at time 39177.0 ns WRITE: Bank = 2 Row = 137, Col = 182, Data = 581653b0
|
# Status: Burst-No: 14 Write Address: 00089aa3 WriteData: 581653b0
|
# Status: Burst-No: 14 Write Address: 00089aa3 WriteData: 581653b0
|
# tb_core.u_sdram32 : at time 38587.0 ns WRITE: Bank = 2 Row = 137, Col = 183, Data = fddf82fb
|
# tb_core.u_sdram32 : at time 39187.0 ns WRITE: Bank = 2 Row = 137, Col = 183, Data = fddf82fb
|
# Status: Burst-No: 15 Write Address: 00089aa3 WriteData: fddf82fb
|
# Status: Burst-No: 15 Write Address: 00089aa3 WriteData: fddf82fb
|
# tb_core.u_sdram32 : at time 38597.0 ns WRITE: Bank = 2 Row = 137, Col = 184, Data = 278dbb4f
|
# tb_core.u_sdram32 : at time 39197.0 ns WRITE: Bank = 2 Row = 137, Col = 184, Data = 278dbb4f
|
# Status: Burst-No: 16 Write Address: 00089aa3 WriteData: 278dbb4f
|
# Status: Burst-No: 16 Write Address: 00089aa3 WriteData: 278dbb4f
|
# tb_core.u_sdram32 : at time 38607.0 ns WRITE: Bank = 2 Row = 137, Col = 185, Data = 984da630
|
# tb_core.u_sdram32 : at time 39207.0 ns WRITE: Bank = 2 Row = 137, Col = 185, Data = 984da630
|
# Status: Burst-No: 17 Write Address: 00089aa3 WriteData: 984da630
|
# Status: Burst-No: 17 Write Address: 00089aa3 WriteData: 984da630
|
# tb_core.u_sdram32 : at time 38617.0 ns WRITE: Bank = 2 Row = 137, Col = 186, Data = 8c38c418
|
# tb_core.u_sdram32 : at time 39217.0 ns WRITE: Bank = 2 Row = 137, Col = 186, Data = 8c38c418
|
# Status: Burst-No: 18 Write Address: 00089aa3 WriteData: 8c38c418
|
# Status: Burst-No: 18 Write Address: 00089aa3 WriteData: 8c38c418
|
# tb_core.u_sdram32 : at time 38627.0 ns WRITE: Bank = 2 Row = 137, Col = 187, Data = ee8118dd
|
# tb_core.u_sdram32 : at time 39227.0 ns WRITE: Bank = 2 Row = 137, Col = 187, Data = ee8118dd
|
# Status: Burst-No: 19 Write Address: 00089aa3 WriteData: ee8118dd
|
# Status: Burst-No: 19 Write Address: 00089aa3 WriteData: ee8118dd
|
# tb_core.u_sdram32 : at time 38637.0 ns WRITE: Bank = 2 Row = 137, Col = 188, Data = a36ae846
|
# tb_core.u_sdram32 : at time 39237.0 ns WRITE: Bank = 2 Row = 137, Col = 188, Data = a36ae846
|
# Status: Burst-No: 20 Write Address: 00089aa3 WriteData: a36ae846
|
# Status: Burst-No: 20 Write Address: 00089aa3 WriteData: a36ae846
|
# tb_core.u_sdram32 : at time 38647.0 ns WRITE: Bank = 2 Row = 137, Col = 189, Data = 30e20f61
|
# tb_core.u_sdram32 : at time 39247.0 ns WRITE: Bank = 2 Row = 137, Col = 189, Data = 30e20f61
|
# Status: Burst-No: 21 Write Address: 00089aa3 WriteData: 30e20f61
|
# Status: Burst-No: 21 Write Address: 00089aa3 WriteData: 30e20f61
|
# tb_core.u_sdram32 : at time 38657.0 ns WRITE: Bank = 2 Row = 137, Col = 190, Data = ac974859
|
# tb_core.u_sdram32 : at time 39257.0 ns WRITE: Bank = 2 Row = 137, Col = 190, Data = ac974859
|
# Status: Burst-No: 22 Write Address: 00089aa3 WriteData: ac974859
|
# Status: Burst-No: 22 Write Address: 00089aa3 WriteData: ac974859
|
# tb_core.u_sdram32 : at time 38667.0 ns WRITE: Bank = 2 Row = 137, Col = 191, Data = 2af17355
|
# tb_core.u_sdram32 : at time 39267.0 ns WRITE: Bank = 2 Row = 137, Col = 191, Data = 2af17355
|
# Status: Burst-No: 23 Write Address: 00089aa3 WriteData: 2af17355
|
# Status: Burst-No: 23 Write Address: 00089aa3 WriteData: 2af17355
|
# tb_core.u_sdram32 : at time 38677.0 ns WRITE: Bank = 2 Row = 137, Col = 192, Data = 178b972f
|
# tb_core.u_sdram32 : at time 39277.0 ns WRITE: Bank = 2 Row = 137, Col = 192, Data = 178b972f
|
# Status: Burst-No: 24 Write Address: 00089aa3 WriteData: 178b972f
|
# Status: Burst-No: 24 Write Address: 00089aa3 WriteData: 178b972f
|
# tb_core.u_sdram32 : at time 38687.0 ns WRITE: Bank = 2 Row = 137, Col = 193, Data = 85ce500b
|
# tb_core.u_sdram32 : at time 39287.0 ns WRITE: Bank = 2 Row = 137, Col = 193, Data = 85ce500b
|
# Status: Burst-No: 25 Write Address: 00089aa3 WriteData: 85ce500b
|
# Status: Burst-No: 25 Write Address: 00089aa3 WriteData: 85ce500b
|
# tb_core.u_sdram32 : at time 38697.0 ns WRITE: Bank = 2 Row = 137, Col = 194, Data = ef1deade
|
# tb_core.u_sdram32 : at time 39297.0 ns WRITE: Bank = 2 Row = 137, Col = 194, Data = ef1deade
|
# Status: Burst-No: 26 Write Address: 00089aa3 WriteData: ef1deade
|
# Status: Burst-No: 26 Write Address: 00089aa3 WriteData: ef1deade
|
# tb_core.u_sdram32 : at time 38707.0 ns WRITE: Bank = 2 Row = 137, Col = 195, Data = e9d22cd3
|
# tb_core.u_sdram32 : at time 39307.0 ns WRITE: Bank = 2 Row = 137, Col = 195, Data = e9d22cd3
|
# Status: Burst-No: 27 Write Address: 00089aa3 WriteData: e9d22cd3
|
# Status: Burst-No: 27 Write Address: 00089aa3 WriteData: e9d22cd3
|
# tb_core.u_sdram32 : at time 38717.0 ns WRITE: Bank = 2 Row = 137, Col = 196, Data = 1445b128
|
# tb_core.u_sdram32 : at time 39317.0 ns WRITE: Bank = 2 Row = 137, Col = 196, Data = 1445b128
|
# Status: Burst-No: 28 Write Address: 00089aa3 WriteData: 1445b128
|
# Status: Burst-No: 28 Write Address: 00089aa3 WriteData: 1445b128
|
# tb_core.u_sdram32 : at time 38727.0 ns WRITE: Bank = 2 Row = 137, Col = 197, Data = 74dc69e9
|
# tb_core.u_sdram32 : at time 39327.0 ns WRITE: Bank = 2 Row = 137, Col = 197, Data = 74dc69e9
|
# Status: Burst-No: 29 Write Address: 00089aa3 WriteData: 74dc69e9
|
# Status: Burst-No: 29 Write Address: 00089aa3 WriteData: 74dc69e9
|
# tb_core.u_sdram32 : at time 38737.0 ns WRITE: Bank = 2 Row = 137, Col = 198, Data = 2c577958
|
# tb_core.u_sdram32 : at time 39337.0 ns WRITE: Bank = 2 Row = 137, Col = 198, Data = 2c577958
|
# Status: Burst-No: 30 Write Address: 00089aa3 WriteData: 2c577958
|
# Status: Burst-No: 30 Write Address: 00089aa3 WriteData: 2c577958
|
# tb_core.u_sdram32 : at time 38747.0 ns WRITE: Bank = 2 Row = 137, Col = 199, Data = 6aa4a1d5
|
# tb_core.u_sdram32 : at time 39347.0 ns WRITE: Bank = 2 Row = 137, Col = 199, Data = 6aa4a1d5
|
# Status: Burst-No: 31 Write Address: 00089aa3 WriteData: 6aa4a1d5
|
# Status: Burst-No: 31 Write Address: 00089aa3 WriteData: 6aa4a1d5
|
# tb_core.u_sdram32 : at time 38757.0 ns WRITE: Bank = 2 Row = 137, Col = 200, Data = 61dbe5c3
|
# tb_core.u_sdram32 : at time 39357.0 ns WRITE: Bank = 2 Row = 137, Col = 200, Data = 61dbe5c3
|
# Status: Burst-No: 32 Write Address: 00089aa3 WriteData: 61dbe5c3
|
# Status: Burst-No: 32 Write Address: 00089aa3 WriteData: 61dbe5c3
|
# tb_core.u_sdram32 : at time 38767.0 ns WRITE: Bank = 2 Row = 137, Col = 201, Data = 6a2c13d4
|
# tb_core.u_sdram32 : at time 39367.0 ns WRITE: Bank = 2 Row = 137, Col = 201, Data = 6a2c13d4
|
# Status: Burst-No: 33 Write Address: 00089aa3 WriteData: 6a2c13d4
|
# Status: Burst-No: 33 Write Address: 00089aa3 WriteData: 6a2c13d4
|
# tb_core.u_sdram32 : at time 38777.0 ns WRITE: Bank = 2 Row = 137, Col = 202, Data = 52397da4
|
# tb_core.u_sdram32 : at time 39377.0 ns WRITE: Bank = 2 Row = 137, Col = 202, Data = 52397da4
|
# Status: Burst-No: 34 Write Address: 00089aa3 WriteData: 52397da4
|
# Status: Burst-No: 34 Write Address: 00089aa3 WriteData: 52397da4
|
# tb_core.u_sdram32 : at time 38787.0 ns WRITE: Bank = 2 Row = 137, Col = 203, Data = 3f25ef7e
|
# tb_core.u_sdram32 : at time 39387.0 ns WRITE: Bank = 2 Row = 137, Col = 203, Data = 3f25ef7e
|
# Status: Burst-No: 35 Write Address: 00089aa3 WriteData: 3f25ef7e
|
# Status: Burst-No: 35 Write Address: 00089aa3 WriteData: 3f25ef7e
|
# tb_core.u_sdram32 : at time 38797.0 ns WRITE: Bank = 2 Row = 137, Col = 204, Data = 6b299dd6
|
# tb_core.u_sdram32 : at time 39397.0 ns WRITE: Bank = 2 Row = 137, Col = 204, Data = 6b299dd6
|
# Status: Burst-No: 36 Write Address: 00089aa3 WriteData: 6b299dd6
|
# Status: Burst-No: 36 Write Address: 00089aa3 WriteData: 6b299dd6
|
# tb_core.u_sdram32 : at time 38807.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 39407.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 38943.0 ns READ : Bank = 3 Row = 571, Col = 97, Data = e4df16c9
|
# tb_core.u_sdram32 : at time 39543.0 ns READ : Bank = 3 Row = 571, Col = 97, Data = e4df16c9
|
# tb_core.u_sdram32 : at time 38953.0 ns READ : Bank = 3 Row = 571, Col = 98, Data = b05f8e60
|
# tb_core.u_sdram32 : at time 39553.0 ns READ : Bank = 3 Row = 571, Col = 98, Data = b05f8e60
|
# READ STATUS: Burst-No: 0 Addr: 0023bd85 Rxd: e4df16c9
|
# READ STATUS: Burst-No: 0 Addr: 0023bd85 Rxd: e4df16c9
|
# tb_core.u_sdram32 : at time 38963.0 ns READ : Bank = 3 Row = 571, Col = 99, Data = a3643246
|
# tb_core.u_sdram32 : at time 39563.0 ns READ : Bank = 3 Row = 571, Col = 99, Data = a3643246
|
# READ STATUS: Burst-No: 1 Addr: 0023bd87 Rxd: b05f8e60
|
# READ STATUS: Burst-No: 1 Addr: 0023bd87 Rxd: b05f8e60
|
# tb_core.u_sdram32 : at time 38973.0 ns READ : Bank = 3 Row = 571, Col = 100, Data = 1e74cb3c
|
# tb_core.u_sdram32 : at time 39573.0 ns READ : Bank = 3 Row = 571, Col = 100, Data = 1e74cb3c
|
# READ STATUS: Burst-No: 2 Addr: 0023bd89 Rxd: a3643246
|
# READ STATUS: Burst-No: 2 Addr: 0023bd89 Rxd: a3643246
|
# tb_core.u_sdram32 : at time 38983.0 ns READ : Bank = 3 Row = 571, Col = 101, Data = 1b855f37
|
# tb_core.u_sdram32 : at time 39583.0 ns READ : Bank = 3 Row = 571, Col = 101, Data = 1b855f37
|
# READ STATUS: Burst-No: 3 Addr: 0023bd8b Rxd: 1e74cb3c
|
# READ STATUS: Burst-No: 3 Addr: 0023bd8b Rxd: 1e74cb3c
|
# tb_core.u_sdram32 : at time 38993.0 ns READ : Bank = 3 Row = 571, Col = 102, Data = 2c0c5558
|
# tb_core.u_sdram32 : at time 39593.0 ns READ : Bank = 3 Row = 571, Col = 102, Data = 2c0c5558
|
# READ STATUS: Burst-No: 4 Addr: 0023bd8d Rxd: 1b855f37
|
# READ STATUS: Burst-No: 4 Addr: 0023bd8d Rxd: 1b855f37
|
# tb_core.u_sdram32 : at time 39003.0 ns READ : Bank = 3 Row = 571, Col = 103, Data = 39d65773
|
# tb_core.u_sdram32 : at time 39603.0 ns READ : Bank = 3 Row = 571, Col = 103, Data = 39d65773
|
# READ STATUS: Burst-No: 5 Addr: 0023bd8f Rxd: 2c0c5558
|
# READ STATUS: Burst-No: 5 Addr: 0023bd8f Rxd: 2c0c5558
|
# tb_core.u_sdram32 : at time 39013.0 ns READ : Bank = 3 Row = 571, Col = 104, Data = 8778d20e
|
# tb_core.u_sdram32 : at time 39613.0 ns READ : Bank = 3 Row = 571, Col = 104, Data = 8778d20e
|
# READ STATUS: Burst-No: 6 Addr: 0023bd91 Rxd: 39d65773
|
# READ STATUS: Burst-No: 6 Addr: 0023bd91 Rxd: 39d65773
|
# tb_core.u_sdram32 : at time 39023.0 ns READ : Bank = 3 Row = 571, Col = 105, Data = 6e6d23dc
|
# tb_core.u_sdram32 : at time 39623.0 ns READ : Bank = 3 Row = 571, Col = 105, Data = 6e6d23dc
|
# READ STATUS: Burst-No: 7 Addr: 0023bd93 Rxd: 8778d20e
|
# READ STATUS: Burst-No: 7 Addr: 0023bd93 Rxd: 8778d20e
|
# tb_core.u_sdram32 : at time 39033.0 ns READ : Bank = 3 Row = 571, Col = 106, Data = 183fc330
|
# tb_core.u_sdram32 : at time 39633.0 ns READ : Bank = 3 Row = 571, Col = 106, Data = 183fc330
|
# READ STATUS: Burst-No: 8 Addr: 0023bd95 Rxd: 6e6d23dc
|
# READ STATUS: Burst-No: 8 Addr: 0023bd95 Rxd: 6e6d23dc
|
# tb_core.u_sdram32 : at time 39043.0 ns READ : Bank = 3 Row = 571, Col = 107, Data = 6845f5d0
|
# tb_core.u_sdram32 : at time 39643.0 ns READ : Bank = 3 Row = 571, Col = 107, Data = 6845f5d0
|
# READ STATUS: Burst-No: 9 Addr: 0023bd97 Rxd: 183fc330
|
# READ STATUS: Burst-No: 9 Addr: 0023bd97 Rxd: 183fc330
|
# tb_core.u_sdram32 : at time 39053.0 ns READ : Bank = 3 Row = 571, Col = 108, Data = 0073e500
|
# tb_core.u_sdram32 : at time 39653.0 ns READ : Bank = 3 Row = 571, Col = 108, Data = 0073e500
|
# READ STATUS: Burst-No: 10 Addr: 0023bd99 Rxd: 6845f5d0
|
# READ STATUS: Burst-No: 10 Addr: 0023bd99 Rxd: 6845f5d0
|
# tb_core.u_sdram32 : at time 39063.0 ns READ : Bank = 3 Row = 571, Col = 109, Data = 21820f43
|
# tb_core.u_sdram32 : at time 39663.0 ns READ : Bank = 3 Row = 571, Col = 109, Data = 21820f43
|
# READ STATUS: Burst-No: 11 Addr: 0023bd9b Rxd: 0073e500
|
# READ STATUS: Burst-No: 11 Addr: 0023bd9b Rxd: 0073e500
|
# tb_core.u_sdram32 : at time 39073.0 ns READ : Bank = 3 Row = 571, Col = 110, Data = 7c6e91f8
|
# tb_core.u_sdram32 : at time 39673.0 ns READ : Bank = 3 Row = 571, Col = 110, Data = 7c6e91f8
|
# READ STATUS: Burst-No: 12 Addr: 0023bd9d Rxd: 21820f43
|
# READ STATUS: Burst-No: 12 Addr: 0023bd9d Rxd: 21820f43
|
# tb_core.u_sdram32 : at time 39083.0 ns READ : Bank = 3 Row = 571, Col = 111, Data = d0b99aa1
|
# tb_core.u_sdram32 : at time 39683.0 ns READ : Bank = 3 Row = 571, Col = 111, Data = d0b99aa1
|
# READ STATUS: Burst-No: 13 Addr: 0023bd9f Rxd: 7c6e91f8
|
# READ STATUS: Burst-No: 13 Addr: 0023bd9f Rxd: 7c6e91f8
|
# tb_core.u_sdram32 : at time 39093.0 ns READ : Bank = 3 Row = 571, Col = 112, Data = 29c01f53
|
# tb_core.u_sdram32 : at time 39693.0 ns READ : Bank = 3 Row = 571, Col = 112, Data = 29c01f53
|
# READ STATUS: Burst-No: 14 Addr: 0023bda1 Rxd: d0b99aa1
|
# READ STATUS: Burst-No: 14 Addr: 0023bda1 Rxd: d0b99aa1
|
# tb_core.u_sdram32 : at time 39103.0 ns READ : Bank = 3 Row = 571, Col = 113, Data = 4c588f98
|
# tb_core.u_sdram32 : at time 39703.0 ns READ : Bank = 3 Row = 571, Col = 113, Data = 4c588f98
|
# READ STATUS: Burst-No: 15 Addr: 0023bda3 Rxd: 29c01f53
|
# READ STATUS: Burst-No: 15 Addr: 0023bda3 Rxd: 29c01f53
|
# tb_core.u_sdram32 : at time 39113.0 ns READ : Bank = 3 Row = 571, Col = 114, Data = 2fef3d5f
|
# tb_core.u_sdram32 : at time 39713.0 ns READ : Bank = 3 Row = 571, Col = 114, Data = 2fef3d5f
|
# READ STATUS: Burst-No: 16 Addr: 0023bda5 Rxd: 4c588f98
|
# READ STATUS: Burst-No: 16 Addr: 0023bda5 Rxd: 4c588f98
|
# tb_core.u_sdram32 : at time 39123.0 ns READ : Bank = 3 Row = 571, Col = 115, Data = c3be9287
|
# tb_core.u_sdram32 : at time 39723.0 ns READ : Bank = 3 Row = 571, Col = 115, Data = c3be9287
|
# READ STATUS: Burst-No: 17 Addr: 0023bda7 Rxd: 2fef3d5f
|
# READ STATUS: Burst-No: 17 Addr: 0023bda7 Rxd: 2fef3d5f
|
# tb_core.u_sdram32 : at time 39133.0 ns READ : Bank = 3 Row = 571, Col = 116, Data = fd5f5afa
|
# tb_core.u_sdram32 : at time 39733.0 ns READ : Bank = 3 Row = 571, Col = 116, Data = fd5f5afa
|
# READ STATUS: Burst-No: 18 Addr: 0023bda9 Rxd: c3be9287
|
# READ STATUS: Burst-No: 18 Addr: 0023bda9 Rxd: c3be9287
|
# tb_core.u_sdram32 : at time 39143.0 ns READ : Bank = 3 Row = 571, Col = 117, Data = 1699d12d
|
# tb_core.u_sdram32 : at time 39743.0 ns READ : Bank = 3 Row = 571, Col = 117, Data = 1699d12d
|
# READ STATUS: Burst-No: 19 Addr: 0023bdab Rxd: fd5f5afa
|
# READ STATUS: Burst-No: 19 Addr: 0023bdab Rxd: fd5f5afa
|
# tb_core.u_sdram32 : at time 39153.0 ns READ : Bank = 3 Row = 571, Col = 118, Data = b8760270
|
# tb_core.u_sdram32 : at time 39753.0 ns READ : Bank = 3 Row = 571, Col = 118, Data = b8760270
|
# READ STATUS: Burst-No: 20 Addr: 0023bdad Rxd: 1699d12d
|
# READ STATUS: Burst-No: 20 Addr: 0023bdad Rxd: 1699d12d
|
# tb_core.u_sdram32 : at time 39163.0 ns READ : Bank = 3 Row = 571, Col = 119, Data = b5b4e86b
|
# tb_core.u_sdram32 : at time 39763.0 ns READ : Bank = 3 Row = 571, Col = 119, Data = b5b4e86b
|
# READ STATUS: Burst-No: 21 Addr: 0023bdaf Rxd: b8760270
|
# READ STATUS: Burst-No: 21 Addr: 0023bdaf Rxd: b8760270
|
# tb_core.u_sdram32 : at time 39173.0 ns READ : Bank = 3 Row = 571, Col = 120, Data = 98d73831
|
# tb_core.u_sdram32 : at time 39773.0 ns READ : Bank = 3 Row = 571, Col = 120, Data = 98d73831
|
# READ STATUS: Burst-No: 22 Addr: 0023bdb1 Rxd: b5b4e86b
|
# READ STATUS: Burst-No: 22 Addr: 0023bdb1 Rxd: b5b4e86b
|
# tb_core.u_sdram32 : at time 39183.0 ns READ : Bank = 3 Row = 571, Col = 121, Data = 892fc012
|
# tb_core.u_sdram32 : at time 39783.0 ns READ : Bank = 3 Row = 571, Col = 121, Data = 892fc012
|
# READ STATUS: Burst-No: 23 Addr: 0023bdb3 Rxd: 98d73831
|
# READ STATUS: Burst-No: 23 Addr: 0023bdb3 Rxd: 98d73831
|
# tb_core.u_sdram32 : at time 39193.0 ns READ : Bank = 3 Row = 571, Col = 122, Data = 0650df0c
|
# tb_core.u_sdram32 : at time 39793.0 ns READ : Bank = 3 Row = 571, Col = 122, Data = 0650df0c
|
# READ STATUS: Burst-No: 24 Addr: 0023bdb5 Rxd: 892fc012
|
# READ STATUS: Burst-No: 24 Addr: 0023bdb5 Rxd: 892fc012
|
# tb_core.u_sdram32 : at time 39203.0 ns READ : Bank = 3 Row = 571, Col = 123, Data = 06db6b0d
|
# tb_core.u_sdram32 : at time 39803.0 ns READ : Bank = 3 Row = 571, Col = 123, Data = 06db6b0d
|
# READ STATUS: Burst-No: 25 Addr: 0023bdb7 Rxd: 0650df0c
|
# READ STATUS: Burst-No: 25 Addr: 0023bdb7 Rxd: 0650df0c
|
# tb_core.u_sdram32 : at time 39213.0 ns READ : Bank = 3 Row = 571, Col = 124, Data = 0acd1315
|
# tb_core.u_sdram32 : at time 39813.0 ns READ : Bank = 3 Row = 571, Col = 124, Data = 0acd1315
|
# READ STATUS: Burst-No: 26 Addr: 0023bdb9 Rxd: 06db6b0d
|
# READ STATUS: Burst-No: 26 Addr: 0023bdb9 Rxd: 06db6b0d
|
# tb_core.u_sdram32 : at time 39223.0 ns READ : Bank = 3 Row = 571, Col = 125, Data = 20310740
|
# tb_core.u_sdram32 : at time 39823.0 ns READ : Bank = 3 Row = 571, Col = 125, Data = 20310740
|
# READ STATUS: Burst-No: 27 Addr: 0023bdbb Rxd: 0acd1315
|
# READ STATUS: Burst-No: 27 Addr: 0023bdbb Rxd: 0acd1315
|
# tb_core.u_sdram32 : at time 39233.0 ns READ : Bank = 3 Row = 571, Col = 126, Data = 4a638d94
|
# tb_core.u_sdram32 : at time 39833.0 ns READ : Bank = 3 Row = 571, Col = 126, Data = 4a638d94
|
# READ STATUS: Burst-No: 28 Addr: 0023bdbd Rxd: 20310740
|
# READ STATUS: Burst-No: 28 Addr: 0023bdbd Rxd: 20310740
|
# tb_core.u_sdram32 : at time 39243.0 ns READ : Bank = 3 Row = 571, Col = 127, Data = 2a1ba354
|
# tb_core.u_sdram32 : at time 39843.0 ns READ : Bank = 3 Row = 571, Col = 127, Data = 2a1ba354
|
# READ STATUS: Burst-No: 29 Addr: 0023bdbf Rxd: 4a638d94
|
# READ STATUS: Burst-No: 29 Addr: 0023bdbf Rxd: 4a638d94
|
# tb_core.u_sdram32 : at time 39253.0 ns READ : Bank = 3 Row = 571, Col = 128, Data = c0620280
|
# tb_core.u_sdram32 : at time 39853.0 ns READ : Bank = 3 Row = 571, Col = 128, Data = c0620280
|
# READ STATUS: Burst-No: 30 Addr: 0023bdc1 Rxd: 2a1ba354
|
# READ STATUS: Burst-No: 30 Addr: 0023bdc1 Rxd: 2a1ba354
|
# tb_core.u_sdram32 : at time 39263.0 ns READ : Bank = 3 Row = 571, Col = 129, Data = 098d1513
|
# tb_core.u_sdram32 : at time 39863.0 ns READ : Bank = 3 Row = 571, Col = 129, Data = 098d1513
|
# READ STATUS: Burst-No: 31 Addr: 0023bdc3 Rxd: c0620280
|
# READ STATUS: Burst-No: 31 Addr: 0023bdc3 Rxd: c0620280
|
# tb_core.u_sdram32 : at time 39273.0 ns READ : Bank = 3 Row = 571, Col = 130, Data = e1e386c3
|
# tb_core.u_sdram32 : at time 39873.0 ns READ : Bank = 3 Row = 571, Col = 130, Data = e1e386c3
|
# READ STATUS: Burst-No: 32 Addr: 0023bdc5 Rxd: 098d1513
|
# READ STATUS: Burst-No: 32 Addr: 0023bdc5 Rxd: 098d1513
|
# tb_core.u_sdram32 : at time 39283.0 ns READ : Bank = 3 Row = 571, Col = 131, Data = f695deed
|
# tb_core.u_sdram32 : at time 39883.0 ns READ : Bank = 3 Row = 571, Col = 131, Data = f695deed
|
# READ STATUS: Burst-No: 33 Addr: 0023bdc7 Rxd: e1e386c3
|
# READ STATUS: Burst-No: 33 Addr: 0023bdc7 Rxd: e1e386c3
|
# tb_core.u_sdram32 : at time 39293.0 ns READ : Bank = 3 Row = 571, Col = 132, Data = ee4ee6dc
|
# tb_core.u_sdram32 : at time 39893.0 ns READ : Bank = 3 Row = 571, Col = 132, Data = ee4ee6dc
|
# READ STATUS: Burst-No: 34 Addr: 0023bdc9 Rxd: f695deed
|
# READ STATUS: Burst-No: 34 Addr: 0023bdc9 Rxd: f695deed
|
# tb_core.u_sdram32 : at time 39303.0 ns READ : Bank = 3 Row = 571, Col = 133, Data = bc781078
|
# tb_core.u_sdram32 : at time 39903.0 ns READ : Bank = 3 Row = 571, Col = 133, Data = bc781078
|
# READ STATUS: Burst-No: 35 Addr: 0023bdcb Rxd: ee4ee6dc
|
# READ STATUS: Burst-No: 35 Addr: 0023bdcb Rxd: ee4ee6dc
|
# tb_core.u_sdram32 : at time 39313.0 ns READ : Bank = 3 Row = 571, Col = 134, Data = 13d40d27
|
# tb_core.u_sdram32 : at time 39913.0 ns READ : Bank = 3 Row = 571, Col = 134, Data = 13d40d27
|
# READ STATUS: Burst-No: 36 Addr: 0023bdcd Rxd: bc781078
|
# READ STATUS: Burst-No: 36 Addr: 0023bdcd Rxd: bc781078
|
# tb_core.u_sdram32 : at time 39323.0 ns READ : Bank = 3 Row = 571, Col = 135, Data = afed265f
|
# tb_core.u_sdram32 : at time 39923.0 ns READ : Bank = 3 Row = 571, Col = 135, Data = afed265f
|
# READ STATUS: Burst-No: 37 Addr: 0023bdcf Rxd: 13d40d27
|
# READ STATUS: Burst-No: 37 Addr: 0023bdcf Rxd: 13d40d27
|
# tb_core.u_sdram32 : at time 39333.0 ns READ : Bank = 3 Row = 571, Col = 136, Data = 11c05b23
|
# tb_core.u_sdram32 : at time 39933.0 ns READ : Bank = 3 Row = 571, Col = 136, Data = 11c05b23
|
# READ STATUS: Burst-No: 38 Addr: 0023bdd1 Rxd: afed265f
|
# READ STATUS: Burst-No: 38 Addr: 0023bdd1 Rxd: afed265f
|
# tb_core.u_sdram32 : at time 39343.0 ns READ : Bank = 3 Row = 571, Col = 137, Data = 5596ebab
|
# tb_core.u_sdram32 : at time 39943.0 ns READ : Bank = 3 Row = 571, Col = 137, Data = 5596ebab
|
# READ STATUS: Burst-No: 39 Addr: 0023bdd3 Rxd: 11c05b23
|
# READ STATUS: Burst-No: 39 Addr: 0023bdd3 Rxd: 11c05b23
|
# tb_core.u_sdram32 : at time 39353.0 ns READ : Bank = 3 Row = 571, Col = 138, Data = 1c421738
|
# tb_core.u_sdram32 : at time 39953.0 ns READ : Bank = 3 Row = 571, Col = 138, Data = 1c421738
|
# READ STATUS: Burst-No: 40 Addr: 0023bdd5 Rxd: 5596ebab
|
# READ STATUS: Burst-No: 40 Addr: 0023bdd5 Rxd: 5596ebab
|
# tb_core.u_sdram32 : at time 39363.0 ns READ : Bank = 3 Row = 571, Col = 139, Data = 11534d22
|
# tb_core.u_sdram32 : at time 39963.0 ns READ : Bank = 3 Row = 571, Col = 139, Data = 11534d22
|
# READ STATUS: Burst-No: 41 Addr: 0023bdd7 Rxd: 1c421738
|
# READ STATUS: Burst-No: 41 Addr: 0023bdd7 Rxd: 1c421738
|
# tb_core.u_sdram32 : at time 39373.0 ns READ : Bank = 3 Row = 571, Col = 140, Data = 64f2bdc9
|
# tb_core.u_sdram32 : at time 39973.0 ns READ : Bank = 3 Row = 571, Col = 140, Data = 64f2bdc9
|
# READ STATUS: Burst-No: 42 Addr: 0023bdd9 Rxd: 11534d22
|
# READ STATUS: Burst-No: 42 Addr: 0023bdd9 Rxd: 11534d22
|
# tb_core.u_sdram32 : at time 39383.0 ns READ : Bank = 3 Row = 571, Col = 141, Data = e3eb4cc7
|
# tb_core.u_sdram32 : at time 39983.0 ns READ : Bank = 3 Row = 571, Col = 141, Data = e3eb4cc7
|
# READ STATUS: Burst-No: 43 Addr: 0023bddb Rxd: 64f2bdc9
|
# READ STATUS: Burst-No: 43 Addr: 0023bddb Rxd: 64f2bdc9
|
# tb_core.u_sdram32 : at time 39393.0 ns READ : Bank = 3 Row = 571, Col = 142, Data = c1406282
|
# tb_core.u_sdram32 : at time 39993.0 ns READ : Bank = 3 Row = 571, Col = 142, Data = c1406282
|
# READ STATUS: Burst-No: 44 Addr: 0023bddd Rxd: e3eb4cc7
|
# READ STATUS: Burst-No: 44 Addr: 0023bddd Rxd: e3eb4cc7
|
# tb_core.u_sdram32 : at time 39403.0 ns READ : Bank = 3 Row = 571, Col = 143, Data = 6754d7ce
|
# tb_core.u_sdram32 : at time 40003.0 ns READ : Bank = 3 Row = 571, Col = 143, Data = 6754d7ce
|
# READ STATUS: Burst-No: 45 Addr: 0023bddf Rxd: c1406282
|
# READ STATUS: Burst-No: 45 Addr: 0023bddf Rxd: c1406282
|
# tb_core.u_sdram32 : at time 39413.0 ns READ : Bank = 3 Row = 571, Col = 144, Data = e38e22c7
|
# tb_core.u_sdram32 : at time 40013.0 ns READ : Bank = 3 Row = 571, Col = 144, Data = e38e22c7
|
# READ STATUS: Burst-No: 46 Addr: 0023bde1 Rxd: 6754d7ce
|
# READ STATUS: Burst-No: 46 Addr: 0023bde1 Rxd: 6754d7ce
|
# tb_core.u_sdram32 : at time 39423.0 ns READ : Bank = 3 Row = 571, Col = 145, Data = 927fa424
|
# tb_core.u_sdram32 : at time 40023.0 ns READ : Bank = 3 Row = 571, Col = 145, Data = 927fa424
|
# READ STATUS: Burst-No: 47 Addr: 0023bde3 Rxd: e38e22c7
|
# READ STATUS: Burst-No: 47 Addr: 0023bde3 Rxd: e38e22c7
|
# tb_core.u_sdram32 : at time 39433.0 ns READ : Bank = 3 Row = 571, Col = 146, Data = 6da36fdb
|
# tb_core.u_sdram32 : at time 40033.0 ns READ : Bank = 3 Row = 571, Col = 146, Data = 6da36fdb
|
# READ STATUS: Burst-No: 48 Addr: 0023bde5 Rxd: 927fa424
|
# READ STATUS: Burst-No: 48 Addr: 0023bde5 Rxd: 927fa424
|
# tb_core.u_sdram32 : at time 39443.0 ns READ : Bank = 3 Row = 571, Col = 147, Data = 84651408
|
# tb_core.u_sdram32 : at time 40043.0 ns READ : Bank = 3 Row = 571, Col = 147, Data = 84651408
|
# READ STATUS: Burst-No: 49 Addr: 0023bde7 Rxd: 6da36fdb
|
# READ STATUS: Burst-No: 49 Addr: 0023bde7 Rxd: 6da36fdb
|
# tb_core.u_sdram32 : at time 39453.0 ns READ : Bank = 3 Row = 571, Col = 148, Data = 3ac26f75
|
# tb_core.u_sdram32 : at time 40053.0 ns READ : Bank = 3 Row = 571, Col = 148, Data = 3ac26f75
|
# READ STATUS: Burst-No: 50 Addr: 0023bde9 Rxd: 84651408
|
# READ STATUS: Burst-No: 50 Addr: 0023bde9 Rxd: 84651408
|
# tb_core.u_sdram32 : at time 39463.0 ns READ : Bank = 3 Row = 571, Col = 149, Data = 5ad31db5
|
# tb_core.u_sdram32 : at time 40063.0 ns READ : Bank = 3 Row = 571, Col = 149, Data = 5ad31db5
|
# READ STATUS: Burst-No: 51 Addr: 0023bdeb Rxd: 3ac26f75
|
# READ STATUS: Burst-No: 51 Addr: 0023bdeb Rxd: 3ac26f75
|
# tb_core.u_sdram32 : at time 39473.0 ns READ : Bank = 3 Row = 571, Col = 150, Data = 8d7d721a
|
# tb_core.u_sdram32 : at time 40073.0 ns READ : Bank = 3 Row = 571, Col = 150, Data = 8d7d721a
|
# READ STATUS: Burst-No: 52 Addr: 0023bded Rxd: 5ad31db5
|
# READ STATUS: Burst-No: 52 Addr: 0023bded Rxd: 5ad31db5
|
# tb_core.u_sdram32 : at time 39483.0 ns READ : Bank = 3 Row = 571, Col = 151, Data = 1c2a1338
|
# tb_core.u_sdram32 : at time 40083.0 ns READ : Bank = 3 Row = 571, Col = 151, Data = 1c2a1338
|
# READ STATUS: Burst-No: 53 Addr: 0023bdef Rxd: 8d7d721a
|
# READ STATUS: Burst-No: 53 Addr: 0023bdef Rxd: 8d7d721a
|
# tb_core.u_sdram32 : at time 39493.0 ns READ : Bank = 3 Row = 571, Col = 152, Data = c1233a82
|
# tb_core.u_sdram32 : at time 40093.0 ns READ : Bank = 3 Row = 571, Col = 152, Data = c1233a82
|
# tb_core.u_sdram32 : at time 39497.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 40097.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 54 Addr: 0023bdf1 Rxd: 1c2a1338
|
# READ STATUS: Burst-No: 54 Addr: 0023bdf1 Rxd: 1c2a1338
|
# tb_core.u_sdram32 : at time 39503.0 ns READ : Bank = 3 Row = 571, Col = 153, Data = ac05a058
|
# tb_core.u_sdram32 : at time 40103.0 ns READ : Bank = 3 Row = 571, Col = 153, Data = ac05a058
|
# READ STATUS: Burst-No: 55 Addr: 0023bdf3 Rxd: c1233a82
|
# READ STATUS: Burst-No: 55 Addr: 0023bdf3 Rxd: c1233a82
|
# tb_core.u_sdram32 : at time 39513.0 ns READ : Bank = 3 Row = 571, Col = 154, Data = a85a6a50
|
# tb_core.u_sdram32 : at time 40113.0 ns READ : Bank = 3 Row = 571, Col = 154, Data = a85a6a50
|
# READ STATUS: Burst-No: 56 Addr: 0023bdf5 Rxd: ac05a058
|
# READ STATUS: Burst-No: 56 Addr: 0023bdf5 Rxd: ac05a058
|
# READ STATUS: Burst-No: 57 Addr: 0023bdf7 Rxd: a85a6a50
|
# READ STATUS: Burst-No: 57 Addr: 0023bdf7 Rxd: a85a6a50
|
# tb_core.u_sdram32 : at time 39683.0 ns READ : Bank = 2 Row = 137, Col = 168, Data = 32c3df65
|
# tb_core.u_sdram32 : at time 40283.0 ns READ : Bank = 2 Row = 137, Col = 168, Data = 32c3df65
|
# tb_core.u_sdram32 : at time 39693.0 ns READ : Bank = 2 Row = 137, Col = 169, Data = 753c17ea
|
# tb_core.u_sdram32 : at time 40293.0 ns READ : Bank = 2 Row = 137, Col = 169, Data = 753c17ea
|
# READ STATUS: Burst-No: 0 Addr: 00089aa3 Rxd: 32c3df65
|
# READ STATUS: Burst-No: 0 Addr: 00089aa3 Rxd: 32c3df65
|
# tb_core.u_sdram32 : at time 39703.0 ns READ : Bank = 2 Row = 137, Col = 170, Data = 03703906
|
# tb_core.u_sdram32 : at time 40303.0 ns READ : Bank = 2 Row = 137, Col = 170, Data = 03703906
|
# READ STATUS: Burst-No: 1 Addr: 00089aa5 Rxd: 753c17ea
|
# READ STATUS: Burst-No: 1 Addr: 00089aa5 Rxd: 753c17ea
|
# tb_core.u_sdram32 : at time 39713.0 ns READ : Bank = 2 Row = 137, Col = 171, Data = aa138054
|
# tb_core.u_sdram32 : at time 40313.0 ns READ : Bank = 2 Row = 137, Col = 171, Data = aa138054
|
# READ STATUS: Burst-No: 2 Addr: 00089aa7 Rxd: 03703906
|
# READ STATUS: Burst-No: 2 Addr: 00089aa7 Rxd: 03703906
|
# tb_core.u_sdram32 : at time 39723.0 ns READ : Bank = 2 Row = 137, Col = 172, Data = adf3405b
|
# tb_core.u_sdram32 : at time 40323.0 ns READ : Bank = 2 Row = 137, Col = 172, Data = adf3405b
|
# READ STATUS: Burst-No: 3 Addr: 00089aa9 Rxd: aa138054
|
# READ STATUS: Burst-No: 3 Addr: 00089aa9 Rxd: aa138054
|
# tb_core.u_sdram32 : at time 39733.0 ns READ : Bank = 2 Row = 137, Col = 173, Data = e455f0c8
|
# tb_core.u_sdram32 : at time 40333.0 ns READ : Bank = 2 Row = 137, Col = 173, Data = e455f0c8
|
# READ STATUS: Burst-No: 4 Addr: 00089aab Rxd: adf3405b
|
# READ STATUS: Burst-No: 4 Addr: 00089aab Rxd: adf3405b
|
# tb_core.u_sdram32 : at time 39743.0 ns READ : Bank = 2 Row = 137, Col = 174, Data = 24673948
|
# tb_core.u_sdram32 : at time 40343.0 ns READ : Bank = 2 Row = 137, Col = 174, Data = 24673948
|
# READ STATUS: Burst-No: 5 Addr: 00089aad Rxd: e455f0c8
|
# READ STATUS: Burst-No: 5 Addr: 00089aad Rxd: e455f0c8
|
# tb_core.u_sdram32 : at time 39753.0 ns READ : Bank = 2 Row = 137, Col = 175, Data = 9bf8f237
|
# tb_core.u_sdram32 : at time 40353.0 ns READ : Bank = 2 Row = 137, Col = 175, Data = 9bf8f237
|
# READ STATUS: Burst-No: 6 Addr: 00089aaf Rxd: 24673948
|
# READ STATUS: Burst-No: 6 Addr: 00089aaf Rxd: 24673948
|
# tb_core.u_sdram32 : at time 39763.0 ns READ : Bank = 2 Row = 137, Col = 176, Data = 7c1df3f8
|
# tb_core.u_sdram32 : at time 40363.0 ns READ : Bank = 2 Row = 137, Col = 176, Data = 7c1df3f8
|
# READ STATUS: Burst-No: 7 Addr: 00089ab1 Rxd: 9bf8f237
|
# READ STATUS: Burst-No: 7 Addr: 00089ab1 Rxd: 9bf8f237
|
# tb_core.u_sdram32 : at time 39773.0 ns READ : Bank = 2 Row = 137, Col = 177, Data = da8932b5
|
# tb_core.u_sdram32 : at time 40373.0 ns READ : Bank = 2 Row = 137, Col = 177, Data = da8932b5
|
# READ STATUS: Burst-No: 8 Addr: 00089ab3 Rxd: 7c1df3f8
|
# READ STATUS: Burst-No: 8 Addr: 00089ab3 Rxd: 7c1df3f8
|
# tb_core.u_sdram32 : at time 39783.0 ns READ : Bank = 2 Row = 137, Col = 178, Data = 28d6a951
|
# tb_core.u_sdram32 : at time 40383.0 ns READ : Bank = 2 Row = 137, Col = 178, Data = 28d6a951
|
# READ STATUS: Burst-No: 9 Addr: 00089ab5 Rxd: da8932b5
|
# READ STATUS: Burst-No: 9 Addr: 00089ab5 Rxd: da8932b5
|
# tb_core.u_sdram32 : at time 39793.0 ns READ : Bank = 2 Row = 137, Col = 179, Data = 41aed583
|
# tb_core.u_sdram32 : at time 40393.0 ns READ : Bank = 2 Row = 137, Col = 179, Data = 41aed583
|
# READ STATUS: Burst-No: 10 Addr: 00089ab7 Rxd: 28d6a951
|
# READ STATUS: Burst-No: 10 Addr: 00089ab7 Rxd: 28d6a951
|
# tb_core.u_sdram32 : at time 39803.0 ns READ : Bank = 2 Row = 137, Col = 180, Data = 4d9ee39b
|
# tb_core.u_sdram32 : at time 40403.0 ns READ : Bank = 2 Row = 137, Col = 180, Data = 4d9ee39b
|
# READ STATUS: Burst-No: 11 Addr: 00089ab9 Rxd: 41aed583
|
# READ STATUS: Burst-No: 11 Addr: 00089ab9 Rxd: 41aed583
|
# tb_core.u_sdram32 : at time 39813.0 ns READ : Bank = 2 Row = 137, Col = 181, Data = 1aa0dd35
|
# tb_core.u_sdram32 : at time 40413.0 ns READ : Bank = 2 Row = 137, Col = 181, Data = 1aa0dd35
|
# READ STATUS: Burst-No: 12 Addr: 00089abb Rxd: 4d9ee39b
|
# READ STATUS: Burst-No: 12 Addr: 00089abb Rxd: 4d9ee39b
|
# tb_core.u_sdram32 : at time 39823.0 ns READ : Bank = 2 Row = 137, Col = 182, Data = 581653b0
|
# tb_core.u_sdram32 : at time 40423.0 ns READ : Bank = 2 Row = 137, Col = 182, Data = 581653b0
|
# READ STATUS: Burst-No: 13 Addr: 00089abd Rxd: 1aa0dd35
|
# READ STATUS: Burst-No: 13 Addr: 00089abd Rxd: 1aa0dd35
|
# tb_core.u_sdram32 : at time 39833.0 ns READ : Bank = 2 Row = 137, Col = 183, Data = fddf82fb
|
# tb_core.u_sdram32 : at time 40433.0 ns READ : Bank = 2 Row = 137, Col = 183, Data = fddf82fb
|
# READ STATUS: Burst-No: 14 Addr: 00089abf Rxd: 581653b0
|
# READ STATUS: Burst-No: 14 Addr: 00089abf Rxd: 581653b0
|
# tb_core.u_sdram32 : at time 39843.0 ns READ : Bank = 2 Row = 137, Col = 184, Data = 278dbb4f
|
# tb_core.u_sdram32 : at time 40443.0 ns READ : Bank = 2 Row = 137, Col = 184, Data = 278dbb4f
|
# READ STATUS: Burst-No: 15 Addr: 00089ac1 Rxd: fddf82fb
|
# READ STATUS: Burst-No: 15 Addr: 00089ac1 Rxd: fddf82fb
|
# tb_core.u_sdram32 : at time 39853.0 ns READ : Bank = 2 Row = 137, Col = 185, Data = 984da630
|
# tb_core.u_sdram32 : at time 40453.0 ns READ : Bank = 2 Row = 137, Col = 185, Data = 984da630
|
# READ STATUS: Burst-No: 16 Addr: 00089ac3 Rxd: 278dbb4f
|
# READ STATUS: Burst-No: 16 Addr: 00089ac3 Rxd: 278dbb4f
|
# tb_core.u_sdram32 : at time 39863.0 ns READ : Bank = 2 Row = 137, Col = 186, Data = 8c38c418
|
# tb_core.u_sdram32 : at time 40463.0 ns READ : Bank = 2 Row = 137, Col = 186, Data = 8c38c418
|
# READ STATUS: Burst-No: 17 Addr: 00089ac5 Rxd: 984da630
|
# READ STATUS: Burst-No: 17 Addr: 00089ac5 Rxd: 984da630
|
# tb_core.u_sdram32 : at time 39873.0 ns READ : Bank = 2 Row = 137, Col = 187, Data = ee8118dd
|
# tb_core.u_sdram32 : at time 40473.0 ns READ : Bank = 2 Row = 137, Col = 187, Data = ee8118dd
|
# READ STATUS: Burst-No: 18 Addr: 00089ac7 Rxd: 8c38c418
|
# READ STATUS: Burst-No: 18 Addr: 00089ac7 Rxd: 8c38c418
|
# tb_core.u_sdram32 : at time 39883.0 ns READ : Bank = 2 Row = 137, Col = 188, Data = a36ae846
|
# tb_core.u_sdram32 : at time 40483.0 ns READ : Bank = 2 Row = 137, Col = 188, Data = a36ae846
|
# READ STATUS: Burst-No: 19 Addr: 00089ac9 Rxd: ee8118dd
|
# READ STATUS: Burst-No: 19 Addr: 00089ac9 Rxd: ee8118dd
|
# tb_core.u_sdram32 : at time 39893.0 ns READ : Bank = 2 Row = 137, Col = 189, Data = 30e20f61
|
# tb_core.u_sdram32 : at time 40493.0 ns READ : Bank = 2 Row = 137, Col = 189, Data = 30e20f61
|
# READ STATUS: Burst-No: 20 Addr: 00089acb Rxd: a36ae846
|
# READ STATUS: Burst-No: 20 Addr: 00089acb Rxd: a36ae846
|
# tb_core.u_sdram32 : at time 39903.0 ns READ : Bank = 2 Row = 137, Col = 190, Data = ac974859
|
# tb_core.u_sdram32 : at time 40503.0 ns READ : Bank = 2 Row = 137, Col = 190, Data = ac974859
|
# READ STATUS: Burst-No: 21 Addr: 00089acd Rxd: 30e20f61
|
# READ STATUS: Burst-No: 21 Addr: 00089acd Rxd: 30e20f61
|
# tb_core.u_sdram32 : at time 39913.0 ns READ : Bank = 2 Row = 137, Col = 191, Data = 2af17355
|
# tb_core.u_sdram32 : at time 40513.0 ns READ : Bank = 2 Row = 137, Col = 191, Data = 2af17355
|
# READ STATUS: Burst-No: 22 Addr: 00089acf Rxd: ac974859
|
# READ STATUS: Burst-No: 22 Addr: 00089acf Rxd: ac974859
|
# tb_core.u_sdram32 : at time 39923.0 ns READ : Bank = 2 Row = 137, Col = 192, Data = 178b972f
|
# tb_core.u_sdram32 : at time 40523.0 ns READ : Bank = 2 Row = 137, Col = 192, Data = 178b972f
|
# READ STATUS: Burst-No: 23 Addr: 00089ad1 Rxd: 2af17355
|
# READ STATUS: Burst-No: 23 Addr: 00089ad1 Rxd: 2af17355
|
# tb_core.u_sdram32 : at time 39933.0 ns READ : Bank = 2 Row = 137, Col = 193, Data = 85ce500b
|
# tb_core.u_sdram32 : at time 40533.0 ns READ : Bank = 2 Row = 137, Col = 193, Data = 85ce500b
|
# READ STATUS: Burst-No: 24 Addr: 00089ad3 Rxd: 178b972f
|
# READ STATUS: Burst-No: 24 Addr: 00089ad3 Rxd: 178b972f
|
# tb_core.u_sdram32 : at time 39943.0 ns READ : Bank = 2 Row = 137, Col = 194, Data = ef1deade
|
# tb_core.u_sdram32 : at time 40543.0 ns READ : Bank = 2 Row = 137, Col = 194, Data = ef1deade
|
# READ STATUS: Burst-No: 25 Addr: 00089ad5 Rxd: 85ce500b
|
# READ STATUS: Burst-No: 25 Addr: 00089ad5 Rxd: 85ce500b
|
# tb_core.u_sdram32 : at time 39953.0 ns READ : Bank = 2 Row = 137, Col = 195, Data = e9d22cd3
|
# tb_core.u_sdram32 : at time 40553.0 ns READ : Bank = 2 Row = 137, Col = 195, Data = e9d22cd3
|
# READ STATUS: Burst-No: 26 Addr: 00089ad7 Rxd: ef1deade
|
# READ STATUS: Burst-No: 26 Addr: 00089ad7 Rxd: ef1deade
|
# tb_core.u_sdram32 : at time 39963.0 ns READ : Bank = 2 Row = 137, Col = 196, Data = 1445b128
|
# tb_core.u_sdram32 : at time 40563.0 ns READ : Bank = 2 Row = 137, Col = 196, Data = 1445b128
|
# READ STATUS: Burst-No: 27 Addr: 00089ad9 Rxd: e9d22cd3
|
# READ STATUS: Burst-No: 27 Addr: 00089ad9 Rxd: e9d22cd3
|
# tb_core.u_sdram32 : at time 39973.0 ns READ : Bank = 2 Row = 137, Col = 197, Data = 74dc69e9
|
# tb_core.u_sdram32 : at time 40573.0 ns READ : Bank = 2 Row = 137, Col = 197, Data = 74dc69e9
|
# READ STATUS: Burst-No: 28 Addr: 00089adb Rxd: 1445b128
|
# READ STATUS: Burst-No: 28 Addr: 00089adb Rxd: 1445b128
|
# tb_core.u_sdram32 : at time 39983.0 ns READ : Bank = 2 Row = 137, Col = 198, Data = 2c577958
|
# tb_core.u_sdram32 : at time 40583.0 ns READ : Bank = 2 Row = 137, Col = 198, Data = 2c577958
|
# READ STATUS: Burst-No: 29 Addr: 00089add Rxd: 74dc69e9
|
# READ STATUS: Burst-No: 29 Addr: 00089add Rxd: 74dc69e9
|
# tb_core.u_sdram32 : at time 39993.0 ns READ : Bank = 2 Row = 137, Col = 199, Data = 6aa4a1d5
|
# tb_core.u_sdram32 : at time 40593.0 ns READ : Bank = 2 Row = 137, Col = 199, Data = 6aa4a1d5
|
# READ STATUS: Burst-No: 30 Addr: 00089adf Rxd: 2c577958
|
# READ STATUS: Burst-No: 30 Addr: 00089adf Rxd: 2c577958
|
# tb_core.u_sdram32 : at time 40003.0 ns READ : Bank = 2 Row = 137, Col = 200, Data = 61dbe5c3
|
# tb_core.u_sdram32 : at time 40603.0 ns READ : Bank = 2 Row = 137, Col = 200, Data = 61dbe5c3
|
# READ STATUS: Burst-No: 31 Addr: 00089ae1 Rxd: 6aa4a1d5
|
# READ STATUS: Burst-No: 31 Addr: 00089ae1 Rxd: 6aa4a1d5
|
# tb_core.u_sdram32 : at time 40013.0 ns READ : Bank = 2 Row = 137, Col = 201, Data = 6a2c13d4
|
# tb_core.u_sdram32 : at time 40613.0 ns READ : Bank = 2 Row = 137, Col = 201, Data = 6a2c13d4
|
# READ STATUS: Burst-No: 32 Addr: 00089ae3 Rxd: 61dbe5c3
|
# READ STATUS: Burst-No: 32 Addr: 00089ae3 Rxd: 61dbe5c3
|
# tb_core.u_sdram32 : at time 40023.0 ns READ : Bank = 2 Row = 137, Col = 202, Data = 52397da4
|
# tb_core.u_sdram32 : at time 40623.0 ns READ : Bank = 2 Row = 137, Col = 202, Data = 52397da4
|
# tb_core.u_sdram32 : at time 40027.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 40627.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 33 Addr: 00089ae5 Rxd: 6a2c13d4
|
# READ STATUS: Burst-No: 33 Addr: 00089ae5 Rxd: 6a2c13d4
|
# tb_core.u_sdram32 : at time 40033.0 ns READ : Bank = 2 Row = 137, Col = 203, Data = 3f25ef7e
|
# tb_core.u_sdram32 : at time 40633.0 ns READ : Bank = 2 Row = 137, Col = 203, Data = 3f25ef7e
|
# READ STATUS: Burst-No: 34 Addr: 00089ae7 Rxd: 52397da4
|
# READ STATUS: Burst-No: 34 Addr: 00089ae7 Rxd: 52397da4
|
# tb_core.u_sdram32 : at time 40043.0 ns READ : Bank = 2 Row = 137, Col = 204, Data = 6b299dd6
|
# tb_core.u_sdram32 : at time 40643.0 ns READ : Bank = 2 Row = 137, Col = 204, Data = 6b299dd6
|
# READ STATUS: Burst-No: 35 Addr: 00089ae9 Rxd: 3f25ef7e
|
# READ STATUS: Burst-No: 35 Addr: 00089ae9 Rxd: 3f25ef7e
|
# READ STATUS: Burst-No: 36 Addr: 00089aeb Rxd: 6b299dd6
|
# READ STATUS: Burst-No: 36 Addr: 00089aeb Rxd: 6b299dd6
|
# Write Address: 002ec80f, Burst Size: 4
|
# Write Address: 002ec80f, Burst Size: 4
|
# tb_core.u_sdram32 : at time 40217.0 ns ACT : Bank = 2 Row = 748
|
# tb_core.u_sdram32 : at time 40817.0 ns ACT : Bank = 2 Row = 748
|
# tb_core.u_sdram32 : at time 40247.0 ns WRITE: Bank = 2 Row = 748, Col = 3, Data = 506aefa0
|
# tb_core.u_sdram32 : at time 40847.0 ns WRITE: Bank = 2 Row = 748, Col = 3, Data = 506aefa0
|
# Status: Burst-No: 0 Write Address: 002ec80f WriteData: 506aefa0
|
# Status: Burst-No: 0 Write Address: 002ec80f WriteData: 506aefa0
|
# tb_core.u_sdram32 : at time 40257.0 ns WRITE: Bank = 2 Row = 748, Col = 4, Data = c10f0482
|
# tb_core.u_sdram32 : at time 40857.0 ns WRITE: Bank = 2 Row = 748, Col = 4, Data = c10f0482
|
# Status: Burst-No: 1 Write Address: 002ec80f WriteData: c10f0482
|
# Status: Burst-No: 1 Write Address: 002ec80f WriteData: c10f0482
|
# tb_core.u_sdram32 : at time 40267.0 ns WRITE: Bank = 2 Row = 748, Col = 5, Data = 5fe3cbbf
|
# tb_core.u_sdram32 : at time 40867.0 ns WRITE: Bank = 2 Row = 748, Col = 5, Data = 5fe3cbbf
|
# Status: Burst-No: 2 Write Address: 002ec80f WriteData: 5fe3cbbf
|
# Status: Burst-No: 2 Write Address: 002ec80f WriteData: 5fe3cbbf
|
# tb_core.u_sdram32 : at time 40277.0 ns WRITE: Bank = 2 Row = 748, Col = 6, Data = 22eadb45
|
# tb_core.u_sdram32 : at time 40877.0 ns WRITE: Bank = 2 Row = 748, Col = 6, Data = 22eadb45
|
# Status: Burst-No: 3 Write Address: 002ec80f WriteData: 22eadb45
|
# Status: Burst-No: 3 Write Address: 002ec80f WriteData: 22eadb45
|
# tb_core.u_sdram32 : at time 40287.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 40887.0 ns BST : Burst Terminate
|
# Write Address: 003c3e77, Burst Size: 6
|
# Write Address: 003c3e77, Burst Size: 6
|
# tb_core.u_sdram32 : at time 40427.0 ns ACT : Bank = 3 Row = 963
|
# tb_core.u_sdram32 : at time 40997.0 ns AREF : Auto Refresh
|
# tb_core.u_sdram32 : at time 40457.0 ns WRITE: Bank = 3 Row = 963, Col = 157, Data = ba941075
|
# tb_core.u_sdram32 : at time 41087.0 ns AREF : Auto Refresh
|
|
# tb_core.u_sdram32 : at time 41177.0 ns AREF : Auto Refresh
|
|
# tb_core.u_sdram32 : at time 41267.0 ns AREF : Auto Refresh
|
|
# tb_core.u_sdram32 : at time 41357.0 ns AREF : Auto Refresh
|
|
# tb_core.u_sdram32 : at time 41447.0 ns AREF : Auto Refresh
|
|
# tb_core.u_sdram32 : at time 41567.0 ns ACT : Bank = 3 Row = 963
|
|
# tb_core.u_sdram32 : at time 41597.0 ns WRITE: Bank = 3 Row = 963, Col = 157, Data = ba941075
|
# Status: Burst-No: 0 Write Address: 003c3e77 WriteData: ba941075
|
# Status: Burst-No: 0 Write Address: 003c3e77 WriteData: ba941075
|
# tb_core.u_sdram32 : at time 40467.0 ns WRITE: Bank = 3 Row = 963, Col = 158, Data = fc670af8
|
# tb_core.u_sdram32 : at time 41607.0 ns WRITE: Bank = 3 Row = 963, Col = 158, Data = fc670af8
|
# Status: Burst-No: 1 Write Address: 003c3e77 WriteData: fc670af8
|
# Status: Burst-No: 1 Write Address: 003c3e77 WriteData: fc670af8
|
# tb_core.u_sdram32 : at time 40477.0 ns WRITE: Bank = 3 Row = 963, Col = 159, Data = 63323bc6
|
# tb_core.u_sdram32 : at time 41617.0 ns WRITE: Bank = 3 Row = 963, Col = 159, Data = 63323bc6
|
# Status: Burst-No: 2 Write Address: 003c3e77 WriteData: 63323bc6
|
# Status: Burst-No: 2 Write Address: 003c3e77 WriteData: 63323bc6
|
# tb_core.u_sdram32 : at time 40487.0 ns WRITE: Bank = 3 Row = 963, Col = 160, Data = 3601596c
|
# tb_core.u_sdram32 : at time 41627.0 ns WRITE: Bank = 3 Row = 963, Col = 160, Data = 3601596c
|
# Status: Burst-No: 3 Write Address: 003c3e77 WriteData: 3601596c
|
# Status: Burst-No: 3 Write Address: 003c3e77 WriteData: 3601596c
|
# tb_core.u_sdram32 : at time 40497.0 ns WRITE: Bank = 3 Row = 963, Col = 161, Data = a84e5850
|
# tb_core.u_sdram32 : at time 41637.0 ns WRITE: Bank = 3 Row = 963, Col = 161, Data = a84e5850
|
# Status: Burst-No: 4 Write Address: 003c3e77 WriteData: a84e5850
|
# Status: Burst-No: 4 Write Address: 003c3e77 WriteData: a84e5850
|
# tb_core.u_sdram32 : at time 40507.0 ns WRITE: Bank = 3 Row = 963, Col = 162, Data = 18bd6331
|
# tb_core.u_sdram32 : at time 41647.0 ns WRITE: Bank = 3 Row = 963, Col = 162, Data = 18bd6331
|
# Status: Burst-No: 5 Write Address: 003c3e77 WriteData: 18bd6331
|
# Status: Burst-No: 5 Write Address: 003c3e77 WriteData: 18bd6331
|
# tb_core.u_sdram32 : at time 40517.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 41657.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 40653.0 ns READ : Bank = 2 Row = 748, Col = 3, Data = 506aefa0
|
# tb_core.u_sdram32 : at time 41797.0 ns ACT : Bank = 2 Row = 748
|
# tb_core.u_sdram32 : at time 40663.0 ns READ : Bank = 2 Row = 748, Col = 4, Data = c10f0482
|
# tb_core.u_sdram32 : at time 41853.0 ns READ : Bank = 2 Row = 748, Col = 3, Data = 506aefa0
|
|
# tb_core.u_sdram32 : at time 41863.0 ns READ : Bank = 2 Row = 748, Col = 4, Data = c10f0482
|
# READ STATUS: Burst-No: 0 Addr: 002ec80f Rxd: 506aefa0
|
# READ STATUS: Burst-No: 0 Addr: 002ec80f Rxd: 506aefa0
|
# tb_core.u_sdram32 : at time 40667.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 41867.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 40673.0 ns READ : Bank = 2 Row = 748, Col = 5, Data = 5fe3cbbf
|
# tb_core.u_sdram32 : at time 41873.0 ns READ : Bank = 2 Row = 748, Col = 5, Data = 5fe3cbbf
|
# READ STATUS: Burst-No: 1 Addr: 002ec811 Rxd: c10f0482
|
# READ STATUS: Burst-No: 1 Addr: 002ec811 Rxd: c10f0482
|
# tb_core.u_sdram32 : at time 40683.0 ns READ : Bank = 2 Row = 748, Col = 6, Data = 22eadb45
|
# tb_core.u_sdram32 : at time 41883.0 ns READ : Bank = 2 Row = 748, Col = 6, Data = 22eadb45
|
# READ STATUS: Burst-No: 2 Addr: 002ec813 Rxd: 5fe3cbbf
|
# READ STATUS: Burst-No: 2 Addr: 002ec813 Rxd: 5fe3cbbf
|
# READ STATUS: Burst-No: 3 Addr: 002ec815 Rxd: 22eadb45
|
# READ STATUS: Burst-No: 3 Addr: 002ec815 Rxd: 22eadb45
|
# tb_core.u_sdram32 : at time 40853.0 ns READ : Bank = 3 Row = 963, Col = 157, Data = ba941075
|
# tb_core.u_sdram32 : at time 42053.0 ns READ : Bank = 3 Row = 963, Col = 157, Data = ba941075
|
# tb_core.u_sdram32 : at time 40863.0 ns READ : Bank = 3 Row = 963, Col = 158, Data = fc670af8
|
# tb_core.u_sdram32 : at time 42063.0 ns READ : Bank = 3 Row = 963, Col = 158, Data = fc670af8
|
# READ STATUS: Burst-No: 0 Addr: 003c3e77 Rxd: ba941075
|
# READ STATUS: Burst-No: 0 Addr: 003c3e77 Rxd: ba941075
|
# tb_core.u_sdram32 : at time 40873.0 ns READ : Bank = 3 Row = 963, Col = 159, Data = 63323bc6
|
# tb_core.u_sdram32 : at time 42073.0 ns READ : Bank = 3 Row = 963, Col = 159, Data = 63323bc6
|
# READ STATUS: Burst-No: 1 Addr: 003c3e79 Rxd: fc670af8
|
# READ STATUS: Burst-No: 1 Addr: 003c3e79 Rxd: fc670af8
|
# tb_core.u_sdram32 : at time 40883.0 ns READ : Bank = 3 Row = 963, Col = 160, Data = 3601596c
|
# tb_core.u_sdram32 : at time 42083.0 ns READ : Bank = 3 Row = 963, Col = 160, Data = 3601596c
|
# tb_core.u_sdram32 : at time 40887.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 42087.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 2 Addr: 003c3e7b Rxd: 63323bc6
|
# READ STATUS: Burst-No: 2 Addr: 003c3e7b Rxd: 63323bc6
|
# tb_core.u_sdram32 : at time 40893.0 ns READ : Bank = 3 Row = 963, Col = 161, Data = a84e5850
|
# tb_core.u_sdram32 : at time 42093.0 ns READ : Bank = 3 Row = 963, Col = 161, Data = a84e5850
|
# READ STATUS: Burst-No: 3 Addr: 003c3e7d Rxd: 3601596c
|
# READ STATUS: Burst-No: 3 Addr: 003c3e7d Rxd: 3601596c
|
# tb_core.u_sdram32 : at time 40903.0 ns READ : Bank = 3 Row = 963, Col = 162, Data = 18bd6331
|
# tb_core.u_sdram32 : at time 42103.0 ns READ : Bank = 3 Row = 963, Col = 162, Data = 18bd6331
|
# READ STATUS: Burst-No: 4 Addr: 003c3e7f Rxd: a84e5850
|
# READ STATUS: Burst-No: 4 Addr: 003c3e7f Rxd: a84e5850
|
# READ STATUS: Burst-No: 5 Addr: 003c3e81 Rxd: 18bd6331
|
# READ STATUS: Burst-No: 5 Addr: 003c3e81 Rxd: 18bd6331
|
# Write Address: 0010fe9c, Burst Size: 61
|
# Write Address: 0010fe9c, Burst Size: 61
|
# tb_core.u_sdram32 : at time 41077.0 ns ACT : Bank = 3 Row = 271
|
# tb_core.u_sdram32 : at time 42277.0 ns ACT : Bank = 3 Row = 271
|
# tb_core.u_sdram32 : at time 41107.0 ns WRITE: Bank = 3 Row = 271, Col = 167, Data = d7e31eaf
|
# tb_core.u_sdram32 : at time 42307.0 ns WRITE: Bank = 3 Row = 271, Col = 167, Data = d7e31eaf
|
# Status: Burst-No: 0 Write Address: 0010fe9c WriteData: d7e31eaf
|
# Status: Burst-No: 0 Write Address: 0010fe9c WriteData: d7e31eaf
|
# tb_core.u_sdram32 : at time 41117.0 ns WRITE: Bank = 3 Row = 271, Col = 168, Data = 872d2c0e
|
# tb_core.u_sdram32 : at time 42317.0 ns WRITE: Bank = 3 Row = 271, Col = 168, Data = 872d2c0e
|
# Status: Burst-No: 1 Write Address: 0010fe9c WriteData: 872d2c0e
|
# Status: Burst-No: 1 Write Address: 0010fe9c WriteData: 872d2c0e
|
# tb_core.u_sdram32 : at time 41127.0 ns WRITE: Bank = 3 Row = 271, Col = 169, Data = b4e46669
|
# tb_core.u_sdram32 : at time 42327.0 ns WRITE: Bank = 3 Row = 271, Col = 169, Data = b4e46669
|
# Status: Burst-No: 2 Write Address: 0010fe9c WriteData: b4e46669
|
# Status: Burst-No: 2 Write Address: 0010fe9c WriteData: b4e46669
|
# tb_core.u_sdram32 : at time 41137.0 ns WRITE: Bank = 3 Row = 271, Col = 170, Data = d95b40b2
|
# tb_core.u_sdram32 : at time 42337.0 ns WRITE: Bank = 3 Row = 271, Col = 170, Data = d95b40b2
|
# Status: Burst-No: 3 Write Address: 0010fe9c WriteData: d95b40b2
|
# Status: Burst-No: 3 Write Address: 0010fe9c WriteData: d95b40b2
|
# tb_core.u_sdram32 : at time 41147.0 ns WRITE: Bank = 3 Row = 271, Col = 171, Data = ef209ede
|
# tb_core.u_sdram32 : at time 42347.0 ns WRITE: Bank = 3 Row = 271, Col = 171, Data = ef209ede
|
# Status: Burst-No: 4 Write Address: 0010fe9c WriteData: ef209ede
|
# Status: Burst-No: 4 Write Address: 0010fe9c WriteData: ef209ede
|
# tb_core.u_sdram32 : at time 41157.0 ns WRITE: Bank = 3 Row = 271, Col = 172, Data = c2e87485
|
# tb_core.u_sdram32 : at time 42357.0 ns WRITE: Bank = 3 Row = 271, Col = 172, Data = c2e87485
|
# Status: Burst-No: 5 Write Address: 0010fe9c WriteData: c2e87485
|
# Status: Burst-No: 5 Write Address: 0010fe9c WriteData: c2e87485
|
# tb_core.u_sdram32 : at time 41167.0 ns WRITE: Bank = 3 Row = 271, Col = 173, Data = 555c0faa
|
# tb_core.u_sdram32 : at time 42367.0 ns WRITE: Bank = 3 Row = 271, Col = 173, Data = 555c0faa
|
# Status: Burst-No: 6 Write Address: 0010fe9c WriteData: 555c0faa
|
# Status: Burst-No: 6 Write Address: 0010fe9c WriteData: 555c0faa
|
# tb_core.u_sdram32 : at time 41177.0 ns WRITE: Bank = 3 Row = 271, Col = 174, Data = 1407f128
|
# tb_core.u_sdram32 : at time 42377.0 ns WRITE: Bank = 3 Row = 271, Col = 174, Data = 1407f128
|
# Status: Burst-No: 7 Write Address: 0010fe9c WriteData: 1407f128
|
# Status: Burst-No: 7 Write Address: 0010fe9c WriteData: 1407f128
|
# tb_core.u_sdram32 : at time 41187.0 ns WRITE: Bank = 3 Row = 271, Col = 175, Data = 610ed5c2
|
# tb_core.u_sdram32 : at time 42387.0 ns WRITE: Bank = 3 Row = 271, Col = 175, Data = 610ed5c2
|
# Status: Burst-No: 8 Write Address: 0010fe9c WriteData: 610ed5c2
|
# Status: Burst-No: 8 Write Address: 0010fe9c WriteData: 610ed5c2
|
# tb_core.u_sdram32 : at time 41197.0 ns WRITE: Bank = 3 Row = 271, Col = 176, Data = 4d20099a
|
# tb_core.u_sdram32 : at time 42397.0 ns WRITE: Bank = 3 Row = 271, Col = 176, Data = 4d20099a
|
# Status: Burst-No: 9 Write Address: 0010fe9c WriteData: 4d20099a
|
# Status: Burst-No: 9 Write Address: 0010fe9c WriteData: 4d20099a
|
# tb_core.u_sdram32 : at time 41207.0 ns WRITE: Bank = 3 Row = 271, Col = 177, Data = 69e751d3
|
# tb_core.u_sdram32 : at time 42407.0 ns WRITE: Bank = 3 Row = 271, Col = 177, Data = 69e751d3
|
# Status: Burst-No: 10 Write Address: 0010fe9c WriteData: 69e751d3
|
# Status: Burst-No: 10 Write Address: 0010fe9c WriteData: 69e751d3
|
# tb_core.u_sdram32 : at time 41217.0 ns WRITE: Bank = 3 Row = 271, Col = 178, Data = dd111aba
|
# tb_core.u_sdram32 : at time 42417.0 ns WRITE: Bank = 3 Row = 271, Col = 178, Data = dd111aba
|
# Status: Burst-No: 11 Write Address: 0010fe9c WriteData: dd111aba
|
# Status: Burst-No: 11 Write Address: 0010fe9c WriteData: dd111aba
|
# tb_core.u_sdram32 : at time 41227.0 ns WRITE: Bank = 3 Row = 271, Col = 179, Data = fdeb7cfb
|
# tb_core.u_sdram32 : at time 42427.0 ns WRITE: Bank = 3 Row = 271, Col = 179, Data = fdeb7cfb
|
# Status: Burst-No: 12 Write Address: 0010fe9c WriteData: fdeb7cfb
|
# Status: Burst-No: 12 Write Address: 0010fe9c WriteData: fdeb7cfb
|
# tb_core.u_sdram32 : at time 41237.0 ns WRITE: Bank = 3 Row = 271, Col = 180, Data = c5cf728b
|
# tb_core.u_sdram32 : at time 42437.0 ns WRITE: Bank = 3 Row = 271, Col = 180, Data = c5cf728b
|
# Status: Burst-No: 13 Write Address: 0010fe9c WriteData: c5cf728b
|
# Status: Burst-No: 13 Write Address: 0010fe9c WriteData: c5cf728b
|
# tb_core.u_sdram32 : at time 41247.0 ns WRITE: Bank = 3 Row = 271, Col = 181, Data = 61114dc2
|
# tb_core.u_sdram32 : at time 42447.0 ns WRITE: Bank = 3 Row = 271, Col = 181, Data = 61114dc2
|
# Status: Burst-No: 14 Write Address: 0010fe9c WriteData: 61114dc2
|
# Status: Burst-No: 14 Write Address: 0010fe9c WriteData: 61114dc2
|
# tb_core.u_sdram32 : at time 41257.0 ns WRITE: Bank = 3 Row = 271, Col = 182, Data = e64828cc
|
# tb_core.u_sdram32 : at time 42457.0 ns WRITE: Bank = 3 Row = 271, Col = 182, Data = e64828cc
|
# Status: Burst-No: 15 Write Address: 0010fe9c WriteData: e64828cc
|
# Status: Burst-No: 15 Write Address: 0010fe9c WriteData: e64828cc
|
# tb_core.u_sdram32 : at time 41267.0 ns WRITE: Bank = 3 Row = 271, Col = 183, Data = 38e61371
|
# tb_core.u_sdram32 : at time 42467.0 ns WRITE: Bank = 3 Row = 271, Col = 183, Data = 38e61371
|
# Status: Burst-No: 16 Write Address: 0010fe9c WriteData: 38e61371
|
# Status: Burst-No: 16 Write Address: 0010fe9c WriteData: 38e61371
|
# tb_core.u_sdram32 : at time 41277.0 ns WRITE: Bank = 3 Row = 271, Col = 184, Data = 4f49019e
|
# tb_core.u_sdram32 : at time 42477.0 ns WRITE: Bank = 3 Row = 271, Col = 184, Data = 4f49019e
|
# Status: Burst-No: 17 Write Address: 0010fe9c WriteData: 4f49019e
|
# Status: Burst-No: 17 Write Address: 0010fe9c WriteData: 4f49019e
|
# tb_core.u_sdram32 : at time 41287.0 ns WRITE: Bank = 3 Row = 271, Col = 185, Data = 309cdb61
|
# tb_core.u_sdram32 : at time 42487.0 ns WRITE: Bank = 3 Row = 271, Col = 185, Data = 309cdb61
|
# Status: Burst-No: 18 Write Address: 0010fe9c WriteData: 309cdb61
|
# Status: Burst-No: 18 Write Address: 0010fe9c WriteData: 309cdb61
|
# tb_core.u_sdram32 : at time 41297.0 ns WRITE: Bank = 3 Row = 271, Col = 186, Data = bde3487b
|
# tb_core.u_sdram32 : at time 42497.0 ns WRITE: Bank = 3 Row = 271, Col = 186, Data = bde3487b
|
# Status: Burst-No: 19 Write Address: 0010fe9c WriteData: bde3487b
|
# Status: Burst-No: 19 Write Address: 0010fe9c WriteData: bde3487b
|
# tb_core.u_sdram32 : at time 41307.0 ns WRITE: Bank = 3 Row = 271, Col = 187, Data = df9bd0bf
|
# tb_core.u_sdram32 : at time 42507.0 ns WRITE: Bank = 3 Row = 271, Col = 187, Data = df9bd0bf
|
# Status: Burst-No: 20 Write Address: 0010fe9c WriteData: df9bd0bf
|
# Status: Burst-No: 20 Write Address: 0010fe9c WriteData: df9bd0bf
|
# tb_core.u_sdram32 : at time 41317.0 ns WRITE: Bank = 3 Row = 271, Col = 188, Data = c881bc91
|
# tb_core.u_sdram32 : at time 42517.0 ns WRITE: Bank = 3 Row = 271, Col = 188, Data = c881bc91
|
# Status: Burst-No: 21 Write Address: 0010fe9c WriteData: c881bc91
|
# Status: Burst-No: 21 Write Address: 0010fe9c WriteData: c881bc91
|
# tb_core.u_sdram32 : at time 41327.0 ns WRITE: Bank = 3 Row = 271, Col = 189, Data = e06098c0
|
# tb_core.u_sdram32 : at time 42527.0 ns WRITE: Bank = 3 Row = 271, Col = 189, Data = e06098c0
|
# Status: Burst-No: 22 Write Address: 0010fe9c WriteData: e06098c0
|
# Status: Burst-No: 22 Write Address: 0010fe9c WriteData: e06098c0
|
# tb_core.u_sdram32 : at time 41337.0 ns WRITE: Bank = 3 Row = 271, Col = 190, Data = 2ca96359
|
# tb_core.u_sdram32 : at time 42537.0 ns WRITE: Bank = 3 Row = 271, Col = 190, Data = 2ca96359
|
# Status: Burst-No: 23 Write Address: 0010fe9c WriteData: 2ca96359
|
# Status: Burst-No: 23 Write Address: 0010fe9c WriteData: 2ca96359
|
# tb_core.u_sdram32 : at time 41347.0 ns WRITE: Bank = 3 Row = 271, Col = 191, Data = bf53b47e
|
# tb_core.u_sdram32 : at time 42547.0 ns WRITE: Bank = 3 Row = 271, Col = 191, Data = bf53b47e
|
# Status: Burst-No: 24 Write Address: 0010fe9c WriteData: bf53b47e
|
# Status: Burst-No: 24 Write Address: 0010fe9c WriteData: bf53b47e
|
# tb_core.u_sdram32 : at time 41357.0 ns WRITE: Bank = 3 Row = 271, Col = 192, Data = 2a1d7354
|
# tb_core.u_sdram32 : at time 42557.0 ns WRITE: Bank = 3 Row = 271, Col = 192, Data = 2a1d7354
|
# Status: Burst-No: 25 Write Address: 0010fe9c WriteData: 2a1d7354
|
# Status: Burst-No: 25 Write Address: 0010fe9c WriteData: 2a1d7354
|
# tb_core.u_sdram32 : at time 41367.0 ns WRITE: Bank = 3 Row = 271, Col = 193, Data = a8e2e251
|
# tb_core.u_sdram32 : at time 42567.0 ns WRITE: Bank = 3 Row = 271, Col = 193, Data = a8e2e251
|
# Status: Burst-No: 26 Write Address: 0010fe9c WriteData: a8e2e251
|
# Status: Burst-No: 26 Write Address: 0010fe9c WriteData: a8e2e251
|
# tb_core.u_sdram32 : at time 41377.0 ns WRITE: Bank = 3 Row = 271, Col = 194, Data = a4de2849
|
# tb_core.u_sdram32 : at time 42577.0 ns WRITE: Bank = 3 Row = 271, Col = 194, Data = a4de2849
|
# Status: Burst-No: 27 Write Address: 0010fe9c WriteData: a4de2849
|
# Status: Burst-No: 27 Write Address: 0010fe9c WriteData: a4de2849
|
# tb_core.u_sdram32 : at time 41387.0 ns WRITE: Bank = 3 Row = 271, Col = 195, Data = 73fa7de7
|
# tb_core.u_sdram32 : at time 42587.0 ns WRITE: Bank = 3 Row = 271, Col = 195, Data = 73fa7de7
|
# Status: Burst-No: 28 Write Address: 0010fe9c WriteData: 73fa7de7
|
# Status: Burst-No: 28 Write Address: 0010fe9c WriteData: 73fa7de7
|
# tb_core.u_sdram32 : at time 41397.0 ns WRITE: Bank = 3 Row = 271, Col = 196, Data = 123aaf24
|
# tb_core.u_sdram32 : at time 42597.0 ns WRITE: Bank = 3 Row = 271, Col = 196, Data = 123aaf24
|
# Status: Burst-No: 29 Write Address: 0010fe9c WriteData: 123aaf24
|
# Status: Burst-No: 29 Write Address: 0010fe9c WriteData: 123aaf24
|
# tb_core.u_sdram32 : at time 41407.0 ns WRITE: Bank = 3 Row = 271, Col = 197, Data = 41b5d583
|
# tb_core.u_sdram32 : at time 42607.0 ns WRITE: Bank = 3 Row = 271, Col = 197, Data = 41b5d583
|
# Status: Burst-No: 30 Write Address: 0010fe9c WriteData: 41b5d583
|
# Status: Burst-No: 30 Write Address: 0010fe9c WriteData: 41b5d583
|
# tb_core.u_sdram32 : at time 41417.0 ns WRITE: Bank = 3 Row = 271, Col = 198, Data = adee005b
|
# tb_core.u_sdram32 : at time 42617.0 ns WRITE: Bank = 3 Row = 271, Col = 198, Data = adee005b
|
# Status: Burst-No: 31 Write Address: 0010fe9c WriteData: adee005b
|
# Status: Burst-No: 31 Write Address: 0010fe9c WriteData: adee005b
|
# tb_core.u_sdram32 : at time 41427.0 ns WRITE: Bank = 3 Row = 271, Col = 199, Data = 5cdea1b9
|
# tb_core.u_sdram32 : at time 42627.0 ns WRITE: Bank = 3 Row = 271, Col = 199, Data = 5cdea1b9
|
# Status: Burst-No: 32 Write Address: 0010fe9c WriteData: 5cdea1b9
|
# Status: Burst-No: 32 Write Address: 0010fe9c WriteData: 5cdea1b9
|
# tb_core.u_sdram32 : at time 41437.0 ns WRITE: Bank = 3 Row = 271, Col = 200, Data = 4afebf95
|
# tb_core.u_sdram32 : at time 42637.0 ns WRITE: Bank = 3 Row = 271, Col = 200, Data = 4afebf95
|
# Status: Burst-No: 33 Write Address: 0010fe9c WriteData: 4afebf95
|
# Status: Burst-No: 33 Write Address: 0010fe9c WriteData: 4afebf95
|
# tb_core.u_sdram32 : at time 41447.0 ns WRITE: Bank = 3 Row = 271, Col = 201, Data = bb934a77
|
# tb_core.u_sdram32 : at time 42647.0 ns WRITE: Bank = 3 Row = 271, Col = 201, Data = bb934a77
|
# Status: Burst-No: 34 Write Address: 0010fe9c WriteData: bb934a77
|
# Status: Burst-No: 34 Write Address: 0010fe9c WriteData: bb934a77
|
# tb_core.u_sdram32 : at time 41457.0 ns WRITE: Bank = 3 Row = 271, Col = 202, Data = f8da1af1
|
# tb_core.u_sdram32 : at time 42657.0 ns WRITE: Bank = 3 Row = 271, Col = 202, Data = f8da1af1
|
# Status: Burst-No: 35 Write Address: 0010fe9c WriteData: f8da1af1
|
# Status: Burst-No: 35 Write Address: 0010fe9c WriteData: f8da1af1
|
# tb_core.u_sdram32 : at time 41467.0 ns WRITE: Bank = 3 Row = 271, Col = 203, Data = 732c5fe6
|
# tb_core.u_sdram32 : at time 42667.0 ns WRITE: Bank = 3 Row = 271, Col = 203, Data = 732c5fe6
|
# Status: Burst-No: 36 Write Address: 0010fe9c WriteData: 732c5fe6
|
# Status: Burst-No: 36 Write Address: 0010fe9c WriteData: 732c5fe6
|
# tb_core.u_sdram32 : at time 41477.0 ns WRITE: Bank = 3 Row = 271, Col = 204, Data = d7e1aeaf
|
# tb_core.u_sdram32 : at time 42677.0 ns WRITE: Bank = 3 Row = 271, Col = 204, Data = d7e1aeaf
|
# Status: Burst-No: 37 Write Address: 0010fe9c WriteData: d7e1aeaf
|
# Status: Burst-No: 37 Write Address: 0010fe9c WriteData: d7e1aeaf
|
# tb_core.u_sdram32 : at time 41487.0 ns WRITE: Bank = 3 Row = 271, Col = 205, Data = 0238e104
|
# tb_core.u_sdram32 : at time 42687.0 ns WRITE: Bank = 3 Row = 271, Col = 205, Data = 0238e104
|
# Status: Burst-No: 38 Write Address: 0010fe9c WriteData: 0238e104
|
# Status: Burst-No: 38 Write Address: 0010fe9c WriteData: 0238e104
|
# tb_core.u_sdram32 : at time 41497.0 ns WRITE: Bank = 3 Row = 271, Col = 206, Data = 89646012
|
# tb_core.u_sdram32 : at time 42697.0 ns WRITE: Bank = 3 Row = 271, Col = 206, Data = 89646012
|
# Status: Burst-No: 39 Write Address: 0010fe9c WriteData: 89646012
|
# Status: Burst-No: 39 Write Address: 0010fe9c WriteData: 89646012
|
# tb_core.u_sdram32 : at time 41507.0 ns WRITE: Bank = 3 Row = 271, Col = 207, Data = 7e29b3fc
|
# tb_core.u_sdram32 : at time 42707.0 ns WRITE: Bank = 3 Row = 271, Col = 207, Data = 7e29b3fc
|
# Status: Burst-No: 40 Write Address: 0010fe9c WriteData: 7e29b3fc
|
# Status: Burst-No: 40 Write Address: 0010fe9c WriteData: 7e29b3fc
|
# tb_core.u_sdram32 : at time 41517.0 ns WRITE: Bank = 3 Row = 271, Col = 208, Data = d5ba48ab
|
# tb_core.u_sdram32 : at time 42717.0 ns WRITE: Bank = 3 Row = 271, Col = 208, Data = d5ba48ab
|
# Status: Burst-No: 41 Write Address: 0010fe9c WriteData: d5ba48ab
|
# Status: Burst-No: 41 Write Address: 0010fe9c WriteData: d5ba48ab
|
# tb_core.u_sdram32 : at time 41527.0 ns WRITE: Bank = 3 Row = 271, Col = 209, Data = e203f0c4
|
# tb_core.u_sdram32 : at time 42727.0 ns WRITE: Bank = 3 Row = 271, Col = 209, Data = e203f0c4
|
# Status: Burst-No: 42 Write Address: 0010fe9c WriteData: e203f0c4
|
# Status: Burst-No: 42 Write Address: 0010fe9c WriteData: e203f0c4
|
# tb_core.u_sdram32 : at time 41537.0 ns WRITE: Bank = 3 Row = 271, Col = 210, Data = 1ffb813f
|
# tb_core.u_sdram32 : at time 42737.0 ns WRITE: Bank = 3 Row = 271, Col = 210, Data = 1ffb813f
|
# Status: Burst-No: 43 Write Address: 0010fe9c WriteData: 1ffb813f
|
# Status: Burst-No: 43 Write Address: 0010fe9c WriteData: 1ffb813f
|
# tb_core.u_sdram32 : at time 41547.0 ns WRITE: Bank = 3 Row = 271, Col = 211, Data = e13256c2
|
# tb_core.u_sdram32 : at time 42747.0 ns WRITE: Bank = 3 Row = 271, Col = 211, Data = e13256c2
|
# Status: Burst-No: 44 Write Address: 0010fe9c WriteData: e13256c2
|
# Status: Burst-No: 44 Write Address: 0010fe9c WriteData: e13256c2
|
# tb_core.u_sdram32 : at time 41557.0 ns WRITE: Bank = 3 Row = 271, Col = 212, Data = 398a1973
|
# tb_core.u_sdram32 : at time 42757.0 ns WRITE: Bank = 3 Row = 271, Col = 212, Data = 398a1973
|
# Status: Burst-No: 45 Write Address: 0010fe9c WriteData: 398a1973
|
# Status: Burst-No: 45 Write Address: 0010fe9c WriteData: 398a1973
|
# tb_core.u_sdram32 : at time 41567.0 ns WRITE: Bank = 3 Row = 271, Col = 213, Data = 2d4d9b5a
|
# tb_core.u_sdram32 : at time 42767.0 ns WRITE: Bank = 3 Row = 271, Col = 213, Data = 2d4d9b5a
|
# Status: Burst-No: 46 Write Address: 0010fe9c WriteData: 2d4d9b5a
|
# Status: Burst-No: 46 Write Address: 0010fe9c WriteData: 2d4d9b5a
|
# tb_core.u_sdram32 : at time 41577.0 ns WRITE: Bank = 3 Row = 271, Col = 214, Data = d066e4a0
|
# tb_core.u_sdram32 : at time 42777.0 ns WRITE: Bank = 3 Row = 271, Col = 214, Data = d066e4a0
|
# Status: Burst-No: 47 Write Address: 0010fe9c WriteData: d066e4a0
|
# Status: Burst-No: 47 Write Address: 0010fe9c WriteData: d066e4a0
|
# tb_core.u_sdram32 : at time 41587.0 ns WRITE: Bank = 3 Row = 271, Col = 215, Data = ff73cafe
|
# tb_core.u_sdram32 : at time 42787.0 ns WRITE: Bank = 3 Row = 271, Col = 215, Data = ff73cafe
|
# Status: Burst-No: 48 Write Address: 0010fe9c WriteData: ff73cafe
|
# Status: Burst-No: 48 Write Address: 0010fe9c WriteData: ff73cafe
|
# tb_core.u_sdram32 : at time 41597.0 ns WRITE: Bank = 3 Row = 271, Col = 216, Data = 3a096b74
|
# tb_core.u_sdram32 : at time 42797.0 ns WRITE: Bank = 3 Row = 271, Col = 216, Data = 3a096b74
|
# Status: Burst-No: 49 Write Address: 0010fe9c WriteData: 3a096b74
|
# Status: Burst-No: 49 Write Address: 0010fe9c WriteData: 3a096b74
|
# tb_core.u_sdram32 : at time 41607.0 ns WRITE: Bank = 3 Row = 271, Col = 217, Data = 5d86b7bb
|
# tb_core.u_sdram32 : at time 42807.0 ns WRITE: Bank = 3 Row = 271, Col = 217, Data = 5d86b7bb
|
# Status: Burst-No: 50 Write Address: 0010fe9c WriteData: 5d86b7bb
|
# Status: Burst-No: 50 Write Address: 0010fe9c WriteData: 5d86b7bb
|
# tb_core.u_sdram32 : at time 41617.0 ns WRITE: Bank = 3 Row = 271, Col = 218, Data = 7132bbe2
|
# tb_core.u_sdram32 : at time 42817.0 ns WRITE: Bank = 3 Row = 271, Col = 218, Data = 7132bbe2
|
# Status: Burst-No: 51 Write Address: 0010fe9c WriteData: 7132bbe2
|
# Status: Burst-No: 51 Write Address: 0010fe9c WriteData: 7132bbe2
|
# tb_core.u_sdram32 : at time 41627.0 ns WRITE: Bank = 3 Row = 271, Col = 219, Data = f16948e2
|
# tb_core.u_sdram32 : at time 42827.0 ns WRITE: Bank = 3 Row = 271, Col = 219, Data = f16948e2
|
# Status: Burst-No: 52 Write Address: 0010fe9c WriteData: f16948e2
|
# Status: Burst-No: 52 Write Address: 0010fe9c WriteData: f16948e2
|
# tb_core.u_sdram32 : at time 41637.0 ns WRITE: Bank = 3 Row = 271, Col = 220, Data = eff34cdf
|
# tb_core.u_sdram32 : at time 42837.0 ns WRITE: Bank = 3 Row = 271, Col = 220, Data = eff34cdf
|
# Status: Burst-No: 53 Write Address: 0010fe9c WriteData: eff34cdf
|
# Status: Burst-No: 53 Write Address: 0010fe9c WriteData: eff34cdf
|
# tb_core.u_sdram32 : at time 41647.0 ns WRITE: Bank = 3 Row = 271, Col = 221, Data = cc13e298
|
# tb_core.u_sdram32 : at time 42847.0 ns WRITE: Bank = 3 Row = 271, Col = 221, Data = cc13e298
|
# Status: Burst-No: 54 Write Address: 0010fe9c WriteData: cc13e298
|
# Status: Burst-No: 54 Write Address: 0010fe9c WriteData: cc13e298
|
# tb_core.u_sdram32 : at time 41657.0 ns WRITE: Bank = 3 Row = 271, Col = 222, Data = 4fdbed9f
|
# tb_core.u_sdram32 : at time 42857.0 ns WRITE: Bank = 3 Row = 271, Col = 222, Data = 4fdbed9f
|
# Status: Burst-No: 55 Write Address: 0010fe9c WriteData: 4fdbed9f
|
# Status: Burst-No: 55 Write Address: 0010fe9c WriteData: 4fdbed9f
|
# tb_core.u_sdram32 : at time 41667.0 ns WRITE: Bank = 3 Row = 271, Col = 223, Data = 0817cb10
|
# tb_core.u_sdram32 : at time 42867.0 ns WRITE: Bank = 3 Row = 271, Col = 223, Data = 0817cb10
|
# Status: Burst-No: 56 Write Address: 0010fe9c WriteData: 0817cb10
|
# Status: Burst-No: 56 Write Address: 0010fe9c WriteData: 0817cb10
|
# tb_core.u_sdram32 : at time 41677.0 ns WRITE: Bank = 3 Row = 271, Col = 224, Data = 791189f2
|
# tb_core.u_sdram32 : at time 42877.0 ns WRITE: Bank = 3 Row = 271, Col = 224, Data = 791189f2
|
# Status: Burst-No: 57 Write Address: 0010fe9c WriteData: 791189f2
|
# Status: Burst-No: 57 Write Address: 0010fe9c WriteData: 791189f2
|
# tb_core.u_sdram32 : at time 41687.0 ns WRITE: Bank = 3 Row = 271, Col = 225, Data = 5ee97bbd
|
# tb_core.u_sdram32 : at time 42887.0 ns WRITE: Bank = 3 Row = 271, Col = 225, Data = 5ee97bbd
|
# Status: Burst-No: 58 Write Address: 0010fe9c WriteData: 5ee97bbd
|
# Status: Burst-No: 58 Write Address: 0010fe9c WriteData: 5ee97bbd
|
# tb_core.u_sdram32 : at time 41697.0 ns WRITE: Bank = 3 Row = 271, Col = 226, Data = 55bc27ab
|
# tb_core.u_sdram32 : at time 42897.0 ns WRITE: Bank = 3 Row = 271, Col = 226, Data = 55bc27ab
|
# Status: Burst-No: 59 Write Address: 0010fe9c WriteData: 55bc27ab
|
# Status: Burst-No: 59 Write Address: 0010fe9c WriteData: 55bc27ab
|
# tb_core.u_sdram32 : at time 41707.0 ns WRITE: Bank = 3 Row = 271, Col = 227, Data = 5a0a0fb4
|
# tb_core.u_sdram32 : at time 42907.0 ns WRITE: Bank = 3 Row = 271, Col = 227, Data = 5a0a0fb4
|
# Status: Burst-No: 60 Write Address: 0010fe9c WriteData: 5a0a0fb4
|
# Status: Burst-No: 60 Write Address: 0010fe9c WriteData: 5a0a0fb4
|
# tb_core.u_sdram32 : at time 41717.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 42917.0 ns BST : Burst Terminate
|
# Write Address: 0008ac54, Burst Size: 10
|
# Write Address: 0008ac54, Burst Size: 10
|
# tb_core.u_sdram32 : at time 41857.0 ns ACT : Bank = 3 Row = 138
|
# tb_core.u_sdram32 : at time 43057.0 ns ACT : Bank = 3 Row = 138
|
# tb_core.u_sdram32 : at time 41887.0 ns WRITE: Bank = 3 Row = 138, Col = 21, Data = 89b5d413
|
# tb_core.u_sdram32 : at time 43087.0 ns WRITE: Bank = 3 Row = 138, Col = 21, Data = 89b5d413
|
# Status: Burst-No: 0 Write Address: 0008ac54 WriteData: 89b5d413
|
# Status: Burst-No: 0 Write Address: 0008ac54 WriteData: 89b5d413
|
# tb_core.u_sdram32 : at time 41897.0 ns WRITE: Bank = 3 Row = 138, Col = 22, Data = 560c91ac
|
# tb_core.u_sdram32 : at time 43097.0 ns WRITE: Bank = 3 Row = 138, Col = 22, Data = 560c91ac
|
# Status: Burst-No: 1 Write Address: 0008ac54 WriteData: 560c91ac
|
# Status: Burst-No: 1 Write Address: 0008ac54 WriteData: 560c91ac
|
# tb_core.u_sdram32 : at time 41907.0 ns WRITE: Bank = 3 Row = 138, Col = 23, Data = 1ae40335
|
# tb_core.u_sdram32 : at time 43107.0 ns WRITE: Bank = 3 Row = 138, Col = 23, Data = 1ae40335
|
# Status: Burst-No: 2 Write Address: 0008ac54 WriteData: 1ae40335
|
# Status: Burst-No: 2 Write Address: 0008ac54 WriteData: 1ae40335
|
# tb_core.u_sdram32 : at time 41917.0 ns WRITE: Bank = 3 Row = 138, Col = 24, Data = 1df61f3b
|
# tb_core.u_sdram32 : at time 43117.0 ns WRITE: Bank = 3 Row = 138, Col = 24, Data = 1df61f3b
|
# Status: Burst-No: 3 Write Address: 0008ac54 WriteData: 1df61f3b
|
# Status: Burst-No: 3 Write Address: 0008ac54 WriteData: 1df61f3b
|
# tb_core.u_sdram32 : at time 41927.0 ns WRITE: Bank = 3 Row = 138, Col = 25, Data = 9aa02435
|
# tb_core.u_sdram32 : at time 43127.0 ns WRITE: Bank = 3 Row = 138, Col = 25, Data = 9aa02435
|
# Status: Burst-No: 4 Write Address: 0008ac54 WriteData: 9aa02435
|
# Status: Burst-No: 4 Write Address: 0008ac54 WriteData: 9aa02435
|
# tb_core.u_sdram32 : at time 41937.0 ns WRITE: Bank = 3 Row = 138, Col = 26, Data = 17a98d2f
|
# tb_core.u_sdram32 : at time 43137.0 ns WRITE: Bank = 3 Row = 138, Col = 26, Data = 17a98d2f
|
# Status: Burst-No: 5 Write Address: 0008ac54 WriteData: 17a98d2f
|
# Status: Burst-No: 5 Write Address: 0008ac54 WriteData: 17a98d2f
|
# tb_core.u_sdram32 : at time 41947.0 ns WRITE: Bank = 3 Row = 138, Col = 27, Data = 1a619934
|
# tb_core.u_sdram32 : at time 43147.0 ns WRITE: Bank = 3 Row = 138, Col = 27, Data = 1a619934
|
# Status: Burst-No: 6 Write Address: 0008ac54 WriteData: 1a619934
|
# Status: Burst-No: 6 Write Address: 0008ac54 WriteData: 1a619934
|
# tb_core.u_sdram32 : at time 41957.0 ns WRITE: Bank = 3 Row = 138, Col = 28, Data = aae0a255
|
# tb_core.u_sdram32 : at time 43157.0 ns WRITE: Bank = 3 Row = 138, Col = 28, Data = aae0a255
|
# Status: Burst-No: 7 Write Address: 0008ac54 WriteData: aae0a255
|
# Status: Burst-No: 7 Write Address: 0008ac54 WriteData: aae0a255
|
# tb_core.u_sdram32 : at time 41967.0 ns WRITE: Bank = 3 Row = 138, Col = 29, Data = de7302bc
|
# tb_core.u_sdram32 : at time 43167.0 ns WRITE: Bank = 3 Row = 138, Col = 29, Data = de7302bc
|
# Status: Burst-No: 8 Write Address: 0008ac54 WriteData: de7302bc
|
# Status: Burst-No: 8 Write Address: 0008ac54 WriteData: de7302bc
|
# tb_core.u_sdram32 : at time 41977.0 ns WRITE: Bank = 3 Row = 138, Col = 30, Data = f964fef2
|
# tb_core.u_sdram32 : at time 43177.0 ns WRITE: Bank = 3 Row = 138, Col = 30, Data = f964fef2
|
# Status: Burst-No: 9 Write Address: 0008ac54 WriteData: f964fef2
|
# Status: Burst-No: 9 Write Address: 0008ac54 WriteData: f964fef2
|
# tb_core.u_sdram32 : at time 41987.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 43187.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 42127.0 ns ACT : Bank = 3 Row = 271
|
# tb_core.u_sdram32 : at time 43327.0 ns ACT : Bank = 3 Row = 271
|
# tb_core.u_sdram32 : at time 42183.0 ns READ : Bank = 3 Row = 271, Col = 167, Data = d7e31eaf
|
# tb_core.u_sdram32 : at time 43383.0 ns READ : Bank = 3 Row = 271, Col = 167, Data = d7e31eaf
|
# tb_core.u_sdram32 : at time 42193.0 ns READ : Bank = 3 Row = 271, Col = 168, Data = 872d2c0e
|
# tb_core.u_sdram32 : at time 43393.0 ns READ : Bank = 3 Row = 271, Col = 168, Data = 872d2c0e
|
# READ STATUS: Burst-No: 0 Addr: 0010fe9c Rxd: d7e31eaf
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# READ STATUS: Burst-No: 0 Addr: 0010fe9c Rxd: d7e31eaf
|
# tb_core.u_sdram32 : at time 42203.0 ns READ : Bank = 3 Row = 271, Col = 169, Data = b4e46669
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# tb_core.u_sdram32 : at time 43403.0 ns READ : Bank = 3 Row = 271, Col = 169, Data = b4e46669
|
# READ STATUS: Burst-No: 1 Addr: 0010fe9e Rxd: 872d2c0e
|
# READ STATUS: Burst-No: 1 Addr: 0010fe9e Rxd: 872d2c0e
|
# tb_core.u_sdram32 : at time 42213.0 ns READ : Bank = 3 Row = 271, Col = 170, Data = d95b40b2
|
# tb_core.u_sdram32 : at time 43413.0 ns READ : Bank = 3 Row = 271, Col = 170, Data = d95b40b2
|
# READ STATUS: Burst-No: 2 Addr: 0010fea0 Rxd: b4e46669
|
# READ STATUS: Burst-No: 2 Addr: 0010fea0 Rxd: b4e46669
|
# tb_core.u_sdram32 : at time 42223.0 ns READ : Bank = 3 Row = 271, Col = 171, Data = ef209ede
|
# tb_core.u_sdram32 : at time 43423.0 ns READ : Bank = 3 Row = 271, Col = 171, Data = ef209ede
|
# READ STATUS: Burst-No: 3 Addr: 0010fea2 Rxd: d95b40b2
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# READ STATUS: Burst-No: 3 Addr: 0010fea2 Rxd: d95b40b2
|
# tb_core.u_sdram32 : at time 42233.0 ns READ : Bank = 3 Row = 271, Col = 172, Data = c2e87485
|
# tb_core.u_sdram32 : at time 43433.0 ns READ : Bank = 3 Row = 271, Col = 172, Data = c2e87485
|
# READ STATUS: Burst-No: 4 Addr: 0010fea4 Rxd: ef209ede
|
# READ STATUS: Burst-No: 4 Addr: 0010fea4 Rxd: ef209ede
|
# tb_core.u_sdram32 : at time 42243.0 ns READ : Bank = 3 Row = 271, Col = 173, Data = 555c0faa
|
# tb_core.u_sdram32 : at time 43443.0 ns READ : Bank = 3 Row = 271, Col = 173, Data = 555c0faa
|
# READ STATUS: Burst-No: 5 Addr: 0010fea6 Rxd: c2e87485
|
# READ STATUS: Burst-No: 5 Addr: 0010fea6 Rxd: c2e87485
|
# tb_core.u_sdram32 : at time 42253.0 ns READ : Bank = 3 Row = 271, Col = 174, Data = 1407f128
|
# tb_core.u_sdram32 : at time 43453.0 ns READ : Bank = 3 Row = 271, Col = 174, Data = 1407f128
|
# READ STATUS: Burst-No: 6 Addr: 0010fea8 Rxd: 555c0faa
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# READ STATUS: Burst-No: 6 Addr: 0010fea8 Rxd: 555c0faa
|
# tb_core.u_sdram32 : at time 42263.0 ns READ : Bank = 3 Row = 271, Col = 175, Data = 610ed5c2
|
# tb_core.u_sdram32 : at time 43463.0 ns READ : Bank = 3 Row = 271, Col = 175, Data = 610ed5c2
|
# READ STATUS: Burst-No: 7 Addr: 0010feaa Rxd: 1407f128
|
# READ STATUS: Burst-No: 7 Addr: 0010feaa Rxd: 1407f128
|
# tb_core.u_sdram32 : at time 42273.0 ns READ : Bank = 3 Row = 271, Col = 176, Data = 4d20099a
|
# tb_core.u_sdram32 : at time 43473.0 ns READ : Bank = 3 Row = 271, Col = 176, Data = 4d20099a
|
# READ STATUS: Burst-No: 8 Addr: 0010feac Rxd: 610ed5c2
|
# READ STATUS: Burst-No: 8 Addr: 0010feac Rxd: 610ed5c2
|
# tb_core.u_sdram32 : at time 42283.0 ns READ : Bank = 3 Row = 271, Col = 177, Data = 69e751d3
|
# tb_core.u_sdram32 : at time 43483.0 ns READ : Bank = 3 Row = 271, Col = 177, Data = 69e751d3
|
# READ STATUS: Burst-No: 9 Addr: 0010feae Rxd: 4d20099a
|
# READ STATUS: Burst-No: 9 Addr: 0010feae Rxd: 4d20099a
|
# tb_core.u_sdram32 : at time 42293.0 ns READ : Bank = 3 Row = 271, Col = 178, Data = dd111aba
|
# tb_core.u_sdram32 : at time 43493.0 ns READ : Bank = 3 Row = 271, Col = 178, Data = dd111aba
|
# READ STATUS: Burst-No: 10 Addr: 0010feb0 Rxd: 69e751d3
|
# READ STATUS: Burst-No: 10 Addr: 0010feb0 Rxd: 69e751d3
|
# tb_core.u_sdram32 : at time 42303.0 ns READ : Bank = 3 Row = 271, Col = 179, Data = fdeb7cfb
|
# tb_core.u_sdram32 : at time 43503.0 ns READ : Bank = 3 Row = 271, Col = 179, Data = fdeb7cfb
|
# READ STATUS: Burst-No: 11 Addr: 0010feb2 Rxd: dd111aba
|
# READ STATUS: Burst-No: 11 Addr: 0010feb2 Rxd: dd111aba
|
# tb_core.u_sdram32 : at time 42313.0 ns READ : Bank = 3 Row = 271, Col = 180, Data = c5cf728b
|
# tb_core.u_sdram32 : at time 43513.0 ns READ : Bank = 3 Row = 271, Col = 180, Data = c5cf728b
|
# READ STATUS: Burst-No: 12 Addr: 0010feb4 Rxd: fdeb7cfb
|
# READ STATUS: Burst-No: 12 Addr: 0010feb4 Rxd: fdeb7cfb
|
# tb_core.u_sdram32 : at time 42323.0 ns READ : Bank = 3 Row = 271, Col = 181, Data = 61114dc2
|
# tb_core.u_sdram32 : at time 43523.0 ns READ : Bank = 3 Row = 271, Col = 181, Data = 61114dc2
|
# READ STATUS: Burst-No: 13 Addr: 0010feb6 Rxd: c5cf728b
|
# READ STATUS: Burst-No: 13 Addr: 0010feb6 Rxd: c5cf728b
|
# tb_core.u_sdram32 : at time 42333.0 ns READ : Bank = 3 Row = 271, Col = 182, Data = e64828cc
|
# tb_core.u_sdram32 : at time 43533.0 ns READ : Bank = 3 Row = 271, Col = 182, Data = e64828cc
|
# READ STATUS: Burst-No: 14 Addr: 0010feb8 Rxd: 61114dc2
|
# READ STATUS: Burst-No: 14 Addr: 0010feb8 Rxd: 61114dc2
|
# tb_core.u_sdram32 : at time 42343.0 ns READ : Bank = 3 Row = 271, Col = 183, Data = 38e61371
|
# tb_core.u_sdram32 : at time 43543.0 ns READ : Bank = 3 Row = 271, Col = 183, Data = 38e61371
|
# READ STATUS: Burst-No: 15 Addr: 0010feba Rxd: e64828cc
|
# READ STATUS: Burst-No: 15 Addr: 0010feba Rxd: e64828cc
|
# tb_core.u_sdram32 : at time 42353.0 ns READ : Bank = 3 Row = 271, Col = 184, Data = 4f49019e
|
# tb_core.u_sdram32 : at time 43553.0 ns READ : Bank = 3 Row = 271, Col = 184, Data = 4f49019e
|
# READ STATUS: Burst-No: 16 Addr: 0010febc Rxd: 38e61371
|
# READ STATUS: Burst-No: 16 Addr: 0010febc Rxd: 38e61371
|
# tb_core.u_sdram32 : at time 42363.0 ns READ : Bank = 3 Row = 271, Col = 185, Data = 309cdb61
|
# tb_core.u_sdram32 : at time 43563.0 ns READ : Bank = 3 Row = 271, Col = 185, Data = 309cdb61
|
# READ STATUS: Burst-No: 17 Addr: 0010febe Rxd: 4f49019e
|
# READ STATUS: Burst-No: 17 Addr: 0010febe Rxd: 4f49019e
|
# tb_core.u_sdram32 : at time 42373.0 ns READ : Bank = 3 Row = 271, Col = 186, Data = bde3487b
|
# tb_core.u_sdram32 : at time 43573.0 ns READ : Bank = 3 Row = 271, Col = 186, Data = bde3487b
|
# READ STATUS: Burst-No: 18 Addr: 0010fec0 Rxd: 309cdb61
|
# READ STATUS: Burst-No: 18 Addr: 0010fec0 Rxd: 309cdb61
|
# tb_core.u_sdram32 : at time 42383.0 ns READ : Bank = 3 Row = 271, Col = 187, Data = df9bd0bf
|
# tb_core.u_sdram32 : at time 43583.0 ns READ : Bank = 3 Row = 271, Col = 187, Data = df9bd0bf
|
# READ STATUS: Burst-No: 19 Addr: 0010fec2 Rxd: bde3487b
|
# READ STATUS: Burst-No: 19 Addr: 0010fec2 Rxd: bde3487b
|
# tb_core.u_sdram32 : at time 42393.0 ns READ : Bank = 3 Row = 271, Col = 188, Data = c881bc91
|
# tb_core.u_sdram32 : at time 43593.0 ns READ : Bank = 3 Row = 271, Col = 188, Data = c881bc91
|
# READ STATUS: Burst-No: 20 Addr: 0010fec4 Rxd: df9bd0bf
|
# READ STATUS: Burst-No: 20 Addr: 0010fec4 Rxd: df9bd0bf
|
# tb_core.u_sdram32 : at time 42403.0 ns READ : Bank = 3 Row = 271, Col = 189, Data = e06098c0
|
# tb_core.u_sdram32 : at time 43603.0 ns READ : Bank = 3 Row = 271, Col = 189, Data = e06098c0
|
# READ STATUS: Burst-No: 21 Addr: 0010fec6 Rxd: c881bc91
|
# READ STATUS: Burst-No: 21 Addr: 0010fec6 Rxd: c881bc91
|
# tb_core.u_sdram32 : at time 42413.0 ns READ : Bank = 3 Row = 271, Col = 190, Data = 2ca96359
|
# tb_core.u_sdram32 : at time 43613.0 ns READ : Bank = 3 Row = 271, Col = 190, Data = 2ca96359
|
# READ STATUS: Burst-No: 22 Addr: 0010fec8 Rxd: e06098c0
|
# READ STATUS: Burst-No: 22 Addr: 0010fec8 Rxd: e06098c0
|
# tb_core.u_sdram32 : at time 42423.0 ns READ : Bank = 3 Row = 271, Col = 191, Data = bf53b47e
|
# tb_core.u_sdram32 : at time 43623.0 ns READ : Bank = 3 Row = 271, Col = 191, Data = bf53b47e
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# READ STATUS: Burst-No: 23 Addr: 0010feca Rxd: 2ca96359
|
# READ STATUS: Burst-No: 23 Addr: 0010feca Rxd: 2ca96359
|
# tb_core.u_sdram32 : at time 42433.0 ns READ : Bank = 3 Row = 271, Col = 192, Data = 2a1d7354
|
# tb_core.u_sdram32 : at time 43633.0 ns READ : Bank = 3 Row = 271, Col = 192, Data = 2a1d7354
|
# READ STATUS: Burst-No: 24 Addr: 0010fecc Rxd: bf53b47e
|
# READ STATUS: Burst-No: 24 Addr: 0010fecc Rxd: bf53b47e
|
# tb_core.u_sdram32 : at time 42443.0 ns READ : Bank = 3 Row = 271, Col = 193, Data = a8e2e251
|
# tb_core.u_sdram32 : at time 43643.0 ns READ : Bank = 3 Row = 271, Col = 193, Data = a8e2e251
|
# READ STATUS: Burst-No: 25 Addr: 0010fece Rxd: 2a1d7354
|
# READ STATUS: Burst-No: 25 Addr: 0010fece Rxd: 2a1d7354
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# tb_core.u_sdram32 : at time 42453.0 ns READ : Bank = 3 Row = 271, Col = 194, Data = a4de2849
|
# tb_core.u_sdram32 : at time 43653.0 ns READ : Bank = 3 Row = 271, Col = 194, Data = a4de2849
|
# READ STATUS: Burst-No: 26 Addr: 0010fed0 Rxd: a8e2e251
|
# READ STATUS: Burst-No: 26 Addr: 0010fed0 Rxd: a8e2e251
|
# tb_core.u_sdram32 : at time 42463.0 ns READ : Bank = 3 Row = 271, Col = 195, Data = 73fa7de7
|
# tb_core.u_sdram32 : at time 43663.0 ns READ : Bank = 3 Row = 271, Col = 195, Data = 73fa7de7
|
# READ STATUS: Burst-No: 27 Addr: 0010fed2 Rxd: a4de2849
|
# READ STATUS: Burst-No: 27 Addr: 0010fed2 Rxd: a4de2849
|
# tb_core.u_sdram32 : at time 42473.0 ns READ : Bank = 3 Row = 271, Col = 196, Data = 123aaf24
|
# tb_core.u_sdram32 : at time 43673.0 ns READ : Bank = 3 Row = 271, Col = 196, Data = 123aaf24
|
# READ STATUS: Burst-No: 28 Addr: 0010fed4 Rxd: 73fa7de7
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# READ STATUS: Burst-No: 28 Addr: 0010fed4 Rxd: 73fa7de7
|
# tb_core.u_sdram32 : at time 42483.0 ns READ : Bank = 3 Row = 271, Col = 197, Data = 41b5d583
|
# tb_core.u_sdram32 : at time 43683.0 ns READ : Bank = 3 Row = 271, Col = 197, Data = 41b5d583
|
# READ STATUS: Burst-No: 29 Addr: 0010fed6 Rxd: 123aaf24
|
# READ STATUS: Burst-No: 29 Addr: 0010fed6 Rxd: 123aaf24
|
# tb_core.u_sdram32 : at time 42493.0 ns READ : Bank = 3 Row = 271, Col = 198, Data = adee005b
|
# tb_core.u_sdram32 : at time 43693.0 ns READ : Bank = 3 Row = 271, Col = 198, Data = adee005b
|
# READ STATUS: Burst-No: 30 Addr: 0010fed8 Rxd: 41b5d583
|
# READ STATUS: Burst-No: 30 Addr: 0010fed8 Rxd: 41b5d583
|
# tb_core.u_sdram32 : at time 42503.0 ns READ : Bank = 3 Row = 271, Col = 199, Data = 5cdea1b9
|
# tb_core.u_sdram32 : at time 43703.0 ns READ : Bank = 3 Row = 271, Col = 199, Data = 5cdea1b9
|
# READ STATUS: Burst-No: 31 Addr: 0010feda Rxd: adee005b
|
# READ STATUS: Burst-No: 31 Addr: 0010feda Rxd: adee005b
|
# tb_core.u_sdram32 : at time 42513.0 ns READ : Bank = 3 Row = 271, Col = 200, Data = 4afebf95
|
# tb_core.u_sdram32 : at time 43713.0 ns READ : Bank = 3 Row = 271, Col = 200, Data = 4afebf95
|
# READ STATUS: Burst-No: 32 Addr: 0010fedc Rxd: 5cdea1b9
|
# READ STATUS: Burst-No: 32 Addr: 0010fedc Rxd: 5cdea1b9
|
# tb_core.u_sdram32 : at time 42523.0 ns READ : Bank = 3 Row = 271, Col = 201, Data = bb934a77
|
# tb_core.u_sdram32 : at time 43723.0 ns READ : Bank = 3 Row = 271, Col = 201, Data = bb934a77
|
# READ STATUS: Burst-No: 33 Addr: 0010fede Rxd: 4afebf95
|
# READ STATUS: Burst-No: 33 Addr: 0010fede Rxd: 4afebf95
|
# tb_core.u_sdram32 : at time 42533.0 ns READ : Bank = 3 Row = 271, Col = 202, Data = f8da1af1
|
# tb_core.u_sdram32 : at time 43733.0 ns READ : Bank = 3 Row = 271, Col = 202, Data = f8da1af1
|
# READ STATUS: Burst-No: 34 Addr: 0010fee0 Rxd: bb934a77
|
# READ STATUS: Burst-No: 34 Addr: 0010fee0 Rxd: bb934a77
|
# tb_core.u_sdram32 : at time 42543.0 ns READ : Bank = 3 Row = 271, Col = 203, Data = 732c5fe6
|
# tb_core.u_sdram32 : at time 43743.0 ns READ : Bank = 3 Row = 271, Col = 203, Data = 732c5fe6
|
# READ STATUS: Burst-No: 35 Addr: 0010fee2 Rxd: f8da1af1
|
# READ STATUS: Burst-No: 35 Addr: 0010fee2 Rxd: f8da1af1
|
# tb_core.u_sdram32 : at time 42553.0 ns READ : Bank = 3 Row = 271, Col = 204, Data = d7e1aeaf
|
# tb_core.u_sdram32 : at time 43753.0 ns READ : Bank = 3 Row = 271, Col = 204, Data = d7e1aeaf
|
# READ STATUS: Burst-No: 36 Addr: 0010fee4 Rxd: 732c5fe6
|
# READ STATUS: Burst-No: 36 Addr: 0010fee4 Rxd: 732c5fe6
|
# tb_core.u_sdram32 : at time 42563.0 ns READ : Bank = 3 Row = 271, Col = 205, Data = 0238e104
|
# tb_core.u_sdram32 : at time 43763.0 ns READ : Bank = 3 Row = 271, Col = 205, Data = 0238e104
|
# READ STATUS: Burst-No: 37 Addr: 0010fee6 Rxd: d7e1aeaf
|
# READ STATUS: Burst-No: 37 Addr: 0010fee6 Rxd: d7e1aeaf
|
# tb_core.u_sdram32 : at time 42573.0 ns READ : Bank = 3 Row = 271, Col = 206, Data = 89646012
|
# tb_core.u_sdram32 : at time 43773.0 ns READ : Bank = 3 Row = 271, Col = 206, Data = 89646012
|
# READ STATUS: Burst-No: 38 Addr: 0010fee8 Rxd: 0238e104
|
# READ STATUS: Burst-No: 38 Addr: 0010fee8 Rxd: 0238e104
|
# tb_core.u_sdram32 : at time 42583.0 ns READ : Bank = 3 Row = 271, Col = 207, Data = 7e29b3fc
|
# tb_core.u_sdram32 : at time 43783.0 ns READ : Bank = 3 Row = 271, Col = 207, Data = 7e29b3fc
|
# READ STATUS: Burst-No: 39 Addr: 0010feea Rxd: 89646012
|
# READ STATUS: Burst-No: 39 Addr: 0010feea Rxd: 89646012
|
# tb_core.u_sdram32 : at time 42593.0 ns READ : Bank = 3 Row = 271, Col = 208, Data = d5ba48ab
|
# tb_core.u_sdram32 : at time 43793.0 ns READ : Bank = 3 Row = 271, Col = 208, Data = d5ba48ab
|
# READ STATUS: Burst-No: 40 Addr: 0010feec Rxd: 7e29b3fc
|
# READ STATUS: Burst-No: 40 Addr: 0010feec Rxd: 7e29b3fc
|
# tb_core.u_sdram32 : at time 42603.0 ns READ : Bank = 3 Row = 271, Col = 209, Data = e203f0c4
|
# tb_core.u_sdram32 : at time 43803.0 ns READ : Bank = 3 Row = 271, Col = 209, Data = e203f0c4
|
# READ STATUS: Burst-No: 41 Addr: 0010feee Rxd: d5ba48ab
|
# READ STATUS: Burst-No: 41 Addr: 0010feee Rxd: d5ba48ab
|
# tb_core.u_sdram32 : at time 42613.0 ns READ : Bank = 3 Row = 271, Col = 210, Data = 1ffb813f
|
# tb_core.u_sdram32 : at time 43813.0 ns READ : Bank = 3 Row = 271, Col = 210, Data = 1ffb813f
|
# READ STATUS: Burst-No: 42 Addr: 0010fef0 Rxd: e203f0c4
|
# READ STATUS: Burst-No: 42 Addr: 0010fef0 Rxd: e203f0c4
|
# tb_core.u_sdram32 : at time 42623.0 ns READ : Bank = 3 Row = 271, Col = 211, Data = e13256c2
|
# tb_core.u_sdram32 : at time 43823.0 ns READ : Bank = 3 Row = 271, Col = 211, Data = e13256c2
|
# READ STATUS: Burst-No: 43 Addr: 0010fef2 Rxd: 1ffb813f
|
# READ STATUS: Burst-No: 43 Addr: 0010fef2 Rxd: 1ffb813f
|
# tb_core.u_sdram32 : at time 42633.0 ns READ : Bank = 3 Row = 271, Col = 212, Data = 398a1973
|
# tb_core.u_sdram32 : at time 43833.0 ns READ : Bank = 3 Row = 271, Col = 212, Data = 398a1973
|
# READ STATUS: Burst-No: 44 Addr: 0010fef4 Rxd: e13256c2
|
# READ STATUS: Burst-No: 44 Addr: 0010fef4 Rxd: e13256c2
|
# tb_core.u_sdram32 : at time 42643.0 ns READ : Bank = 3 Row = 271, Col = 213, Data = 2d4d9b5a
|
# tb_core.u_sdram32 : at time 43843.0 ns READ : Bank = 3 Row = 271, Col = 213, Data = 2d4d9b5a
|
# READ STATUS: Burst-No: 45 Addr: 0010fef6 Rxd: 398a1973
|
# READ STATUS: Burst-No: 45 Addr: 0010fef6 Rxd: 398a1973
|
# tb_core.u_sdram32 : at time 42653.0 ns READ : Bank = 3 Row = 271, Col = 214, Data = d066e4a0
|
# tb_core.u_sdram32 : at time 43853.0 ns READ : Bank = 3 Row = 271, Col = 214, Data = d066e4a0
|
# READ STATUS: Burst-No: 46 Addr: 0010fef8 Rxd: 2d4d9b5a
|
# READ STATUS: Burst-No: 46 Addr: 0010fef8 Rxd: 2d4d9b5a
|
# tb_core.u_sdram32 : at time 42663.0 ns READ : Bank = 3 Row = 271, Col = 215, Data = ff73cafe
|
# tb_core.u_sdram32 : at time 43863.0 ns READ : Bank = 3 Row = 271, Col = 215, Data = ff73cafe
|
# READ STATUS: Burst-No: 47 Addr: 0010fefa Rxd: d066e4a0
|
# READ STATUS: Burst-No: 47 Addr: 0010fefa Rxd: d066e4a0
|
# tb_core.u_sdram32 : at time 42673.0 ns READ : Bank = 3 Row = 271, Col = 216, Data = 3a096b74
|
# tb_core.u_sdram32 : at time 43873.0 ns READ : Bank = 3 Row = 271, Col = 216, Data = 3a096b74
|
# READ STATUS: Burst-No: 48 Addr: 0010fefc Rxd: ff73cafe
|
# READ STATUS: Burst-No: 48 Addr: 0010fefc Rxd: ff73cafe
|
# tb_core.u_sdram32 : at time 42683.0 ns READ : Bank = 3 Row = 271, Col = 217, Data = 5d86b7bb
|
# tb_core.u_sdram32 : at time 43883.0 ns READ : Bank = 3 Row = 271, Col = 217, Data = 5d86b7bb
|
# READ STATUS: Burst-No: 49 Addr: 0010fefe Rxd: 3a096b74
|
# READ STATUS: Burst-No: 49 Addr: 0010fefe Rxd: 3a096b74
|
# tb_core.u_sdram32 : at time 42693.0 ns READ : Bank = 3 Row = 271, Col = 218, Data = 7132bbe2
|
# tb_core.u_sdram32 : at time 43893.0 ns READ : Bank = 3 Row = 271, Col = 218, Data = 7132bbe2
|
# READ STATUS: Burst-No: 50 Addr: 0010ff00 Rxd: 5d86b7bb
|
# READ STATUS: Burst-No: 50 Addr: 0010ff00 Rxd: 5d86b7bb
|
# tb_core.u_sdram32 : at time 42703.0 ns READ : Bank = 3 Row = 271, Col = 219, Data = f16948e2
|
# tb_core.u_sdram32 : at time 43903.0 ns READ : Bank = 3 Row = 271, Col = 219, Data = f16948e2
|
# READ STATUS: Burst-No: 51 Addr: 0010ff02 Rxd: 7132bbe2
|
# READ STATUS: Burst-No: 51 Addr: 0010ff02 Rxd: 7132bbe2
|
# tb_core.u_sdram32 : at time 42713.0 ns READ : Bank = 3 Row = 271, Col = 220, Data = eff34cdf
|
# tb_core.u_sdram32 : at time 43913.0 ns READ : Bank = 3 Row = 271, Col = 220, Data = eff34cdf
|
# READ STATUS: Burst-No: 52 Addr: 0010ff04 Rxd: f16948e2
|
# READ STATUS: Burst-No: 52 Addr: 0010ff04 Rxd: f16948e2
|
# tb_core.u_sdram32 : at time 42723.0 ns READ : Bank = 3 Row = 271, Col = 221, Data = cc13e298
|
# tb_core.u_sdram32 : at time 43923.0 ns READ : Bank = 3 Row = 271, Col = 221, Data = cc13e298
|
# READ STATUS: Burst-No: 53 Addr: 0010ff06 Rxd: eff34cdf
|
# READ STATUS: Burst-No: 53 Addr: 0010ff06 Rxd: eff34cdf
|
# tb_core.u_sdram32 : at time 42733.0 ns READ : Bank = 3 Row = 271, Col = 222, Data = 4fdbed9f
|
# tb_core.u_sdram32 : at time 43933.0 ns READ : Bank = 3 Row = 271, Col = 222, Data = 4fdbed9f
|
# READ STATUS: Burst-No: 54 Addr: 0010ff08 Rxd: cc13e298
|
# READ STATUS: Burst-No: 54 Addr: 0010ff08 Rxd: cc13e298
|
# tb_core.u_sdram32 : at time 42743.0 ns READ : Bank = 3 Row = 271, Col = 223, Data = 0817cb10
|
# tb_core.u_sdram32 : at time 43943.0 ns READ : Bank = 3 Row = 271, Col = 223, Data = 0817cb10
|
# READ STATUS: Burst-No: 55 Addr: 0010ff0a Rxd: 4fdbed9f
|
# READ STATUS: Burst-No: 55 Addr: 0010ff0a Rxd: 4fdbed9f
|
# tb_core.u_sdram32 : at time 42753.0 ns READ : Bank = 3 Row = 271, Col = 224, Data = 791189f2
|
# tb_core.u_sdram32 : at time 43953.0 ns READ : Bank = 3 Row = 271, Col = 224, Data = 791189f2
|
# READ STATUS: Burst-No: 56 Addr: 0010ff0c Rxd: 0817cb10
|
# READ STATUS: Burst-No: 56 Addr: 0010ff0c Rxd: 0817cb10
|
# tb_core.u_sdram32 : at time 42763.0 ns READ : Bank = 3 Row = 271, Col = 225, Data = 5ee97bbd
|
# tb_core.u_sdram32 : at time 43963.0 ns READ : Bank = 3 Row = 271, Col = 225, Data = 5ee97bbd
|
# tb_core.u_sdram32 : at time 42767.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 43967.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 57 Addr: 0010ff0e Rxd: 791189f2
|
# READ STATUS: Burst-No: 57 Addr: 0010ff0e Rxd: 791189f2
|
# tb_core.u_sdram32 : at time 42773.0 ns READ : Bank = 3 Row = 271, Col = 226, Data = 55bc27ab
|
# tb_core.u_sdram32 : at time 43973.0 ns READ : Bank = 3 Row = 271, Col = 226, Data = 55bc27ab
|
# READ STATUS: Burst-No: 58 Addr: 0010ff10 Rxd: 5ee97bbd
|
# READ STATUS: Burst-No: 58 Addr: 0010ff10 Rxd: 5ee97bbd
|
# tb_core.u_sdram32 : at time 42783.0 ns READ : Bank = 3 Row = 271, Col = 227, Data = 5a0a0fb4
|
# tb_core.u_sdram32 : at time 43983.0 ns READ : Bank = 3 Row = 271, Col = 227, Data = 5a0a0fb4
|
# READ STATUS: Burst-No: 59 Addr: 0010ff12 Rxd: 55bc27ab
|
# READ STATUS: Burst-No: 59 Addr: 0010ff12 Rxd: 55bc27ab
|
# READ STATUS: Burst-No: 60 Addr: 0010ff14 Rxd: 5a0a0fb4
|
# READ STATUS: Burst-No: 60 Addr: 0010ff14 Rxd: 5a0a0fb4
|
# tb_core.u_sdram32 : at time 42957.0 ns ACT : Bank = 3 Row = 138
|
# tb_core.u_sdram32 : at time 44157.0 ns ACT : Bank = 3 Row = 138
|
# tb_core.u_sdram32 : at time 43013.0 ns READ : Bank = 3 Row = 138, Col = 21, Data = 89b5d413
|
# tb_core.u_sdram32 : at time 44213.0 ns READ : Bank = 3 Row = 138, Col = 21, Data = 89b5d413
|
# tb_core.u_sdram32 : at time 43023.0 ns READ : Bank = 3 Row = 138, Col = 22, Data = 560c91ac
|
# tb_core.u_sdram32 : at time 44223.0 ns READ : Bank = 3 Row = 138, Col = 22, Data = 560c91ac
|
# READ STATUS: Burst-No: 0 Addr: 0008ac54 Rxd: 89b5d413
|
# READ STATUS: Burst-No: 0 Addr: 0008ac54 Rxd: 89b5d413
|
# tb_core.u_sdram32 : at time 43033.0 ns READ : Bank = 3 Row = 138, Col = 23, Data = 1ae40335
|
# tb_core.u_sdram32 : at time 44233.0 ns READ : Bank = 3 Row = 138, Col = 23, Data = 1ae40335
|
# READ STATUS: Burst-No: 1 Addr: 0008ac56 Rxd: 560c91ac
|
# READ STATUS: Burst-No: 1 Addr: 0008ac56 Rxd: 560c91ac
|
# tb_core.u_sdram32 : at time 43043.0 ns READ : Bank = 3 Row = 138, Col = 24, Data = 1df61f3b
|
# tb_core.u_sdram32 : at time 44243.0 ns READ : Bank = 3 Row = 138, Col = 24, Data = 1df61f3b
|
# READ STATUS: Burst-No: 2 Addr: 0008ac58 Rxd: 1ae40335
|
# READ STATUS: Burst-No: 2 Addr: 0008ac58 Rxd: 1ae40335
|
# tb_core.u_sdram32 : at time 43053.0 ns READ : Bank = 3 Row = 138, Col = 25, Data = 9aa02435
|
# tb_core.u_sdram32 : at time 44253.0 ns READ : Bank = 3 Row = 138, Col = 25, Data = 9aa02435
|
# READ STATUS: Burst-No: 3 Addr: 0008ac5a Rxd: 1df61f3b
|
# READ STATUS: Burst-No: 3 Addr: 0008ac5a Rxd: 1df61f3b
|
# tb_core.u_sdram32 : at time 43063.0 ns READ : Bank = 3 Row = 138, Col = 26, Data = 17a98d2f
|
# tb_core.u_sdram32 : at time 44263.0 ns READ : Bank = 3 Row = 138, Col = 26, Data = 17a98d2f
|
# READ STATUS: Burst-No: 4 Addr: 0008ac5c Rxd: 9aa02435
|
# READ STATUS: Burst-No: 4 Addr: 0008ac5c Rxd: 9aa02435
|
# tb_core.u_sdram32 : at time 43073.0 ns READ : Bank = 3 Row = 138, Col = 27, Data = 1a619934
|
# tb_core.u_sdram32 : at time 44273.0 ns READ : Bank = 3 Row = 138, Col = 27, Data = 1a619934
|
# READ STATUS: Burst-No: 5 Addr: 0008ac5e Rxd: 17a98d2f
|
# READ STATUS: Burst-No: 5 Addr: 0008ac5e Rxd: 17a98d2f
|
# tb_core.u_sdram32 : at time 43083.0 ns READ : Bank = 3 Row = 138, Col = 28, Data = aae0a255
|
# tb_core.u_sdram32 : at time 44283.0 ns READ : Bank = 3 Row = 138, Col = 28, Data = aae0a255
|
# tb_core.u_sdram32 : at time 43087.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 44287.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 6 Addr: 0008ac60 Rxd: 1a619934
|
# READ STATUS: Burst-No: 6 Addr: 0008ac60 Rxd: 1a619934
|
# tb_core.u_sdram32 : at time 43093.0 ns READ : Bank = 3 Row = 138, Col = 29, Data = de7302bc
|
# tb_core.u_sdram32 : at time 44293.0 ns READ : Bank = 3 Row = 138, Col = 29, Data = de7302bc
|
# READ STATUS: Burst-No: 7 Addr: 0008ac62 Rxd: aae0a255
|
# READ STATUS: Burst-No: 7 Addr: 0008ac62 Rxd: aae0a255
|
# tb_core.u_sdram32 : at time 43103.0 ns READ : Bank = 3 Row = 138, Col = 30, Data = f964fef2
|
# tb_core.u_sdram32 : at time 44303.0 ns READ : Bank = 3 Row = 138, Col = 30, Data = f964fef2
|
# READ STATUS: Burst-No: 8 Addr: 0008ac64 Rxd: de7302bc
|
# READ STATUS: Burst-No: 8 Addr: 0008ac64 Rxd: de7302bc
|
# READ STATUS: Burst-No: 9 Addr: 0008ac66 Rxd: f964fef2
|
# READ STATUS: Burst-No: 9 Addr: 0008ac66 Rxd: f964fef2
|
# Write Address: 003e36a7, Burst Size: 2
|
# Write Address: 003e36a7, Burst Size: 2
|
# tb_core.u_sdram32 : at time 43277.0 ns ACT : Bank = 1 Row = 995
|
# tb_core.u_sdram32 : at time 44477.0 ns ACT : Bank = 1 Row = 995
|
# tb_core.u_sdram32 : at time 43307.0 ns WRITE: Bank = 1 Row = 995, Col = 169, Data = f23316e4
|
# tb_core.u_sdram32 : at time 44507.0 ns WRITE: Bank = 1 Row = 995, Col = 169, Data = f23316e4
|
# Status: Burst-No: 0 Write Address: 003e36a7 WriteData: f23316e4
|
# Status: Burst-No: 0 Write Address: 003e36a7 WriteData: f23316e4
|
# tb_core.u_sdram32 : at time 43317.0 ns WRITE: Bank = 1 Row = 995, Col = 170, Data = a0b8a241
|
# tb_core.u_sdram32 : at time 44517.0 ns WRITE: Bank = 1 Row = 995, Col = 170, Data = a0b8a241
|
# Status: Burst-No: 1 Write Address: 003e36a7 WriteData: a0b8a241
|
# Status: Burst-No: 1 Write Address: 003e36a7 WriteData: a0b8a241
|
# tb_core.u_sdram32 : at time 43327.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 44527.0 ns BST : Burst Terminate
|
# Write Address: 00016c69, Burst Size: 59
|
# Write Address: 00016c69, Burst Size: 59
|
# tb_core.u_sdram32 : at time 43467.0 ns ACT : Bank = 3 Row = 22
|
# tb_core.u_sdram32 : at time 44667.0 ns ACT : Bank = 3 Row = 22
|
# tb_core.u_sdram32 : at time 43497.0 ns WRITE: Bank = 3 Row = 22, Col = 26, Data = e69dd0cd
|
# tb_core.u_sdram32 : at time 44697.0 ns WRITE: Bank = 3 Row = 22, Col = 26, Data = e69dd0cd
|
# Status: Burst-No: 0 Write Address: 00016c69 WriteData: e69dd0cd
|
# Status: Burst-No: 0 Write Address: 00016c69 WriteData: e69dd0cd
|
# tb_core.u_sdram32 : at time 43507.0 ns WRITE: Bank = 3 Row = 22, Col = 27, Data = 7fcff3ff
|
# tb_core.u_sdram32 : at time 44707.0 ns WRITE: Bank = 3 Row = 22, Col = 27, Data = 7fcff3ff
|
# Status: Burst-No: 1 Write Address: 00016c69 WriteData: 7fcff3ff
|
# Status: Burst-No: 1 Write Address: 00016c69 WriteData: 7fcff3ff
|
# tb_core.u_sdram32 : at time 43517.0 ns WRITE: Bank = 3 Row = 22, Col = 28, Data = dac986b5
|
# tb_core.u_sdram32 : at time 44717.0 ns WRITE: Bank = 3 Row = 22, Col = 28, Data = dac986b5
|
# Status: Burst-No: 2 Write Address: 00016c69 WriteData: dac986b5
|
# Status: Burst-No: 2 Write Address: 00016c69 WriteData: dac986b5
|
# tb_core.u_sdram32 : at time 43527.0 ns WRITE: Bank = 3 Row = 22, Col = 29, Data = f42082e8
|
# tb_core.u_sdram32 : at time 44727.0 ns WRITE: Bank = 3 Row = 22, Col = 29, Data = f42082e8
|
# Status: Burst-No: 3 Write Address: 00016c69 WriteData: f42082e8
|
# Status: Burst-No: 3 Write Address: 00016c69 WriteData: f42082e8
|
# tb_core.u_sdram32 : at time 43537.0 ns WRITE: Bank = 3 Row = 22, Col = 30, Data = a5955c4b
|
# tb_core.u_sdram32 : at time 44737.0 ns WRITE: Bank = 3 Row = 22, Col = 30, Data = a5955c4b
|
# Status: Burst-No: 4 Write Address: 00016c69 WriteData: a5955c4b
|
# Status: Burst-No: 4 Write Address: 00016c69 WriteData: a5955c4b
|
# tb_core.u_sdram32 : at time 43547.0 ns WRITE: Bank = 3 Row = 22, Col = 31, Data = 89042e12
|
# tb_core.u_sdram32 : at time 44747.0 ns WRITE: Bank = 3 Row = 22, Col = 31, Data = 89042e12
|
# Status: Burst-No: 5 Write Address: 00016c69 WriteData: 89042e12
|
# Status: Burst-No: 5 Write Address: 00016c69 WriteData: 89042e12
|
# tb_core.u_sdram32 : at time 43557.0 ns WRITE: Bank = 3 Row = 22, Col = 32, Data = 1b978f37
|
# tb_core.u_sdram32 : at time 44757.0 ns WRITE: Bank = 3 Row = 22, Col = 32, Data = 1b978f37
|
# Status: Burst-No: 6 Write Address: 00016c69 WriteData: 1b978f37
|
# Status: Burst-No: 6 Write Address: 00016c69 WriteData: 1b978f37
|
# tb_core.u_sdram32 : at time 43567.0 ns WRITE: Bank = 3 Row = 22, Col = 33, Data = 574e1dae
|
# tb_core.u_sdram32 : at time 44767.0 ns WRITE: Bank = 3 Row = 22, Col = 33, Data = 574e1dae
|
# Status: Burst-No: 7 Write Address: 00016c69 WriteData: 574e1dae
|
# Status: Burst-No: 7 Write Address: 00016c69 WriteData: 574e1dae
|
# tb_core.u_sdram32 : at time 43577.0 ns WRITE: Bank = 3 Row = 22, Col = 34, Data = fc4ca4f8
|
# tb_core.u_sdram32 : at time 44777.0 ns WRITE: Bank = 3 Row = 22, Col = 34, Data = fc4ca4f8
|
# Status: Burst-No: 8 Write Address: 00016c69 WriteData: fc4ca4f8
|
# Status: Burst-No: 8 Write Address: 00016c69 WriteData: fc4ca4f8
|
# tb_core.u_sdram32 : at time 43587.0 ns WRITE: Bank = 3 Row = 22, Col = 35, Data = 90184e20
|
# tb_core.u_sdram32 : at time 44787.0 ns WRITE: Bank = 3 Row = 22, Col = 35, Data = 90184e20
|
# Status: Burst-No: 9 Write Address: 00016c69 WriteData: 90184e20
|
# Status: Burst-No: 9 Write Address: 00016c69 WriteData: 90184e20
|
# tb_core.u_sdram32 : at time 43597.0 ns WRITE: Bank = 3 Row = 22, Col = 36, Data = ed1b50da
|
# tb_core.u_sdram32 : at time 44797.0 ns WRITE: Bank = 3 Row = 22, Col = 36, Data = ed1b50da
|
# Status: Burst-No: 10 Write Address: 00016c69 WriteData: ed1b50da
|
# Status: Burst-No: 10 Write Address: 00016c69 WriteData: ed1b50da
|
# tb_core.u_sdram32 : at time 43607.0 ns WRITE: Bank = 3 Row = 22, Col = 37, Data = 913e0222
|
# tb_core.u_sdram32 : at time 44807.0 ns WRITE: Bank = 3 Row = 22, Col = 37, Data = 913e0222
|
# Status: Burst-No: 11 Write Address: 00016c69 WriteData: 913e0222
|
# Status: Burst-No: 11 Write Address: 00016c69 WriteData: 913e0222
|
# tb_core.u_sdram32 : at time 43617.0 ns WRITE: Bank = 3 Row = 22, Col = 38, Data = 763355ec
|
# tb_core.u_sdram32 : at time 44817.0 ns WRITE: Bank = 3 Row = 22, Col = 38, Data = 763355ec
|
# Status: Burst-No: 12 Write Address: 00016c69 WriteData: 763355ec
|
# Status: Burst-No: 12 Write Address: 00016c69 WriteData: 763355ec
|
# tb_core.u_sdram32 : at time 43627.0 ns WRITE: Bank = 3 Row = 22, Col = 39, Data = 9535122a
|
# tb_core.u_sdram32 : at time 44827.0 ns WRITE: Bank = 3 Row = 22, Col = 39, Data = 9535122a
|
# Status: Burst-No: 13 Write Address: 00016c69 WriteData: 9535122a
|
# Status: Burst-No: 13 Write Address: 00016c69 WriteData: 9535122a
|
# tb_core.u_sdram32 : at time 43637.0 ns WRITE: Bank = 3 Row = 22, Col = 40, Data = 3d7f5b7a
|
# tb_core.u_sdram32 : at time 44837.0 ns WRITE: Bank = 3 Row = 22, Col = 40, Data = 3d7f5b7a
|
# Status: Burst-No: 14 Write Address: 00016c69 WriteData: 3d7f5b7a
|
# Status: Burst-No: 14 Write Address: 00016c69 WriteData: 3d7f5b7a
|
# tb_core.u_sdram32 : at time 43647.0 ns WRITE: Bank = 3 Row = 22, Col = 41, Data = 0f1e511e
|
# tb_core.u_sdram32 : at time 44847.0 ns WRITE: Bank = 3 Row = 22, Col = 41, Data = 0f1e511e
|
# Status: Burst-No: 15 Write Address: 00016c69 WriteData: 0f1e511e
|
# Status: Burst-No: 15 Write Address: 00016c69 WriteData: 0f1e511e
|
# tb_core.u_sdram32 : at time 43657.0 ns WRITE: Bank = 3 Row = 22, Col = 42, Data = f4a1dae9
|
# tb_core.u_sdram32 : at time 44857.0 ns WRITE: Bank = 3 Row = 22, Col = 42, Data = f4a1dae9
|
# Status: Burst-No: 16 Write Address: 00016c69 WriteData: f4a1dae9
|
# Status: Burst-No: 16 Write Address: 00016c69 WriteData: f4a1dae9
|
# tb_core.u_sdram32 : at time 43667.0 ns WRITE: Bank = 3 Row = 22, Col = 43, Data = f5a4f2eb
|
# tb_core.u_sdram32 : at time 44867.0 ns WRITE: Bank = 3 Row = 22, Col = 43, Data = f5a4f2eb
|
# Status: Burst-No: 17 Write Address: 00016c69 WriteData: f5a4f2eb
|
# Status: Burst-No: 17 Write Address: 00016c69 WriteData: f5a4f2eb
|
# tb_core.u_sdram32 : at time 43677.0 ns WRITE: Bank = 3 Row = 22, Col = 44, Data = 05b4f70b
|
# tb_core.u_sdram32 : at time 44877.0 ns WRITE: Bank = 3 Row = 22, Col = 44, Data = 05b4f70b
|
# Status: Burst-No: 18 Write Address: 00016c69 WriteData: 05b4f70b
|
# Status: Burst-No: 18 Write Address: 00016c69 WriteData: 05b4f70b
|
# tb_core.u_sdram32 : at time 43687.0 ns WRITE: Bank = 3 Row = 22, Col = 45, Data = b704e26e
|
# tb_core.u_sdram32 : at time 44887.0 ns WRITE: Bank = 3 Row = 22, Col = 45, Data = b704e26e
|
# Status: Burst-No: 19 Write Address: 00016c69 WriteData: b704e26e
|
# Status: Burst-No: 19 Write Address: 00016c69 WriteData: b704e26e
|
# tb_core.u_sdram32 : at time 43697.0 ns WRITE: Bank = 3 Row = 22, Col = 46, Data = af455e5e
|
# tb_core.u_sdram32 : at time 44897.0 ns WRITE: Bank = 3 Row = 22, Col = 46, Data = af455e5e
|
# Status: Burst-No: 20 Write Address: 00016c69 WriteData: af455e5e
|
# Status: Burst-No: 20 Write Address: 00016c69 WriteData: af455e5e
|
# tb_core.u_sdram32 : at time 43707.0 ns WRITE: Bank = 3 Row = 22, Col = 47, Data = 3e502d7c
|
# tb_core.u_sdram32 : at time 44907.0 ns WRITE: Bank = 3 Row = 22, Col = 47, Data = 3e502d7c
|
# Status: Burst-No: 21 Write Address: 00016c69 WriteData: 3e502d7c
|
# Status: Burst-No: 21 Write Address: 00016c69 WriteData: 3e502d7c
|
# tb_core.u_sdram32 : at time 43717.0 ns WRITE: Bank = 3 Row = 22, Col = 48, Data = 22c03145
|
# tb_core.u_sdram32 : at time 44917.0 ns WRITE: Bank = 3 Row = 22, Col = 48, Data = 22c03145
|
# Status: Burst-No: 22 Write Address: 00016c69 WriteData: 22c03145
|
# Status: Burst-No: 22 Write Address: 00016c69 WriteData: 22c03145
|
# tb_core.u_sdram32 : at time 43727.0 ns WRITE: Bank = 3 Row = 22, Col = 49, Data = c5cb548b
|
# tb_core.u_sdram32 : at time 44927.0 ns WRITE: Bank = 3 Row = 22, Col = 49, Data = c5cb548b
|
# Status: Burst-No: 23 Write Address: 00016c69 WriteData: c5cb548b
|
# Status: Burst-No: 23 Write Address: 00016c69 WriteData: c5cb548b
|
# tb_core.u_sdram32 : at time 43737.0 ns WRITE: Bank = 3 Row = 22, Col = 50, Data = 094bd312
|
# tb_core.u_sdram32 : at time 44937.0 ns WRITE: Bank = 3 Row = 22, Col = 50, Data = 094bd312
|
# Status: Burst-No: 24 Write Address: 00016c69 WriteData: 094bd312
|
# Status: Burst-No: 24 Write Address: 00016c69 WriteData: 094bd312
|
# tb_core.u_sdram32 : at time 43747.0 ns WRITE: Bank = 3 Row = 22, Col = 51, Data = 1bf8bd37
|
# tb_core.u_sdram32 : at time 44947.0 ns WRITE: Bank = 3 Row = 22, Col = 51, Data = 1bf8bd37
|
# Status: Burst-No: 25 Write Address: 00016c69 WriteData: 1bf8bd37
|
# Status: Burst-No: 25 Write Address: 00016c69 WriteData: 1bf8bd37
|
# tb_core.u_sdram32 : at time 43757.0 ns WRITE: Bank = 3 Row = 22, Col = 52, Data = c1c3d683
|
# tb_core.u_sdram32 : at time 44957.0 ns WRITE: Bank = 3 Row = 22, Col = 52, Data = c1c3d683
|
# Status: Burst-No: 26 Write Address: 00016c69 WriteData: c1c3d683
|
# Status: Burst-No: 26 Write Address: 00016c69 WriteData: c1c3d683
|
# tb_core.u_sdram32 : at time 43767.0 ns WRITE: Bank = 3 Row = 22, Col = 53, Data = f0ab00e1
|
# tb_core.u_sdram32 : at time 44967.0 ns WRITE: Bank = 3 Row = 22, Col = 53, Data = f0ab00e1
|
# Status: Burst-No: 27 Write Address: 00016c69 WriteData: f0ab00e1
|
# Status: Burst-No: 27 Write Address: 00016c69 WriteData: f0ab00e1
|
# tb_core.u_sdram32 : at time 43777.0 ns WRITE: Bank = 3 Row = 22, Col = 54, Data = 674fdfce
|
# tb_core.u_sdram32 : at time 44977.0 ns WRITE: Bank = 3 Row = 22, Col = 54, Data = 674fdfce
|
# Status: Burst-No: 28 Write Address: 00016c69 WriteData: 674fdfce
|
# Status: Burst-No: 28 Write Address: 00016c69 WriteData: 674fdfce
|
# tb_core.u_sdram32 : at time 43787.0 ns WRITE: Bank = 3 Row = 22, Col = 55, Data = a5365c4a
|
# tb_core.u_sdram32 : at time 44987.0 ns WRITE: Bank = 3 Row = 22, Col = 55, Data = a5365c4a
|
# Status: Burst-No: 29 Write Address: 00016c69 WriteData: a5365c4a
|
# Status: Burst-No: 29 Write Address: 00016c69 WriteData: a5365c4a
|
# tb_core.u_sdram32 : at time 43797.0 ns WRITE: Bank = 3 Row = 22, Col = 56, Data = 6acd73d5
|
# tb_core.u_sdram32 : at time 44997.0 ns WRITE: Bank = 3 Row = 22, Col = 56, Data = 6acd73d5
|
# Status: Burst-No: 30 Write Address: 00016c69 WriteData: 6acd73d5
|
# Status: Burst-No: 30 Write Address: 00016c69 WriteData: 6acd73d5
|
# tb_core.u_sdram32 : at time 43807.0 ns WRITE: Bank = 3 Row = 22, Col = 57, Data = 669907cd
|
# tb_core.u_sdram32 : at time 45007.0 ns WRITE: Bank = 3 Row = 22, Col = 57, Data = 669907cd
|
# Status: Burst-No: 31 Write Address: 00016c69 WriteData: 669907cd
|
# Status: Burst-No: 31 Write Address: 00016c69 WriteData: 669907cd
|
# tb_core.u_sdram32 : at time 43817.0 ns WRITE: Bank = 3 Row = 22, Col = 58, Data = f204eee4
|
# tb_core.u_sdram32 : at time 45017.0 ns WRITE: Bank = 3 Row = 22, Col = 58, Data = f204eee4
|
# Status: Burst-No: 32 Write Address: 00016c69 WriteData: f204eee4
|
# Status: Burst-No: 32 Write Address: 00016c69 WriteData: f204eee4
|
# tb_core.u_sdram32 : at time 43827.0 ns WRITE: Bank = 3 Row = 22, Col = 59, Data = fa328cf4
|
# tb_core.u_sdram32 : at time 45027.0 ns WRITE: Bank = 3 Row = 22, Col = 59, Data = fa328cf4
|
# Status: Burst-No: 33 Write Address: 00016c69 WriteData: fa328cf4
|
# Status: Burst-No: 33 Write Address: 00016c69 WriteData: fa328cf4
|
# tb_core.u_sdram32 : at time 43837.0 ns WRITE: Bank = 3 Row = 22, Col = 60, Data = 766153ec
|
# tb_core.u_sdram32 : at time 45037.0 ns WRITE: Bank = 3 Row = 22, Col = 60, Data = 766153ec
|
# Status: Burst-No: 34 Write Address: 00016c69 WriteData: 766153ec
|
# Status: Burst-No: 34 Write Address: 00016c69 WriteData: 766153ec
|
# tb_core.u_sdram32 : at time 43847.0 ns WRITE: Bank = 3 Row = 22, Col = 61, Data = 0d623f1a
|
# tb_core.u_sdram32 : at time 45047.0 ns WRITE: Bank = 3 Row = 22, Col = 61, Data = 0d623f1a
|
# Status: Burst-No: 35 Write Address: 00016c69 WriteData: 0d623f1a
|
# Status: Burst-No: 35 Write Address: 00016c69 WriteData: 0d623f1a
|
# tb_core.u_sdram32 : at time 43857.0 ns WRITE: Bank = 3 Row = 22, Col = 62, Data = f1a32ee3
|
# tb_core.u_sdram32 : at time 45057.0 ns WRITE: Bank = 3 Row = 22, Col = 62, Data = f1a32ee3
|
# Status: Burst-No: 36 Write Address: 00016c69 WriteData: f1a32ee3
|
# Status: Burst-No: 36 Write Address: 00016c69 WriteData: f1a32ee3
|
# tb_core.u_sdram32 : at time 43867.0 ns WRITE: Bank = 3 Row = 22, Col = 63, Data = f62484ec
|
# tb_core.u_sdram32 : at time 45067.0 ns WRITE: Bank = 3 Row = 22, Col = 63, Data = f62484ec
|
# Status: Burst-No: 37 Write Address: 00016c69 WriteData: f62484ec
|
# Status: Burst-No: 37 Write Address: 00016c69 WriteData: f62484ec
|
# tb_core.u_sdram32 : at time 43877.0 ns WRITE: Bank = 3 Row = 22, Col = 64, Data = 79c681f3
|
# tb_core.u_sdram32 : at time 45077.0 ns WRITE: Bank = 3 Row = 22, Col = 64, Data = 79c681f3
|
# Status: Burst-No: 38 Write Address: 00016c69 WriteData: 79c681f3
|
# Status: Burst-No: 38 Write Address: 00016c69 WriteData: 79c681f3
|
# tb_core.u_sdram32 : at time 43887.0 ns WRITE: Bank = 3 Row = 22, Col = 65, Data = 1687472d
|
# tb_core.u_sdram32 : at time 45087.0 ns WRITE: Bank = 3 Row = 22, Col = 65, Data = 1687472d
|
# Status: Burst-No: 39 Write Address: 00016c69 WriteData: 1687472d
|
# Status: Burst-No: 39 Write Address: 00016c69 WriteData: 1687472d
|
# tb_core.u_sdram32 : at time 43897.0 ns WRITE: Bank = 3 Row = 22, Col = 66, Data = 2e138d5c
|
# tb_core.u_sdram32 : at time 45097.0 ns WRITE: Bank = 3 Row = 22, Col = 66, Data = 2e138d5c
|
# Status: Burst-No: 40 Write Address: 00016c69 WriteData: 2e138d5c
|
# Status: Burst-No: 40 Write Address: 00016c69 WriteData: 2e138d5c
|
# tb_core.u_sdram32 : at time 43907.0 ns WRITE: Bank = 3 Row = 22, Col = 67, Data = 6e8d45dd
|
# tb_core.u_sdram32 : at time 45107.0 ns WRITE: Bank = 3 Row = 22, Col = 67, Data = 6e8d45dd
|
# Status: Burst-No: 41 Write Address: 00016c69 WriteData: 6e8d45dd
|
# Status: Burst-No: 41 Write Address: 00016c69 WriteData: 6e8d45dd
|
# tb_core.u_sdram32 : at time 43917.0 ns WRITE: Bank = 3 Row = 22, Col = 68, Data = f612c8ec
|
# tb_core.u_sdram32 : at time 45117.0 ns WRITE: Bank = 3 Row = 22, Col = 68, Data = f612c8ec
|
# Status: Burst-No: 42 Write Address: 00016c69 WriteData: f612c8ec
|
# Status: Burst-No: 42 Write Address: 00016c69 WriteData: f612c8ec
|
# tb_core.u_sdram32 : at time 43927.0 ns WRITE: Bank = 3 Row = 22, Col = 69, Data = c7d87a8f
|
# tb_core.u_sdram32 : at time 45127.0 ns WRITE: Bank = 3 Row = 22, Col = 69, Data = c7d87a8f
|
# Status: Burst-No: 43 Write Address: 00016c69 WriteData: c7d87a8f
|
# Status: Burst-No: 43 Write Address: 00016c69 WriteData: c7d87a8f
|
# tb_core.u_sdram32 : at time 43937.0 ns WRITE: Bank = 3 Row = 22, Col = 70, Data = 7fdbb3ff
|
# tb_core.u_sdram32 : at time 45137.0 ns WRITE: Bank = 3 Row = 22, Col = 70, Data = 7fdbb3ff
|
# Status: Burst-No: 44 Write Address: 00016c69 WriteData: 7fdbb3ff
|
# Status: Burst-No: 44 Write Address: 00016c69 WriteData: 7fdbb3ff
|
# tb_core.u_sdram32 : at time 43947.0 ns WRITE: Bank = 3 Row = 22, Col = 71, Data = 3c338578
|
# tb_core.u_sdram32 : at time 45147.0 ns WRITE: Bank = 3 Row = 22, Col = 71, Data = 3c338578
|
# Status: Burst-No: 45 Write Address: 00016c69 WriteData: 3c338578
|
# Status: Burst-No: 45 Write Address: 00016c69 WriteData: 3c338578
|
# tb_core.u_sdram32 : at time 43957.0 ns WRITE: Bank = 3 Row = 22, Col = 72, Data = 55f6b9ab
|
# tb_core.u_sdram32 : at time 45157.0 ns WRITE: Bank = 3 Row = 22, Col = 72, Data = 55f6b9ab
|
# Status: Burst-No: 46 Write Address: 00016c69 WriteData: 55f6b9ab
|
# Status: Burst-No: 46 Write Address: 00016c69 WriteData: 55f6b9ab
|
# tb_core.u_sdram32 : at time 43967.0 ns WRITE: Bank = 3 Row = 22, Col = 73, Data = 13d1f727
|
# tb_core.u_sdram32 : at time 45167.0 ns WRITE: Bank = 3 Row = 22, Col = 73, Data = 13d1f727
|
# Status: Burst-No: 47 Write Address: 00016c69 WriteData: 13d1f727
|
# Status: Burst-No: 47 Write Address: 00016c69 WriteData: 13d1f727
|
# tb_core.u_sdram32 : at time 43977.0 ns WRITE: Bank = 3 Row = 22, Col = 74, Data = 7dca0ffb
|
# tb_core.u_sdram32 : at time 45177.0 ns WRITE: Bank = 3 Row = 22, Col = 74, Data = 7dca0ffb
|
# Status: Burst-No: 48 Write Address: 00016c69 WriteData: 7dca0ffb
|
# Status: Burst-No: 48 Write Address: 00016c69 WriteData: 7dca0ffb
|
# tb_core.u_sdram32 : at time 43987.0 ns WRITE: Bank = 3 Row = 22, Col = 75, Data = 09dfc313
|
# tb_core.u_sdram32 : at time 45187.0 ns WRITE: Bank = 3 Row = 22, Col = 75, Data = 09dfc313
|
# Status: Burst-No: 49 Write Address: 00016c69 WriteData: 09dfc313
|
# Status: Burst-No: 49 Write Address: 00016c69 WriteData: 09dfc313
|
# tb_core.u_sdram32 : at time 43997.0 ns WRITE: Bank = 3 Row = 22, Col = 76, Data = 06499b0c
|
# tb_core.u_sdram32 : at time 45197.0 ns WRITE: Bank = 3 Row = 22, Col = 76, Data = 06499b0c
|
# Status: Burst-No: 50 Write Address: 00016c69 WriteData: 06499b0c
|
# Status: Burst-No: 50 Write Address: 00016c69 WriteData: 06499b0c
|
# tb_core.u_sdram32 : at time 44007.0 ns WRITE: Bank = 3 Row = 22, Col = 77, Data = 5db797bb
|
# tb_core.u_sdram32 : at time 45207.0 ns WRITE: Bank = 3 Row = 22, Col = 77, Data = 5db797bb
|
# Status: Burst-No: 51 Write Address: 00016c69 WriteData: 5db797bb
|
# Status: Burst-No: 51 Write Address: 00016c69 WriteData: 5db797bb
|
# tb_core.u_sdram32 : at time 44017.0 ns WRITE: Bank = 3 Row = 22, Col = 78, Data = f361cae6
|
# tb_core.u_sdram32 : at time 45217.0 ns WRITE: Bank = 3 Row = 22, Col = 78, Data = f361cae6
|
# Status: Burst-No: 52 Write Address: 00016c69 WriteData: f361cae6
|
# Status: Burst-No: 52 Write Address: 00016c69 WriteData: f361cae6
|
# tb_core.u_sdram32 : at time 44027.0 ns WRITE: Bank = 3 Row = 22, Col = 79, Data = a4d83a49
|
# tb_core.u_sdram32 : at time 45227.0 ns WRITE: Bank = 3 Row = 22, Col = 79, Data = a4d83a49
|
# Status: Burst-No: 53 Write Address: 00016c69 WriteData: a4d83a49
|
# Status: Burst-No: 53 Write Address: 00016c69 WriteData: a4d83a49
|
# tb_core.u_sdram32 : at time 44037.0 ns WRITE: Bank = 3 Row = 22, Col = 80, Data = 35557b6a
|
# tb_core.u_sdram32 : at time 45237.0 ns WRITE: Bank = 3 Row = 22, Col = 80, Data = 35557b6a
|
# Status: Burst-No: 54 Write Address: 00016c69 WriteData: 35557b6a
|
# Status: Burst-No: 54 Write Address: 00016c69 WriteData: 35557b6a
|
# tb_core.u_sdram32 : at time 44047.0 ns WRITE: Bank = 3 Row = 22, Col = 81, Data = 8570f60a
|
# tb_core.u_sdram32 : at time 45247.0 ns WRITE: Bank = 3 Row = 22, Col = 81, Data = 8570f60a
|
# Status: Burst-No: 55 Write Address: 00016c69 WriteData: 8570f60a
|
# Status: Burst-No: 55 Write Address: 00016c69 WriteData: 8570f60a
|
# tb_core.u_sdram32 : at time 44057.0 ns WRITE: Bank = 3 Row = 22, Col = 82, Data = 8c06d218
|
# tb_core.u_sdram32 : at time 45257.0 ns WRITE: Bank = 3 Row = 22, Col = 82, Data = 8c06d218
|
# Status: Burst-No: 56 Write Address: 00016c69 WriteData: 8c06d218
|
# Status: Burst-No: 56 Write Address: 00016c69 WriteData: 8c06d218
|
# tb_core.u_sdram32 : at time 44067.0 ns WRITE: Bank = 3 Row = 22, Col = 83, Data = 4b1ce996
|
# tb_core.u_sdram32 : at time 45267.0 ns WRITE: Bank = 3 Row = 22, Col = 83, Data = 4b1ce996
|
# Status: Burst-No: 57 Write Address: 00016c69 WriteData: 4b1ce996
|
# Status: Burst-No: 57 Write Address: 00016c69 WriteData: 4b1ce996
|
# tb_core.u_sdram32 : at time 44077.0 ns WRITE: Bank = 3 Row = 22, Col = 84, Data = 84e32609
|
# tb_core.u_sdram32 : at time 45277.0 ns WRITE: Bank = 3 Row = 22, Col = 84, Data = 84e32609
|
# Status: Burst-No: 58 Write Address: 00016c69 WriteData: 84e32609
|
# Status: Burst-No: 58 Write Address: 00016c69 WriteData: 84e32609
|
# tb_core.u_sdram32 : at time 44087.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 45287.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 44217.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 45417.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 44223.0 ns READ : Bank = 1 Row = 995, Col = 169, Data = f23316e4
|
# tb_core.u_sdram32 : at time 45423.0 ns READ : Bank = 1 Row = 995, Col = 169, Data = f23316e4
|
# tb_core.u_sdram32 : at time 44233.0 ns READ : Bank = 1 Row = 995, Col = 170, Data = a0b8a241
|
# tb_core.u_sdram32 : at time 45433.0 ns READ : Bank = 1 Row = 995, Col = 170, Data = a0b8a241
|
# READ STATUS: Burst-No: 0 Addr: 003e36a7 Rxd: f23316e4
|
# READ STATUS: Burst-No: 0 Addr: 003e36a7 Rxd: f23316e4
|
# READ STATUS: Burst-No: 1 Addr: 003e36a9 Rxd: a0b8a241
|
# READ STATUS: Burst-No: 1 Addr: 003e36a9 Rxd: a0b8a241
|
# tb_core.u_sdram32 : at time 44403.0 ns READ : Bank = 3 Row = 22, Col = 26, Data = e69dd0cd
|
# tb_core.u_sdram32 : at time 45603.0 ns READ : Bank = 3 Row = 22, Col = 26, Data = e69dd0cd
|
# tb_core.u_sdram32 : at time 44413.0 ns READ : Bank = 3 Row = 22, Col = 27, Data = 7fcff3ff
|
# tb_core.u_sdram32 : at time 45613.0 ns READ : Bank = 3 Row = 22, Col = 27, Data = 7fcff3ff
|
# READ STATUS: Burst-No: 0 Addr: 00016c69 Rxd: e69dd0cd
|
# READ STATUS: Burst-No: 0 Addr: 00016c69 Rxd: e69dd0cd
|
# tb_core.u_sdram32 : at time 44423.0 ns READ : Bank = 3 Row = 22, Col = 28, Data = dac986b5
|
# tb_core.u_sdram32 : at time 45623.0 ns READ : Bank = 3 Row = 22, Col = 28, Data = dac986b5
|
# READ STATUS: Burst-No: 1 Addr: 00016c6b Rxd: 7fcff3ff
|
# READ STATUS: Burst-No: 1 Addr: 00016c6b Rxd: 7fcff3ff
|
# tb_core.u_sdram32 : at time 44433.0 ns READ : Bank = 3 Row = 22, Col = 29, Data = f42082e8
|
# tb_core.u_sdram32 : at time 45633.0 ns READ : Bank = 3 Row = 22, Col = 29, Data = f42082e8
|
# READ STATUS: Burst-No: 2 Addr: 00016c6d Rxd: dac986b5
|
# READ STATUS: Burst-No: 2 Addr: 00016c6d Rxd: dac986b5
|
# tb_core.u_sdram32 : at time 44443.0 ns READ : Bank = 3 Row = 22, Col = 30, Data = a5955c4b
|
# tb_core.u_sdram32 : at time 45643.0 ns READ : Bank = 3 Row = 22, Col = 30, Data = a5955c4b
|
# READ STATUS: Burst-No: 3 Addr: 00016c6f Rxd: f42082e8
|
# READ STATUS: Burst-No: 3 Addr: 00016c6f Rxd: f42082e8
|
# tb_core.u_sdram32 : at time 44453.0 ns READ : Bank = 3 Row = 22, Col = 31, Data = 89042e12
|
# tb_core.u_sdram32 : at time 45653.0 ns READ : Bank = 3 Row = 22, Col = 31, Data = 89042e12
|
# READ STATUS: Burst-No: 4 Addr: 00016c71 Rxd: a5955c4b
|
# READ STATUS: Burst-No: 4 Addr: 00016c71 Rxd: a5955c4b
|
# tb_core.u_sdram32 : at time 44463.0 ns READ : Bank = 3 Row = 22, Col = 32, Data = 1b978f37
|
# tb_core.u_sdram32 : at time 45663.0 ns READ : Bank = 3 Row = 22, Col = 32, Data = 1b978f37
|
# READ STATUS: Burst-No: 5 Addr: 00016c73 Rxd: 89042e12
|
# READ STATUS: Burst-No: 5 Addr: 00016c73 Rxd: 89042e12
|
# tb_core.u_sdram32 : at time 44473.0 ns READ : Bank = 3 Row = 22, Col = 33, Data = 574e1dae
|
# tb_core.u_sdram32 : at time 45673.0 ns READ : Bank = 3 Row = 22, Col = 33, Data = 574e1dae
|
# READ STATUS: Burst-No: 6 Addr: 00016c75 Rxd: 1b978f37
|
# READ STATUS: Burst-No: 6 Addr: 00016c75 Rxd: 1b978f37
|
# tb_core.u_sdram32 : at time 44483.0 ns READ : Bank = 3 Row = 22, Col = 34, Data = fc4ca4f8
|
# tb_core.u_sdram32 : at time 45683.0 ns READ : Bank = 3 Row = 22, Col = 34, Data = fc4ca4f8
|
# READ STATUS: Burst-No: 7 Addr: 00016c77 Rxd: 574e1dae
|
# READ STATUS: Burst-No: 7 Addr: 00016c77 Rxd: 574e1dae
|
# tb_core.u_sdram32 : at time 44493.0 ns READ : Bank = 3 Row = 22, Col = 35, Data = 90184e20
|
# tb_core.u_sdram32 : at time 45693.0 ns READ : Bank = 3 Row = 22, Col = 35, Data = 90184e20
|
# READ STATUS: Burst-No: 8 Addr: 00016c79 Rxd: fc4ca4f8
|
# READ STATUS: Burst-No: 8 Addr: 00016c79 Rxd: fc4ca4f8
|
# tb_core.u_sdram32 : at time 44503.0 ns READ : Bank = 3 Row = 22, Col = 36, Data = ed1b50da
|
# tb_core.u_sdram32 : at time 45703.0 ns READ : Bank = 3 Row = 22, Col = 36, Data = ed1b50da
|
# READ STATUS: Burst-No: 9 Addr: 00016c7b Rxd: 90184e20
|
# READ STATUS: Burst-No: 9 Addr: 00016c7b Rxd: 90184e20
|
# tb_core.u_sdram32 : at time 44513.0 ns READ : Bank = 3 Row = 22, Col = 37, Data = 913e0222
|
# tb_core.u_sdram32 : at time 45713.0 ns READ : Bank = 3 Row = 22, Col = 37, Data = 913e0222
|
# READ STATUS: Burst-No: 10 Addr: 00016c7d Rxd: ed1b50da
|
# READ STATUS: Burst-No: 10 Addr: 00016c7d Rxd: ed1b50da
|
# tb_core.u_sdram32 : at time 44523.0 ns READ : Bank = 3 Row = 22, Col = 38, Data = 763355ec
|
# tb_core.u_sdram32 : at time 45723.0 ns READ : Bank = 3 Row = 22, Col = 38, Data = 763355ec
|
# READ STATUS: Burst-No: 11 Addr: 00016c7f Rxd: 913e0222
|
# READ STATUS: Burst-No: 11 Addr: 00016c7f Rxd: 913e0222
|
# tb_core.u_sdram32 : at time 44533.0 ns READ : Bank = 3 Row = 22, Col = 39, Data = 9535122a
|
# tb_core.u_sdram32 : at time 45733.0 ns READ : Bank = 3 Row = 22, Col = 39, Data = 9535122a
|
# READ STATUS: Burst-No: 12 Addr: 00016c81 Rxd: 763355ec
|
# READ STATUS: Burst-No: 12 Addr: 00016c81 Rxd: 763355ec
|
# tb_core.u_sdram32 : at time 44543.0 ns READ : Bank = 3 Row = 22, Col = 40, Data = 3d7f5b7a
|
# tb_core.u_sdram32 : at time 45743.0 ns READ : Bank = 3 Row = 22, Col = 40, Data = 3d7f5b7a
|
# READ STATUS: Burst-No: 13 Addr: 00016c83 Rxd: 9535122a
|
# READ STATUS: Burst-No: 13 Addr: 00016c83 Rxd: 9535122a
|
# tb_core.u_sdram32 : at time 44553.0 ns READ : Bank = 3 Row = 22, Col = 41, Data = 0f1e511e
|
# tb_core.u_sdram32 : at time 45753.0 ns READ : Bank = 3 Row = 22, Col = 41, Data = 0f1e511e
|
# READ STATUS: Burst-No: 14 Addr: 00016c85 Rxd: 3d7f5b7a
|
# READ STATUS: Burst-No: 14 Addr: 00016c85 Rxd: 3d7f5b7a
|
# tb_core.u_sdram32 : at time 44563.0 ns READ : Bank = 3 Row = 22, Col = 42, Data = f4a1dae9
|
# tb_core.u_sdram32 : at time 45763.0 ns READ : Bank = 3 Row = 22, Col = 42, Data = f4a1dae9
|
# READ STATUS: Burst-No: 15 Addr: 00016c87 Rxd: 0f1e511e
|
# READ STATUS: Burst-No: 15 Addr: 00016c87 Rxd: 0f1e511e
|
# tb_core.u_sdram32 : at time 44573.0 ns READ : Bank = 3 Row = 22, Col = 43, Data = f5a4f2eb
|
# tb_core.u_sdram32 : at time 45773.0 ns READ : Bank = 3 Row = 22, Col = 43, Data = f5a4f2eb
|
# READ STATUS: Burst-No: 16 Addr: 00016c89 Rxd: f4a1dae9
|
# READ STATUS: Burst-No: 16 Addr: 00016c89 Rxd: f4a1dae9
|
# tb_core.u_sdram32 : at time 44583.0 ns READ : Bank = 3 Row = 22, Col = 44, Data = 05b4f70b
|
# tb_core.u_sdram32 : at time 45783.0 ns READ : Bank = 3 Row = 22, Col = 44, Data = 05b4f70b
|
# READ STATUS: Burst-No: 17 Addr: 00016c8b Rxd: f5a4f2eb
|
# READ STATUS: Burst-No: 17 Addr: 00016c8b Rxd: f5a4f2eb
|
# tb_core.u_sdram32 : at time 44593.0 ns READ : Bank = 3 Row = 22, Col = 45, Data = b704e26e
|
# tb_core.u_sdram32 : at time 45793.0 ns READ : Bank = 3 Row = 22, Col = 45, Data = b704e26e
|
# READ STATUS: Burst-No: 18 Addr: 00016c8d Rxd: 05b4f70b
|
# READ STATUS: Burst-No: 18 Addr: 00016c8d Rxd: 05b4f70b
|
# tb_core.u_sdram32 : at time 44603.0 ns READ : Bank = 3 Row = 22, Col = 46, Data = af455e5e
|
# tb_core.u_sdram32 : at time 45803.0 ns READ : Bank = 3 Row = 22, Col = 46, Data = af455e5e
|
# READ STATUS: Burst-No: 19 Addr: 00016c8f Rxd: b704e26e
|
# READ STATUS: Burst-No: 19 Addr: 00016c8f Rxd: b704e26e
|
# tb_core.u_sdram32 : at time 44613.0 ns READ : Bank = 3 Row = 22, Col = 47, Data = 3e502d7c
|
# tb_core.u_sdram32 : at time 45813.0 ns READ : Bank = 3 Row = 22, Col = 47, Data = 3e502d7c
|
# READ STATUS: Burst-No: 20 Addr: 00016c91 Rxd: af455e5e
|
# READ STATUS: Burst-No: 20 Addr: 00016c91 Rxd: af455e5e
|
# tb_core.u_sdram32 : at time 44623.0 ns READ : Bank = 3 Row = 22, Col = 48, Data = 22c03145
|
# tb_core.u_sdram32 : at time 45823.0 ns READ : Bank = 3 Row = 22, Col = 48, Data = 22c03145
|
# READ STATUS: Burst-No: 21 Addr: 00016c93 Rxd: 3e502d7c
|
# READ STATUS: Burst-No: 21 Addr: 00016c93 Rxd: 3e502d7c
|
# tb_core.u_sdram32 : at time 44633.0 ns READ : Bank = 3 Row = 22, Col = 49, Data = c5cb548b
|
# tb_core.u_sdram32 : at time 45833.0 ns READ : Bank = 3 Row = 22, Col = 49, Data = c5cb548b
|
# READ STATUS: Burst-No: 22 Addr: 00016c95 Rxd: 22c03145
|
# READ STATUS: Burst-No: 22 Addr: 00016c95 Rxd: 22c03145
|
# tb_core.u_sdram32 : at time 44643.0 ns READ : Bank = 3 Row = 22, Col = 50, Data = 094bd312
|
# tb_core.u_sdram32 : at time 45843.0 ns READ : Bank = 3 Row = 22, Col = 50, Data = 094bd312
|
# READ STATUS: Burst-No: 23 Addr: 00016c97 Rxd: c5cb548b
|
# READ STATUS: Burst-No: 23 Addr: 00016c97 Rxd: c5cb548b
|
# tb_core.u_sdram32 : at time 44653.0 ns READ : Bank = 3 Row = 22, Col = 51, Data = 1bf8bd37
|
# tb_core.u_sdram32 : at time 45853.0 ns READ : Bank = 3 Row = 22, Col = 51, Data = 1bf8bd37
|
# READ STATUS: Burst-No: 24 Addr: 00016c99 Rxd: 094bd312
|
# READ STATUS: Burst-No: 24 Addr: 00016c99 Rxd: 094bd312
|
# tb_core.u_sdram32 : at time 44663.0 ns READ : Bank = 3 Row = 22, Col = 52, Data = c1c3d683
|
# tb_core.u_sdram32 : at time 45863.0 ns READ : Bank = 3 Row = 22, Col = 52, Data = c1c3d683
|
# READ STATUS: Burst-No: 25 Addr: 00016c9b Rxd: 1bf8bd37
|
# READ STATUS: Burst-No: 25 Addr: 00016c9b Rxd: 1bf8bd37
|
# tb_core.u_sdram32 : at time 44673.0 ns READ : Bank = 3 Row = 22, Col = 53, Data = f0ab00e1
|
# tb_core.u_sdram32 : at time 45873.0 ns READ : Bank = 3 Row = 22, Col = 53, Data = f0ab00e1
|
# READ STATUS: Burst-No: 26 Addr: 00016c9d Rxd: c1c3d683
|
# READ STATUS: Burst-No: 26 Addr: 00016c9d Rxd: c1c3d683
|
# tb_core.u_sdram32 : at time 44683.0 ns READ : Bank = 3 Row = 22, Col = 54, Data = 674fdfce
|
# tb_core.u_sdram32 : at time 45883.0 ns READ : Bank = 3 Row = 22, Col = 54, Data = 674fdfce
|
# READ STATUS: Burst-No: 27 Addr: 00016c9f Rxd: f0ab00e1
|
# READ STATUS: Burst-No: 27 Addr: 00016c9f Rxd: f0ab00e1
|
# tb_core.u_sdram32 : at time 44693.0 ns READ : Bank = 3 Row = 22, Col = 55, Data = a5365c4a
|
# tb_core.u_sdram32 : at time 45893.0 ns READ : Bank = 3 Row = 22, Col = 55, Data = a5365c4a
|
# READ STATUS: Burst-No: 28 Addr: 00016ca1 Rxd: 674fdfce
|
# READ STATUS: Burst-No: 28 Addr: 00016ca1 Rxd: 674fdfce
|
# tb_core.u_sdram32 : at time 44703.0 ns READ : Bank = 3 Row = 22, Col = 56, Data = 6acd73d5
|
# tb_core.u_sdram32 : at time 45903.0 ns READ : Bank = 3 Row = 22, Col = 56, Data = 6acd73d5
|
# READ STATUS: Burst-No: 29 Addr: 00016ca3 Rxd: a5365c4a
|
# READ STATUS: Burst-No: 29 Addr: 00016ca3 Rxd: a5365c4a
|
# tb_core.u_sdram32 : at time 44713.0 ns READ : Bank = 3 Row = 22, Col = 57, Data = 669907cd
|
# tb_core.u_sdram32 : at time 45913.0 ns READ : Bank = 3 Row = 22, Col = 57, Data = 669907cd
|
# READ STATUS: Burst-No: 30 Addr: 00016ca5 Rxd: 6acd73d5
|
# READ STATUS: Burst-No: 30 Addr: 00016ca5 Rxd: 6acd73d5
|
# tb_core.u_sdram32 : at time 44723.0 ns READ : Bank = 3 Row = 22, Col = 58, Data = f204eee4
|
# tb_core.u_sdram32 : at time 45923.0 ns READ : Bank = 3 Row = 22, Col = 58, Data = f204eee4
|
# READ STATUS: Burst-No: 31 Addr: 00016ca7 Rxd: 669907cd
|
# READ STATUS: Burst-No: 31 Addr: 00016ca7 Rxd: 669907cd
|
# tb_core.u_sdram32 : at time 44733.0 ns READ : Bank = 3 Row = 22, Col = 59, Data = fa328cf4
|
# tb_core.u_sdram32 : at time 45933.0 ns READ : Bank = 3 Row = 22, Col = 59, Data = fa328cf4
|
# READ STATUS: Burst-No: 32 Addr: 00016ca9 Rxd: f204eee4
|
# READ STATUS: Burst-No: 32 Addr: 00016ca9 Rxd: f204eee4
|
# tb_core.u_sdram32 : at time 44743.0 ns READ : Bank = 3 Row = 22, Col = 60, Data = 766153ec
|
# tb_core.u_sdram32 : at time 45943.0 ns READ : Bank = 3 Row = 22, Col = 60, Data = 766153ec
|
# READ STATUS: Burst-No: 33 Addr: 00016cab Rxd: fa328cf4
|
# READ STATUS: Burst-No: 33 Addr: 00016cab Rxd: fa328cf4
|
# tb_core.u_sdram32 : at time 44753.0 ns READ : Bank = 3 Row = 22, Col = 61, Data = 0d623f1a
|
# tb_core.u_sdram32 : at time 45953.0 ns READ : Bank = 3 Row = 22, Col = 61, Data = 0d623f1a
|
# READ STATUS: Burst-No: 34 Addr: 00016cad Rxd: 766153ec
|
# READ STATUS: Burst-No: 34 Addr: 00016cad Rxd: 766153ec
|
# tb_core.u_sdram32 : at time 44763.0 ns READ : Bank = 3 Row = 22, Col = 62, Data = f1a32ee3
|
# tb_core.u_sdram32 : at time 45963.0 ns READ : Bank = 3 Row = 22, Col = 62, Data = f1a32ee3
|
# READ STATUS: Burst-No: 35 Addr: 00016caf Rxd: 0d623f1a
|
# READ STATUS: Burst-No: 35 Addr: 00016caf Rxd: 0d623f1a
|
# tb_core.u_sdram32 : at time 44773.0 ns READ : Bank = 3 Row = 22, Col = 63, Data = f62484ec
|
# tb_core.u_sdram32 : at time 45973.0 ns READ : Bank = 3 Row = 22, Col = 63, Data = f62484ec
|
# READ STATUS: Burst-No: 36 Addr: 00016cb1 Rxd: f1a32ee3
|
# READ STATUS: Burst-No: 36 Addr: 00016cb1 Rxd: f1a32ee3
|
# tb_core.u_sdram32 : at time 44783.0 ns READ : Bank = 3 Row = 22, Col = 64, Data = 79c681f3
|
# tb_core.u_sdram32 : at time 45983.0 ns READ : Bank = 3 Row = 22, Col = 64, Data = 79c681f3
|
# READ STATUS: Burst-No: 37 Addr: 00016cb3 Rxd: f62484ec
|
# READ STATUS: Burst-No: 37 Addr: 00016cb3 Rxd: f62484ec
|
# tb_core.u_sdram32 : at time 44793.0 ns READ : Bank = 3 Row = 22, Col = 65, Data = 1687472d
|
# tb_core.u_sdram32 : at time 45993.0 ns READ : Bank = 3 Row = 22, Col = 65, Data = 1687472d
|
# READ STATUS: Burst-No: 38 Addr: 00016cb5 Rxd: 79c681f3
|
# READ STATUS: Burst-No: 38 Addr: 00016cb5 Rxd: 79c681f3
|
# tb_core.u_sdram32 : at time 44803.0 ns READ : Bank = 3 Row = 22, Col = 66, Data = 2e138d5c
|
# tb_core.u_sdram32 : at time 46003.0 ns READ : Bank = 3 Row = 22, Col = 66, Data = 2e138d5c
|
# READ STATUS: Burst-No: 39 Addr: 00016cb7 Rxd: 1687472d
|
# READ STATUS: Burst-No: 39 Addr: 00016cb7 Rxd: 1687472d
|
# tb_core.u_sdram32 : at time 44813.0 ns READ : Bank = 3 Row = 22, Col = 67, Data = 6e8d45dd
|
# tb_core.u_sdram32 : at time 46013.0 ns READ : Bank = 3 Row = 22, Col = 67, Data = 6e8d45dd
|
# READ STATUS: Burst-No: 40 Addr: 00016cb9 Rxd: 2e138d5c
|
# READ STATUS: Burst-No: 40 Addr: 00016cb9 Rxd: 2e138d5c
|
# tb_core.u_sdram32 : at time 44823.0 ns READ : Bank = 3 Row = 22, Col = 68, Data = f612c8ec
|
# tb_core.u_sdram32 : at time 46023.0 ns READ : Bank = 3 Row = 22, Col = 68, Data = f612c8ec
|
# READ STATUS: Burst-No: 41 Addr: 00016cbb Rxd: 6e8d45dd
|
# READ STATUS: Burst-No: 41 Addr: 00016cbb Rxd: 6e8d45dd
|
# tb_core.u_sdram32 : at time 44833.0 ns READ : Bank = 3 Row = 22, Col = 69, Data = c7d87a8f
|
# tb_core.u_sdram32 : at time 46033.0 ns READ : Bank = 3 Row = 22, Col = 69, Data = c7d87a8f
|
# READ STATUS: Burst-No: 42 Addr: 00016cbd Rxd: f612c8ec
|
# READ STATUS: Burst-No: 42 Addr: 00016cbd Rxd: f612c8ec
|
# tb_core.u_sdram32 : at time 44843.0 ns READ : Bank = 3 Row = 22, Col = 70, Data = 7fdbb3ff
|
# tb_core.u_sdram32 : at time 46043.0 ns READ : Bank = 3 Row = 22, Col = 70, Data = 7fdbb3ff
|
# READ STATUS: Burst-No: 43 Addr: 00016cbf Rxd: c7d87a8f
|
# READ STATUS: Burst-No: 43 Addr: 00016cbf Rxd: c7d87a8f
|
# tb_core.u_sdram32 : at time 44853.0 ns READ : Bank = 3 Row = 22, Col = 71, Data = 3c338578
|
# tb_core.u_sdram32 : at time 46053.0 ns READ : Bank = 3 Row = 22, Col = 71, Data = 3c338578
|
# READ STATUS: Burst-No: 44 Addr: 00016cc1 Rxd: 7fdbb3ff
|
# READ STATUS: Burst-No: 44 Addr: 00016cc1 Rxd: 7fdbb3ff
|
# tb_core.u_sdram32 : at time 44863.0 ns READ : Bank = 3 Row = 22, Col = 72, Data = 55f6b9ab
|
# tb_core.u_sdram32 : at time 46063.0 ns READ : Bank = 3 Row = 22, Col = 72, Data = 55f6b9ab
|
# READ STATUS: Burst-No: 45 Addr: 00016cc3 Rxd: 3c338578
|
# READ STATUS: Burst-No: 45 Addr: 00016cc3 Rxd: 3c338578
|
# tb_core.u_sdram32 : at time 44873.0 ns READ : Bank = 3 Row = 22, Col = 73, Data = 13d1f727
|
# tb_core.u_sdram32 : at time 46073.0 ns READ : Bank = 3 Row = 22, Col = 73, Data = 13d1f727
|
# READ STATUS: Burst-No: 46 Addr: 00016cc5 Rxd: 55f6b9ab
|
# READ STATUS: Burst-No: 46 Addr: 00016cc5 Rxd: 55f6b9ab
|
# tb_core.u_sdram32 : at time 44883.0 ns READ : Bank = 3 Row = 22, Col = 74, Data = 7dca0ffb
|
# tb_core.u_sdram32 : at time 46083.0 ns READ : Bank = 3 Row = 22, Col = 74, Data = 7dca0ffb
|
# READ STATUS: Burst-No: 47 Addr: 00016cc7 Rxd: 13d1f727
|
# READ STATUS: Burst-No: 47 Addr: 00016cc7 Rxd: 13d1f727
|
# tb_core.u_sdram32 : at time 44893.0 ns READ : Bank = 3 Row = 22, Col = 75, Data = 09dfc313
|
# tb_core.u_sdram32 : at time 46093.0 ns READ : Bank = 3 Row = 22, Col = 75, Data = 09dfc313
|
# READ STATUS: Burst-No: 48 Addr: 00016cc9 Rxd: 7dca0ffb
|
# READ STATUS: Burst-No: 48 Addr: 00016cc9 Rxd: 7dca0ffb
|
# tb_core.u_sdram32 : at time 44903.0 ns READ : Bank = 3 Row = 22, Col = 76, Data = 06499b0c
|
# tb_core.u_sdram32 : at time 46103.0 ns READ : Bank = 3 Row = 22, Col = 76, Data = 06499b0c
|
# READ STATUS: Burst-No: 49 Addr: 00016ccb Rxd: 09dfc313
|
# READ STATUS: Burst-No: 49 Addr: 00016ccb Rxd: 09dfc313
|
# tb_core.u_sdram32 : at time 44913.0 ns READ : Bank = 3 Row = 22, Col = 77, Data = 5db797bb
|
# tb_core.u_sdram32 : at time 46113.0 ns READ : Bank = 3 Row = 22, Col = 77, Data = 5db797bb
|
# READ STATUS: Burst-No: 50 Addr: 00016ccd Rxd: 06499b0c
|
# READ STATUS: Burst-No: 50 Addr: 00016ccd Rxd: 06499b0c
|
# tb_core.u_sdram32 : at time 44923.0 ns READ : Bank = 3 Row = 22, Col = 78, Data = f361cae6
|
# tb_core.u_sdram32 : at time 46123.0 ns READ : Bank = 3 Row = 22, Col = 78, Data = f361cae6
|
# READ STATUS: Burst-No: 51 Addr: 00016ccf Rxd: 5db797bb
|
# READ STATUS: Burst-No: 51 Addr: 00016ccf Rxd: 5db797bb
|
# tb_core.u_sdram32 : at time 44933.0 ns READ : Bank = 3 Row = 22, Col = 79, Data = a4d83a49
|
# tb_core.u_sdram32 : at time 46133.0 ns READ : Bank = 3 Row = 22, Col = 79, Data = a4d83a49
|
# READ STATUS: Burst-No: 52 Addr: 00016cd1 Rxd: f361cae6
|
# READ STATUS: Burst-No: 52 Addr: 00016cd1 Rxd: f361cae6
|
# tb_core.u_sdram32 : at time 44943.0 ns READ : Bank = 3 Row = 22, Col = 80, Data = 35557b6a
|
# tb_core.u_sdram32 : at time 46143.0 ns READ : Bank = 3 Row = 22, Col = 80, Data = 35557b6a
|
# READ STATUS: Burst-No: 53 Addr: 00016cd3 Rxd: a4d83a49
|
# READ STATUS: Burst-No: 53 Addr: 00016cd3 Rxd: a4d83a49
|
# tb_core.u_sdram32 : at time 44953.0 ns READ : Bank = 3 Row = 22, Col = 81, Data = 8570f60a
|
# tb_core.u_sdram32 : at time 46153.0 ns READ : Bank = 3 Row = 22, Col = 81, Data = 8570f60a
|
# READ STATUS: Burst-No: 54 Addr: 00016cd5 Rxd: 35557b6a
|
# READ STATUS: Burst-No: 54 Addr: 00016cd5 Rxd: 35557b6a
|
# tb_core.u_sdram32 : at time 44963.0 ns READ : Bank = 3 Row = 22, Col = 82, Data = 8c06d218
|
# tb_core.u_sdram32 : at time 46163.0 ns READ : Bank = 3 Row = 22, Col = 82, Data = 8c06d218
|
# tb_core.u_sdram32 : at time 44967.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 46167.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 55 Addr: 00016cd7 Rxd: 8570f60a
|
# READ STATUS: Burst-No: 55 Addr: 00016cd7 Rxd: 8570f60a
|
# tb_core.u_sdram32 : at time 44973.0 ns READ : Bank = 3 Row = 22, Col = 83, Data = 4b1ce996
|
# tb_core.u_sdram32 : at time 46173.0 ns READ : Bank = 3 Row = 22, Col = 83, Data = 4b1ce996
|
# READ STATUS: Burst-No: 56 Addr: 00016cd9 Rxd: 8c06d218
|
# READ STATUS: Burst-No: 56 Addr: 00016cd9 Rxd: 8c06d218
|
# tb_core.u_sdram32 : at time 44983.0 ns READ : Bank = 3 Row = 22, Col = 84, Data = 84e32609
|
# tb_core.u_sdram32 : at time 46183.0 ns READ : Bank = 3 Row = 22, Col = 84, Data = 84e32609
|
# READ STATUS: Burst-No: 57 Addr: 00016cdb Rxd: 4b1ce996
|
# READ STATUS: Burst-No: 57 Addr: 00016cdb Rxd: 4b1ce996
|
# READ STATUS: Burst-No: 58 Addr: 00016cdd Rxd: 84e32609
|
# READ STATUS: Burst-No: 58 Addr: 00016cdd Rxd: 84e32609
|
# Write Address: 0025712e, Burst Size: 62
|
# Write Address: 0025712e, Burst Size: 62
|
# tb_core.u_sdram32 : at time 45157.0 ns ACT : Bank = 0 Row = 599
|
# tb_core.u_sdram32 : at time 46357.0 ns ACT : Bank = 0 Row = 599
|
# tb_core.u_sdram32 : at time 45187.0 ns WRITE: Bank = 0 Row = 599, Col = 75, Data = 33638966
|
# tb_core.u_sdram32 : at time 46387.0 ns WRITE: Bank = 0 Row = 599, Col = 75, Data = 33638966
|
# Status: Burst-No: 0 Write Address: 0025712e WriteData: 33638966
|
# Status: Burst-No: 0 Write Address: 0025712e WriteData: 33638966
|
# tb_core.u_sdram32 : at time 45197.0 ns WRITE: Bank = 0 Row = 599, Col = 76, Data = bb062876
|
# tb_core.u_sdram32 : at time 46397.0 ns WRITE: Bank = 0 Row = 599, Col = 76, Data = bb062876
|
# Status: Burst-No: 1 Write Address: 0025712e WriteData: bb062876
|
# Status: Burst-No: 1 Write Address: 0025712e WriteData: bb062876
|
# tb_core.u_sdram32 : at time 45207.0 ns WRITE: Bank = 0 Row = 599, Col = 77, Data = 3a982575
|
# tb_core.u_sdram32 : at time 46407.0 ns WRITE: Bank = 0 Row = 599, Col = 77, Data = 3a982575
|
# Status: Burst-No: 2 Write Address: 0025712e WriteData: 3a982575
|
# Status: Burst-No: 2 Write Address: 0025712e WriteData: 3a982575
|
# tb_core.u_sdram32 : at time 45217.0 ns WRITE: Bank = 0 Row = 599, Col = 78, Data = c7b43a8f
|
# tb_core.u_sdram32 : at time 46417.0 ns WRITE: Bank = 0 Row = 599, Col = 78, Data = c7b43a8f
|
# Status: Burst-No: 3 Write Address: 0025712e WriteData: c7b43a8f
|
# Status: Burst-No: 3 Write Address: 0025712e WriteData: c7b43a8f
|
# tb_core.u_sdram32 : at time 45227.0 ns WRITE: Bank = 0 Row = 599, Col = 79, Data = 4ad39595
|
# tb_core.u_sdram32 : at time 46427.0 ns WRITE: Bank = 0 Row = 599, Col = 79, Data = 4ad39595
|
# Status: Burst-No: 4 Write Address: 0025712e WriteData: 4ad39595
|
# Status: Burst-No: 4 Write Address: 0025712e WriteData: 4ad39595
|
# tb_core.u_sdram32 : at time 45237.0 ns WRITE: Bank = 0 Row = 599, Col = 80, Data = 3da8cd7b
|
# tb_core.u_sdram32 : at time 46437.0 ns WRITE: Bank = 0 Row = 599, Col = 80, Data = 3da8cd7b
|
# Status: Burst-No: 5 Write Address: 0025712e WriteData: 3da8cd7b
|
# Status: Burst-No: 5 Write Address: 0025712e WriteData: 3da8cd7b
|
# tb_core.u_sdram32 : at time 45247.0 ns WRITE: Bank = 0 Row = 599, Col = 81, Data = be43ea7c
|
# tb_core.u_sdram32 : at time 46447.0 ns WRITE: Bank = 0 Row = 599, Col = 81, Data = be43ea7c
|
# Status: Burst-No: 6 Write Address: 0025712e WriteData: be43ea7c
|
# Status: Burst-No: 6 Write Address: 0025712e WriteData: be43ea7c
|
# tb_core.u_sdram32 : at time 45257.0 ns WRITE: Bank = 0 Row = 599, Col = 82, Data = b7f4306f
|
# tb_core.u_sdram32 : at time 46457.0 ns WRITE: Bank = 0 Row = 599, Col = 82, Data = b7f4306f
|
# Status: Burst-No: 7 Write Address: 0025712e WriteData: b7f4306f
|
# Status: Burst-No: 7 Write Address: 0025712e WriteData: b7f4306f
|
# tb_core.u_sdram32 : at time 45267.0 ns WRITE: Bank = 0 Row = 599, Col = 83, Data = e4824cc9
|
# tb_core.u_sdram32 : at time 46467.0 ns WRITE: Bank = 0 Row = 599, Col = 83, Data = e4824cc9
|
# Status: Burst-No: 8 Write Address: 0025712e WriteData: e4824cc9
|
# Status: Burst-No: 8 Write Address: 0025712e WriteData: e4824cc9
|
# tb_core.u_sdram32 : at time 45277.0 ns WRITE: Bank = 0 Row = 599, Col = 84, Data = e4d820c9
|
# tb_core.u_sdram32 : at time 46477.0 ns WRITE: Bank = 0 Row = 599, Col = 84, Data = e4d820c9
|
# Status: Burst-No: 9 Write Address: 0025712e WriteData: e4d820c9
|
# Status: Burst-No: 9 Write Address: 0025712e WriteData: e4d820c9
|
# tb_core.u_sdram32 : at time 45287.0 ns WRITE: Bank = 0 Row = 599, Col = 85, Data = 5a3761b4
|
# tb_core.u_sdram32 : at time 46487.0 ns WRITE: Bank = 0 Row = 599, Col = 85, Data = 5a3761b4
|
# Status: Burst-No: 10 Write Address: 0025712e WriteData: 5a3761b4
|
# Status: Burst-No: 10 Write Address: 0025712e WriteData: 5a3761b4
|
# tb_core.u_sdram32 : at time 45297.0 ns WRITE: Bank = 0 Row = 599, Col = 86, Data = 6d48a5da
|
# tb_core.u_sdram32 : at time 46497.0 ns WRITE: Bank = 0 Row = 599, Col = 86, Data = 6d48a5da
|
# Status: Burst-No: 11 Write Address: 0025712e WriteData: 6d48a5da
|
# Status: Burst-No: 11 Write Address: 0025712e WriteData: 6d48a5da
|
# tb_core.u_sdram32 : at time 45307.0 ns WRITE: Bank = 0 Row = 599, Col = 87, Data = d6aea8ad
|
# tb_core.u_sdram32 : at time 46507.0 ns WRITE: Bank = 0 Row = 599, Col = 87, Data = d6aea8ad
|
# Status: Burst-No: 12 Write Address: 0025712e WriteData: d6aea8ad
|
# Status: Burst-No: 12 Write Address: 0025712e WriteData: d6aea8ad
|
# tb_core.u_sdram32 : at time 45317.0 ns WRITE: Bank = 0 Row = 599, Col = 88, Data = 6fcff1df
|
# tb_core.u_sdram32 : at time 46517.0 ns WRITE: Bank = 0 Row = 599, Col = 88, Data = 6fcff1df
|
# Status: Burst-No: 13 Write Address: 0025712e WriteData: 6fcff1df
|
# Status: Burst-No: 13 Write Address: 0025712e WriteData: 6fcff1df
|
# tb_core.u_sdram32 : at time 45327.0 ns WRITE: Bank = 0 Row = 599, Col = 89, Data = 06b0e30d
|
# tb_core.u_sdram32 : at time 46527.0 ns WRITE: Bank = 0 Row = 599, Col = 89, Data = 06b0e30d
|
# Status: Burst-No: 14 Write Address: 0025712e WriteData: 06b0e30d
|
# Status: Burst-No: 14 Write Address: 0025712e WriteData: 06b0e30d
|
# tb_core.u_sdram32 : at time 45337.0 ns WRITE: Bank = 0 Row = 599, Col = 90, Data = 384d4170
|
# tb_core.u_sdram32 : at time 46537.0 ns WRITE: Bank = 0 Row = 599, Col = 90, Data = 384d4170
|
# Status: Burst-No: 15 Write Address: 0025712e WriteData: 384d4170
|
# Status: Burst-No: 15 Write Address: 0025712e WriteData: 384d4170
|
# tb_core.u_sdram32 : at time 45347.0 ns WRITE: Bank = 0 Row = 599, Col = 91, Data = 41bd6783
|
# tb_core.u_sdram32 : at time 46547.0 ns WRITE: Bank = 0 Row = 599, Col = 91, Data = 41bd6783
|
# Status: Burst-No: 16 Write Address: 0025712e WriteData: 41bd6783
|
# Status: Burst-No: 16 Write Address: 0025712e WriteData: 41bd6783
|
# tb_core.u_sdram32 : at time 45357.0 ns WRITE: Bank = 0 Row = 599, Col = 92, Data = a8c6c451
|
# tb_core.u_sdram32 : at time 46557.0 ns WRITE: Bank = 0 Row = 599, Col = 92, Data = a8c6c451
|
# Status: Burst-No: 17 Write Address: 0025712e WriteData: a8c6c451
|
# Status: Burst-No: 17 Write Address: 0025712e WriteData: a8c6c451
|
# tb_core.u_sdram32 : at time 45367.0 ns WRITE: Bank = 0 Row = 599, Col = 93, Data = 027a8d04
|
# tb_core.u_sdram32 : at time 46567.0 ns WRITE: Bank = 0 Row = 599, Col = 93, Data = 027a8d04
|
# Status: Burst-No: 18 Write Address: 0025712e WriteData: 027a8d04
|
# Status: Burst-No: 18 Write Address: 0025712e WriteData: 027a8d04
|
# tb_core.u_sdram32 : at time 45377.0 ns WRITE: Bank = 0 Row = 599, Col = 94, Data = c0467280
|
# tb_core.u_sdram32 : at time 46577.0 ns WRITE: Bank = 0 Row = 599, Col = 94, Data = c0467280
|
# Status: Burst-No: 19 Write Address: 0025712e WriteData: c0467280
|
# Status: Burst-No: 19 Write Address: 0025712e WriteData: c0467280
|
# tb_core.u_sdram32 : at time 45387.0 ns WRITE: Bank = 0 Row = 599, Col = 95, Data = fcf504f9
|
# tb_core.u_sdram32 : at time 46587.0 ns WRITE: Bank = 0 Row = 599, Col = 95, Data = fcf504f9
|
# Status: Burst-No: 20 Write Address: 0025712e WriteData: fcf504f9
|
# Status: Burst-No: 20 Write Address: 0025712e WriteData: fcf504f9
|
# tb_core.u_sdram32 : at time 45397.0 ns WRITE: Bank = 0 Row = 599, Col = 96, Data = 0379ed06
|
# tb_core.u_sdram32 : at time 46597.0 ns WRITE: Bank = 0 Row = 599, Col = 96, Data = 0379ed06
|
# Status: Burst-No: 21 Write Address: 0025712e WriteData: 0379ed06
|
# Status: Burst-No: 21 Write Address: 0025712e WriteData: 0379ed06
|
# tb_core.u_sdram32 : at time 45407.0 ns WRITE: Bank = 0 Row = 599, Col = 97, Data = e5063aca
|
# tb_core.u_sdram32 : at time 46607.0 ns WRITE: Bank = 0 Row = 599, Col = 97, Data = e5063aca
|
# Status: Burst-No: 22 Write Address: 0025712e WriteData: e5063aca
|
# Status: Burst-No: 22 Write Address: 0025712e WriteData: e5063aca
|
# tb_core.u_sdram32 : at time 45417.0 ns WRITE: Bank = 0 Row = 599, Col = 98, Data = ef8d64df
|
# tb_core.u_sdram32 : at time 46617.0 ns WRITE: Bank = 0 Row = 599, Col = 98, Data = ef8d64df
|
# Status: Burst-No: 23 Write Address: 0025712e WriteData: ef8d64df
|
# Status: Burst-No: 23 Write Address: 0025712e WriteData: ef8d64df
|
# tb_core.u_sdram32 : at time 45427.0 ns WRITE: Bank = 0 Row = 599, Col = 99, Data = 64f9bbc9
|
# tb_core.u_sdram32 : at time 46627.0 ns WRITE: Bank = 0 Row = 599, Col = 99, Data = 64f9bbc9
|
# Status: Burst-No: 24 Write Address: 0025712e WriteData: 64f9bbc9
|
# Status: Burst-No: 24 Write Address: 0025712e WriteData: 64f9bbc9
|
# tb_core.u_sdram32 : at time 45437.0 ns WRITE: Bank = 0 Row = 599, Col = 100, Data = 42797584
|
# tb_core.u_sdram32 : at time 46637.0 ns WRITE: Bank = 0 Row = 599, Col = 100, Data = 42797584
|
# Status: Burst-No: 25 Write Address: 0025712e WriteData: 42797584
|
# Status: Burst-No: 25 Write Address: 0025712e WriteData: 42797584
|
# tb_core.u_sdram32 : at time 45447.0 ns WRITE: Bank = 0 Row = 599, Col = 101, Data = d84988b0
|
# tb_core.u_sdram32 : at time 46647.0 ns WRITE: Bank = 0 Row = 599, Col = 101, Data = d84988b0
|
# Status: Burst-No: 26 Write Address: 0025712e WriteData: d84988b0
|
# Status: Burst-No: 26 Write Address: 0025712e WriteData: d84988b0
|
# tb_core.u_sdram32 : at time 45457.0 ns WRITE: Bank = 0 Row = 599, Col = 102, Data = 74bc03e9
|
# tb_core.u_sdram32 : at time 46657.0 ns WRITE: Bank = 0 Row = 599, Col = 102, Data = 74bc03e9
|
# Status: Burst-No: 27 Write Address: 0025712e WriteData: 74bc03e9
|
# Status: Burst-No: 27 Write Address: 0025712e WriteData: 74bc03e9
|
# tb_core.u_sdram32 : at time 45467.0 ns WRITE: Bank = 0 Row = 599, Col = 103, Data = 08098510
|
# tb_core.u_sdram32 : at time 46667.0 ns WRITE: Bank = 0 Row = 599, Col = 103, Data = 08098510
|
# Status: Burst-No: 28 Write Address: 0025712e WriteData: 08098510
|
# Status: Burst-No: 28 Write Address: 0025712e WriteData: 08098510
|
# tb_core.u_sdram32 : at time 45477.0 ns WRITE: Bank = 0 Row = 599, Col = 104, Data = 6f3425de
|
# tb_core.u_sdram32 : at time 46677.0 ns WRITE: Bank = 0 Row = 599, Col = 104, Data = 6f3425de
|
# Status: Burst-No: 29 Write Address: 0025712e WriteData: 6f3425de
|
# Status: Burst-No: 29 Write Address: 0025712e WriteData: 6f3425de
|
# tb_core.u_sdram32 : at time 45487.0 ns WRITE: Bank = 0 Row = 599, Col = 105, Data = d659d0ac
|
# tb_core.u_sdram32 : at time 46687.0 ns WRITE: Bank = 0 Row = 599, Col = 105, Data = d659d0ac
|
# Status: Burst-No: 30 Write Address: 0025712e WriteData: d659d0ac
|
# Status: Burst-No: 30 Write Address: 0025712e WriteData: d659d0ac
|
# tb_core.u_sdram32 : at time 45497.0 ns WRITE: Bank = 0 Row = 599, Col = 106, Data = 0498fb09
|
# tb_core.u_sdram32 : at time 46697.0 ns WRITE: Bank = 0 Row = 599, Col = 106, Data = 0498fb09
|
# Status: Burst-No: 31 Write Address: 0025712e WriteData: 0498fb09
|
# Status: Burst-No: 31 Write Address: 0025712e WriteData: 0498fb09
|
# tb_core.u_sdram32 : at time 45507.0 ns WRITE: Bank = 0 Row = 599, Col = 107, Data = 6bf823d7
|
# tb_core.u_sdram32 : at time 46707.0 ns WRITE: Bank = 0 Row = 599, Col = 107, Data = 6bf823d7
|
# Status: Burst-No: 32 Write Address: 0025712e WriteData: 6bf823d7
|
# Status: Burst-No: 32 Write Address: 0025712e WriteData: 6bf823d7
|
# tb_core.u_sdram32 : at time 45517.0 ns WRITE: Bank = 0 Row = 599, Col = 108, Data = 30c38f61
|
# tb_core.u_sdram32 : at time 46717.0 ns WRITE: Bank = 0 Row = 599, Col = 108, Data = 30c38f61
|
# Status: Burst-No: 33 Write Address: 0025712e WriteData: 30c38f61
|
# Status: Burst-No: 33 Write Address: 0025712e WriteData: 30c38f61
|
# tb_core.u_sdram32 : at time 45527.0 ns WRITE: Bank = 0 Row = 599, Col = 109, Data = 86c8320d
|
# tb_core.u_sdram32 : at time 46727.0 ns WRITE: Bank = 0 Row = 599, Col = 109, Data = 86c8320d
|
# Status: Burst-No: 34 Write Address: 0025712e WriteData: 86c8320d
|
# Status: Burst-No: 34 Write Address: 0025712e WriteData: 86c8320d
|
# tb_core.u_sdram32 : at time 45537.0 ns WRITE: Bank = 0 Row = 599, Col = 110, Data = 48c3b791
|
# tb_core.u_sdram32 : at time 46737.0 ns WRITE: Bank = 0 Row = 599, Col = 110, Data = 48c3b791
|
# Status: Burst-No: 35 Write Address: 0025712e WriteData: 48c3b791
|
# Status: Burst-No: 35 Write Address: 0025712e WriteData: 48c3b791
|
# tb_core.u_sdram32 : at time 45547.0 ns WRITE: Bank = 0 Row = 599, Col = 111, Data = e9eb0ed3
|
# tb_core.u_sdram32 : at time 46747.0 ns WRITE: Bank = 0 Row = 599, Col = 111, Data = e9eb0ed3
|
# Status: Burst-No: 36 Write Address: 0025712e WriteData: e9eb0ed3
|
# Status: Burst-No: 36 Write Address: 0025712e WriteData: e9eb0ed3
|
# tb_core.u_sdram32 : at time 45557.0 ns WRITE: Bank = 0 Row = 599, Col = 112, Data = 4d77f99a
|
# tb_core.u_sdram32 : at time 46757.0 ns WRITE: Bank = 0 Row = 599, Col = 112, Data = 4d77f99a
|
# Status: Burst-No: 37 Write Address: 0025712e WriteData: 4d77f99a
|
# Status: Burst-No: 37 Write Address: 0025712e WriteData: 4d77f99a
|
# tb_core.u_sdram32 : at time 45567.0 ns WRITE: Bank = 0 Row = 599, Col = 113, Data = 17bd872f
|
# tb_core.u_sdram32 : at time 46767.0 ns WRITE: Bank = 0 Row = 599, Col = 113, Data = 17bd872f
|
# Status: Burst-No: 38 Write Address: 0025712e WriteData: 17bd872f
|
# Status: Burst-No: 38 Write Address: 0025712e WriteData: 17bd872f
|
# tb_core.u_sdram32 : at time 45577.0 ns WRITE: Bank = 0 Row = 599, Col = 114, Data = 2720634e
|
# tb_core.u_sdram32 : at time 46777.0 ns WRITE: Bank = 0 Row = 599, Col = 114, Data = 2720634e
|
# Status: Burst-No: 39 Write Address: 0025712e WriteData: 2720634e
|
# Status: Burst-No: 39 Write Address: 0025712e WriteData: 2720634e
|
# tb_core.u_sdram32 : at time 45587.0 ns WRITE: Bank = 0 Row = 599, Col = 115, Data = 5bd583b7
|
# tb_core.u_sdram32 : at time 46787.0 ns WRITE: Bank = 0 Row = 599, Col = 115, Data = 5bd583b7
|
# Status: Burst-No: 40 Write Address: 0025712e WriteData: 5bd583b7
|
# Status: Burst-No: 40 Write Address: 0025712e WriteData: 5bd583b7
|
# tb_core.u_sdram32 : at time 45597.0 ns WRITE: Bank = 0 Row = 599, Col = 116, Data = e32472c6
|
# tb_core.u_sdram32 : at time 46797.0 ns WRITE: Bank = 0 Row = 599, Col = 116, Data = e32472c6
|
# Status: Burst-No: 41 Write Address: 0025712e WriteData: e32472c6
|
# Status: Burst-No: 41 Write Address: 0025712e WriteData: e32472c6
|
# tb_core.u_sdram32 : at time 45607.0 ns WRITE: Bank = 0 Row = 599, Col = 117, Data = 2ed66b5d
|
# tb_core.u_sdram32 : at time 46807.0 ns WRITE: Bank = 0 Row = 599, Col = 117, Data = 2ed66b5d
|
# Status: Burst-No: 42 Write Address: 0025712e WriteData: 2ed66b5d
|
# Status: Burst-No: 42 Write Address: 0025712e WriteData: 2ed66b5d
|
# tb_core.u_sdram32 : at time 45617.0 ns WRITE: Bank = 0 Row = 599, Col = 118, Data = ce03ec9c
|
# tb_core.u_sdram32 : at time 46817.0 ns WRITE: Bank = 0 Row = 599, Col = 118, Data = ce03ec9c
|
# Status: Burst-No: 43 Write Address: 0025712e WriteData: ce03ec9c
|
# Status: Burst-No: 43 Write Address: 0025712e WriteData: ce03ec9c
|
# tb_core.u_sdram32 : at time 45627.0 ns WRITE: Bank = 0 Row = 599, Col = 119, Data = 17b47f2f
|
# tb_core.u_sdram32 : at time 46827.0 ns WRITE: Bank = 0 Row = 599, Col = 119, Data = 17b47f2f
|
# Status: Burst-No: 44 Write Address: 0025712e WriteData: 17b47f2f
|
# Status: Burst-No: 44 Write Address: 0025712e WriteData: 17b47f2f
|
# tb_core.u_sdram32 : at time 45637.0 ns WRITE: Bank = 0 Row = 599, Col = 120, Data = a22ac644
|
# tb_core.u_sdram32 : at time 46837.0 ns WRITE: Bank = 0 Row = 599, Col = 120, Data = a22ac644
|
# Status: Burst-No: 45 Write Address: 0025712e WriteData: a22ac644
|
# Status: Burst-No: 45 Write Address: 0025712e WriteData: a22ac644
|
# tb_core.u_sdram32 : at time 45647.0 ns WRITE: Bank = 0 Row = 599, Col = 121, Data = cdbf3a9b
|
# tb_core.u_sdram32 : at time 46847.0 ns WRITE: Bank = 0 Row = 599, Col = 121, Data = cdbf3a9b
|
# Status: Burst-No: 46 Write Address: 0025712e WriteData: cdbf3a9b
|
# Status: Burst-No: 46 Write Address: 0025712e WriteData: cdbf3a9b
|
# tb_core.u_sdram32 : at time 45657.0 ns WRITE: Bank = 0 Row = 599, Col = 122, Data = b1200062
|
# tb_core.u_sdram32 : at time 46857.0 ns WRITE: Bank = 0 Row = 599, Col = 122, Data = b1200062
|
# Status: Burst-No: 47 Write Address: 0025712e WriteData: b1200062
|
# Status: Burst-No: 47 Write Address: 0025712e WriteData: b1200062
|
# tb_core.u_sdram32 : at time 45667.0 ns WRITE: Bank = 0 Row = 599, Col = 123, Data = 748abbe9
|
# tb_core.u_sdram32 : at time 46867.0 ns WRITE: Bank = 0 Row = 599, Col = 123, Data = 748abbe9
|
# Status: Burst-No: 48 Write Address: 0025712e WriteData: 748abbe9
|
# Status: Burst-No: 48 Write Address: 0025712e WriteData: 748abbe9
|
# tb_core.u_sdram32 : at time 45677.0 ns WRITE: Bank = 0 Row = 599, Col = 124, Data = 1747832e
|
# tb_core.u_sdram32 : at time 46877.0 ns WRITE: Bank = 0 Row = 599, Col = 124, Data = 1747832e
|
# Status: Burst-No: 49 Write Address: 0025712e WriteData: 1747832e
|
# Status: Burst-No: 49 Write Address: 0025712e WriteData: 1747832e
|
# tb_core.u_sdram32 : at time 45687.0 ns WRITE: Bank = 0 Row = 599, Col = 125, Data = c690128d
|
# tb_core.u_sdram32 : at time 46887.0 ns WRITE: Bank = 0 Row = 599, Col = 125, Data = c690128d
|
# Status: Burst-No: 50 Write Address: 0025712e WriteData: c690128d
|
# Status: Burst-No: 50 Write Address: 0025712e WriteData: c690128d
|
# tb_core.u_sdram32 : at time 45697.0 ns WRITE: Bank = 0 Row = 599, Col = 126, Data = 632f07c6
|
# tb_core.u_sdram32 : at time 46897.0 ns WRITE: Bank = 0 Row = 599, Col = 126, Data = 632f07c6
|
# Status: Burst-No: 51 Write Address: 0025712e WriteData: 632f07c6
|
# Status: Burst-No: 51 Write Address: 0025712e WriteData: 632f07c6
|
# tb_core.u_sdram32 : at time 45707.0 ns WRITE: Bank = 0 Row = 599, Col = 127, Data = d51cb4aa
|
# tb_core.u_sdram32 : at time 46907.0 ns WRITE: Bank = 0 Row = 599, Col = 127, Data = d51cb4aa
|
# Status: Burst-No: 52 Write Address: 0025712e WriteData: d51cb4aa
|
# Status: Burst-No: 52 Write Address: 0025712e WriteData: d51cb4aa
|
# tb_core.u_sdram32 : at time 45717.0 ns WRITE: Bank = 0 Row = 599, Col = 128, Data = d01df0a0
|
# tb_core.u_sdram32 : at time 46917.0 ns WRITE: Bank = 0 Row = 599, Col = 128, Data = d01df0a0
|
# Status: Burst-No: 53 Write Address: 0025712e WriteData: d01df0a0
|
# Status: Burst-No: 53 Write Address: 0025712e WriteData: d01df0a0
|
# tb_core.u_sdram32 : at time 45727.0 ns WRITE: Bank = 0 Row = 599, Col = 129, Data = 1be8cf37
|
# tb_core.u_sdram32 : at time 46927.0 ns WRITE: Bank = 0 Row = 599, Col = 129, Data = 1be8cf37
|
# Status: Burst-No: 54 Write Address: 0025712e WriteData: 1be8cf37
|
# Status: Burst-No: 54 Write Address: 0025712e WriteData: 1be8cf37
|
# tb_core.u_sdram32 : at time 45737.0 ns WRITE: Bank = 0 Row = 599, Col = 130, Data = f8602ef0
|
# tb_core.u_sdram32 : at time 46937.0 ns WRITE: Bank = 0 Row = 599, Col = 130, Data = f8602ef0
|
# Status: Burst-No: 55 Write Address: 0025712e WriteData: f8602ef0
|
# Status: Burst-No: 55 Write Address: 0025712e WriteData: f8602ef0
|
# tb_core.u_sdram32 : at time 45747.0 ns WRITE: Bank = 0 Row = 599, Col = 131, Data = f46ca8e8
|
# tb_core.u_sdram32 : at time 46947.0 ns WRITE: Bank = 0 Row = 599, Col = 131, Data = f46ca8e8
|
# Status: Burst-No: 56 Write Address: 0025712e WriteData: f46ca8e8
|
# Status: Burst-No: 56 Write Address: 0025712e WriteData: f46ca8e8
|
# tb_core.u_sdram32 : at time 45757.0 ns WRITE: Bank = 0 Row = 599, Col = 132, Data = e6841ccd
|
# tb_core.u_sdram32 : at time 46957.0 ns WRITE: Bank = 0 Row = 599, Col = 132, Data = e6841ccd
|
# Status: Burst-No: 57 Write Address: 0025712e WriteData: e6841ccd
|
# Status: Burst-No: 57 Write Address: 0025712e WriteData: e6841ccd
|
# tb_core.u_sdram32 : at time 45767.0 ns WRITE: Bank = 0 Row = 599, Col = 133, Data = 68cd09d1
|
# tb_core.u_sdram32 : at time 46967.0 ns WRITE: Bank = 0 Row = 599, Col = 133, Data = 68cd09d1
|
# Status: Burst-No: 58 Write Address: 0025712e WriteData: 68cd09d1
|
# Status: Burst-No: 58 Write Address: 0025712e WriteData: 68cd09d1
|
# tb_core.u_sdram32 : at time 45777.0 ns WRITE: Bank = 0 Row = 599, Col = 134, Data = 5d8363bb
|
# tb_core.u_sdram32 : at time 46977.0 ns WRITE: Bank = 0 Row = 599, Col = 134, Data = 5d8363bb
|
# Status: Burst-No: 59 Write Address: 0025712e WriteData: 5d8363bb
|
# Status: Burst-No: 59 Write Address: 0025712e WriteData: 5d8363bb
|
# tb_core.u_sdram32 : at time 45787.0 ns WRITE: Bank = 0 Row = 599, Col = 135, Data = eff692df
|
# tb_core.u_sdram32 : at time 46987.0 ns WRITE: Bank = 0 Row = 599, Col = 135, Data = eff692df
|
# Status: Burst-No: 60 Write Address: 0025712e WriteData: eff692df
|
# Status: Burst-No: 60 Write Address: 0025712e WriteData: eff692df
|
# tb_core.u_sdram32 : at time 45797.0 ns WRITE: Bank = 0 Row = 599, Col = 136, Data = 3e8ed57d
|
# tb_core.u_sdram32 : at time 46997.0 ns WRITE: Bank = 0 Row = 599, Col = 136, Data = 3e8ed57d
|
# Status: Burst-No: 61 Write Address: 0025712e WriteData: 3e8ed57d
|
# Status: Burst-No: 61 Write Address: 0025712e WriteData: 3e8ed57d
|
# tb_core.u_sdram32 : at time 45807.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 47007.0 ns BST : Burst Terminate
|
# Write Address: 00002158, Burst Size: 32
|
# Write Address: 00002158, Burst Size: 32
|
# tb_core.u_sdram32 : at time 45947.0 ns ACT : Bank = 0 Row = 2
|
# tb_core.u_sdram32 : at time 47147.0 ns ACT : Bank = 0 Row = 2
|
# tb_core.u_sdram32 : at time 45977.0 ns WRITE: Bank = 0 Row = 2, Col = 86, Data = 4bac2f97
|
# tb_core.u_sdram32 : at time 47177.0 ns WRITE: Bank = 0 Row = 2, Col = 86, Data = 4bac2f97
|
# Status: Burst-No: 0 Write Address: 00002158 WriteData: 4bac2f97
|
# Status: Burst-No: 0 Write Address: 00002158 WriteData: 4bac2f97
|
# tb_core.u_sdram32 : at time 45987.0 ns WRITE: Bank = 0 Row = 2, Col = 87, Data = 835da206
|
# tb_core.u_sdram32 : at time 47187.0 ns WRITE: Bank = 0 Row = 2, Col = 87, Data = 835da206
|
# Status: Burst-No: 1 Write Address: 00002158 WriteData: 835da206
|
# Status: Burst-No: 1 Write Address: 00002158 WriteData: 835da206
|
# tb_core.u_sdram32 : at time 45997.0 ns WRITE: Bank = 0 Row = 2, Col = 88, Data = 94a12e29
|
# tb_core.u_sdram32 : at time 47197.0 ns WRITE: Bank = 0 Row = 2, Col = 88, Data = 94a12e29
|
# Status: Burst-No: 2 Write Address: 00002158 WriteData: 94a12e29
|
# Status: Burst-No: 2 Write Address: 00002158 WriteData: 94a12e29
|
# tb_core.u_sdram32 : at time 46007.0 ns WRITE: Bank = 0 Row = 2, Col = 89, Data = 624b63c4
|
# tb_core.u_sdram32 : at time 47207.0 ns WRITE: Bank = 0 Row = 2, Col = 89, Data = 624b63c4
|
# Status: Burst-No: 3 Write Address: 00002158 WriteData: 624b63c4
|
# Status: Burst-No: 3 Write Address: 00002158 WriteData: 624b63c4
|
# tb_core.u_sdram32 : at time 46017.0 ns WRITE: Bank = 0 Row = 2, Col = 90, Data = ebb0f6d7
|
# tb_core.u_sdram32 : at time 47217.0 ns WRITE: Bank = 0 Row = 2, Col = 90, Data = ebb0f6d7
|
# Status: Burst-No: 4 Write Address: 00002158 WriteData: ebb0f6d7
|
# Status: Burst-No: 4 Write Address: 00002158 WriteData: ebb0f6d7
|
# tb_core.u_sdram32 : at time 46027.0 ns WRITE: Bank = 0 Row = 2, Col = 91, Data = aea6d45d
|
# tb_core.u_sdram32 : at time 47227.0 ns WRITE: Bank = 0 Row = 2, Col = 91, Data = aea6d45d
|
# Status: Burst-No: 5 Write Address: 00002158 WriteData: aea6d45d
|
# Status: Burst-No: 5 Write Address: 00002158 WriteData: aea6d45d
|
# tb_core.u_sdram32 : at time 46037.0 ns WRITE: Bank = 0 Row = 2, Col = 92, Data = 26c7134d
|
# tb_core.u_sdram32 : at time 47237.0 ns WRITE: Bank = 0 Row = 2, Col = 92, Data = 26c7134d
|
# Status: Burst-No: 6 Write Address: 00002158 WriteData: 26c7134d
|
# Status: Burst-No: 6 Write Address: 00002158 WriteData: 26c7134d
|
# tb_core.u_sdram32 : at time 46047.0 ns WRITE: Bank = 0 Row = 2, Col = 93, Data = 39bfc773
|
# tb_core.u_sdram32 : at time 47247.0 ns WRITE: Bank = 0 Row = 2, Col = 93, Data = 39bfc773
|
# Status: Burst-No: 7 Write Address: 00002158 WriteData: 39bfc773
|
# Status: Burst-No: 7 Write Address: 00002158 WriteData: 39bfc773
|
# tb_core.u_sdram32 : at time 46057.0 ns WRITE: Bank = 0 Row = 2, Col = 94, Data = bfd62a7f
|
# tb_core.u_sdram32 : at time 47257.0 ns WRITE: Bank = 0 Row = 2, Col = 94, Data = bfd62a7f
|
# Status: Burst-No: 8 Write Address: 00002158 WriteData: bfd62a7f
|
# Status: Burst-No: 8 Write Address: 00002158 WriteData: bfd62a7f
|
# tb_core.u_sdram32 : at time 46067.0 ns WRITE: Bank = 0 Row = 2, Col = 95, Data = a703744e
|
# tb_core.u_sdram32 : at time 47267.0 ns WRITE: Bank = 0 Row = 2, Col = 95, Data = a703744e
|
# Status: Burst-No: 9 Write Address: 00002158 WriteData: a703744e
|
# Status: Burst-No: 9 Write Address: 00002158 WriteData: a703744e
|
# tb_core.u_sdram32 : at time 46077.0 ns WRITE: Bank = 0 Row = 2, Col = 96, Data = 5cdc65b9
|
# tb_core.u_sdram32 : at time 47277.0 ns WRITE: Bank = 0 Row = 2, Col = 96, Data = 5cdc65b9
|
# Status: Burst-No: 10 Write Address: 00002158 WriteData: 5cdc65b9
|
# Status: Burst-No: 10 Write Address: 00002158 WriteData: 5cdc65b9
|
# tb_core.u_sdram32 : at time 46087.0 ns WRITE: Bank = 0 Row = 2, Col = 97, Data = f05d64e0
|
# tb_core.u_sdram32 : at time 47287.0 ns WRITE: Bank = 0 Row = 2, Col = 97, Data = f05d64e0
|
# Status: Burst-No: 11 Write Address: 00002158 WriteData: f05d64e0
|
# Status: Burst-No: 11 Write Address: 00002158 WriteData: f05d64e0
|
# tb_core.u_sdram32 : at time 46097.0 ns WRITE: Bank = 0 Row = 2, Col = 98, Data = 9cd6c239
|
# tb_core.u_sdram32 : at time 47297.0 ns WRITE: Bank = 0 Row = 2, Col = 98, Data = 9cd6c239
|
# Status: Burst-No: 12 Write Address: 00002158 WriteData: 9cd6c239
|
# Status: Burst-No: 12 Write Address: 00002158 WriteData: 9cd6c239
|
# tb_core.u_sdram32 : at time 46107.0 ns WRITE: Bank = 0 Row = 2, Col = 99, Data = 40fb4f81
|
# tb_core.u_sdram32 : at time 47307.0 ns WRITE: Bank = 0 Row = 2, Col = 99, Data = 40fb4f81
|
# Status: Burst-No: 13 Write Address: 00002158 WriteData: 40fb4f81
|
# Status: Burst-No: 13 Write Address: 00002158 WriteData: 40fb4f81
|
# tb_core.u_sdram32 : at time 46117.0 ns WRITE: Bank = 0 Row = 2, Col = 100, Data = 18fb8331
|
# tb_core.u_sdram32 : at time 47317.0 ns WRITE: Bank = 0 Row = 2, Col = 100, Data = 18fb8331
|
# Status: Burst-No: 14 Write Address: 00002158 WriteData: 18fb8331
|
# Status: Burst-No: 14 Write Address: 00002158 WriteData: 18fb8331
|
# tb_core.u_sdram32 : at time 46127.0 ns WRITE: Bank = 0 Row = 2, Col = 101, Data = 47ebef8f
|
# tb_core.u_sdram32 : at time 47327.0 ns WRITE: Bank = 0 Row = 2, Col = 101, Data = 47ebef8f
|
# Status: Burst-No: 15 Write Address: 00002158 WriteData: 47ebef8f
|
# Status: Burst-No: 15 Write Address: 00002158 WriteData: 47ebef8f
|
# tb_core.u_sdram32 : at time 46137.0 ns WRITE: Bank = 0 Row = 2, Col = 102, Data = 7f537dfe
|
# tb_core.u_sdram32 : at time 47337.0 ns WRITE: Bank = 0 Row = 2, Col = 102, Data = 7f537dfe
|
# Status: Burst-No: 16 Write Address: 00002158 WriteData: 7f537dfe
|
# Status: Burst-No: 16 Write Address: 00002158 WriteData: 7f537dfe
|
# tb_core.u_sdram32 : at time 46147.0 ns WRITE: Bank = 0 Row = 2, Col = 103, Data = aed0f05d
|
# tb_core.u_sdram32 : at time 47347.0 ns WRITE: Bank = 0 Row = 2, Col = 103, Data = aed0f05d
|
# Status: Burst-No: 17 Write Address: 00002158 WriteData: aed0f05d
|
# Status: Burst-No: 17 Write Address: 00002158 WriteData: aed0f05d
|
# tb_core.u_sdram32 : at time 46157.0 ns WRITE: Bank = 0 Row = 2, Col = 104, Data = 878a880f
|
# tb_core.u_sdram32 : at time 47357.0 ns WRITE: Bank = 0 Row = 2, Col = 104, Data = 878a880f
|
# Status: Burst-No: 18 Write Address: 00002158 WriteData: 878a880f
|
# Status: Burst-No: 18 Write Address: 00002158 WriteData: 878a880f
|
# tb_core.u_sdram32 : at time 46167.0 ns WRITE: Bank = 0 Row = 2, Col = 105, Data = 199bcb33
|
# tb_core.u_sdram32 : at time 47367.0 ns WRITE: Bank = 0 Row = 2, Col = 105, Data = 199bcb33
|
# Status: Burst-No: 19 Write Address: 00002158 WriteData: 199bcb33
|
# Status: Burst-No: 19 Write Address: 00002158 WriteData: 199bcb33
|
# tb_core.u_sdram32 : at time 46177.0 ns WRITE: Bank = 0 Row = 2, Col = 106, Data = 348ed569
|
# tb_core.u_sdram32 : at time 47377.0 ns WRITE: Bank = 0 Row = 2, Col = 106, Data = 348ed569
|
# Status: Burst-No: 20 Write Address: 00002158 WriteData: 348ed569
|
# Status: Burst-No: 20 Write Address: 00002158 WriteData: 348ed569
|
# tb_core.u_sdram32 : at time 46187.0 ns WRITE: Bank = 0 Row = 2, Col = 107, Data = 2b0da556
|
# tb_core.u_sdram32 : at time 47387.0 ns WRITE: Bank = 0 Row = 2, Col = 107, Data = 2b0da556
|
# Status: Burst-No: 21 Write Address: 00002158 WriteData: 2b0da556
|
# Status: Burst-No: 21 Write Address: 00002158 WriteData: 2b0da556
|
# tb_core.u_sdram32 : at time 46197.0 ns WRITE: Bank = 0 Row = 2, Col = 108, Data = cd57529a
|
# tb_core.u_sdram32 : at time 47397.0 ns WRITE: Bank = 0 Row = 2, Col = 108, Data = cd57529a
|
# Status: Burst-No: 22 Write Address: 00002158 WriteData: cd57529a
|
# Status: Burst-No: 22 Write Address: 00002158 WriteData: cd57529a
|
# tb_core.u_sdram32 : at time 46207.0 ns WRITE: Bank = 0 Row = 2, Col = 109, Data = 2e72295c
|
# tb_core.u_sdram32 : at time 47407.0 ns WRITE: Bank = 0 Row = 2, Col = 109, Data = 2e72295c
|
# Status: Burst-No: 23 Write Address: 00002158 WriteData: 2e72295c
|
# Status: Burst-No: 23 Write Address: 00002158 WriteData: 2e72295c
|
# tb_core.u_sdram32 : at time 46217.0 ns WRITE: Bank = 0 Row = 2, Col = 110, Data = 24e90749
|
# tb_core.u_sdram32 : at time 47417.0 ns WRITE: Bank = 0 Row = 2, Col = 110, Data = 24e90749
|
# Status: Burst-No: 24 Write Address: 00002158 WriteData: 24e90749
|
# Status: Burst-No: 24 Write Address: 00002158 WriteData: 24e90749
|
# tb_core.u_sdram32 : at time 46227.0 ns WRITE: Bank = 0 Row = 2, Col = 111, Data = 69cd77d3
|
# tb_core.u_sdram32 : at time 47427.0 ns WRITE: Bank = 0 Row = 2, Col = 111, Data = 69cd77d3
|
# Status: Burst-No: 25 Write Address: 00002158 WriteData: 69cd77d3
|
# Status: Burst-No: 25 Write Address: 00002158 WriteData: 69cd77d3
|
# tb_core.u_sdram32 : at time 46237.0 ns WRITE: Bank = 0 Row = 2, Col = 112, Data = 9d737a3a
|
# tb_core.u_sdram32 : at time 47437.0 ns WRITE: Bank = 0 Row = 2, Col = 112, Data = 9d737a3a
|
# Status: Burst-No: 26 Write Address: 00002158 WriteData: 9d737a3a
|
# Status: Burst-No: 26 Write Address: 00002158 WriteData: 9d737a3a
|
# tb_core.u_sdram32 : at time 46247.0 ns WRITE: Bank = 0 Row = 2, Col = 113, Data = 6c74f5d8
|
# tb_core.u_sdram32 : at time 47447.0 ns WRITE: Bank = 0 Row = 2, Col = 113, Data = 6c74f5d8
|
# Status: Burst-No: 27 Write Address: 00002158 WriteData: 6c74f5d8
|
# Status: Burst-No: 27 Write Address: 00002158 WriteData: 6c74f5d8
|
# tb_core.u_sdram32 : at time 46257.0 ns WRITE: Bank = 0 Row = 2, Col = 114, Data = bc1c0e78
|
# tb_core.u_sdram32 : at time 47457.0 ns WRITE: Bank = 0 Row = 2, Col = 114, Data = bc1c0e78
|
# Status: Burst-No: 28 Write Address: 00002158 WriteData: bc1c0e78
|
# Status: Burst-No: 28 Write Address: 00002158 WriteData: bc1c0e78
|
# tb_core.u_sdram32 : at time 46267.0 ns WRITE: Bank = 0 Row = 2, Col = 115, Data = 1ccb3539
|
# tb_core.u_sdram32 : at time 47467.0 ns WRITE: Bank = 0 Row = 2, Col = 115, Data = 1ccb3539
|
# Status: Burst-No: 29 Write Address: 00002158 WriteData: 1ccb3539
|
# Status: Burst-No: 29 Write Address: 00002158 WriteData: 1ccb3539
|
# tb_core.u_sdram32 : at time 46277.0 ns WRITE: Bank = 0 Row = 2, Col = 116, Data = 92d06025
|
# tb_core.u_sdram32 : at time 47477.0 ns WRITE: Bank = 0 Row = 2, Col = 116, Data = 92d06025
|
# Status: Burst-No: 30 Write Address: 00002158 WriteData: 92d06025
|
# Status: Burst-No: 30 Write Address: 00002158 WriteData: 92d06025
|
# tb_core.u_sdram32 : at time 46287.0 ns WRITE: Bank = 0 Row = 2, Col = 117, Data = 8496d609
|
# tb_core.u_sdram32 : at time 47487.0 ns WRITE: Bank = 0 Row = 2, Col = 117, Data = 8496d609
|
# Status: Burst-No: 31 Write Address: 00002158 WriteData: 8496d609
|
# Status: Burst-No: 31 Write Address: 00002158 WriteData: 8496d609
|
# tb_core.u_sdram32 : at time 46297.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 47497.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 46437.0 ns ACT : Bank = 0 Row = 599
|
# tb_core.u_sdram32 : at time 47637.0 ns ACT : Bank = 0 Row = 599
|
# tb_core.u_sdram32 : at time 46493.0 ns READ : Bank = 0 Row = 599, Col = 75, Data = 33638966
|
# tb_core.u_sdram32 : at time 47693.0 ns READ : Bank = 0 Row = 599, Col = 75, Data = 33638966
|
# tb_core.u_sdram32 : at time 46503.0 ns READ : Bank = 0 Row = 599, Col = 76, Data = bb062876
|
# tb_core.u_sdram32 : at time 47703.0 ns READ : Bank = 0 Row = 599, Col = 76, Data = bb062876
|
# READ STATUS: Burst-No: 0 Addr: 0025712e Rxd: 33638966
|
# READ STATUS: Burst-No: 0 Addr: 0025712e Rxd: 33638966
|
# tb_core.u_sdram32 : at time 46513.0 ns READ : Bank = 0 Row = 599, Col = 77, Data = 3a982575
|
# tb_core.u_sdram32 : at time 47713.0 ns READ : Bank = 0 Row = 599, Col = 77, Data = 3a982575
|
# READ STATUS: Burst-No: 1 Addr: 00257130 Rxd: bb062876
|
# READ STATUS: Burst-No: 1 Addr: 00257130 Rxd: bb062876
|
# tb_core.u_sdram32 : at time 46523.0 ns READ : Bank = 0 Row = 599, Col = 78, Data = c7b43a8f
|
# tb_core.u_sdram32 : at time 47723.0 ns READ : Bank = 0 Row = 599, Col = 78, Data = c7b43a8f
|
# READ STATUS: Burst-No: 2 Addr: 00257132 Rxd: 3a982575
|
# READ STATUS: Burst-No: 2 Addr: 00257132 Rxd: 3a982575
|
# tb_core.u_sdram32 : at time 46533.0 ns READ : Bank = 0 Row = 599, Col = 79, Data = 4ad39595
|
# tb_core.u_sdram32 : at time 47733.0 ns READ : Bank = 0 Row = 599, Col = 79, Data = 4ad39595
|
# READ STATUS: Burst-No: 3 Addr: 00257134 Rxd: c7b43a8f
|
# READ STATUS: Burst-No: 3 Addr: 00257134 Rxd: c7b43a8f
|
# tb_core.u_sdram32 : at time 46543.0 ns READ : Bank = 0 Row = 599, Col = 80, Data = 3da8cd7b
|
# tb_core.u_sdram32 : at time 47743.0 ns READ : Bank = 0 Row = 599, Col = 80, Data = 3da8cd7b
|
# READ STATUS: Burst-No: 4 Addr: 00257136 Rxd: 4ad39595
|
# READ STATUS: Burst-No: 4 Addr: 00257136 Rxd: 4ad39595
|
# tb_core.u_sdram32 : at time 46553.0 ns READ : Bank = 0 Row = 599, Col = 81, Data = be43ea7c
|
# tb_core.u_sdram32 : at time 47753.0 ns READ : Bank = 0 Row = 599, Col = 81, Data = be43ea7c
|
# READ STATUS: Burst-No: 5 Addr: 00257138 Rxd: 3da8cd7b
|
# READ STATUS: Burst-No: 5 Addr: 00257138 Rxd: 3da8cd7b
|
# tb_core.u_sdram32 : at time 46563.0 ns READ : Bank = 0 Row = 599, Col = 82, Data = b7f4306f
|
# tb_core.u_sdram32 : at time 47763.0 ns READ : Bank = 0 Row = 599, Col = 82, Data = b7f4306f
|
# READ STATUS: Burst-No: 6 Addr: 0025713a Rxd: be43ea7c
|
# READ STATUS: Burst-No: 6 Addr: 0025713a Rxd: be43ea7c
|
# tb_core.u_sdram32 : at time 46573.0 ns READ : Bank = 0 Row = 599, Col = 83, Data = e4824cc9
|
# tb_core.u_sdram32 : at time 47773.0 ns READ : Bank = 0 Row = 599, Col = 83, Data = e4824cc9
|
# READ STATUS: Burst-No: 7 Addr: 0025713c Rxd: b7f4306f
|
# READ STATUS: Burst-No: 7 Addr: 0025713c Rxd: b7f4306f
|
# tb_core.u_sdram32 : at time 46583.0 ns READ : Bank = 0 Row = 599, Col = 84, Data = e4d820c9
|
# tb_core.u_sdram32 : at time 47783.0 ns READ : Bank = 0 Row = 599, Col = 84, Data = e4d820c9
|
# READ STATUS: Burst-No: 8 Addr: 0025713e Rxd: e4824cc9
|
# READ STATUS: Burst-No: 8 Addr: 0025713e Rxd: e4824cc9
|
# tb_core.u_sdram32 : at time 46593.0 ns READ : Bank = 0 Row = 599, Col = 85, Data = 5a3761b4
|
# tb_core.u_sdram32 : at time 47793.0 ns READ : Bank = 0 Row = 599, Col = 85, Data = 5a3761b4
|
# READ STATUS: Burst-No: 9 Addr: 00257140 Rxd: e4d820c9
|
# READ STATUS: Burst-No: 9 Addr: 00257140 Rxd: e4d820c9
|
# tb_core.u_sdram32 : at time 46603.0 ns READ : Bank = 0 Row = 599, Col = 86, Data = 6d48a5da
|
# tb_core.u_sdram32 : at time 47803.0 ns READ : Bank = 0 Row = 599, Col = 86, Data = 6d48a5da
|
# READ STATUS: Burst-No: 10 Addr: 00257142 Rxd: 5a3761b4
|
# READ STATUS: Burst-No: 10 Addr: 00257142 Rxd: 5a3761b4
|
# tb_core.u_sdram32 : at time 46613.0 ns READ : Bank = 0 Row = 599, Col = 87, Data = d6aea8ad
|
# tb_core.u_sdram32 : at time 47813.0 ns READ : Bank = 0 Row = 599, Col = 87, Data = d6aea8ad
|
# READ STATUS: Burst-No: 11 Addr: 00257144 Rxd: 6d48a5da
|
# READ STATUS: Burst-No: 11 Addr: 00257144 Rxd: 6d48a5da
|
# tb_core.u_sdram32 : at time 46623.0 ns READ : Bank = 0 Row = 599, Col = 88, Data = 6fcff1df
|
# tb_core.u_sdram32 : at time 47823.0 ns READ : Bank = 0 Row = 599, Col = 88, Data = 6fcff1df
|
# READ STATUS: Burst-No: 12 Addr: 00257146 Rxd: d6aea8ad
|
# READ STATUS: Burst-No: 12 Addr: 00257146 Rxd: d6aea8ad
|
# tb_core.u_sdram32 : at time 46633.0 ns READ : Bank = 0 Row = 599, Col = 89, Data = 06b0e30d
|
# tb_core.u_sdram32 : at time 47833.0 ns READ : Bank = 0 Row = 599, Col = 89, Data = 06b0e30d
|
# READ STATUS: Burst-No: 13 Addr: 00257148 Rxd: 6fcff1df
|
# READ STATUS: Burst-No: 13 Addr: 00257148 Rxd: 6fcff1df
|
# tb_core.u_sdram32 : at time 46643.0 ns READ : Bank = 0 Row = 599, Col = 90, Data = 384d4170
|
# tb_core.u_sdram32 : at time 47843.0 ns READ : Bank = 0 Row = 599, Col = 90, Data = 384d4170
|
# READ STATUS: Burst-No: 14 Addr: 0025714a Rxd: 06b0e30d
|
# READ STATUS: Burst-No: 14 Addr: 0025714a Rxd: 06b0e30d
|
# tb_core.u_sdram32 : at time 46653.0 ns READ : Bank = 0 Row = 599, Col = 91, Data = 41bd6783
|
# tb_core.u_sdram32 : at time 47853.0 ns READ : Bank = 0 Row = 599, Col = 91, Data = 41bd6783
|
# READ STATUS: Burst-No: 15 Addr: 0025714c Rxd: 384d4170
|
# READ STATUS: Burst-No: 15 Addr: 0025714c Rxd: 384d4170
|
# tb_core.u_sdram32 : at time 46663.0 ns READ : Bank = 0 Row = 599, Col = 92, Data = a8c6c451
|
# tb_core.u_sdram32 : at time 47863.0 ns READ : Bank = 0 Row = 599, Col = 92, Data = a8c6c451
|
# READ STATUS: Burst-No: 16 Addr: 0025714e Rxd: 41bd6783
|
# READ STATUS: Burst-No: 16 Addr: 0025714e Rxd: 41bd6783
|
# tb_core.u_sdram32 : at time 46673.0 ns READ : Bank = 0 Row = 599, Col = 93, Data = 027a8d04
|
# tb_core.u_sdram32 : at time 47873.0 ns READ : Bank = 0 Row = 599, Col = 93, Data = 027a8d04
|
# READ STATUS: Burst-No: 17 Addr: 00257150 Rxd: a8c6c451
|
# READ STATUS: Burst-No: 17 Addr: 00257150 Rxd: a8c6c451
|
# tb_core.u_sdram32 : at time 46683.0 ns READ : Bank = 0 Row = 599, Col = 94, Data = c0467280
|
# tb_core.u_sdram32 : at time 47883.0 ns READ : Bank = 0 Row = 599, Col = 94, Data = c0467280
|
# READ STATUS: Burst-No: 18 Addr: 00257152 Rxd: 027a8d04
|
# READ STATUS: Burst-No: 18 Addr: 00257152 Rxd: 027a8d04
|
# tb_core.u_sdram32 : at time 46693.0 ns READ : Bank = 0 Row = 599, Col = 95, Data = fcf504f9
|
# tb_core.u_sdram32 : at time 47893.0 ns READ : Bank = 0 Row = 599, Col = 95, Data = fcf504f9
|
# READ STATUS: Burst-No: 19 Addr: 00257154 Rxd: c0467280
|
# READ STATUS: Burst-No: 19 Addr: 00257154 Rxd: c0467280
|
# tb_core.u_sdram32 : at time 46703.0 ns READ : Bank = 0 Row = 599, Col = 96, Data = 0379ed06
|
# tb_core.u_sdram32 : at time 47903.0 ns READ : Bank = 0 Row = 599, Col = 96, Data = 0379ed06
|
# READ STATUS: Burst-No: 20 Addr: 00257156 Rxd: fcf504f9
|
# READ STATUS: Burst-No: 20 Addr: 00257156 Rxd: fcf504f9
|
# tb_core.u_sdram32 : at time 46713.0 ns READ : Bank = 0 Row = 599, Col = 97, Data = e5063aca
|
# tb_core.u_sdram32 : at time 47913.0 ns READ : Bank = 0 Row = 599, Col = 97, Data = e5063aca
|
# READ STATUS: Burst-No: 21 Addr: 00257158 Rxd: 0379ed06
|
# READ STATUS: Burst-No: 21 Addr: 00257158 Rxd: 0379ed06
|
# tb_core.u_sdram32 : at time 46723.0 ns READ : Bank = 0 Row = 599, Col = 98, Data = ef8d64df
|
# tb_core.u_sdram32 : at time 47923.0 ns READ : Bank = 0 Row = 599, Col = 98, Data = ef8d64df
|
# READ STATUS: Burst-No: 22 Addr: 0025715a Rxd: e5063aca
|
# READ STATUS: Burst-No: 22 Addr: 0025715a Rxd: e5063aca
|
# tb_core.u_sdram32 : at time 46733.0 ns READ : Bank = 0 Row = 599, Col = 99, Data = 64f9bbc9
|
# tb_core.u_sdram32 : at time 47933.0 ns READ : Bank = 0 Row = 599, Col = 99, Data = 64f9bbc9
|
# READ STATUS: Burst-No: 23 Addr: 0025715c Rxd: ef8d64df
|
# READ STATUS: Burst-No: 23 Addr: 0025715c Rxd: ef8d64df
|
# tb_core.u_sdram32 : at time 46743.0 ns READ : Bank = 0 Row = 599, Col = 100, Data = 42797584
|
# tb_core.u_sdram32 : at time 47943.0 ns READ : Bank = 0 Row = 599, Col = 100, Data = 42797584
|
# READ STATUS: Burst-No: 24 Addr: 0025715e Rxd: 64f9bbc9
|
# READ STATUS: Burst-No: 24 Addr: 0025715e Rxd: 64f9bbc9
|
# tb_core.u_sdram32 : at time 46753.0 ns READ : Bank = 0 Row = 599, Col = 101, Data = d84988b0
|
# tb_core.u_sdram32 : at time 47953.0 ns READ : Bank = 0 Row = 599, Col = 101, Data = d84988b0
|
# READ STATUS: Burst-No: 25 Addr: 00257160 Rxd: 42797584
|
# READ STATUS: Burst-No: 25 Addr: 00257160 Rxd: 42797584
|
# tb_core.u_sdram32 : at time 46763.0 ns READ : Bank = 0 Row = 599, Col = 102, Data = 74bc03e9
|
# tb_core.u_sdram32 : at time 47963.0 ns READ : Bank = 0 Row = 599, Col = 102, Data = 74bc03e9
|
# READ STATUS: Burst-No: 26 Addr: 00257162 Rxd: d84988b0
|
# READ STATUS: Burst-No: 26 Addr: 00257162 Rxd: d84988b0
|
# tb_core.u_sdram32 : at time 46773.0 ns READ : Bank = 0 Row = 599, Col = 103, Data = 08098510
|
# tb_core.u_sdram32 : at time 47973.0 ns READ : Bank = 0 Row = 599, Col = 103, Data = 08098510
|
# READ STATUS: Burst-No: 27 Addr: 00257164 Rxd: 74bc03e9
|
# READ STATUS: Burst-No: 27 Addr: 00257164 Rxd: 74bc03e9
|
# tb_core.u_sdram32 : at time 46783.0 ns READ : Bank = 0 Row = 599, Col = 104, Data = 6f3425de
|
# tb_core.u_sdram32 : at time 47983.0 ns READ : Bank = 0 Row = 599, Col = 104, Data = 6f3425de
|
# READ STATUS: Burst-No: 28 Addr: 00257166 Rxd: 08098510
|
# READ STATUS: Burst-No: 28 Addr: 00257166 Rxd: 08098510
|
# tb_core.u_sdram32 : at time 46793.0 ns READ : Bank = 0 Row = 599, Col = 105, Data = d659d0ac
|
# tb_core.u_sdram32 : at time 47993.0 ns READ : Bank = 0 Row = 599, Col = 105, Data = d659d0ac
|
# READ STATUS: Burst-No: 29 Addr: 00257168 Rxd: 6f3425de
|
# READ STATUS: Burst-No: 29 Addr: 00257168 Rxd: 6f3425de
|
# tb_core.u_sdram32 : at time 46803.0 ns READ : Bank = 0 Row = 599, Col = 106, Data = 0498fb09
|
# tb_core.u_sdram32 : at time 48003.0 ns READ : Bank = 0 Row = 599, Col = 106, Data = 0498fb09
|
# READ STATUS: Burst-No: 30 Addr: 0025716a Rxd: d659d0ac
|
# READ STATUS: Burst-No: 30 Addr: 0025716a Rxd: d659d0ac
|
# tb_core.u_sdram32 : at time 46813.0 ns READ : Bank = 0 Row = 599, Col = 107, Data = 6bf823d7
|
# tb_core.u_sdram32 : at time 48013.0 ns READ : Bank = 0 Row = 599, Col = 107, Data = 6bf823d7
|
# READ STATUS: Burst-No: 31 Addr: 0025716c Rxd: 0498fb09
|
# READ STATUS: Burst-No: 31 Addr: 0025716c Rxd: 0498fb09
|
# tb_core.u_sdram32 : at time 46823.0 ns READ : Bank = 0 Row = 599, Col = 108, Data = 30c38f61
|
# tb_core.u_sdram32 : at time 48023.0 ns READ : Bank = 0 Row = 599, Col = 108, Data = 30c38f61
|
# READ STATUS: Burst-No: 32 Addr: 0025716e Rxd: 6bf823d7
|
# READ STATUS: Burst-No: 32 Addr: 0025716e Rxd: 6bf823d7
|
# tb_core.u_sdram32 : at time 46833.0 ns READ : Bank = 0 Row = 599, Col = 109, Data = 86c8320d
|
# tb_core.u_sdram32 : at time 48033.0 ns READ : Bank = 0 Row = 599, Col = 109, Data = 86c8320d
|
# READ STATUS: Burst-No: 33 Addr: 00257170 Rxd: 30c38f61
|
# READ STATUS: Burst-No: 33 Addr: 00257170 Rxd: 30c38f61
|
# tb_core.u_sdram32 : at time 46843.0 ns READ : Bank = 0 Row = 599, Col = 110, Data = 48c3b791
|
# tb_core.u_sdram32 : at time 48043.0 ns READ : Bank = 0 Row = 599, Col = 110, Data = 48c3b791
|
# READ STATUS: Burst-No: 34 Addr: 00257172 Rxd: 86c8320d
|
# READ STATUS: Burst-No: 34 Addr: 00257172 Rxd: 86c8320d
|
# tb_core.u_sdram32 : at time 46853.0 ns READ : Bank = 0 Row = 599, Col = 111, Data = e9eb0ed3
|
# tb_core.u_sdram32 : at time 48053.0 ns READ : Bank = 0 Row = 599, Col = 111, Data = e9eb0ed3
|
# READ STATUS: Burst-No: 35 Addr: 00257174 Rxd: 48c3b791
|
# READ STATUS: Burst-No: 35 Addr: 00257174 Rxd: 48c3b791
|
# tb_core.u_sdram32 : at time 46863.0 ns READ : Bank = 0 Row = 599, Col = 112, Data = 4d77f99a
|
# tb_core.u_sdram32 : at time 48063.0 ns READ : Bank = 0 Row = 599, Col = 112, Data = 4d77f99a
|
# READ STATUS: Burst-No: 36 Addr: 00257176 Rxd: e9eb0ed3
|
# READ STATUS: Burst-No: 36 Addr: 00257176 Rxd: e9eb0ed3
|
# tb_core.u_sdram32 : at time 46873.0 ns READ : Bank = 0 Row = 599, Col = 113, Data = 17bd872f
|
# tb_core.u_sdram32 : at time 48073.0 ns READ : Bank = 0 Row = 599, Col = 113, Data = 17bd872f
|
# READ STATUS: Burst-No: 37 Addr: 00257178 Rxd: 4d77f99a
|
# READ STATUS: Burst-No: 37 Addr: 00257178 Rxd: 4d77f99a
|
# tb_core.u_sdram32 : at time 46883.0 ns READ : Bank = 0 Row = 599, Col = 114, Data = 2720634e
|
# tb_core.u_sdram32 : at time 48083.0 ns READ : Bank = 0 Row = 599, Col = 114, Data = 2720634e
|
# READ STATUS: Burst-No: 38 Addr: 0025717a Rxd: 17bd872f
|
# READ STATUS: Burst-No: 38 Addr: 0025717a Rxd: 17bd872f
|
# tb_core.u_sdram32 : at time 46893.0 ns READ : Bank = 0 Row = 599, Col = 115, Data = 5bd583b7
|
# tb_core.u_sdram32 : at time 48093.0 ns READ : Bank = 0 Row = 599, Col = 115, Data = 5bd583b7
|
# READ STATUS: Burst-No: 39 Addr: 0025717c Rxd: 2720634e
|
# READ STATUS: Burst-No: 39 Addr: 0025717c Rxd: 2720634e
|
# tb_core.u_sdram32 : at time 46903.0 ns READ : Bank = 0 Row = 599, Col = 116, Data = e32472c6
|
# tb_core.u_sdram32 : at time 48103.0 ns READ : Bank = 0 Row = 599, Col = 116, Data = e32472c6
|
# READ STATUS: Burst-No: 40 Addr: 0025717e Rxd: 5bd583b7
|
# READ STATUS: Burst-No: 40 Addr: 0025717e Rxd: 5bd583b7
|
# tb_core.u_sdram32 : at time 46913.0 ns READ : Bank = 0 Row = 599, Col = 117, Data = 2ed66b5d
|
# tb_core.u_sdram32 : at time 48113.0 ns READ : Bank = 0 Row = 599, Col = 117, Data = 2ed66b5d
|
# READ STATUS: Burst-No: 41 Addr: 00257180 Rxd: e32472c6
|
# READ STATUS: Burst-No: 41 Addr: 00257180 Rxd: e32472c6
|
# tb_core.u_sdram32 : at time 46923.0 ns READ : Bank = 0 Row = 599, Col = 118, Data = ce03ec9c
|
# tb_core.u_sdram32 : at time 48123.0 ns READ : Bank = 0 Row = 599, Col = 118, Data = ce03ec9c
|
# READ STATUS: Burst-No: 42 Addr: 00257182 Rxd: 2ed66b5d
|
# READ STATUS: Burst-No: 42 Addr: 00257182 Rxd: 2ed66b5d
|
# tb_core.u_sdram32 : at time 46933.0 ns READ : Bank = 0 Row = 599, Col = 119, Data = 17b47f2f
|
# tb_core.u_sdram32 : at time 48133.0 ns READ : Bank = 0 Row = 599, Col = 119, Data = 17b47f2f
|
# READ STATUS: Burst-No: 43 Addr: 00257184 Rxd: ce03ec9c
|
# READ STATUS: Burst-No: 43 Addr: 00257184 Rxd: ce03ec9c
|
# tb_core.u_sdram32 : at time 46943.0 ns READ : Bank = 0 Row = 599, Col = 120, Data = a22ac644
|
# tb_core.u_sdram32 : at time 48143.0 ns READ : Bank = 0 Row = 599, Col = 120, Data = a22ac644
|
# READ STATUS: Burst-No: 44 Addr: 00257186 Rxd: 17b47f2f
|
# READ STATUS: Burst-No: 44 Addr: 00257186 Rxd: 17b47f2f
|
# tb_core.u_sdram32 : at time 46953.0 ns READ : Bank = 0 Row = 599, Col = 121, Data = cdbf3a9b
|
# tb_core.u_sdram32 : at time 48153.0 ns READ : Bank = 0 Row = 599, Col = 121, Data = cdbf3a9b
|
# READ STATUS: Burst-No: 45 Addr: 00257188 Rxd: a22ac644
|
# READ STATUS: Burst-No: 45 Addr: 00257188 Rxd: a22ac644
|
# tb_core.u_sdram32 : at time 46963.0 ns READ : Bank = 0 Row = 599, Col = 122, Data = b1200062
|
# tb_core.u_sdram32 : at time 48163.0 ns READ : Bank = 0 Row = 599, Col = 122, Data = b1200062
|
# READ STATUS: Burst-No: 46 Addr: 0025718a Rxd: cdbf3a9b
|
# READ STATUS: Burst-No: 46 Addr: 0025718a Rxd: cdbf3a9b
|
# tb_core.u_sdram32 : at time 46973.0 ns READ : Bank = 0 Row = 599, Col = 123, Data = 748abbe9
|
# tb_core.u_sdram32 : at time 48173.0 ns READ : Bank = 0 Row = 599, Col = 123, Data = 748abbe9
|
# READ STATUS: Burst-No: 47 Addr: 0025718c Rxd: b1200062
|
# READ STATUS: Burst-No: 47 Addr: 0025718c Rxd: b1200062
|
# tb_core.u_sdram32 : at time 46983.0 ns READ : Bank = 0 Row = 599, Col = 124, Data = 1747832e
|
# tb_core.u_sdram32 : at time 48183.0 ns READ : Bank = 0 Row = 599, Col = 124, Data = 1747832e
|
# READ STATUS: Burst-No: 48 Addr: 0025718e Rxd: 748abbe9
|
# READ STATUS: Burst-No: 48 Addr: 0025718e Rxd: 748abbe9
|
# tb_core.u_sdram32 : at time 46993.0 ns READ : Bank = 0 Row = 599, Col = 125, Data = c690128d
|
# tb_core.u_sdram32 : at time 48193.0 ns READ : Bank = 0 Row = 599, Col = 125, Data = c690128d
|
# READ STATUS: Burst-No: 49 Addr: 00257190 Rxd: 1747832e
|
# READ STATUS: Burst-No: 49 Addr: 00257190 Rxd: 1747832e
|
# tb_core.u_sdram32 : at time 47003.0 ns READ : Bank = 0 Row = 599, Col = 126, Data = 632f07c6
|
# tb_core.u_sdram32 : at time 48203.0 ns READ : Bank = 0 Row = 599, Col = 126, Data = 632f07c6
|
# READ STATUS: Burst-No: 50 Addr: 00257192 Rxd: c690128d
|
# READ STATUS: Burst-No: 50 Addr: 00257192 Rxd: c690128d
|
# tb_core.u_sdram32 : at time 47013.0 ns READ : Bank = 0 Row = 599, Col = 127, Data = d51cb4aa
|
# tb_core.u_sdram32 : at time 48213.0 ns READ : Bank = 0 Row = 599, Col = 127, Data = d51cb4aa
|
# READ STATUS: Burst-No: 51 Addr: 00257194 Rxd: 632f07c6
|
# READ STATUS: Burst-No: 51 Addr: 00257194 Rxd: 632f07c6
|
# tb_core.u_sdram32 : at time 47023.0 ns READ : Bank = 0 Row = 599, Col = 128, Data = d01df0a0
|
# tb_core.u_sdram32 : at time 48223.0 ns READ : Bank = 0 Row = 599, Col = 128, Data = d01df0a0
|
# READ STATUS: Burst-No: 52 Addr: 00257196 Rxd: d51cb4aa
|
# READ STATUS: Burst-No: 52 Addr: 00257196 Rxd: d51cb4aa
|
# tb_core.u_sdram32 : at time 47033.0 ns READ : Bank = 0 Row = 599, Col = 129, Data = 1be8cf37
|
# tb_core.u_sdram32 : at time 48233.0 ns READ : Bank = 0 Row = 599, Col = 129, Data = 1be8cf37
|
# READ STATUS: Burst-No: 53 Addr: 00257198 Rxd: d01df0a0
|
# READ STATUS: Burst-No: 53 Addr: 00257198 Rxd: d01df0a0
|
# tb_core.u_sdram32 : at time 47043.0 ns READ : Bank = 0 Row = 599, Col = 130, Data = f8602ef0
|
# tb_core.u_sdram32 : at time 48243.0 ns READ : Bank = 0 Row = 599, Col = 130, Data = f8602ef0
|
# READ STATUS: Burst-No: 54 Addr: 0025719a Rxd: 1be8cf37
|
# READ STATUS: Burst-No: 54 Addr: 0025719a Rxd: 1be8cf37
|
# tb_core.u_sdram32 : at time 47053.0 ns READ : Bank = 0 Row = 599, Col = 131, Data = f46ca8e8
|
# tb_core.u_sdram32 : at time 48253.0 ns READ : Bank = 0 Row = 599, Col = 131, Data = f46ca8e8
|
# READ STATUS: Burst-No: 55 Addr: 0025719c Rxd: f8602ef0
|
# READ STATUS: Burst-No: 55 Addr: 0025719c Rxd: f8602ef0
|
# tb_core.u_sdram32 : at time 47063.0 ns READ : Bank = 0 Row = 599, Col = 132, Data = e6841ccd
|
# tb_core.u_sdram32 : at time 48263.0 ns READ : Bank = 0 Row = 599, Col = 132, Data = e6841ccd
|
# READ STATUS: Burst-No: 56 Addr: 0025719e Rxd: f46ca8e8
|
# READ STATUS: Burst-No: 56 Addr: 0025719e Rxd: f46ca8e8
|
# tb_core.u_sdram32 : at time 47073.0 ns READ : Bank = 0 Row = 599, Col = 133, Data = 68cd09d1
|
# tb_core.u_sdram32 : at time 48273.0 ns READ : Bank = 0 Row = 599, Col = 133, Data = 68cd09d1
|
# READ STATUS: Burst-No: 57 Addr: 002571a0 Rxd: e6841ccd
|
# READ STATUS: Burst-No: 57 Addr: 002571a0 Rxd: e6841ccd
|
# tb_core.u_sdram32 : at time 47083.0 ns READ : Bank = 0 Row = 599, Col = 134, Data = 5d8363bb
|
# tb_core.u_sdram32 : at time 48283.0 ns READ : Bank = 0 Row = 599, Col = 134, Data = 5d8363bb
|
# tb_core.u_sdram32 : at time 47087.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 48287.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 58 Addr: 002571a2 Rxd: 68cd09d1
|
# READ STATUS: Burst-No: 58 Addr: 002571a2 Rxd: 68cd09d1
|
# tb_core.u_sdram32 : at time 47093.0 ns READ : Bank = 0 Row = 599, Col = 135, Data = eff692df
|
# tb_core.u_sdram32 : at time 48293.0 ns READ : Bank = 0 Row = 599, Col = 135, Data = eff692df
|
# READ STATUS: Burst-No: 59 Addr: 002571a4 Rxd: 5d8363bb
|
# READ STATUS: Burst-No: 59 Addr: 002571a4 Rxd: 5d8363bb
|
# tb_core.u_sdram32 : at time 47103.0 ns READ : Bank = 0 Row = 599, Col = 136, Data = 3e8ed57d
|
# tb_core.u_sdram32 : at time 48303.0 ns READ : Bank = 0 Row = 599, Col = 136, Data = 3e8ed57d
|
# READ STATUS: Burst-No: 60 Addr: 002571a6 Rxd: eff692df
|
# READ STATUS: Burst-No: 60 Addr: 002571a6 Rxd: eff692df
|
# READ STATUS: Burst-No: 61 Addr: 002571a8 Rxd: 3e8ed57d
|
# READ STATUS: Burst-No: 61 Addr: 002571a8 Rxd: 3e8ed57d
|
# tb_core.u_sdram32 : at time 47277.0 ns ACT : Bank = 0 Row = 2
|
# tb_core.u_sdram32 : at time 48477.0 ns ACT : Bank = 0 Row = 2
|
# tb_core.u_sdram32 : at time 47333.0 ns READ : Bank = 0 Row = 2, Col = 86, Data = 4bac2f97
|
# tb_core.u_sdram32 : at time 48533.0 ns READ : Bank = 0 Row = 2, Col = 86, Data = 4bac2f97
|
# tb_core.u_sdram32 : at time 47343.0 ns READ : Bank = 0 Row = 2, Col = 87, Data = 835da206
|
# tb_core.u_sdram32 : at time 48543.0 ns READ : Bank = 0 Row = 2, Col = 87, Data = 835da206
|
# READ STATUS: Burst-No: 0 Addr: 00002158 Rxd: 4bac2f97
|
# READ STATUS: Burst-No: 0 Addr: 00002158 Rxd: 4bac2f97
|
# tb_core.u_sdram32 : at time 47353.0 ns READ : Bank = 0 Row = 2, Col = 88, Data = 94a12e29
|
# tb_core.u_sdram32 : at time 48553.0 ns READ : Bank = 0 Row = 2, Col = 88, Data = 94a12e29
|
# READ STATUS: Burst-No: 1 Addr: 0000215a Rxd: 835da206
|
# READ STATUS: Burst-No: 1 Addr: 0000215a Rxd: 835da206
|
# tb_core.u_sdram32 : at time 47363.0 ns READ : Bank = 0 Row = 2, Col = 89, Data = 624b63c4
|
# tb_core.u_sdram32 : at time 48563.0 ns READ : Bank = 0 Row = 2, Col = 89, Data = 624b63c4
|
# READ STATUS: Burst-No: 2 Addr: 0000215c Rxd: 94a12e29
|
# READ STATUS: Burst-No: 2 Addr: 0000215c Rxd: 94a12e29
|
# tb_core.u_sdram32 : at time 47373.0 ns READ : Bank = 0 Row = 2, Col = 90, Data = ebb0f6d7
|
# tb_core.u_sdram32 : at time 48573.0 ns READ : Bank = 0 Row = 2, Col = 90, Data = ebb0f6d7
|
# READ STATUS: Burst-No: 3 Addr: 0000215e Rxd: 624b63c4
|
# READ STATUS: Burst-No: 3 Addr: 0000215e Rxd: 624b63c4
|
# tb_core.u_sdram32 : at time 47383.0 ns READ : Bank = 0 Row = 2, Col = 91, Data = aea6d45d
|
# tb_core.u_sdram32 : at time 48583.0 ns READ : Bank = 0 Row = 2, Col = 91, Data = aea6d45d
|
# READ STATUS: Burst-No: 4 Addr: 00002160 Rxd: ebb0f6d7
|
# READ STATUS: Burst-No: 4 Addr: 00002160 Rxd: ebb0f6d7
|
# tb_core.u_sdram32 : at time 47393.0 ns READ : Bank = 0 Row = 2, Col = 92, Data = 26c7134d
|
# tb_core.u_sdram32 : at time 48593.0 ns READ : Bank = 0 Row = 2, Col = 92, Data = 26c7134d
|
# READ STATUS: Burst-No: 5 Addr: 00002162 Rxd: aea6d45d
|
# READ STATUS: Burst-No: 5 Addr: 00002162 Rxd: aea6d45d
|
# tb_core.u_sdram32 : at time 47403.0 ns READ : Bank = 0 Row = 2, Col = 93, Data = 39bfc773
|
# tb_core.u_sdram32 : at time 48603.0 ns READ : Bank = 0 Row = 2, Col = 93, Data = 39bfc773
|
# READ STATUS: Burst-No: 6 Addr: 00002164 Rxd: 26c7134d
|
# READ STATUS: Burst-No: 6 Addr: 00002164 Rxd: 26c7134d
|
# tb_core.u_sdram32 : at time 47413.0 ns READ : Bank = 0 Row = 2, Col = 94, Data = bfd62a7f
|
# tb_core.u_sdram32 : at time 48613.0 ns READ : Bank = 0 Row = 2, Col = 94, Data = bfd62a7f
|
# READ STATUS: Burst-No: 7 Addr: 00002166 Rxd: 39bfc773
|
# READ STATUS: Burst-No: 7 Addr: 00002166 Rxd: 39bfc773
|
# tb_core.u_sdram32 : at time 47423.0 ns READ : Bank = 0 Row = 2, Col = 95, Data = a703744e
|
# tb_core.u_sdram32 : at time 48623.0 ns READ : Bank = 0 Row = 2, Col = 95, Data = a703744e
|
# READ STATUS: Burst-No: 8 Addr: 00002168 Rxd: bfd62a7f
|
# READ STATUS: Burst-No: 8 Addr: 00002168 Rxd: bfd62a7f
|
# tb_core.u_sdram32 : at time 47433.0 ns READ : Bank = 0 Row = 2, Col = 96, Data = 5cdc65b9
|
# tb_core.u_sdram32 : at time 48633.0 ns READ : Bank = 0 Row = 2, Col = 96, Data = 5cdc65b9
|
# READ STATUS: Burst-No: 9 Addr: 0000216a Rxd: a703744e
|
# READ STATUS: Burst-No: 9 Addr: 0000216a Rxd: a703744e
|
# tb_core.u_sdram32 : at time 47443.0 ns READ : Bank = 0 Row = 2, Col = 97, Data = f05d64e0
|
# tb_core.u_sdram32 : at time 48643.0 ns READ : Bank = 0 Row = 2, Col = 97, Data = f05d64e0
|
# READ STATUS: Burst-No: 10 Addr: 0000216c Rxd: 5cdc65b9
|
# READ STATUS: Burst-No: 10 Addr: 0000216c Rxd: 5cdc65b9
|
# tb_core.u_sdram32 : at time 47453.0 ns READ : Bank = 0 Row = 2, Col = 98, Data = 9cd6c239
|
# tb_core.u_sdram32 : at time 48653.0 ns READ : Bank = 0 Row = 2, Col = 98, Data = 9cd6c239
|
# READ STATUS: Burst-No: 11 Addr: 0000216e Rxd: f05d64e0
|
# READ STATUS: Burst-No: 11 Addr: 0000216e Rxd: f05d64e0
|
# tb_core.u_sdram32 : at time 47463.0 ns READ : Bank = 0 Row = 2, Col = 99, Data = 40fb4f81
|
# tb_core.u_sdram32 : at time 48663.0 ns READ : Bank = 0 Row = 2, Col = 99, Data = 40fb4f81
|
# READ STATUS: Burst-No: 12 Addr: 00002170 Rxd: 9cd6c239
|
# READ STATUS: Burst-No: 12 Addr: 00002170 Rxd: 9cd6c239
|
# tb_core.u_sdram32 : at time 47473.0 ns READ : Bank = 0 Row = 2, Col = 100, Data = 18fb8331
|
# tb_core.u_sdram32 : at time 48673.0 ns READ : Bank = 0 Row = 2, Col = 100, Data = 18fb8331
|
# READ STATUS: Burst-No: 13 Addr: 00002172 Rxd: 40fb4f81
|
# READ STATUS: Burst-No: 13 Addr: 00002172 Rxd: 40fb4f81
|
# tb_core.u_sdram32 : at time 47483.0 ns READ : Bank = 0 Row = 2, Col = 101, Data = 47ebef8f
|
# tb_core.u_sdram32 : at time 48683.0 ns READ : Bank = 0 Row = 2, Col = 101, Data = 47ebef8f
|
# READ STATUS: Burst-No: 14 Addr: 00002174 Rxd: 18fb8331
|
# READ STATUS: Burst-No: 14 Addr: 00002174 Rxd: 18fb8331
|
# tb_core.u_sdram32 : at time 47493.0 ns READ : Bank = 0 Row = 2, Col = 102, Data = 7f537dfe
|
# tb_core.u_sdram32 : at time 48693.0 ns READ : Bank = 0 Row = 2, Col = 102, Data = 7f537dfe
|
# READ STATUS: Burst-No: 15 Addr: 00002176 Rxd: 47ebef8f
|
# READ STATUS: Burst-No: 15 Addr: 00002176 Rxd: 47ebef8f
|
# tb_core.u_sdram32 : at time 47503.0 ns READ : Bank = 0 Row = 2, Col = 103, Data = aed0f05d
|
# tb_core.u_sdram32 : at time 48703.0 ns READ : Bank = 0 Row = 2, Col = 103, Data = aed0f05d
|
# READ STATUS: Burst-No: 16 Addr: 00002178 Rxd: 7f537dfe
|
# READ STATUS: Burst-No: 16 Addr: 00002178 Rxd: 7f537dfe
|
# tb_core.u_sdram32 : at time 47513.0 ns READ : Bank = 0 Row = 2, Col = 104, Data = 878a880f
|
# tb_core.u_sdram32 : at time 48713.0 ns READ : Bank = 0 Row = 2, Col = 104, Data = 878a880f
|
# READ STATUS: Burst-No: 17 Addr: 0000217a Rxd: aed0f05d
|
# READ STATUS: Burst-No: 17 Addr: 0000217a Rxd: aed0f05d
|
# tb_core.u_sdram32 : at time 47523.0 ns READ : Bank = 0 Row = 2, Col = 105, Data = 199bcb33
|
# tb_core.u_sdram32 : at time 48723.0 ns READ : Bank = 0 Row = 2, Col = 105, Data = 199bcb33
|
# READ STATUS: Burst-No: 18 Addr: 0000217c Rxd: 878a880f
|
# READ STATUS: Burst-No: 18 Addr: 0000217c Rxd: 878a880f
|
# tb_core.u_sdram32 : at time 47533.0 ns READ : Bank = 0 Row = 2, Col = 106, Data = 348ed569
|
# tb_core.u_sdram32 : at time 48733.0 ns READ : Bank = 0 Row = 2, Col = 106, Data = 348ed569
|
# READ STATUS: Burst-No: 19 Addr: 0000217e Rxd: 199bcb33
|
# READ STATUS: Burst-No: 19 Addr: 0000217e Rxd: 199bcb33
|
# tb_core.u_sdram32 : at time 47543.0 ns READ : Bank = 0 Row = 2, Col = 107, Data = 2b0da556
|
# tb_core.u_sdram32 : at time 48743.0 ns READ : Bank = 0 Row = 2, Col = 107, Data = 2b0da556
|
# READ STATUS: Burst-No: 20 Addr: 00002180 Rxd: 348ed569
|
# READ STATUS: Burst-No: 20 Addr: 00002180 Rxd: 348ed569
|
# tb_core.u_sdram32 : at time 47553.0 ns READ : Bank = 0 Row = 2, Col = 108, Data = cd57529a
|
# tb_core.u_sdram32 : at time 48753.0 ns READ : Bank = 0 Row = 2, Col = 108, Data = cd57529a
|
# READ STATUS: Burst-No: 21 Addr: 00002182 Rxd: 2b0da556
|
# READ STATUS: Burst-No: 21 Addr: 00002182 Rxd: 2b0da556
|
# tb_core.u_sdram32 : at time 47563.0 ns READ : Bank = 0 Row = 2, Col = 109, Data = 2e72295c
|
# tb_core.u_sdram32 : at time 48763.0 ns READ : Bank = 0 Row = 2, Col = 109, Data = 2e72295c
|
# READ STATUS: Burst-No: 22 Addr: 00002184 Rxd: cd57529a
|
# READ STATUS: Burst-No: 22 Addr: 00002184 Rxd: cd57529a
|
# tb_core.u_sdram32 : at time 47573.0 ns READ : Bank = 0 Row = 2, Col = 110, Data = 24e90749
|
# tb_core.u_sdram32 : at time 48773.0 ns READ : Bank = 0 Row = 2, Col = 110, Data = 24e90749
|
# READ STATUS: Burst-No: 23 Addr: 00002186 Rxd: 2e72295c
|
# READ STATUS: Burst-No: 23 Addr: 00002186 Rxd: 2e72295c
|
# tb_core.u_sdram32 : at time 47583.0 ns READ : Bank = 0 Row = 2, Col = 111, Data = 69cd77d3
|
# tb_core.u_sdram32 : at time 48783.0 ns READ : Bank = 0 Row = 2, Col = 111, Data = 69cd77d3
|
# READ STATUS: Burst-No: 24 Addr: 00002188 Rxd: 24e90749
|
# READ STATUS: Burst-No: 24 Addr: 00002188 Rxd: 24e90749
|
# tb_core.u_sdram32 : at time 47593.0 ns READ : Bank = 0 Row = 2, Col = 112, Data = 9d737a3a
|
# tb_core.u_sdram32 : at time 48793.0 ns READ : Bank = 0 Row = 2, Col = 112, Data = 9d737a3a
|
# READ STATUS: Burst-No: 25 Addr: 0000218a Rxd: 69cd77d3
|
# READ STATUS: Burst-No: 25 Addr: 0000218a Rxd: 69cd77d3
|
# tb_core.u_sdram32 : at time 47603.0 ns READ : Bank = 0 Row = 2, Col = 113, Data = 6c74f5d8
|
# tb_core.u_sdram32 : at time 48803.0 ns READ : Bank = 0 Row = 2, Col = 113, Data = 6c74f5d8
|
# READ STATUS: Burst-No: 26 Addr: 0000218c Rxd: 9d737a3a
|
# READ STATUS: Burst-No: 26 Addr: 0000218c Rxd: 9d737a3a
|
# tb_core.u_sdram32 : at time 47613.0 ns READ : Bank = 0 Row = 2, Col = 114, Data = bc1c0e78
|
# tb_core.u_sdram32 : at time 48813.0 ns READ : Bank = 0 Row = 2, Col = 114, Data = bc1c0e78
|
# READ STATUS: Burst-No: 27 Addr: 0000218e Rxd: 6c74f5d8
|
# READ STATUS: Burst-No: 27 Addr: 0000218e Rxd: 6c74f5d8
|
# tb_core.u_sdram32 : at time 47623.0 ns READ : Bank = 0 Row = 2, Col = 115, Data = 1ccb3539
|
# tb_core.u_sdram32 : at time 48823.0 ns READ : Bank = 0 Row = 2, Col = 115, Data = 1ccb3539
|
# tb_core.u_sdram32 : at time 47627.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 48827.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 28 Addr: 00002190 Rxd: bc1c0e78
|
# READ STATUS: Burst-No: 28 Addr: 00002190 Rxd: bc1c0e78
|
# tb_core.u_sdram32 : at time 47633.0 ns READ : Bank = 0 Row = 2, Col = 116, Data = 92d06025
|
# tb_core.u_sdram32 : at time 48833.0 ns READ : Bank = 0 Row = 2, Col = 116, Data = 92d06025
|
# READ STATUS: Burst-No: 29 Addr: 00002192 Rxd: 1ccb3539
|
# READ STATUS: Burst-No: 29 Addr: 00002192 Rxd: 1ccb3539
|
# tb_core.u_sdram32 : at time 47643.0 ns READ : Bank = 0 Row = 2, Col = 117, Data = 8496d609
|
# tb_core.u_sdram32 : at time 48843.0 ns READ : Bank = 0 Row = 2, Col = 117, Data = 8496d609
|
# READ STATUS: Burst-No: 30 Addr: 00002194 Rxd: 92d06025
|
# READ STATUS: Burst-No: 30 Addr: 00002194 Rxd: 92d06025
|
# READ STATUS: Burst-No: 31 Addr: 00002196 Rxd: 8496d609
|
# READ STATUS: Burst-No: 31 Addr: 00002196 Rxd: 8496d609
|
# Write Address: 0037a856, Burst Size: 45
|
# Write Address: 0037a856, Burst Size: 45
|
# tb_core.u_sdram32 : at time 47817.0 ns ACT : Bank = 2 Row = 890
|
# tb_core.u_sdram32 : at time 49017.0 ns ACT : Bank = 2 Row = 890
|
# tb_core.u_sdram32 : at time 47847.0 ns WRITE: Bank = 2 Row = 890, Col = 21, Data = e99b1cd3
|
# tb_core.u_sdram32 : at time 49047.0 ns WRITE: Bank = 2 Row = 890, Col = 21, Data = e99b1cd3
|
# Status: Burst-No: 0 Write Address: 0037a856 WriteData: e99b1cd3
|
# Status: Burst-No: 0 Write Address: 0037a856 WriteData: e99b1cd3
|
# tb_core.u_sdram32 : at time 47857.0 ns WRITE: Bank = 2 Row = 890, Col = 22, Data = 0d633f1a
|
# tb_core.u_sdram32 : at time 49057.0 ns WRITE: Bank = 2 Row = 890, Col = 22, Data = 0d633f1a
|
# Status: Burst-No: 1 Write Address: 0037a856 WriteData: 0d633f1a
|
# Status: Burst-No: 1 Write Address: 0037a856 WriteData: 0d633f1a
|
# tb_core.u_sdram32 : at time 47867.0 ns WRITE: Bank = 2 Row = 890, Col = 23, Data = 005d5100
|
# tb_core.u_sdram32 : at time 49067.0 ns WRITE: Bank = 2 Row = 890, Col = 23, Data = 005d5100
|
# Status: Burst-No: 2 Write Address: 0037a856 WriteData: 005d5100
|
# Status: Burst-No: 2 Write Address: 0037a856 WriteData: 005d5100
|
# tb_core.u_sdram32 : at time 47877.0 ns WRITE: Bank = 2 Row = 890, Col = 24, Data = 560d5fac
|
# tb_core.u_sdram32 : at time 49077.0 ns WRITE: Bank = 2 Row = 890, Col = 24, Data = 560d5fac
|
# Status: Burst-No: 3 Write Address: 0037a856 WriteData: 560d5fac
|
# Status: Burst-No: 3 Write Address: 0037a856 WriteData: 560d5fac
|
# tb_core.u_sdram32 : at time 47887.0 ns WRITE: Bank = 2 Row = 890, Col = 25, Data = f4588ee8
|
# tb_core.u_sdram32 : at time 49087.0 ns WRITE: Bank = 2 Row = 890, Col = 25, Data = f4588ee8
|
# Status: Burst-No: 4 Write Address: 0037a856 WriteData: f4588ee8
|
# Status: Burst-No: 4 Write Address: 0037a856 WriteData: f4588ee8
|
# tb_core.u_sdram32 : at time 47897.0 ns WRITE: Bank = 2 Row = 890, Col = 26, Data = b66a586c
|
# tb_core.u_sdram32 : at time 49097.0 ns WRITE: Bank = 2 Row = 890, Col = 26, Data = b66a586c
|
# Status: Burst-No: 5 Write Address: 0037a856 WriteData: b66a586c
|
# Status: Burst-No: 5 Write Address: 0037a856 WriteData: b66a586c
|
# tb_core.u_sdram32 : at time 47907.0 ns WRITE: Bank = 2 Row = 890, Col = 27, Data = d03c40a0
|
# tb_core.u_sdram32 : at time 49107.0 ns WRITE: Bank = 2 Row = 890, Col = 27, Data = d03c40a0
|
# Status: Burst-No: 6 Write Address: 0037a856 WriteData: d03c40a0
|
# Status: Burst-No: 6 Write Address: 0037a856 WriteData: d03c40a0
|
# tb_core.u_sdram32 : at time 47917.0 ns WRITE: Bank = 2 Row = 890, Col = 28, Data = 0ecd251d
|
# tb_core.u_sdram32 : at time 49117.0 ns WRITE: Bank = 2 Row = 890, Col = 28, Data = 0ecd251d
|
# Status: Burst-No: 7 Write Address: 0037a856 WriteData: 0ecd251d
|
# Status: Burst-No: 7 Write Address: 0037a856 WriteData: 0ecd251d
|
# tb_core.u_sdram32 : at time 47927.0 ns WRITE: Bank = 2 Row = 890, Col = 29, Data = 68c14fd1
|
# tb_core.u_sdram32 : at time 49127.0 ns WRITE: Bank = 2 Row = 890, Col = 29, Data = 68c14fd1
|
# Status: Burst-No: 8 Write Address: 0037a856 WriteData: 68c14fd1
|
# Status: Burst-No: 8 Write Address: 0037a856 WriteData: 68c14fd1
|
# tb_core.u_sdram32 : at time 47937.0 ns WRITE: Bank = 2 Row = 890, Col = 30, Data = 006d0f00
|
# tb_core.u_sdram32 : at time 49137.0 ns WRITE: Bank = 2 Row = 890, Col = 30, Data = 006d0f00
|
# Status: Burst-No: 9 Write Address: 0037a856 WriteData: 006d0f00
|
# Status: Burst-No: 9 Write Address: 0037a856 WriteData: 006d0f00
|
# tb_core.u_sdram32 : at time 47947.0 ns WRITE: Bank = 2 Row = 890, Col = 31, Data = ed4d78da
|
# tb_core.u_sdram32 : at time 49147.0 ns WRITE: Bank = 2 Row = 890, Col = 31, Data = ed4d78da
|
# Status: Burst-No: 10 Write Address: 0037a856 WriteData: ed4d78da
|
# Status: Burst-No: 10 Write Address: 0037a856 WriteData: ed4d78da
|
# tb_core.u_sdram32 : at time 47957.0 ns WRITE: Bank = 2 Row = 890, Col = 32, Data = 6c1987d8
|
# tb_core.u_sdram32 : at time 49157.0 ns WRITE: Bank = 2 Row = 890, Col = 32, Data = 6c1987d8
|
# Status: Burst-No: 11 Write Address: 0037a856 WriteData: 6c1987d8
|
# Status: Burst-No: 11 Write Address: 0037a856 WriteData: 6c1987d8
|
# tb_core.u_sdram32 : at time 47967.0 ns WRITE: Bank = 2 Row = 890, Col = 33, Data = 605dbbc0
|
# tb_core.u_sdram32 : at time 49167.0 ns WRITE: Bank = 2 Row = 890, Col = 33, Data = 605dbbc0
|
# Status: Burst-No: 12 Write Address: 0037a856 WriteData: 605dbbc0
|
# Status: Burst-No: 12 Write Address: 0037a856 WriteData: 605dbbc0
|
# tb_core.u_sdram32 : at time 47977.0 ns WRITE: Bank = 2 Row = 890, Col = 34, Data = a6490c4c
|
# tb_core.u_sdram32 : at time 49177.0 ns WRITE: Bank = 2 Row = 890, Col = 34, Data = a6490c4c
|
# Status: Burst-No: 13 Write Address: 0037a856 WriteData: a6490c4c
|
# Status: Burst-No: 13 Write Address: 0037a856 WriteData: a6490c4c
|
# tb_core.u_sdram32 : at time 47987.0 ns WRITE: Bank = 2 Row = 890, Col = 35, Data = e8cfb0d1
|
# tb_core.u_sdram32 : at time 49187.0 ns WRITE: Bank = 2 Row = 890, Col = 35, Data = e8cfb0d1
|
# Status: Burst-No: 14 Write Address: 0037a856 WriteData: e8cfb0d1
|
# Status: Burst-No: 14 Write Address: 0037a856 WriteData: e8cfb0d1
|
# tb_core.u_sdram32 : at time 47997.0 ns WRITE: Bank = 2 Row = 890, Col = 36, Data = a8bb0c51
|
# tb_core.u_sdram32 : at time 49197.0 ns WRITE: Bank = 2 Row = 890, Col = 36, Data = a8bb0c51
|
# Status: Burst-No: 15 Write Address: 0037a856 WriteData: a8bb0c51
|
# Status: Burst-No: 15 Write Address: 0037a856 WriteData: a8bb0c51
|
# tb_core.u_sdram32 : at time 48007.0 ns WRITE: Bank = 2 Row = 890, Col = 37, Data = a8e1ee51
|
# tb_core.u_sdram32 : at time 49207.0 ns WRITE: Bank = 2 Row = 890, Col = 37, Data = a8e1ee51
|
# Status: Burst-No: 16 Write Address: 0037a856 WriteData: a8e1ee51
|
# Status: Burst-No: 16 Write Address: 0037a856 WriteData: a8e1ee51
|
# tb_core.u_sdram32 : at time 48017.0 ns WRITE: Bank = 2 Row = 890, Col = 38, Data = a2a4be45
|
# tb_core.u_sdram32 : at time 49217.0 ns WRITE: Bank = 2 Row = 890, Col = 38, Data = a2a4be45
|
# Status: Burst-No: 17 Write Address: 0037a856 WriteData: a2a4be45
|
# Status: Burst-No: 17 Write Address: 0037a856 WriteData: a2a4be45
|
# tb_core.u_sdram32 : at time 48027.0 ns WRITE: Bank = 2 Row = 890, Col = 39, Data = 598367b3
|
# tb_core.u_sdram32 : at time 49227.0 ns WRITE: Bank = 2 Row = 890, Col = 39, Data = 598367b3
|
# Status: Burst-No: 18 Write Address: 0037a856 WriteData: 598367b3
|
# Status: Burst-No: 18 Write Address: 0037a856 WriteData: 598367b3
|
# tb_core.u_sdram32 : at time 48037.0 ns WRITE: Bank = 2 Row = 890, Col = 40, Data = bf21067e
|
# tb_core.u_sdram32 : at time 49237.0 ns WRITE: Bank = 2 Row = 890, Col = 40, Data = bf21067e
|
# Status: Burst-No: 19 Write Address: 0037a856 WriteData: bf21067e
|
# Status: Burst-No: 19 Write Address: 0037a856 WriteData: bf21067e
|
# tb_core.u_sdram32 : at time 48047.0 ns WRITE: Bank = 2 Row = 890, Col = 41, Data = c049c680
|
# tb_core.u_sdram32 : at time 49247.0 ns WRITE: Bank = 2 Row = 890, Col = 41, Data = c049c680
|
# Status: Burst-No: 20 Write Address: 0037a856 WriteData: c049c680
|
# Status: Burst-No: 20 Write Address: 0037a856 WriteData: c049c680
|
# tb_core.u_sdram32 : at time 48057.0 ns WRITE: Bank = 2 Row = 890, Col = 42, Data = 7e5b53fc
|
# tb_core.u_sdram32 : at time 49257.0 ns WRITE: Bank = 2 Row = 890, Col = 42, Data = 7e5b53fc
|
# Status: Burst-No: 21 Write Address: 0037a856 WriteData: 7e5b53fc
|
# Status: Burst-No: 21 Write Address: 0037a856 WriteData: 7e5b53fc
|
# tb_core.u_sdram32 : at time 48067.0 ns WRITE: Bank = 2 Row = 890, Col = 43, Data = 2426d748
|
# tb_core.u_sdram32 : at time 49267.0 ns WRITE: Bank = 2 Row = 890, Col = 43, Data = 2426d748
|
# Status: Burst-No: 22 Write Address: 0037a856 WriteData: 2426d748
|
# Status: Burst-No: 22 Write Address: 0037a856 WriteData: 2426d748
|
# tb_core.u_sdram32 : at time 48077.0 ns WRITE: Bank = 2 Row = 890, Col = 44, Data = c0ad8081
|
# tb_core.u_sdram32 : at time 49277.0 ns WRITE: Bank = 2 Row = 890, Col = 44, Data = c0ad8081
|
# Status: Burst-No: 23 Write Address: 0037a856 WriteData: c0ad8081
|
# Status: Burst-No: 23 Write Address: 0037a856 WriteData: c0ad8081
|
# tb_core.u_sdram32 : at time 48087.0 ns WRITE: Bank = 2 Row = 890, Col = 45, Data = 98b4dc31
|
# tb_core.u_sdram32 : at time 49287.0 ns WRITE: Bank = 2 Row = 890, Col = 45, Data = 98b4dc31
|
# Status: Burst-No: 24 Write Address: 0037a856 WriteData: 98b4dc31
|
# Status: Burst-No: 24 Write Address: 0037a856 WriteData: 98b4dc31
|
# tb_core.u_sdram32 : at time 48097.0 ns WRITE: Bank = 2 Row = 890, Col = 46, Data = 53a8b5a7
|
# tb_core.u_sdram32 : at time 49297.0 ns WRITE: Bank = 2 Row = 890, Col = 46, Data = 53a8b5a7
|
# Status: Burst-No: 25 Write Address: 0037a856 WriteData: 53a8b5a7
|
# Status: Burst-No: 25 Write Address: 0037a856 WriteData: 53a8b5a7
|
# tb_core.u_sdram32 : at time 48107.0 ns WRITE: Bank = 2 Row = 890, Col = 47, Data = 41b1fd83
|
# tb_core.u_sdram32 : at time 49307.0 ns WRITE: Bank = 2 Row = 890, Col = 47, Data = 41b1fd83
|
# Status: Burst-No: 26 Write Address: 0037a856 WriteData: 41b1fd83
|
# Status: Burst-No: 26 Write Address: 0037a856 WriteData: 41b1fd83
|
# tb_core.u_sdram32 : at time 48117.0 ns WRITE: Bank = 2 Row = 890, Col = 48, Data = 9fc1423f
|
# tb_core.u_sdram32 : at time 49317.0 ns WRITE: Bank = 2 Row = 890, Col = 48, Data = 9fc1423f
|
# Status: Burst-No: 27 Write Address: 0037a856 WriteData: 9fc1423f
|
# Status: Burst-No: 27 Write Address: 0037a856 WriteData: 9fc1423f
|
# tb_core.u_sdram32 : at time 48127.0 ns WRITE: Bank = 2 Row = 890, Col = 49, Data = 00029100
|
# tb_core.u_sdram32 : at time 49327.0 ns WRITE: Bank = 2 Row = 890, Col = 49, Data = 00029100
|
# Status: Burst-No: 28 Write Address: 0037a856 WriteData: 00029100
|
# Status: Burst-No: 28 Write Address: 0037a856 WriteData: 00029100
|
# tb_core.u_sdram32 : at time 48137.0 ns WRITE: Bank = 2 Row = 890, Col = 50, Data = b2158c64
|
# tb_core.u_sdram32 : at time 49337.0 ns WRITE: Bank = 2 Row = 890, Col = 50, Data = b2158c64
|
# Status: Burst-No: 29 Write Address: 0037a856 WriteData: b2158c64
|
# Status: Burst-No: 29 Write Address: 0037a856 WriteData: b2158c64
|
# tb_core.u_sdram32 : at time 48147.0 ns WRITE: Bank = 2 Row = 890, Col = 51, Data = 3f52937e
|
# tb_core.u_sdram32 : at time 49347.0 ns WRITE: Bank = 2 Row = 890, Col = 51, Data = 3f52937e
|
# Status: Burst-No: 30 Write Address: 0037a856 WriteData: 3f52937e
|
# Status: Burst-No: 30 Write Address: 0037a856 WriteData: 3f52937e
|
# tb_core.u_sdram32 : at time 48157.0 ns WRITE: Bank = 2 Row = 890, Col = 52, Data = 7887dff1
|
# tb_core.u_sdram32 : at time 49357.0 ns WRITE: Bank = 2 Row = 890, Col = 52, Data = 7887dff1
|
# Status: Burst-No: 31 Write Address: 0037a856 WriteData: 7887dff1
|
# Status: Burst-No: 31 Write Address: 0037a856 WriteData: 7887dff1
|
# tb_core.u_sdram32 : at time 48167.0 ns WRITE: Bank = 2 Row = 890, Col = 53, Data = 472dfb8e
|
# tb_core.u_sdram32 : at time 49367.0 ns WRITE: Bank = 2 Row = 890, Col = 53, Data = 472dfb8e
|
# Status: Burst-No: 32 Write Address: 0037a856 WriteData: 472dfb8e
|
# Status: Burst-No: 32 Write Address: 0037a856 WriteData: 472dfb8e
|
# tb_core.u_sdram32 : at time 48177.0 ns WRITE: Bank = 2 Row = 890, Col = 54, Data = 4f234d9e
|
# tb_core.u_sdram32 : at time 49377.0 ns WRITE: Bank = 2 Row = 890, Col = 54, Data = 4f234d9e
|
# Status: Burst-No: 33 Write Address: 0037a856 WriteData: 4f234d9e
|
# Status: Burst-No: 33 Write Address: 0037a856 WriteData: 4f234d9e
|
# tb_core.u_sdram32 : at time 48187.0 ns WRITE: Bank = 2 Row = 890, Col = 55, Data = 742819e8
|
# tb_core.u_sdram32 : at time 49387.0 ns WRITE: Bank = 2 Row = 890, Col = 55, Data = 742819e8
|
# Status: Burst-No: 34 Write Address: 0037a856 WriteData: 742819e8
|
# Status: Burst-No: 34 Write Address: 0037a856 WriteData: 742819e8
|
# tb_core.u_sdram32 : at time 48197.0 ns WRITE: Bank = 2 Row = 890, Col = 56, Data = 24839b49
|
# tb_core.u_sdram32 : at time 49397.0 ns WRITE: Bank = 2 Row = 890, Col = 56, Data = 24839b49
|
# Status: Burst-No: 35 Write Address: 0037a856 WriteData: 24839b49
|
# Status: Burst-No: 35 Write Address: 0037a856 WriteData: 24839b49
|
# tb_core.u_sdram32 : at time 48207.0 ns WRITE: Bank = 2 Row = 890, Col = 57, Data = 8569fa0a
|
# tb_core.u_sdram32 : at time 49407.0 ns WRITE: Bank = 2 Row = 890, Col = 57, Data = 8569fa0a
|
# Status: Burst-No: 36 Write Address: 0037a856 WriteData: 8569fa0a
|
# Status: Burst-No: 36 Write Address: 0037a856 WriteData: 8569fa0a
|
# tb_core.u_sdram32 : at time 48217.0 ns WRITE: Bank = 2 Row = 890, Col = 58, Data = 2fb81b5f
|
# tb_core.u_sdram32 : at time 49417.0 ns WRITE: Bank = 2 Row = 890, Col = 58, Data = 2fb81b5f
|
# Status: Burst-No: 37 Write Address: 0037a856 WriteData: 2fb81b5f
|
# Status: Burst-No: 37 Write Address: 0037a856 WriteData: 2fb81b5f
|
# tb_core.u_sdram32 : at time 48227.0 ns WRITE: Bank = 2 Row = 890, Col = 59, Data = a8bfc851
|
# tb_core.u_sdram32 : at time 49427.0 ns WRITE: Bank = 2 Row = 890, Col = 59, Data = a8bfc851
|
# Status: Burst-No: 38 Write Address: 0037a856 WriteData: a8bfc851
|
# Status: Burst-No: 38 Write Address: 0037a856 WriteData: a8bfc851
|
# tb_core.u_sdram32 : at time 48237.0 ns WRITE: Bank = 2 Row = 890, Col = 60, Data = a4d98649
|
# tb_core.u_sdram32 : at time 49437.0 ns WRITE: Bank = 2 Row = 890, Col = 60, Data = a4d98649
|
# Status: Burst-No: 39 Write Address: 0037a856 WriteData: a4d98649
|
# Status: Burst-No: 39 Write Address: 0037a856 WriteData: a4d98649
|
# tb_core.u_sdram32 : at time 48247.0 ns WRITE: Bank = 2 Row = 890, Col = 61, Data = 92fd2825
|
# tb_core.u_sdram32 : at time 49447.0 ns WRITE: Bank = 2 Row = 890, Col = 61, Data = 92fd2825
|
# Status: Burst-No: 40 Write Address: 0037a856 WriteData: 92fd2825
|
# Status: Burst-No: 40 Write Address: 0037a856 WriteData: 92fd2825
|
# tb_core.u_sdram32 : at time 48257.0 ns WRITE: Bank = 2 Row = 890, Col = 62, Data = b64ae66c
|
# tb_core.u_sdram32 : at time 49457.0 ns WRITE: Bank = 2 Row = 890, Col = 62, Data = b64ae66c
|
# Status: Burst-No: 41 Write Address: 0037a856 WriteData: b64ae66c
|
# Status: Burst-No: 41 Write Address: 0037a856 WriteData: b64ae66c
|
# tb_core.u_sdram32 : at time 48267.0 ns WRITE: Bank = 2 Row = 890, Col = 63, Data = ac509c58
|
# tb_core.u_sdram32 : at time 49467.0 ns WRITE: Bank = 2 Row = 890, Col = 63, Data = ac509c58
|
# Status: Burst-No: 42 Write Address: 0037a856 WriteData: ac509c58
|
# Status: Burst-No: 42 Write Address: 0037a856 WriteData: ac509c58
|
# tb_core.u_sdram32 : at time 48277.0 ns WRITE: Bank = 2 Row = 890, Col = 64, Data = af5d6c5e
|
# tb_core.u_sdram32 : at time 49477.0 ns WRITE: Bank = 2 Row = 890, Col = 64, Data = af5d6c5e
|
# Status: Burst-No: 43 Write Address: 0037a856 WriteData: af5d6c5e
|
# Status: Burst-No: 43 Write Address: 0037a856 WriteData: af5d6c5e
|
# tb_core.u_sdram32 : at time 48287.0 ns WRITE: Bank = 2 Row = 890, Col = 65, Data = 97dde22f
|
# tb_core.u_sdram32 : at time 49487.0 ns WRITE: Bank = 2 Row = 890, Col = 65, Data = 97dde22f
|
# Status: Burst-No: 44 Write Address: 0037a856 WriteData: 97dde22f
|
# Status: Burst-No: 44 Write Address: 0037a856 WriteData: 97dde22f
|
# tb_core.u_sdram32 : at time 48297.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 49497.0 ns BST : Burst Terminate
|
# Write Address: 000f5a83, Burst Size: 40
|
# Write Address: 000f5a83, Burst Size: 40
|
# tb_core.u_sdram32 : at time 48437.0 ns ACT : Bank = 2 Row = 245
|
# tb_core.u_sdram32 : at time 49637.0 ns ACT : Bank = 2 Row = 245
|
# tb_core.u_sdram32 : at time 48467.0 ns WRITE: Bank = 2 Row = 245, Col = 160, Data = 6a5ddbd4
|
# tb_core.u_sdram32 : at time 49667.0 ns WRITE: Bank = 2 Row = 245, Col = 160, Data = 6a5ddbd4
|
# Status: Burst-No: 0 Write Address: 000f5a83 WriteData: 6a5ddbd4
|
# Status: Burst-No: 0 Write Address: 000f5a83 WriteData: 6a5ddbd4
|
# tb_core.u_sdram32 : at time 48477.0 ns WRITE: Bank = 2 Row = 245, Col = 161, Data = ca0e4494
|
# tb_core.u_sdram32 : at time 49677.0 ns WRITE: Bank = 2 Row = 245, Col = 161, Data = ca0e4494
|
# Status: Burst-No: 1 Write Address: 000f5a83 WriteData: ca0e4494
|
# Status: Burst-No: 1 Write Address: 000f5a83 WriteData: ca0e4494
|
# tb_core.u_sdram32 : at time 48487.0 ns WRITE: Bank = 2 Row = 245, Col = 162, Data = c961e492
|
# tb_core.u_sdram32 : at time 49687.0 ns WRITE: Bank = 2 Row = 245, Col = 162, Data = c961e492
|
# Status: Burst-No: 2 Write Address: 000f5a83 WriteData: c961e492
|
# Status: Burst-No: 2 Write Address: 000f5a83 WriteData: c961e492
|
# tb_core.u_sdram32 : at time 48497.0 ns WRITE: Bank = 2 Row = 245, Col = 163, Data = 1e32673c
|
# tb_core.u_sdram32 : at time 49697.0 ns WRITE: Bank = 2 Row = 245, Col = 163, Data = 1e32673c
|
# Status: Burst-No: 3 Write Address: 000f5a83 WriteData: 1e32673c
|
# Status: Burst-No: 3 Write Address: 000f5a83 WriteData: 1e32673c
|
# tb_core.u_sdram32 : at time 48507.0 ns WRITE: Bank = 2 Row = 245, Col = 164, Data = 23301b46
|
# tb_core.u_sdram32 : at time 49707.0 ns WRITE: Bank = 2 Row = 245, Col = 164, Data = 23301b46
|
# Status: Burst-No: 4 Write Address: 000f5a83 WriteData: 23301b46
|
# Status: Burst-No: 4 Write Address: 000f5a83 WriteData: 23301b46
|
# tb_core.u_sdram32 : at time 48517.0 ns WRITE: Bank = 2 Row = 245, Col = 165, Data = b7b82a6f
|
# tb_core.u_sdram32 : at time 49717.0 ns WRITE: Bank = 2 Row = 245, Col = 165, Data = b7b82a6f
|
# Status: Burst-No: 5 Write Address: 000f5a83 WriteData: b7b82a6f
|
# Status: Burst-No: 5 Write Address: 000f5a83 WriteData: b7b82a6f
|
# tb_core.u_sdram32 : at time 48527.0 ns WRITE: Bank = 2 Row = 245, Col = 166, Data = a0b3ae41
|
# tb_core.u_sdram32 : at time 49727.0 ns WRITE: Bank = 2 Row = 245, Col = 166, Data = a0b3ae41
|
# Status: Burst-No: 6 Write Address: 000f5a83 WriteData: a0b3ae41
|
# Status: Burst-No: 6 Write Address: 000f5a83 WriteData: a0b3ae41
|
# tb_core.u_sdram32 : at time 48537.0 ns WRITE: Bank = 2 Row = 245, Col = 167, Data = 7bde15f7
|
# tb_core.u_sdram32 : at time 49737.0 ns WRITE: Bank = 2 Row = 245, Col = 167, Data = 7bde15f7
|
# Status: Burst-No: 7 Write Address: 000f5a83 WriteData: 7bde15f7
|
# Status: Burst-No: 7 Write Address: 000f5a83 WriteData: 7bde15f7
|
# tb_core.u_sdram32 : at time 48547.0 ns WRITE: Bank = 2 Row = 245, Col = 168, Data = 8b7c3816
|
# tb_core.u_sdram32 : at time 49747.0 ns WRITE: Bank = 2 Row = 245, Col = 168, Data = 8b7c3816
|
# Status: Burst-No: 8 Write Address: 000f5a83 WriteData: 8b7c3816
|
# Status: Burst-No: 8 Write Address: 000f5a83 WriteData: 8b7c3816
|
# tb_core.u_sdram32 : at time 48557.0 ns WRITE: Bank = 2 Row = 245, Col = 169, Data = 39092f72
|
# tb_core.u_sdram32 : at time 49757.0 ns WRITE: Bank = 2 Row = 245, Col = 169, Data = 39092f72
|
# Status: Burst-No: 9 Write Address: 000f5a83 WriteData: 39092f72
|
# Status: Burst-No: 9 Write Address: 000f5a83 WriteData: 39092f72
|
# tb_core.u_sdram32 : at time 48567.0 ns WRITE: Bank = 2 Row = 245, Col = 170, Data = 5136a5a2
|
# tb_core.u_sdram32 : at time 49767.0 ns WRITE: Bank = 2 Row = 245, Col = 170, Data = 5136a5a2
|
# Status: Burst-No: 10 Write Address: 000f5a83 WriteData: 5136a5a2
|
# Status: Burst-No: 10 Write Address: 000f5a83 WriteData: 5136a5a2
|
# tb_core.u_sdram32 : at time 48577.0 ns WRITE: Bank = 2 Row = 245, Col = 171, Data = 71f059e3
|
# tb_core.u_sdram32 : at time 49777.0 ns WRITE: Bank = 2 Row = 245, Col = 171, Data = 71f059e3
|
# Status: Burst-No: 11 Write Address: 000f5a83 WriteData: 71f059e3
|
# Status: Burst-No: 11 Write Address: 000f5a83 WriteData: 71f059e3
|
# tb_core.u_sdram32 : at time 48587.0 ns WRITE: Bank = 2 Row = 245, Col = 172, Data = c9490292
|
# tb_core.u_sdram32 : at time 49787.0 ns WRITE: Bank = 2 Row = 245, Col = 172, Data = c9490292
|
# Status: Burst-No: 12 Write Address: 000f5a83 WriteData: c9490292
|
# Status: Burst-No: 12 Write Address: 000f5a83 WriteData: c9490292
|
# tb_core.u_sdram32 : at time 48597.0 ns WRITE: Bank = 2 Row = 245, Col = 173, Data = e5ceb0cb
|
# tb_core.u_sdram32 : at time 49797.0 ns WRITE: Bank = 2 Row = 245, Col = 173, Data = e5ceb0cb
|
# Status: Burst-No: 13 Write Address: 000f5a83 WriteData: e5ceb0cb
|
# Status: Burst-No: 13 Write Address: 000f5a83 WriteData: e5ceb0cb
|
# tb_core.u_sdram32 : at time 48607.0 ns WRITE: Bank = 2 Row = 245, Col = 174, Data = 34097568
|
# tb_core.u_sdram32 : at time 49807.0 ns WRITE: Bank = 2 Row = 245, Col = 174, Data = 34097568
|
# Status: Burst-No: 14 Write Address: 000f5a83 WriteData: 34097568
|
# Status: Burst-No: 14 Write Address: 000f5a83 WriteData: 34097568
|
# tb_core.u_sdram32 : at time 48617.0 ns WRITE: Bank = 2 Row = 245, Col = 175, Data = 98b4ee31
|
# tb_core.u_sdram32 : at time 49817.0 ns WRITE: Bank = 2 Row = 245, Col = 175, Data = 98b4ee31
|
# Status: Burst-No: 15 Write Address: 000f5a83 WriteData: 98b4ee31
|
# Status: Burst-No: 15 Write Address: 000f5a83 WriteData: 98b4ee31
|
# tb_core.u_sdram32 : at time 48627.0 ns WRITE: Bank = 2 Row = 245, Col = 176, Data = 65c803cb
|
# tb_core.u_sdram32 : at time 49827.0 ns WRITE: Bank = 2 Row = 245, Col = 176, Data = 65c803cb
|
# Status: Burst-No: 16 Write Address: 000f5a83 WriteData: 65c803cb
|
# Status: Burst-No: 16 Write Address: 000f5a83 WriteData: 65c803cb
|
# tb_core.u_sdram32 : at time 48637.0 ns WRITE: Bank = 2 Row = 245, Col = 177, Data = aad1c855
|
# tb_core.u_sdram32 : at time 49837.0 ns WRITE: Bank = 2 Row = 245, Col = 177, Data = aad1c855
|
# Status: Burst-No: 17 Write Address: 000f5a83 WriteData: aad1c855
|
# Status: Burst-No: 17 Write Address: 000f5a83 WriteData: aad1c855
|
# tb_core.u_sdram32 : at time 48647.0 ns WRITE: Bank = 2 Row = 245, Col = 178, Data = 38a38971
|
# tb_core.u_sdram32 : at time 49847.0 ns WRITE: Bank = 2 Row = 245, Col = 178, Data = 38a38971
|
# Status: Burst-No: 18 Write Address: 000f5a83 WriteData: 38a38971
|
# Status: Burst-No: 18 Write Address: 000f5a83 WriteData: 38a38971
|
# tb_core.u_sdram32 : at time 48657.0 ns WRITE: Bank = 2 Row = 245, Col = 179, Data = 2f49535e
|
# tb_core.u_sdram32 : at time 49857.0 ns WRITE: Bank = 2 Row = 245, Col = 179, Data = 2f49535e
|
# Status: Burst-No: 19 Write Address: 000f5a83 WriteData: 2f49535e
|
# Status: Burst-No: 19 Write Address: 000f5a83 WriteData: 2f49535e
|
# tb_core.u_sdram32 : at time 48667.0 ns WRITE: Bank = 2 Row = 245, Col = 180, Data = e6e186cd
|
# tb_core.u_sdram32 : at time 49867.0 ns WRITE: Bank = 2 Row = 245, Col = 180, Data = e6e186cd
|
# Status: Burst-No: 20 Write Address: 000f5a83 WriteData: e6e186cd
|
# Status: Burst-No: 20 Write Address: 000f5a83 WriteData: e6e186cd
|
# tb_core.u_sdram32 : at time 48677.0 ns WRITE: Bank = 2 Row = 245, Col = 181, Data = daf356b5
|
# tb_core.u_sdram32 : at time 49877.0 ns WRITE: Bank = 2 Row = 245, Col = 181, Data = daf356b5
|
# Status: Burst-No: 21 Write Address: 000f5a83 WriteData: daf356b5
|
# Status: Burst-No: 21 Write Address: 000f5a83 WriteData: daf356b5
|
# tb_core.u_sdram32 : at time 48687.0 ns WRITE: Bank = 2 Row = 245, Col = 182, Data = 04410d08
|
# tb_core.u_sdram32 : at time 49887.0 ns WRITE: Bank = 2 Row = 245, Col = 182, Data = 04410d08
|
# Status: Burst-No: 22 Write Address: 000f5a83 WriteData: 04410d08
|
# Status: Burst-No: 22 Write Address: 000f5a83 WriteData: 04410d08
|
# tb_core.u_sdram32 : at time 48697.0 ns WRITE: Bank = 2 Row = 245, Col = 183, Data = c118be82
|
# tb_core.u_sdram32 : at time 49897.0 ns WRITE: Bank = 2 Row = 245, Col = 183, Data = c118be82
|
# Status: Burst-No: 23 Write Address: 000f5a83 WriteData: c118be82
|
# Status: Burst-No: 23 Write Address: 000f5a83 WriteData: c118be82
|
# tb_core.u_sdram32 : at time 48707.0 ns WRITE: Bank = 2 Row = 245, Col = 184, Data = 9f80983f
|
# tb_core.u_sdram32 : at time 49907.0 ns WRITE: Bank = 2 Row = 245, Col = 184, Data = 9f80983f
|
# Status: Burst-No: 24 Write Address: 000f5a83 WriteData: 9f80983f
|
# Status: Burst-No: 24 Write Address: 000f5a83 WriteData: 9f80983f
|
# tb_core.u_sdram32 : at time 48717.0 ns WRITE: Bank = 2 Row = 245, Col = 185, Data = d807f2b0
|
# tb_core.u_sdram32 : at time 49917.0 ns WRITE: Bank = 2 Row = 245, Col = 185, Data = d807f2b0
|
# Status: Burst-No: 25 Write Address: 000f5a83 WriteData: d807f2b0
|
# Status: Burst-No: 25 Write Address: 000f5a83 WriteData: d807f2b0
|
# tb_core.u_sdram32 : at time 48727.0 ns WRITE: Bank = 2 Row = 245, Col = 186, Data = 560eefac
|
# tb_core.u_sdram32 : at time 49927.0 ns WRITE: Bank = 2 Row = 245, Col = 186, Data = 560eefac
|
# Status: Burst-No: 26 Write Address: 000f5a83 WriteData: 560eefac
|
# Status: Burst-No: 26 Write Address: 000f5a83 WriteData: 560eefac
|
# tb_core.u_sdram32 : at time 48737.0 ns WRITE: Bank = 2 Row = 245, Col = 187, Data = 99183032
|
# tb_core.u_sdram32 : at time 49937.0 ns WRITE: Bank = 2 Row = 245, Col = 187, Data = 99183032
|
# Status: Burst-No: 27 Write Address: 000f5a83 WriteData: 99183032
|
# Status: Burst-No: 27 Write Address: 000f5a83 WriteData: 99183032
|
# tb_core.u_sdram32 : at time 48747.0 ns WRITE: Bank = 2 Row = 245, Col = 188, Data = 029f0505
|
# tb_core.u_sdram32 : at time 49947.0 ns WRITE: Bank = 2 Row = 245, Col = 188, Data = 029f0505
|
# Status: Burst-No: 28 Write Address: 000f5a83 WriteData: 029f0505
|
# Status: Burst-No: 28 Write Address: 000f5a83 WriteData: 029f0505
|
# tb_core.u_sdram32 : at time 48757.0 ns WRITE: Bank = 2 Row = 245, Col = 189, Data = 2f73fb5e
|
# tb_core.u_sdram32 : at time 49957.0 ns WRITE: Bank = 2 Row = 245, Col = 189, Data = 2f73fb5e
|
# Status: Burst-No: 29 Write Address: 000f5a83 WriteData: 2f73fb5e
|
# Status: Burst-No: 29 Write Address: 000f5a83 WriteData: 2f73fb5e
|
# tb_core.u_sdram32 : at time 48767.0 ns WRITE: Bank = 2 Row = 245, Col = 190, Data = dc16d8b8
|
# tb_core.u_sdram32 : at time 49967.0 ns WRITE: Bank = 2 Row = 245, Col = 190, Data = dc16d8b8
|
# Status: Burst-No: 30 Write Address: 000f5a83 WriteData: dc16d8b8
|
# Status: Burst-No: 30 Write Address: 000f5a83 WriteData: dc16d8b8
|
# tb_core.u_sdram32 : at time 48777.0 ns WRITE: Bank = 2 Row = 245, Col = 191, Data = 3ec2677d
|
# tb_core.u_sdram32 : at time 49977.0 ns WRITE: Bank = 2 Row = 245, Col = 191, Data = 3ec2677d
|
# Status: Burst-No: 31 Write Address: 000f5a83 WriteData: 3ec2677d
|
# Status: Burst-No: 31 Write Address: 000f5a83 WriteData: 3ec2677d
|
# tb_core.u_sdram32 : at time 48787.0 ns WRITE: Bank = 2 Row = 245, Col = 192, Data = 8511580a
|
# tb_core.u_sdram32 : at time 49987.0 ns WRITE: Bank = 2 Row = 245, Col = 192, Data = 8511580a
|
# Status: Burst-No: 32 Write Address: 000f5a83 WriteData: 8511580a
|
# Status: Burst-No: 32 Write Address: 000f5a83 WriteData: 8511580a
|
# tb_core.u_sdram32 : at time 48797.0 ns WRITE: Bank = 2 Row = 245, Col = 193, Data = c6878a8d
|
# tb_core.u_sdram32 : at time 49997.0 ns WRITE: Bank = 2 Row = 245, Col = 193, Data = c6878a8d
|
# Status: Burst-No: 33 Write Address: 000f5a83 WriteData: c6878a8d
|
# Status: Burst-No: 33 Write Address: 000f5a83 WriteData: c6878a8d
|
# tb_core.u_sdram32 : at time 48807.0 ns WRITE: Bank = 2 Row = 245, Col = 194, Data = 64eb39c9
|
# tb_core.u_sdram32 : at time 50007.0 ns WRITE: Bank = 2 Row = 245, Col = 194, Data = 64eb39c9
|
# Status: Burst-No: 34 Write Address: 000f5a83 WriteData: 64eb39c9
|
# Status: Burst-No: 34 Write Address: 000f5a83 WriteData: 64eb39c9
|
# tb_core.u_sdram32 : at time 48817.0 ns WRITE: Bank = 2 Row = 245, Col = 195, Data = f8d3d8f1
|
# tb_core.u_sdram32 : at time 50017.0 ns WRITE: Bank = 2 Row = 245, Col = 195, Data = f8d3d8f1
|
# Status: Burst-No: 35 Write Address: 000f5a83 WriteData: f8d3d8f1
|
# Status: Burst-No: 35 Write Address: 000f5a83 WriteData: f8d3d8f1
|
# tb_core.u_sdram32 : at time 48827.0 ns WRITE: Bank = 2 Row = 245, Col = 196, Data = da12deb4
|
# tb_core.u_sdram32 : at time 50027.0 ns WRITE: Bank = 2 Row = 245, Col = 196, Data = da12deb4
|
# Status: Burst-No: 36 Write Address: 000f5a83 WriteData: da12deb4
|
# Status: Burst-No: 36 Write Address: 000f5a83 WriteData: da12deb4
|
# tb_core.u_sdram32 : at time 48837.0 ns WRITE: Bank = 2 Row = 245, Col = 197, Data = 729a7fe5
|
# tb_core.u_sdram32 : at time 50037.0 ns WRITE: Bank = 2 Row = 245, Col = 197, Data = 729a7fe5
|
# Status: Burst-No: 37 Write Address: 000f5a83 WriteData: 729a7fe5
|
# Status: Burst-No: 37 Write Address: 000f5a83 WriteData: 729a7fe5
|
# tb_core.u_sdram32 : at time 48847.0 ns WRITE: Bank = 2 Row = 245, Col = 198, Data = 1a133934
|
# tb_core.u_sdram32 : at time 50047.0 ns WRITE: Bank = 2 Row = 245, Col = 198, Data = 1a133934
|
# Status: Burst-No: 38 Write Address: 000f5a83 WriteData: 1a133934
|
# Status: Burst-No: 38 Write Address: 000f5a83 WriteData: 1a133934
|
# tb_core.u_sdram32 : at time 48857.0 ns WRITE: Bank = 2 Row = 245, Col = 199, Data = 11c6c523
|
# tb_core.u_sdram32 : at time 50057.0 ns WRITE: Bank = 2 Row = 245, Col = 199, Data = 11c6c523
|
# Status: Burst-No: 39 Write Address: 000f5a83 WriteData: 11c6c523
|
# Status: Burst-No: 39 Write Address: 000f5a83 WriteData: 11c6c523
|
# tb_core.u_sdram32 : at time 48867.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 50067.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 49007.0 ns ACT : Bank = 2 Row = 890
|
# tb_core.u_sdram32 : at time 50207.0 ns ACT : Bank = 2 Row = 890
|
# tb_core.u_sdram32 : at time 49063.0 ns READ : Bank = 2 Row = 890, Col = 21, Data = e99b1cd3
|
# tb_core.u_sdram32 : at time 50263.0 ns READ : Bank = 2 Row = 890, Col = 21, Data = e99b1cd3
|
# tb_core.u_sdram32 : at time 49073.0 ns READ : Bank = 2 Row = 890, Col = 22, Data = 0d633f1a
|
# tb_core.u_sdram32 : at time 50273.0 ns READ : Bank = 2 Row = 890, Col = 22, Data = 0d633f1a
|
# READ STATUS: Burst-No: 0 Addr: 0037a856 Rxd: e99b1cd3
|
# READ STATUS: Burst-No: 0 Addr: 0037a856 Rxd: e99b1cd3
|
# tb_core.u_sdram32 : at time 49083.0 ns READ : Bank = 2 Row = 890, Col = 23, Data = 005d5100
|
# tb_core.u_sdram32 : at time 50283.0 ns READ : Bank = 2 Row = 890, Col = 23, Data = 005d5100
|
# READ STATUS: Burst-No: 1 Addr: 0037a858 Rxd: 0d633f1a
|
# READ STATUS: Burst-No: 1 Addr: 0037a858 Rxd: 0d633f1a
|
# tb_core.u_sdram32 : at time 49093.0 ns READ : Bank = 2 Row = 890, Col = 24, Data = 560d5fac
|
# tb_core.u_sdram32 : at time 50293.0 ns READ : Bank = 2 Row = 890, Col = 24, Data = 560d5fac
|
# READ STATUS: Burst-No: 2 Addr: 0037a85a Rxd: 005d5100
|
# READ STATUS: Burst-No: 2 Addr: 0037a85a Rxd: 005d5100
|
# tb_core.u_sdram32 : at time 49103.0 ns READ : Bank = 2 Row = 890, Col = 25, Data = f4588ee8
|
# tb_core.u_sdram32 : at time 50303.0 ns READ : Bank = 2 Row = 890, Col = 25, Data = f4588ee8
|
# READ STATUS: Burst-No: 3 Addr: 0037a85c Rxd: 560d5fac
|
# READ STATUS: Burst-No: 3 Addr: 0037a85c Rxd: 560d5fac
|
# tb_core.u_sdram32 : at time 49113.0 ns READ : Bank = 2 Row = 890, Col = 26, Data = b66a586c
|
# tb_core.u_sdram32 : at time 50313.0 ns READ : Bank = 2 Row = 890, Col = 26, Data = b66a586c
|
# READ STATUS: Burst-No: 4 Addr: 0037a85e Rxd: f4588ee8
|
# READ STATUS: Burst-No: 4 Addr: 0037a85e Rxd: f4588ee8
|
# tb_core.u_sdram32 : at time 49123.0 ns READ : Bank = 2 Row = 890, Col = 27, Data = d03c40a0
|
# tb_core.u_sdram32 : at time 50323.0 ns READ : Bank = 2 Row = 890, Col = 27, Data = d03c40a0
|
# READ STATUS: Burst-No: 5 Addr: 0037a860 Rxd: b66a586c
|
# READ STATUS: Burst-No: 5 Addr: 0037a860 Rxd: b66a586c
|
# tb_core.u_sdram32 : at time 49133.0 ns READ : Bank = 2 Row = 890, Col = 28, Data = 0ecd251d
|
# tb_core.u_sdram32 : at time 50333.0 ns READ : Bank = 2 Row = 890, Col = 28, Data = 0ecd251d
|
# READ STATUS: Burst-No: 6 Addr: 0037a862 Rxd: d03c40a0
|
# READ STATUS: Burst-No: 6 Addr: 0037a862 Rxd: d03c40a0
|
# tb_core.u_sdram32 : at time 49143.0 ns READ : Bank = 2 Row = 890, Col = 29, Data = 68c14fd1
|
# tb_core.u_sdram32 : at time 50343.0 ns READ : Bank = 2 Row = 890, Col = 29, Data = 68c14fd1
|
# READ STATUS: Burst-No: 7 Addr: 0037a864 Rxd: 0ecd251d
|
# READ STATUS: Burst-No: 7 Addr: 0037a864 Rxd: 0ecd251d
|
# tb_core.u_sdram32 : at time 49153.0 ns READ : Bank = 2 Row = 890, Col = 30, Data = 006d0f00
|
# tb_core.u_sdram32 : at time 50353.0 ns READ : Bank = 2 Row = 890, Col = 30, Data = 006d0f00
|
# READ STATUS: Burst-No: 8 Addr: 0037a866 Rxd: 68c14fd1
|
# READ STATUS: Burst-No: 8 Addr: 0037a866 Rxd: 68c14fd1
|
# tb_core.u_sdram32 : at time 49163.0 ns READ : Bank = 2 Row = 890, Col = 31, Data = ed4d78da
|
# tb_core.u_sdram32 : at time 50363.0 ns READ : Bank = 2 Row = 890, Col = 31, Data = ed4d78da
|
# READ STATUS: Burst-No: 9 Addr: 0037a868 Rxd: 006d0f00
|
# READ STATUS: Burst-No: 9 Addr: 0037a868 Rxd: 006d0f00
|
# tb_core.u_sdram32 : at time 49173.0 ns READ : Bank = 2 Row = 890, Col = 32, Data = 6c1987d8
|
# tb_core.u_sdram32 : at time 50373.0 ns READ : Bank = 2 Row = 890, Col = 32, Data = 6c1987d8
|
# READ STATUS: Burst-No: 10 Addr: 0037a86a Rxd: ed4d78da
|
# READ STATUS: Burst-No: 10 Addr: 0037a86a Rxd: ed4d78da
|
# tb_core.u_sdram32 : at time 49183.0 ns READ : Bank = 2 Row = 890, Col = 33, Data = 605dbbc0
|
# tb_core.u_sdram32 : at time 50383.0 ns READ : Bank = 2 Row = 890, Col = 33, Data = 605dbbc0
|
# READ STATUS: Burst-No: 11 Addr: 0037a86c Rxd: 6c1987d8
|
# READ STATUS: Burst-No: 11 Addr: 0037a86c Rxd: 6c1987d8
|
# tb_core.u_sdram32 : at time 49193.0 ns READ : Bank = 2 Row = 890, Col = 34, Data = a6490c4c
|
# tb_core.u_sdram32 : at time 50393.0 ns READ : Bank = 2 Row = 890, Col = 34, Data = a6490c4c
|
# READ STATUS: Burst-No: 12 Addr: 0037a86e Rxd: 605dbbc0
|
# READ STATUS: Burst-No: 12 Addr: 0037a86e Rxd: 605dbbc0
|
# tb_core.u_sdram32 : at time 49203.0 ns READ : Bank = 2 Row = 890, Col = 35, Data = e8cfb0d1
|
# tb_core.u_sdram32 : at time 50403.0 ns READ : Bank = 2 Row = 890, Col = 35, Data = e8cfb0d1
|
# READ STATUS: Burst-No: 13 Addr: 0037a870 Rxd: a6490c4c
|
# READ STATUS: Burst-No: 13 Addr: 0037a870 Rxd: a6490c4c
|
# tb_core.u_sdram32 : at time 49213.0 ns READ : Bank = 2 Row = 890, Col = 36, Data = a8bb0c51
|
# tb_core.u_sdram32 : at time 50413.0 ns READ : Bank = 2 Row = 890, Col = 36, Data = a8bb0c51
|
# READ STATUS: Burst-No: 14 Addr: 0037a872 Rxd: e8cfb0d1
|
# READ STATUS: Burst-No: 14 Addr: 0037a872 Rxd: e8cfb0d1
|
# tb_core.u_sdram32 : at time 49223.0 ns READ : Bank = 2 Row = 890, Col = 37, Data = a8e1ee51
|
# tb_core.u_sdram32 : at time 50423.0 ns READ : Bank = 2 Row = 890, Col = 37, Data = a8e1ee51
|
# READ STATUS: Burst-No: 15 Addr: 0037a874 Rxd: a8bb0c51
|
# READ STATUS: Burst-No: 15 Addr: 0037a874 Rxd: a8bb0c51
|
# tb_core.u_sdram32 : at time 49233.0 ns READ : Bank = 2 Row = 890, Col = 38, Data = a2a4be45
|
# tb_core.u_sdram32 : at time 50433.0 ns READ : Bank = 2 Row = 890, Col = 38, Data = a2a4be45
|
# READ STATUS: Burst-No: 16 Addr: 0037a876 Rxd: a8e1ee51
|
# READ STATUS: Burst-No: 16 Addr: 0037a876 Rxd: a8e1ee51
|
# tb_core.u_sdram32 : at time 49243.0 ns READ : Bank = 2 Row = 890, Col = 39, Data = 598367b3
|
# tb_core.u_sdram32 : at time 50443.0 ns READ : Bank = 2 Row = 890, Col = 39, Data = 598367b3
|
# READ STATUS: Burst-No: 17 Addr: 0037a878 Rxd: a2a4be45
|
# READ STATUS: Burst-No: 17 Addr: 0037a878 Rxd: a2a4be45
|
# tb_core.u_sdram32 : at time 49253.0 ns READ : Bank = 2 Row = 890, Col = 40, Data = bf21067e
|
# tb_core.u_sdram32 : at time 50453.0 ns READ : Bank = 2 Row = 890, Col = 40, Data = bf21067e
|
# READ STATUS: Burst-No: 18 Addr: 0037a87a Rxd: 598367b3
|
# READ STATUS: Burst-No: 18 Addr: 0037a87a Rxd: 598367b3
|
# tb_core.u_sdram32 : at time 49263.0 ns READ : Bank = 2 Row = 890, Col = 41, Data = c049c680
|
# tb_core.u_sdram32 : at time 50463.0 ns READ : Bank = 2 Row = 890, Col = 41, Data = c049c680
|
# READ STATUS: Burst-No: 19 Addr: 0037a87c Rxd: bf21067e
|
# READ STATUS: Burst-No: 19 Addr: 0037a87c Rxd: bf21067e
|
# tb_core.u_sdram32 : at time 49273.0 ns READ : Bank = 2 Row = 890, Col = 42, Data = 7e5b53fc
|
# tb_core.u_sdram32 : at time 50473.0 ns READ : Bank = 2 Row = 890, Col = 42, Data = 7e5b53fc
|
# READ STATUS: Burst-No: 20 Addr: 0037a87e Rxd: c049c680
|
# READ STATUS: Burst-No: 20 Addr: 0037a87e Rxd: c049c680
|
# tb_core.u_sdram32 : at time 49283.0 ns READ : Bank = 2 Row = 890, Col = 43, Data = 2426d748
|
# tb_core.u_sdram32 : at time 50483.0 ns READ : Bank = 2 Row = 890, Col = 43, Data = 2426d748
|
# READ STATUS: Burst-No: 21 Addr: 0037a880 Rxd: 7e5b53fc
|
# READ STATUS: Burst-No: 21 Addr: 0037a880 Rxd: 7e5b53fc
|
# tb_core.u_sdram32 : at time 49293.0 ns READ : Bank = 2 Row = 890, Col = 44, Data = c0ad8081
|
# tb_core.u_sdram32 : at time 50493.0 ns READ : Bank = 2 Row = 890, Col = 44, Data = c0ad8081
|
# READ STATUS: Burst-No: 22 Addr: 0037a882 Rxd: 2426d748
|
# READ STATUS: Burst-No: 22 Addr: 0037a882 Rxd: 2426d748
|
# tb_core.u_sdram32 : at time 49303.0 ns READ : Bank = 2 Row = 890, Col = 45, Data = 98b4dc31
|
# tb_core.u_sdram32 : at time 50503.0 ns READ : Bank = 2 Row = 890, Col = 45, Data = 98b4dc31
|
# READ STATUS: Burst-No: 23 Addr: 0037a884 Rxd: c0ad8081
|
# READ STATUS: Burst-No: 23 Addr: 0037a884 Rxd: c0ad8081
|
# tb_core.u_sdram32 : at time 49313.0 ns READ : Bank = 2 Row = 890, Col = 46, Data = 53a8b5a7
|
# tb_core.u_sdram32 : at time 50513.0 ns READ : Bank = 2 Row = 890, Col = 46, Data = 53a8b5a7
|
# READ STATUS: Burst-No: 24 Addr: 0037a886 Rxd: 98b4dc31
|
# READ STATUS: Burst-No: 24 Addr: 0037a886 Rxd: 98b4dc31
|
# tb_core.u_sdram32 : at time 49323.0 ns READ : Bank = 2 Row = 890, Col = 47, Data = 41b1fd83
|
# tb_core.u_sdram32 : at time 50523.0 ns READ : Bank = 2 Row = 890, Col = 47, Data = 41b1fd83
|
# READ STATUS: Burst-No: 25 Addr: 0037a888 Rxd: 53a8b5a7
|
# READ STATUS: Burst-No: 25 Addr: 0037a888 Rxd: 53a8b5a7
|
# tb_core.u_sdram32 : at time 49333.0 ns READ : Bank = 2 Row = 890, Col = 48, Data = 9fc1423f
|
# tb_core.u_sdram32 : at time 50533.0 ns READ : Bank = 2 Row = 890, Col = 48, Data = 9fc1423f
|
# READ STATUS: Burst-No: 26 Addr: 0037a88a Rxd: 41b1fd83
|
# READ STATUS: Burst-No: 26 Addr: 0037a88a Rxd: 41b1fd83
|
# tb_core.u_sdram32 : at time 49343.0 ns READ : Bank = 2 Row = 890, Col = 49, Data = 00029100
|
# tb_core.u_sdram32 : at time 50543.0 ns READ : Bank = 2 Row = 890, Col = 49, Data = 00029100
|
# READ STATUS: Burst-No: 27 Addr: 0037a88c Rxd: 9fc1423f
|
# READ STATUS: Burst-No: 27 Addr: 0037a88c Rxd: 9fc1423f
|
# tb_core.u_sdram32 : at time 49353.0 ns READ : Bank = 2 Row = 890, Col = 50, Data = b2158c64
|
# tb_core.u_sdram32 : at time 50553.0 ns READ : Bank = 2 Row = 890, Col = 50, Data = b2158c64
|
# READ STATUS: Burst-No: 28 Addr: 0037a88e Rxd: 00029100
|
# READ STATUS: Burst-No: 28 Addr: 0037a88e Rxd: 00029100
|
# tb_core.u_sdram32 : at time 49363.0 ns READ : Bank = 2 Row = 890, Col = 51, Data = 3f52937e
|
# tb_core.u_sdram32 : at time 50563.0 ns READ : Bank = 2 Row = 890, Col = 51, Data = 3f52937e
|
# READ STATUS: Burst-No: 29 Addr: 0037a890 Rxd: b2158c64
|
# READ STATUS: Burst-No: 29 Addr: 0037a890 Rxd: b2158c64
|
# tb_core.u_sdram32 : at time 49373.0 ns READ : Bank = 2 Row = 890, Col = 52, Data = 7887dff1
|
# tb_core.u_sdram32 : at time 50573.0 ns READ : Bank = 2 Row = 890, Col = 52, Data = 7887dff1
|
# READ STATUS: Burst-No: 30 Addr: 0037a892 Rxd: 3f52937e
|
# READ STATUS: Burst-No: 30 Addr: 0037a892 Rxd: 3f52937e
|
# tb_core.u_sdram32 : at time 49383.0 ns READ : Bank = 2 Row = 890, Col = 53, Data = 472dfb8e
|
# tb_core.u_sdram32 : at time 50583.0 ns READ : Bank = 2 Row = 890, Col = 53, Data = 472dfb8e
|
# READ STATUS: Burst-No: 31 Addr: 0037a894 Rxd: 7887dff1
|
# READ STATUS: Burst-No: 31 Addr: 0037a894 Rxd: 7887dff1
|
# tb_core.u_sdram32 : at time 49393.0 ns READ : Bank = 2 Row = 890, Col = 54, Data = 4f234d9e
|
# tb_core.u_sdram32 : at time 50593.0 ns READ : Bank = 2 Row = 890, Col = 54, Data = 4f234d9e
|
# READ STATUS: Burst-No: 32 Addr: 0037a896 Rxd: 472dfb8e
|
# READ STATUS: Burst-No: 32 Addr: 0037a896 Rxd: 472dfb8e
|
# tb_core.u_sdram32 : at time 49403.0 ns READ : Bank = 2 Row = 890, Col = 55, Data = 742819e8
|
# tb_core.u_sdram32 : at time 50603.0 ns READ : Bank = 2 Row = 890, Col = 55, Data = 742819e8
|
# READ STATUS: Burst-No: 33 Addr: 0037a898 Rxd: 4f234d9e
|
# READ STATUS: Burst-No: 33 Addr: 0037a898 Rxd: 4f234d9e
|
# tb_core.u_sdram32 : at time 49413.0 ns READ : Bank = 2 Row = 890, Col = 56, Data = 24839b49
|
# tb_core.u_sdram32 : at time 50613.0 ns READ : Bank = 2 Row = 890, Col = 56, Data = 24839b49
|
# READ STATUS: Burst-No: 34 Addr: 0037a89a Rxd: 742819e8
|
# READ STATUS: Burst-No: 34 Addr: 0037a89a Rxd: 742819e8
|
# tb_core.u_sdram32 : at time 49423.0 ns READ : Bank = 2 Row = 890, Col = 57, Data = 8569fa0a
|
# tb_core.u_sdram32 : at time 50623.0 ns READ : Bank = 2 Row = 890, Col = 57, Data = 8569fa0a
|
# READ STATUS: Burst-No: 35 Addr: 0037a89c Rxd: 24839b49
|
# READ STATUS: Burst-No: 35 Addr: 0037a89c Rxd: 24839b49
|
# tb_core.u_sdram32 : at time 49433.0 ns READ : Bank = 2 Row = 890, Col = 58, Data = 2fb81b5f
|
# tb_core.u_sdram32 : at time 50633.0 ns READ : Bank = 2 Row = 890, Col = 58, Data = 2fb81b5f
|
# READ STATUS: Burst-No: 36 Addr: 0037a89e Rxd: 8569fa0a
|
# READ STATUS: Burst-No: 36 Addr: 0037a89e Rxd: 8569fa0a
|
# tb_core.u_sdram32 : at time 49443.0 ns READ : Bank = 2 Row = 890, Col = 59, Data = a8bfc851
|
# tb_core.u_sdram32 : at time 50643.0 ns READ : Bank = 2 Row = 890, Col = 59, Data = a8bfc851
|
# READ STATUS: Burst-No: 37 Addr: 0037a8a0 Rxd: 2fb81b5f
|
# READ STATUS: Burst-No: 37 Addr: 0037a8a0 Rxd: 2fb81b5f
|
# tb_core.u_sdram32 : at time 49453.0 ns READ : Bank = 2 Row = 890, Col = 60, Data = a4d98649
|
# tb_core.u_sdram32 : at time 50653.0 ns READ : Bank = 2 Row = 890, Col = 60, Data = a4d98649
|
# READ STATUS: Burst-No: 38 Addr: 0037a8a2 Rxd: a8bfc851
|
# READ STATUS: Burst-No: 38 Addr: 0037a8a2 Rxd: a8bfc851
|
# tb_core.u_sdram32 : at time 49463.0 ns READ : Bank = 2 Row = 890, Col = 61, Data = 92fd2825
|
# tb_core.u_sdram32 : at time 50663.0 ns READ : Bank = 2 Row = 890, Col = 61, Data = 92fd2825
|
# READ STATUS: Burst-No: 39 Addr: 0037a8a4 Rxd: a4d98649
|
# READ STATUS: Burst-No: 39 Addr: 0037a8a4 Rxd: a4d98649
|
# tb_core.u_sdram32 : at time 49473.0 ns READ : Bank = 2 Row = 890, Col = 62, Data = b64ae66c
|
# tb_core.u_sdram32 : at time 50673.0 ns READ : Bank = 2 Row = 890, Col = 62, Data = b64ae66c
|
# READ STATUS: Burst-No: 40 Addr: 0037a8a6 Rxd: 92fd2825
|
# READ STATUS: Burst-No: 40 Addr: 0037a8a6 Rxd: 92fd2825
|
# tb_core.u_sdram32 : at time 49483.0 ns READ : Bank = 2 Row = 890, Col = 63, Data = ac509c58
|
# tb_core.u_sdram32 : at time 50683.0 ns READ : Bank = 2 Row = 890, Col = 63, Data = ac509c58
|
# tb_core.u_sdram32 : at time 49487.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 50687.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 41 Addr: 0037a8a8 Rxd: b64ae66c
|
# READ STATUS: Burst-No: 41 Addr: 0037a8a8 Rxd: b64ae66c
|
# tb_core.u_sdram32 : at time 49493.0 ns READ : Bank = 2 Row = 890, Col = 64, Data = af5d6c5e
|
# tb_core.u_sdram32 : at time 50693.0 ns READ : Bank = 2 Row = 890, Col = 64, Data = af5d6c5e
|
# READ STATUS: Burst-No: 42 Addr: 0037a8aa Rxd: ac509c58
|
# READ STATUS: Burst-No: 42 Addr: 0037a8aa Rxd: ac509c58
|
# tb_core.u_sdram32 : at time 49503.0 ns READ : Bank = 2 Row = 890, Col = 65, Data = 97dde22f
|
# tb_core.u_sdram32 : at time 50703.0 ns READ : Bank = 2 Row = 890, Col = 65, Data = 97dde22f
|
# READ STATUS: Burst-No: 43 Addr: 0037a8ac Rxd: af5d6c5e
|
# READ STATUS: Burst-No: 43 Addr: 0037a8ac Rxd: af5d6c5e
|
# READ STATUS: Burst-No: 44 Addr: 0037a8ae Rxd: 97dde22f
|
# READ STATUS: Burst-No: 44 Addr: 0037a8ae Rxd: 97dde22f
|
# tb_core.u_sdram32 : at time 49677.0 ns ACT : Bank = 2 Row = 245
|
# tb_core.u_sdram32 : at time 50877.0 ns ACT : Bank = 2 Row = 245
|
# tb_core.u_sdram32 : at time 49733.0 ns READ : Bank = 2 Row = 245, Col = 160, Data = 6a5ddbd4
|
# tb_core.u_sdram32 : at time 50933.0 ns READ : Bank = 2 Row = 245, Col = 160, Data = 6a5ddbd4
|
# tb_core.u_sdram32 : at time 49743.0 ns READ : Bank = 2 Row = 245, Col = 161, Data = ca0e4494
|
# tb_core.u_sdram32 : at time 50943.0 ns READ : Bank = 2 Row = 245, Col = 161, Data = ca0e4494
|
# READ STATUS: Burst-No: 0 Addr: 000f5a83 Rxd: 6a5ddbd4
|
# READ STATUS: Burst-No: 0 Addr: 000f5a83 Rxd: 6a5ddbd4
|
# tb_core.u_sdram32 : at time 49753.0 ns READ : Bank = 2 Row = 245, Col = 162, Data = c961e492
|
# tb_core.u_sdram32 : at time 50953.0 ns READ : Bank = 2 Row = 245, Col = 162, Data = c961e492
|
# READ STATUS: Burst-No: 1 Addr: 000f5a85 Rxd: ca0e4494
|
# READ STATUS: Burst-No: 1 Addr: 000f5a85 Rxd: ca0e4494
|
# tb_core.u_sdram32 : at time 49763.0 ns READ : Bank = 2 Row = 245, Col = 163, Data = 1e32673c
|
# tb_core.u_sdram32 : at time 50963.0 ns READ : Bank = 2 Row = 245, Col = 163, Data = 1e32673c
|
# READ STATUS: Burst-No: 2 Addr: 000f5a87 Rxd: c961e492
|
# READ STATUS: Burst-No: 2 Addr: 000f5a87 Rxd: c961e492
|
# tb_core.u_sdram32 : at time 49773.0 ns READ : Bank = 2 Row = 245, Col = 164, Data = 23301b46
|
# tb_core.u_sdram32 : at time 50973.0 ns READ : Bank = 2 Row = 245, Col = 164, Data = 23301b46
|
# READ STATUS: Burst-No: 3 Addr: 000f5a89 Rxd: 1e32673c
|
# READ STATUS: Burst-No: 3 Addr: 000f5a89 Rxd: 1e32673c
|
# tb_core.u_sdram32 : at time 49783.0 ns READ : Bank = 2 Row = 245, Col = 165, Data = b7b82a6f
|
# tb_core.u_sdram32 : at time 50983.0 ns READ : Bank = 2 Row = 245, Col = 165, Data = b7b82a6f
|
# READ STATUS: Burst-No: 4 Addr: 000f5a8b Rxd: 23301b46
|
# READ STATUS: Burst-No: 4 Addr: 000f5a8b Rxd: 23301b46
|
# tb_core.u_sdram32 : at time 49793.0 ns READ : Bank = 2 Row = 245, Col = 166, Data = a0b3ae41
|
# tb_core.u_sdram32 : at time 50993.0 ns READ : Bank = 2 Row = 245, Col = 166, Data = a0b3ae41
|
# READ STATUS: Burst-No: 5 Addr: 000f5a8d Rxd: b7b82a6f
|
# READ STATUS: Burst-No: 5 Addr: 000f5a8d Rxd: b7b82a6f
|
# tb_core.u_sdram32 : at time 49803.0 ns READ : Bank = 2 Row = 245, Col = 167, Data = 7bde15f7
|
# tb_core.u_sdram32 : at time 51003.0 ns READ : Bank = 2 Row = 245, Col = 167, Data = 7bde15f7
|
# READ STATUS: Burst-No: 6 Addr: 000f5a8f Rxd: a0b3ae41
|
# READ STATUS: Burst-No: 6 Addr: 000f5a8f Rxd: a0b3ae41
|
# tb_core.u_sdram32 : at time 49813.0 ns READ : Bank = 2 Row = 245, Col = 168, Data = 8b7c3816
|
# tb_core.u_sdram32 : at time 51013.0 ns READ : Bank = 2 Row = 245, Col = 168, Data = 8b7c3816
|
# READ STATUS: Burst-No: 7 Addr: 000f5a91 Rxd: 7bde15f7
|
# READ STATUS: Burst-No: 7 Addr: 000f5a91 Rxd: 7bde15f7
|
# tb_core.u_sdram32 : at time 49823.0 ns READ : Bank = 2 Row = 245, Col = 169, Data = 39092f72
|
# tb_core.u_sdram32 : at time 51023.0 ns READ : Bank = 2 Row = 245, Col = 169, Data = 39092f72
|
# READ STATUS: Burst-No: 8 Addr: 000f5a93 Rxd: 8b7c3816
|
# READ STATUS: Burst-No: 8 Addr: 000f5a93 Rxd: 8b7c3816
|
# tb_core.u_sdram32 : at time 49833.0 ns READ : Bank = 2 Row = 245, Col = 170, Data = 5136a5a2
|
# tb_core.u_sdram32 : at time 51033.0 ns READ : Bank = 2 Row = 245, Col = 170, Data = 5136a5a2
|
# READ STATUS: Burst-No: 9 Addr: 000f5a95 Rxd: 39092f72
|
# READ STATUS: Burst-No: 9 Addr: 000f5a95 Rxd: 39092f72
|
# tb_core.u_sdram32 : at time 49843.0 ns READ : Bank = 2 Row = 245, Col = 171, Data = 71f059e3
|
# tb_core.u_sdram32 : at time 51043.0 ns READ : Bank = 2 Row = 245, Col = 171, Data = 71f059e3
|
# READ STATUS: Burst-No: 10 Addr: 000f5a97 Rxd: 5136a5a2
|
# READ STATUS: Burst-No: 10 Addr: 000f5a97 Rxd: 5136a5a2
|
# tb_core.u_sdram32 : at time 49853.0 ns READ : Bank = 2 Row = 245, Col = 172, Data = c9490292
|
# tb_core.u_sdram32 : at time 51053.0 ns READ : Bank = 2 Row = 245, Col = 172, Data = c9490292
|
# READ STATUS: Burst-No: 11 Addr: 000f5a99 Rxd: 71f059e3
|
# READ STATUS: Burst-No: 11 Addr: 000f5a99 Rxd: 71f059e3
|
# tb_core.u_sdram32 : at time 49863.0 ns READ : Bank = 2 Row = 245, Col = 173, Data = e5ceb0cb
|
# tb_core.u_sdram32 : at time 51063.0 ns READ : Bank = 2 Row = 245, Col = 173, Data = e5ceb0cb
|
# READ STATUS: Burst-No: 12 Addr: 000f5a9b Rxd: c9490292
|
# READ STATUS: Burst-No: 12 Addr: 000f5a9b Rxd: c9490292
|
# tb_core.u_sdram32 : at time 49873.0 ns READ : Bank = 2 Row = 245, Col = 174, Data = 34097568
|
# tb_core.u_sdram32 : at time 51073.0 ns READ : Bank = 2 Row = 245, Col = 174, Data = 34097568
|
# READ STATUS: Burst-No: 13 Addr: 000f5a9d Rxd: e5ceb0cb
|
# READ STATUS: Burst-No: 13 Addr: 000f5a9d Rxd: e5ceb0cb
|
# tb_core.u_sdram32 : at time 49883.0 ns READ : Bank = 2 Row = 245, Col = 175, Data = 98b4ee31
|
# tb_core.u_sdram32 : at time 51083.0 ns READ : Bank = 2 Row = 245, Col = 175, Data = 98b4ee31
|
# READ STATUS: Burst-No: 14 Addr: 000f5a9f Rxd: 34097568
|
# READ STATUS: Burst-No: 14 Addr: 000f5a9f Rxd: 34097568
|
# tb_core.u_sdram32 : at time 49893.0 ns READ : Bank = 2 Row = 245, Col = 176, Data = 65c803cb
|
# tb_core.u_sdram32 : at time 51093.0 ns READ : Bank = 2 Row = 245, Col = 176, Data = 65c803cb
|
# READ STATUS: Burst-No: 15 Addr: 000f5aa1 Rxd: 98b4ee31
|
# READ STATUS: Burst-No: 15 Addr: 000f5aa1 Rxd: 98b4ee31
|
# tb_core.u_sdram32 : at time 49903.0 ns READ : Bank = 2 Row = 245, Col = 177, Data = aad1c855
|
# tb_core.u_sdram32 : at time 51103.0 ns READ : Bank = 2 Row = 245, Col = 177, Data = aad1c855
|
# READ STATUS: Burst-No: 16 Addr: 000f5aa3 Rxd: 65c803cb
|
# READ STATUS: Burst-No: 16 Addr: 000f5aa3 Rxd: 65c803cb
|
# tb_core.u_sdram32 : at time 49913.0 ns READ : Bank = 2 Row = 245, Col = 178, Data = 38a38971
|
# tb_core.u_sdram32 : at time 51113.0 ns READ : Bank = 2 Row = 245, Col = 178, Data = 38a38971
|
# READ STATUS: Burst-No: 17 Addr: 000f5aa5 Rxd: aad1c855
|
# READ STATUS: Burst-No: 17 Addr: 000f5aa5 Rxd: aad1c855
|
# tb_core.u_sdram32 : at time 49923.0 ns READ : Bank = 2 Row = 245, Col = 179, Data = 2f49535e
|
# tb_core.u_sdram32 : at time 51123.0 ns READ : Bank = 2 Row = 245, Col = 179, Data = 2f49535e
|
# READ STATUS: Burst-No: 18 Addr: 000f5aa7 Rxd: 38a38971
|
# READ STATUS: Burst-No: 18 Addr: 000f5aa7 Rxd: 38a38971
|
# tb_core.u_sdram32 : at time 49933.0 ns READ : Bank = 2 Row = 245, Col = 180, Data = e6e186cd
|
# tb_core.u_sdram32 : at time 51133.0 ns READ : Bank = 2 Row = 245, Col = 180, Data = e6e186cd
|
# READ STATUS: Burst-No: 19 Addr: 000f5aa9 Rxd: 2f49535e
|
# READ STATUS: Burst-No: 19 Addr: 000f5aa9 Rxd: 2f49535e
|
# tb_core.u_sdram32 : at time 49943.0 ns READ : Bank = 2 Row = 245, Col = 181, Data = daf356b5
|
# tb_core.u_sdram32 : at time 51143.0 ns READ : Bank = 2 Row = 245, Col = 181, Data = daf356b5
|
# READ STATUS: Burst-No: 20 Addr: 000f5aab Rxd: e6e186cd
|
# READ STATUS: Burst-No: 20 Addr: 000f5aab Rxd: e6e186cd
|
# tb_core.u_sdram32 : at time 49953.0 ns READ : Bank = 2 Row = 245, Col = 182, Data = 04410d08
|
# tb_core.u_sdram32 : at time 51153.0 ns READ : Bank = 2 Row = 245, Col = 182, Data = 04410d08
|
# READ STATUS: Burst-No: 21 Addr: 000f5aad Rxd: daf356b5
|
# READ STATUS: Burst-No: 21 Addr: 000f5aad Rxd: daf356b5
|
# tb_core.u_sdram32 : at time 49963.0 ns READ : Bank = 2 Row = 245, Col = 183, Data = c118be82
|
# tb_core.u_sdram32 : at time 51163.0 ns READ : Bank = 2 Row = 245, Col = 183, Data = c118be82
|
# READ STATUS: Burst-No: 22 Addr: 000f5aaf Rxd: 04410d08
|
# READ STATUS: Burst-No: 22 Addr: 000f5aaf Rxd: 04410d08
|
# tb_core.u_sdram32 : at time 49973.0 ns READ : Bank = 2 Row = 245, Col = 184, Data = 9f80983f
|
# tb_core.u_sdram32 : at time 51173.0 ns READ : Bank = 2 Row = 245, Col = 184, Data = 9f80983f
|
# READ STATUS: Burst-No: 23 Addr: 000f5ab1 Rxd: c118be82
|
# READ STATUS: Burst-No: 23 Addr: 000f5ab1 Rxd: c118be82
|
# tb_core.u_sdram32 : at time 49983.0 ns READ : Bank = 2 Row = 245, Col = 185, Data = d807f2b0
|
# tb_core.u_sdram32 : at time 51183.0 ns READ : Bank = 2 Row = 245, Col = 185, Data = d807f2b0
|
# READ STATUS: Burst-No: 24 Addr: 000f5ab3 Rxd: 9f80983f
|
# READ STATUS: Burst-No: 24 Addr: 000f5ab3 Rxd: 9f80983f
|
# tb_core.u_sdram32 : at time 49993.0 ns READ : Bank = 2 Row = 245, Col = 186, Data = 560eefac
|
# tb_core.u_sdram32 : at time 51193.0 ns READ : Bank = 2 Row = 245, Col = 186, Data = 560eefac
|
# READ STATUS: Burst-No: 25 Addr: 000f5ab5 Rxd: d807f2b0
|
# READ STATUS: Burst-No: 25 Addr: 000f5ab5 Rxd: d807f2b0
|
# tb_core.u_sdram32 : at time 50003.0 ns READ : Bank = 2 Row = 245, Col = 187, Data = 99183032
|
# tb_core.u_sdram32 : at time 51203.0 ns READ : Bank = 2 Row = 245, Col = 187, Data = 99183032
|
# READ STATUS: Burst-No: 26 Addr: 000f5ab7 Rxd: 560eefac
|
# READ STATUS: Burst-No: 26 Addr: 000f5ab7 Rxd: 560eefac
|
# tb_core.u_sdram32 : at time 50013.0 ns READ : Bank = 2 Row = 245, Col = 188, Data = 029f0505
|
# tb_core.u_sdram32 : at time 51213.0 ns READ : Bank = 2 Row = 245, Col = 188, Data = 029f0505
|
# READ STATUS: Burst-No: 27 Addr: 000f5ab9 Rxd: 99183032
|
# READ STATUS: Burst-No: 27 Addr: 000f5ab9 Rxd: 99183032
|
# tb_core.u_sdram32 : at time 50023.0 ns READ : Bank = 2 Row = 245, Col = 189, Data = 2f73fb5e
|
# tb_core.u_sdram32 : at time 51223.0 ns READ : Bank = 2 Row = 245, Col = 189, Data = 2f73fb5e
|
# READ STATUS: Burst-No: 28 Addr: 000f5abb Rxd: 029f0505
|
# READ STATUS: Burst-No: 28 Addr: 000f5abb Rxd: 029f0505
|
# tb_core.u_sdram32 : at time 50033.0 ns READ : Bank = 2 Row = 245, Col = 190, Data = dc16d8b8
|
# tb_core.u_sdram32 : at time 51233.0 ns READ : Bank = 2 Row = 245, Col = 190, Data = dc16d8b8
|
# READ STATUS: Burst-No: 29 Addr: 000f5abd Rxd: 2f73fb5e
|
# READ STATUS: Burst-No: 29 Addr: 000f5abd Rxd: 2f73fb5e
|
# tb_core.u_sdram32 : at time 50043.0 ns READ : Bank = 2 Row = 245, Col = 191, Data = 3ec2677d
|
# tb_core.u_sdram32 : at time 51243.0 ns READ : Bank = 2 Row = 245, Col = 191, Data = 3ec2677d
|
# READ STATUS: Burst-No: 30 Addr: 000f5abf Rxd: dc16d8b8
|
# READ STATUS: Burst-No: 30 Addr: 000f5abf Rxd: dc16d8b8
|
# tb_core.u_sdram32 : at time 50053.0 ns READ : Bank = 2 Row = 245, Col = 192, Data = 8511580a
|
# tb_core.u_sdram32 : at time 51253.0 ns READ : Bank = 2 Row = 245, Col = 192, Data = 8511580a
|
# READ STATUS: Burst-No: 31 Addr: 000f5ac1 Rxd: 3ec2677d
|
# READ STATUS: Burst-No: 31 Addr: 000f5ac1 Rxd: 3ec2677d
|
# tb_core.u_sdram32 : at time 50063.0 ns READ : Bank = 2 Row = 245, Col = 193, Data = c6878a8d
|
# tb_core.u_sdram32 : at time 51263.0 ns READ : Bank = 2 Row = 245, Col = 193, Data = c6878a8d
|
# READ STATUS: Burst-No: 32 Addr: 000f5ac3 Rxd: 8511580a
|
# READ STATUS: Burst-No: 32 Addr: 000f5ac3 Rxd: 8511580a
|
# tb_core.u_sdram32 : at time 50073.0 ns READ : Bank = 2 Row = 245, Col = 194, Data = 64eb39c9
|
# tb_core.u_sdram32 : at time 51273.0 ns READ : Bank = 2 Row = 245, Col = 194, Data = 64eb39c9
|
# READ STATUS: Burst-No: 33 Addr: 000f5ac5 Rxd: c6878a8d
|
# READ STATUS: Burst-No: 33 Addr: 000f5ac5 Rxd: c6878a8d
|
# tb_core.u_sdram32 : at time 50083.0 ns READ : Bank = 2 Row = 245, Col = 195, Data = f8d3d8f1
|
# tb_core.u_sdram32 : at time 51283.0 ns READ : Bank = 2 Row = 245, Col = 195, Data = f8d3d8f1
|
# READ STATUS: Burst-No: 34 Addr: 000f5ac7 Rxd: 64eb39c9
|
# READ STATUS: Burst-No: 34 Addr: 000f5ac7 Rxd: 64eb39c9
|
# tb_core.u_sdram32 : at time 50093.0 ns READ : Bank = 2 Row = 245, Col = 196, Data = da12deb4
|
# tb_core.u_sdram32 : at time 51293.0 ns READ : Bank = 2 Row = 245, Col = 196, Data = da12deb4
|
# READ STATUS: Burst-No: 35 Addr: 000f5ac9 Rxd: f8d3d8f1
|
# READ STATUS: Burst-No: 35 Addr: 000f5ac9 Rxd: f8d3d8f1
|
# tb_core.u_sdram32 : at time 50103.0 ns READ : Bank = 2 Row = 245, Col = 197, Data = 729a7fe5
|
# tb_core.u_sdram32 : at time 51303.0 ns READ : Bank = 2 Row = 245, Col = 197, Data = 729a7fe5
|
# tb_core.u_sdram32 : at time 50107.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 51307.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 36 Addr: 000f5acb Rxd: da12deb4
|
# READ STATUS: Burst-No: 36 Addr: 000f5acb Rxd: da12deb4
|
# tb_core.u_sdram32 : at time 50113.0 ns READ : Bank = 2 Row = 245, Col = 198, Data = 1a133934
|
# tb_core.u_sdram32 : at time 51313.0 ns READ : Bank = 2 Row = 245, Col = 198, Data = 1a133934
|
# READ STATUS: Burst-No: 37 Addr: 000f5acd Rxd: 729a7fe5
|
# READ STATUS: Burst-No: 37 Addr: 000f5acd Rxd: 729a7fe5
|
# tb_core.u_sdram32 : at time 50123.0 ns READ : Bank = 2 Row = 245, Col = 199, Data = 11c6c523
|
# tb_core.u_sdram32 : at time 51323.0 ns READ : Bank = 2 Row = 245, Col = 199, Data = 11c6c523
|
# READ STATUS: Burst-No: 38 Addr: 000f5acf Rxd: 1a133934
|
# READ STATUS: Burst-No: 38 Addr: 000f5acf Rxd: 1a133934
|
# READ STATUS: Burst-No: 39 Addr: 000f5ad1 Rxd: 11c6c523
|
# READ STATUS: Burst-No: 39 Addr: 000f5ad1 Rxd: 11c6c523
|
# Write Address: 0011a32d, Burst Size: 50
|
# Write Address: 0011a32d, Burst Size: 50
|
# tb_core.u_sdram32 : at time 50297.0 ns ACT : Bank = 0 Row = 282
|
# tb_core.u_sdram32 : at time 51497.0 ns ACT : Bank = 0 Row = 282
|
# tb_core.u_sdram32 : at time 50327.0 ns WRITE: Bank = 0 Row = 282, Col = 203, Data = 2f36c55e
|
# tb_core.u_sdram32 : at time 51527.0 ns WRITE: Bank = 0 Row = 282, Col = 203, Data = 2f36c55e
|
# Status: Burst-No: 0 Write Address: 0011a32d WriteData: 2f36c55e
|
# Status: Burst-No: 0 Write Address: 0011a32d WriteData: 2f36c55e
|
# tb_core.u_sdram32 : at time 50337.0 ns WRITE: Bank = 0 Row = 282, Col = 204, Data = 5a0f27b4
|
# tb_core.u_sdram32 : at time 51537.0 ns WRITE: Bank = 0 Row = 282, Col = 204, Data = 5a0f27b4
|
# Status: Burst-No: 1 Write Address: 0011a32d WriteData: 5a0f27b4
|
# Status: Burst-No: 1 Write Address: 0011a32d WriteData: 5a0f27b4
|
# tb_core.u_sdram32 : at time 50347.0 ns WRITE: Bank = 0 Row = 282, Col = 205, Data = 073a730e
|
# tb_core.u_sdram32 : at time 51547.0 ns WRITE: Bank = 0 Row = 282, Col = 205, Data = 073a730e
|
# Status: Burst-No: 2 Write Address: 0011a32d WriteData: 073a730e
|
# Status: Burst-No: 2 Write Address: 0011a32d WriteData: 073a730e
|
# tb_core.u_sdram32 : at time 50357.0 ns WRITE: Bank = 0 Row = 282, Col = 206, Data = 322cc164
|
# tb_core.u_sdram32 : at time 51557.0 ns WRITE: Bank = 0 Row = 282, Col = 206, Data = 322cc164
|
# Status: Burst-No: 3 Write Address: 0011a32d WriteData: 322cc164
|
# Status: Burst-No: 3 Write Address: 0011a32d WriteData: 322cc164
|
# tb_core.u_sdram32 : at time 50367.0 ns WRITE: Bank = 0 Row = 282, Col = 207, Data = 320a8b64
|
# tb_core.u_sdram32 : at time 51567.0 ns WRITE: Bank = 0 Row = 282, Col = 207, Data = 320a8b64
|
# Status: Burst-No: 4 Write Address: 0011a32d WriteData: 320a8b64
|
# Status: Burst-No: 4 Write Address: 0011a32d WriteData: 320a8b64
|
# tb_core.u_sdram32 : at time 50377.0 ns WRITE: Bank = 0 Row = 282, Col = 208, Data = 2416b948
|
# tb_core.u_sdram32 : at time 51577.0 ns WRITE: Bank = 0 Row = 282, Col = 208, Data = 2416b948
|
# Status: Burst-No: 5 Write Address: 0011a32d WriteData: 2416b948
|
# Status: Burst-No: 5 Write Address: 0011a32d WriteData: 2416b948
|
# tb_core.u_sdram32 : at time 50387.0 ns WRITE: Bank = 0 Row = 282, Col = 209, Data = c544d88a
|
# tb_core.u_sdram32 : at time 51587.0 ns WRITE: Bank = 0 Row = 282, Col = 209, Data = c544d88a
|
# Status: Burst-No: 6 Write Address: 0011a32d WriteData: c544d88a
|
# Status: Burst-No: 6 Write Address: 0011a32d WriteData: c544d88a
|
# tb_core.u_sdram32 : at time 50397.0 ns WRITE: Bank = 0 Row = 282, Col = 210, Data = 4dfe879b
|
# tb_core.u_sdram32 : at time 51597.0 ns WRITE: Bank = 0 Row = 282, Col = 210, Data = 4dfe879b
|
# Status: Burst-No: 7 Write Address: 0011a32d WriteData: 4dfe879b
|
# Status: Burst-No: 7 Write Address: 0011a32d WriteData: 4dfe879b
|
# tb_core.u_sdram32 : at time 50407.0 ns WRITE: Bank = 0 Row = 282, Col = 211, Data = e6fbf4cd
|
# tb_core.u_sdram32 : at time 51607.0 ns WRITE: Bank = 0 Row = 282, Col = 211, Data = e6fbf4cd
|
# Status: Burst-No: 8 Write Address: 0011a32d WriteData: e6fbf4cd
|
# Status: Burst-No: 8 Write Address: 0011a32d WriteData: e6fbf4cd
|
# tb_core.u_sdram32 : at time 50417.0 ns WRITE: Bank = 0 Row = 282, Col = 212, Data = b5f8fa6b
|
# tb_core.u_sdram32 : at time 51617.0 ns WRITE: Bank = 0 Row = 282, Col = 212, Data = b5f8fa6b
|
# Status: Burst-No: 9 Write Address: 0011a32d WriteData: b5f8fa6b
|
# Status: Burst-No: 9 Write Address: 0011a32d WriteData: b5f8fa6b
|
# tb_core.u_sdram32 : at time 50427.0 ns WRITE: Bank = 0 Row = 282, Col = 213, Data = 55ff23ab
|
# tb_core.u_sdram32 : at time 51627.0 ns WRITE: Bank = 0 Row = 282, Col = 213, Data = 55ff23ab
|
# Status: Burst-No: 10 Write Address: 0011a32d WriteData: 55ff23ab
|
# Status: Burst-No: 10 Write Address: 0011a32d WriteData: 55ff23ab
|
# tb_core.u_sdram32 : at time 50437.0 ns WRITE: Bank = 0 Row = 282, Col = 214, Data = f1eca2e3
|
# tb_core.u_sdram32 : at time 51637.0 ns WRITE: Bank = 0 Row = 282, Col = 214, Data = f1eca2e3
|
# Status: Burst-No: 11 Write Address: 0011a32d WriteData: f1eca2e3
|
# Status: Burst-No: 11 Write Address: 0011a32d WriteData: f1eca2e3
|
# tb_core.u_sdram32 : at time 50447.0 ns WRITE: Bank = 0 Row = 282, Col = 215, Data = 5e9d2fbd
|
# tb_core.u_sdram32 : at time 51647.0 ns WRITE: Bank = 0 Row = 282, Col = 215, Data = 5e9d2fbd
|
# Status: Burst-No: 12 Write Address: 0011a32d WriteData: 5e9d2fbd
|
# Status: Burst-No: 12 Write Address: 0011a32d WriteData: 5e9d2fbd
|
# tb_core.u_sdram32 : at time 50457.0 ns WRITE: Bank = 0 Row = 282, Col = 216, Data = ecff24d9
|
# tb_core.u_sdram32 : at time 51657.0 ns WRITE: Bank = 0 Row = 282, Col = 216, Data = ecff24d9
|
# Status: Burst-No: 13 Write Address: 0011a32d WriteData: ecff24d9
|
# Status: Burst-No: 13 Write Address: 0011a32d WriteData: ecff24d9
|
# tb_core.u_sdram32 : at time 50467.0 ns WRITE: Bank = 0 Row = 282, Col = 217, Data = e11a58c2
|
# tb_core.u_sdram32 : at time 51667.0 ns WRITE: Bank = 0 Row = 282, Col = 217, Data = e11a58c2
|
# Status: Burst-No: 14 Write Address: 0011a32d WriteData: e11a58c2
|
# Status: Burst-No: 14 Write Address: 0011a32d WriteData: e11a58c2
|
# tb_core.u_sdram32 : at time 50477.0 ns WRITE: Bank = 0 Row = 282, Col = 218, Data = f059ace0
|
# tb_core.u_sdram32 : at time 51677.0 ns WRITE: Bank = 0 Row = 282, Col = 218, Data = f059ace0
|
# Status: Burst-No: 15 Write Address: 0011a32d WriteData: f059ace0
|
# Status: Burst-No: 15 Write Address: 0011a32d WriteData: f059ace0
|
# tb_core.u_sdram32 : at time 50487.0 ns WRITE: Bank = 0 Row = 282, Col = 219, Data = afd1265f
|
# tb_core.u_sdram32 : at time 51687.0 ns WRITE: Bank = 0 Row = 282, Col = 219, Data = afd1265f
|
# Status: Burst-No: 16 Write Address: 0011a32d WriteData: afd1265f
|
# Status: Burst-No: 16 Write Address: 0011a32d WriteData: afd1265f
|
# tb_core.u_sdram32 : at time 50497.0 ns WRITE: Bank = 0 Row = 282, Col = 220, Data = 8edc361d
|
# tb_core.u_sdram32 : at time 51697.0 ns WRITE: Bank = 0 Row = 282, Col = 220, Data = 8edc361d
|
# Status: Burst-No: 17 Write Address: 0011a32d WriteData: 8edc361d
|
# Status: Burst-No: 17 Write Address: 0011a32d WriteData: 8edc361d
|
# tb_core.u_sdram32 : at time 50507.0 ns WRITE: Bank = 0 Row = 282, Col = 221, Data = c9b64c93
|
# tb_core.u_sdram32 : at time 51707.0 ns WRITE: Bank = 0 Row = 282, Col = 221, Data = c9b64c93
|
# Status: Burst-No: 18 Write Address: 0011a32d WriteData: c9b64c93
|
# Status: Burst-No: 18 Write Address: 0011a32d WriteData: c9b64c93
|
# tb_core.u_sdram32 : at time 50517.0 ns WRITE: Bank = 0 Row = 282, Col = 222, Data = 13180326
|
# tb_core.u_sdram32 : at time 51717.0 ns WRITE: Bank = 0 Row = 282, Col = 222, Data = 13180326
|
# Status: Burst-No: 19 Write Address: 0011a32d WriteData: 13180326
|
# Status: Burst-No: 19 Write Address: 0011a32d WriteData: 13180326
|
# tb_core.u_sdram32 : at time 50527.0 ns WRITE: Bank = 0 Row = 282, Col = 223, Data = 82b78605
|
# tb_core.u_sdram32 : at time 51727.0 ns WRITE: Bank = 0 Row = 282, Col = 223, Data = 82b78605
|
# Status: Burst-No: 20 Write Address: 0011a32d WriteData: 82b78605
|
# Status: Burst-No: 20 Write Address: 0011a32d WriteData: 82b78605
|
# tb_core.u_sdram32 : at time 50537.0 ns WRITE: Bank = 0 Row = 282, Col = 224, Data = 84a8e809
|
# tb_core.u_sdram32 : at time 51737.0 ns WRITE: Bank = 0 Row = 282, Col = 224, Data = 84a8e809
|
# Status: Burst-No: 21 Write Address: 0011a32d WriteData: 84a8e809
|
# Status: Burst-No: 21 Write Address: 0011a32d WriteData: 84a8e809
|
# tb_core.u_sdram32 : at time 50547.0 ns WRITE: Bank = 0 Row = 282, Col = 225, Data = b62d846c
|
# tb_core.u_sdram32 : at time 51747.0 ns WRITE: Bank = 0 Row = 282, Col = 225, Data = b62d846c
|
# Status: Burst-No: 22 Write Address: 0011a32d WriteData: b62d846c
|
# Status: Burst-No: 22 Write Address: 0011a32d WriteData: b62d846c
|
# tb_core.u_sdram32 : at time 50557.0 ns WRITE: Bank = 0 Row = 282, Col = 226, Data = b5c5c06b
|
# tb_core.u_sdram32 : at time 51757.0 ns WRITE: Bank = 0 Row = 282, Col = 226, Data = b5c5c06b
|
# Status: Burst-No: 23 Write Address: 0011a32d WriteData: b5c5c06b
|
# Status: Burst-No: 23 Write Address: 0011a32d WriteData: b5c5c06b
|
# tb_core.u_sdram32 : at time 50567.0 ns WRITE: Bank = 0 Row = 282, Col = 227, Data = 5858bdb0
|
# tb_core.u_sdram32 : at time 51767.0 ns WRITE: Bank = 0 Row = 282, Col = 227, Data = 5858bdb0
|
# Status: Burst-No: 24 Write Address: 0011a32d WriteData: 5858bdb0
|
# Status: Burst-No: 24 Write Address: 0011a32d WriteData: 5858bdb0
|
# tb_core.u_sdram32 : at time 50577.0 ns WRITE: Bank = 0 Row = 282, Col = 228, Data = fb9fb8f7
|
# tb_core.u_sdram32 : at time 51777.0 ns WRITE: Bank = 0 Row = 282, Col = 228, Data = fb9fb8f7
|
# Status: Burst-No: 25 Write Address: 0011a32d WriteData: fb9fb8f7
|
# Status: Burst-No: 25 Write Address: 0011a32d WriteData: fb9fb8f7
|
# tb_core.u_sdram32 : at time 50587.0 ns WRITE: Bank = 0 Row = 282, Col = 229, Data = 52a151a5
|
# tb_core.u_sdram32 : at time 51787.0 ns WRITE: Bank = 0 Row = 282, Col = 229, Data = 52a151a5
|
# Status: Burst-No: 26 Write Address: 0011a32d WriteData: 52a151a5
|
# Status: Burst-No: 26 Write Address: 0011a32d WriteData: 52a151a5
|
# tb_core.u_sdram32 : at time 50597.0 ns WRITE: Bank = 0 Row = 282, Col = 230, Data = abe8c057
|
# tb_core.u_sdram32 : at time 51797.0 ns WRITE: Bank = 0 Row = 282, Col = 230, Data = abe8c057
|
# Status: Burst-No: 27 Write Address: 0011a32d WriteData: abe8c057
|
# Status: Burst-No: 27 Write Address: 0011a32d WriteData: abe8c057
|
# tb_core.u_sdram32 : at time 50607.0 ns WRITE: Bank = 0 Row = 282, Col = 231, Data = 3b11f376
|
# tb_core.u_sdram32 : at time 51807.0 ns WRITE: Bank = 0 Row = 282, Col = 231, Data = 3b11f376
|
# Status: Burst-No: 28 Write Address: 0011a32d WriteData: 3b11f376
|
# Status: Burst-No: 28 Write Address: 0011a32d WriteData: 3b11f376
|
# tb_core.u_sdram32 : at time 50617.0 ns WRITE: Bank = 0 Row = 282, Col = 232, Data = 2798e34f
|
# tb_core.u_sdram32 : at time 51817.0 ns WRITE: Bank = 0 Row = 282, Col = 232, Data = 2798e34f
|
# Status: Burst-No: 29 Write Address: 0011a32d WriteData: 2798e34f
|
# Status: Burst-No: 29 Write Address: 0011a32d WriteData: 2798e34f
|
# tb_core.u_sdram32 : at time 50627.0 ns WRITE: Bank = 0 Row = 282, Col = 233, Data = 5a45bdb4
|
# tb_core.u_sdram32 : at time 51827.0 ns WRITE: Bank = 0 Row = 282, Col = 233, Data = 5a45bdb4
|
# Status: Burst-No: 30 Write Address: 0011a32d WriteData: 5a45bdb4
|
# Status: Burst-No: 30 Write Address: 0011a32d WriteData: 5a45bdb4
|
# tb_core.u_sdram32 : at time 50637.0 ns WRITE: Bank = 0 Row = 282, Col = 234, Data = 8ecaa21d
|
# tb_core.u_sdram32 : at time 51837.0 ns WRITE: Bank = 0 Row = 282, Col = 234, Data = 8ecaa21d
|
# Status: Burst-No: 31 Write Address: 0011a32d WriteData: 8ecaa21d
|
# Status: Burst-No: 31 Write Address: 0011a32d WriteData: 8ecaa21d
|
# tb_core.u_sdram32 : at time 50647.0 ns WRITE: Bank = 0 Row = 282, Col = 235, Data = 43c11587
|
# tb_core.u_sdram32 : at time 51847.0 ns WRITE: Bank = 0 Row = 282, Col = 235, Data = 43c11587
|
# Status: Burst-No: 32 Write Address: 0011a32d WriteData: 43c11587
|
# Status: Burst-No: 32 Write Address: 0011a32d WriteData: 43c11587
|
# tb_core.u_sdram32 : at time 50657.0 ns WRITE: Bank = 0 Row = 282, Col = 236, Data = 23466346
|
# tb_core.u_sdram32 : at time 51857.0 ns WRITE: Bank = 0 Row = 282, Col = 236, Data = 23466346
|
# Status: Burst-No: 33 Write Address: 0011a32d WriteData: 23466346
|
# Status: Burst-No: 33 Write Address: 0011a32d WriteData: 23466346
|
# tb_core.u_sdram32 : at time 50667.0 ns WRITE: Bank = 0 Row = 282, Col = 237, Data = 336d9366
|
# tb_core.u_sdram32 : at time 51867.0 ns WRITE: Bank = 0 Row = 282, Col = 237, Data = 336d9366
|
# Status: Burst-No: 34 Write Address: 0011a32d WriteData: 336d9366
|
# Status: Burst-No: 34 Write Address: 0011a32d WriteData: 336d9366
|
# tb_core.u_sdram32 : at time 50677.0 ns WRITE: Bank = 0 Row = 282, Col = 238, Data = 4f14c19e
|
# tb_core.u_sdram32 : at time 51877.0 ns WRITE: Bank = 0 Row = 282, Col = 238, Data = 4f14c19e
|
# Status: Burst-No: 35 Write Address: 0011a32d WriteData: 4f14c19e
|
# Status: Burst-No: 35 Write Address: 0011a32d WriteData: 4f14c19e
|
# tb_core.u_sdram32 : at time 50687.0 ns WRITE: Bank = 0 Row = 282, Col = 239, Data = 1fb0d13f
|
# tb_core.u_sdram32 : at time 51887.0 ns WRITE: Bank = 0 Row = 282, Col = 239, Data = 1fb0d13f
|
# Status: Burst-No: 36 Write Address: 0011a32d WriteData: 1fb0d13f
|
# Status: Burst-No: 36 Write Address: 0011a32d WriteData: 1fb0d13f
|
# tb_core.u_sdram32 : at time 50697.0 ns WRITE: Bank = 0 Row = 282, Col = 240, Data = 2a2ff554
|
# tb_core.u_sdram32 : at time 51897.0 ns WRITE: Bank = 0 Row = 282, Col = 240, Data = 2a2ff554
|
# Status: Burst-No: 37 Write Address: 0011a32d WriteData: 2a2ff554
|
# Status: Burst-No: 37 Write Address: 0011a32d WriteData: 2a2ff554
|
# tb_core.u_sdram32 : at time 50707.0 ns WRITE: Bank = 0 Row = 282, Col = 241, Data = 2a565f54
|
# tb_core.u_sdram32 : at time 51907.0 ns WRITE: Bank = 0 Row = 282, Col = 241, Data = 2a565f54
|
# Status: Burst-No: 38 Write Address: 0011a32d WriteData: 2a565f54
|
# Status: Burst-No: 38 Write Address: 0011a32d WriteData: 2a565f54
|
# tb_core.u_sdram32 : at time 50717.0 ns WRITE: Bank = 0 Row = 282, Col = 242, Data = a62c344c
|
# tb_core.u_sdram32 : at time 51917.0 ns WRITE: Bank = 0 Row = 282, Col = 242, Data = a62c344c
|
# Status: Burst-No: 39 Write Address: 0011a32d WriteData: a62c344c
|
# Status: Burst-No: 39 Write Address: 0011a32d WriteData: a62c344c
|
# tb_core.u_sdram32 : at time 50727.0 ns WRITE: Bank = 0 Row = 282, Col = 243, Data = 83449006
|
# tb_core.u_sdram32 : at time 51927.0 ns WRITE: Bank = 0 Row = 282, Col = 243, Data = 83449006
|
# Status: Burst-No: 40 Write Address: 0011a32d WriteData: 83449006
|
# Status: Burst-No: 40 Write Address: 0011a32d WriteData: 83449006
|
# tb_core.u_sdram32 : at time 50737.0 ns WRITE: Bank = 0 Row = 282, Col = 244, Data = 286f1350
|
# tb_core.u_sdram32 : at time 51937.0 ns WRITE: Bank = 0 Row = 282, Col = 244, Data = 286f1350
|
# Status: Burst-No: 41 Write Address: 0011a32d WriteData: 286f1350
|
# Status: Burst-No: 41 Write Address: 0011a32d WriteData: 286f1350
|
# tb_core.u_sdram32 : at time 50747.0 ns WRITE: Bank = 0 Row = 282, Col = 245, Data = 16b46d2d
|
# tb_core.u_sdram32 : at time 51947.0 ns WRITE: Bank = 0 Row = 282, Col = 245, Data = 16b46d2d
|
# Status: Burst-No: 42 Write Address: 0011a32d WriteData: 16b46d2d
|
# Status: Burst-No: 42 Write Address: 0011a32d WriteData: 16b46d2d
|
# tb_core.u_sdram32 : at time 50757.0 ns WRITE: Bank = 0 Row = 282, Col = 246, Data = c34ddc86
|
# tb_core.u_sdram32 : at time 51957.0 ns WRITE: Bank = 0 Row = 282, Col = 246, Data = c34ddc86
|
# Status: Burst-No: 43 Write Address: 0011a32d WriteData: c34ddc86
|
# Status: Burst-No: 43 Write Address: 0011a32d WriteData: c34ddc86
|
# tb_core.u_sdram32 : at time 50767.0 ns WRITE: Bank = 0 Row = 282, Col = 247, Data = 3564836a
|
# tb_core.u_sdram32 : at time 51967.0 ns WRITE: Bank = 0 Row = 282, Col = 247, Data = 3564836a
|
# Status: Burst-No: 44 Write Address: 0011a32d WriteData: 3564836a
|
# Status: Burst-No: 44 Write Address: 0011a32d WriteData: 3564836a
|
# tb_core.u_sdram32 : at time 50777.0 ns WRITE: Bank = 0 Row = 282, Col = 248, Data = 5c2afdb8
|
# tb_core.u_sdram32 : at time 51977.0 ns WRITE: Bank = 0 Row = 282, Col = 248, Data = 5c2afdb8
|
# Status: Burst-No: 45 Write Address: 0011a32d WriteData: 5c2afdb8
|
# Status: Burst-No: 45 Write Address: 0011a32d WriteData: 5c2afdb8
|
# tb_core.u_sdram32 : at time 50787.0 ns WRITE: Bank = 0 Row = 282, Col = 249, Data = f7fecaef
|
# tb_core.u_sdram32 : at time 51987.0 ns WRITE: Bank = 0 Row = 282, Col = 249, Data = f7fecaef
|
# Status: Burst-No: 46 Write Address: 0011a32d WriteData: f7fecaef
|
# Status: Burst-No: 46 Write Address: 0011a32d WriteData: f7fecaef
|
# tb_core.u_sdram32 : at time 50797.0 ns WRITE: Bank = 0 Row = 282, Col = 250, Data = 506a57a0
|
# tb_core.u_sdram32 : at time 51997.0 ns WRITE: Bank = 0 Row = 282, Col = 250, Data = 506a57a0
|
# Status: Burst-No: 47 Write Address: 0011a32d WriteData: 506a57a0
|
# Status: Burst-No: 47 Write Address: 0011a32d WriteData: 506a57a0
|
# tb_core.u_sdram32 : at time 50807.0 ns WRITE: Bank = 0 Row = 282, Col = 251, Data = 1fa98f3f
|
# tb_core.u_sdram32 : at time 52007.0 ns WRITE: Bank = 0 Row = 282, Col = 251, Data = 1fa98f3f
|
# Status: Burst-No: 48 Write Address: 0011a32d WriteData: 1fa98f3f
|
# Status: Burst-No: 48 Write Address: 0011a32d WriteData: 1fa98f3f
|
# tb_core.u_sdram32 : at time 50817.0 ns WRITE: Bank = 0 Row = 282, Col = 252, Data = 84d4aa09
|
# tb_core.u_sdram32 : at time 52017.0 ns WRITE: Bank = 0 Row = 282, Col = 252, Data = 84d4aa09
|
# Status: Burst-No: 49 Write Address: 0011a32d WriteData: 84d4aa09
|
# Status: Burst-No: 49 Write Address: 0011a32d WriteData: 84d4aa09
|
# tb_core.u_sdram32 : at time 50827.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 52027.0 ns BST : Burst Terminate
|
# Write Address: 003b42a8, Burst Size: 22
|
# Write Address: 003b42a8, Burst Size: 22
|
# tb_core.u_sdram32 : at time 50967.0 ns ACT : Bank = 0 Row = 948
|
# tb_core.u_sdram32 : at time 52167.0 ns ACT : Bank = 0 Row = 948
|
# tb_core.u_sdram32 : at time 50997.0 ns WRITE: Bank = 0 Row = 948, Col = 170, Data = 8f49661e
|
# tb_core.u_sdram32 : at time 52197.0 ns WRITE: Bank = 0 Row = 948, Col = 170, Data = 8f49661e
|
# Status: Burst-No: 0 Write Address: 003b42a8 WriteData: 8f49661e
|
# Status: Burst-No: 0 Write Address: 003b42a8 WriteData: 8f49661e
|
# tb_core.u_sdram32 : at time 51007.0 ns WRITE: Bank = 0 Row = 948, Col = 171, Data = dc22dcb8
|
# tb_core.u_sdram32 : at time 52207.0 ns WRITE: Bank = 0 Row = 948, Col = 171, Data = dc22dcb8
|
# Status: Burst-No: 1 Write Address: 003b42a8 WriteData: dc22dcb8
|
# Status: Burst-No: 1 Write Address: 003b42a8 WriteData: dc22dcb8
|
# tb_core.u_sdram32 : at time 51017.0 ns WRITE: Bank = 0 Row = 948, Col = 172, Data = e70a62ce
|
# tb_core.u_sdram32 : at time 52217.0 ns WRITE: Bank = 0 Row = 948, Col = 172, Data = e70a62ce
|
# Status: Burst-No: 2 Write Address: 003b42a8 WriteData: e70a62ce
|
# Status: Burst-No: 2 Write Address: 003b42a8 WriteData: e70a62ce
|
# tb_core.u_sdram32 : at time 51027.0 ns WRITE: Bank = 0 Row = 948, Col = 173, Data = eb40e6d6
|
# tb_core.u_sdram32 : at time 52227.0 ns WRITE: Bank = 0 Row = 948, Col = 173, Data = eb40e6d6
|
# Status: Burst-No: 3 Write Address: 003b42a8 WriteData: eb40e6d6
|
# Status: Burst-No: 3 Write Address: 003b42a8 WriteData: eb40e6d6
|
# tb_core.u_sdram32 : at time 51037.0 ns WRITE: Bank = 0 Row = 948, Col = 174, Data = 92c27025
|
# tb_core.u_sdram32 : at time 52237.0 ns WRITE: Bank = 0 Row = 948, Col = 174, Data = 92c27025
|
# Status: Burst-No: 4 Write Address: 003b42a8 WriteData: 92c27025
|
# Status: Burst-No: 4 Write Address: 003b42a8 WriteData: 92c27025
|
# tb_core.u_sdram32 : at time 51047.0 ns WRITE: Bank = 0 Row = 948, Col = 175, Data = d4ce0aa9
|
# tb_core.u_sdram32 : at time 52247.0 ns WRITE: Bank = 0 Row = 948, Col = 175, Data = d4ce0aa9
|
# Status: Burst-No: 5 Write Address: 003b42a8 WriteData: d4ce0aa9
|
# Status: Burst-No: 5 Write Address: 003b42a8 WriteData: d4ce0aa9
|
# tb_core.u_sdram32 : at time 51057.0 ns WRITE: Bank = 0 Row = 948, Col = 176, Data = e7b374cf
|
# tb_core.u_sdram32 : at time 52257.0 ns WRITE: Bank = 0 Row = 948, Col = 176, Data = e7b374cf
|
# Status: Burst-No: 6 Write Address: 003b42a8 WriteData: e7b374cf
|
# Status: Burst-No: 6 Write Address: 003b42a8 WriteData: e7b374cf
|
# tb_core.u_sdram32 : at time 51067.0 ns WRITE: Bank = 0 Row = 948, Col = 177, Data = 1a9af535
|
# tb_core.u_sdram32 : at time 52267.0 ns WRITE: Bank = 0 Row = 948, Col = 177, Data = 1a9af535
|
# Status: Burst-No: 7 Write Address: 003b42a8 WriteData: 1a9af535
|
# Status: Burst-No: 7 Write Address: 003b42a8 WriteData: 1a9af535
|
# tb_core.u_sdram32 : at time 51077.0 ns WRITE: Bank = 0 Row = 948, Col = 178, Data = 2047dd40
|
# tb_core.u_sdram32 : at time 52277.0 ns WRITE: Bank = 0 Row = 948, Col = 178, Data = 2047dd40
|
# Status: Burst-No: 8 Write Address: 003b42a8 WriteData: 2047dd40
|
# Status: Burst-No: 8 Write Address: 003b42a8 WriteData: 2047dd40
|
# tb_core.u_sdram32 : at time 51087.0 ns WRITE: Bank = 0 Row = 948, Col = 179, Data = 5b0c73b6
|
# tb_core.u_sdram32 : at time 52287.0 ns WRITE: Bank = 0 Row = 948, Col = 179, Data = 5b0c73b6
|
# Status: Burst-No: 9 Write Address: 003b42a8 WriteData: 5b0c73b6
|
# Status: Burst-No: 9 Write Address: 003b42a8 WriteData: 5b0c73b6
|
# tb_core.u_sdram32 : at time 51097.0 ns WRITE: Bank = 0 Row = 948, Col = 180, Data = faf084f5
|
# tb_core.u_sdram32 : at time 52297.0 ns WRITE: Bank = 0 Row = 948, Col = 180, Data = faf084f5
|
# Status: Burst-No: 10 Write Address: 003b42a8 WriteData: faf084f5
|
# Status: Burst-No: 10 Write Address: 003b42a8 WriteData: faf084f5
|
# tb_core.u_sdram32 : at time 51107.0 ns WRITE: Bank = 0 Row = 948, Col = 181, Data = ad27c45a
|
# tb_core.u_sdram32 : at time 52307.0 ns WRITE: Bank = 0 Row = 948, Col = 181, Data = ad27c45a
|
# Status: Burst-No: 11 Write Address: 003b42a8 WriteData: ad27c45a
|
# Status: Burst-No: 11 Write Address: 003b42a8 WriteData: ad27c45a
|
# tb_core.u_sdram32 : at time 51117.0 ns WRITE: Bank = 0 Row = 948, Col = 182, Data = 70ed97e1
|
# tb_core.u_sdram32 : at time 52317.0 ns WRITE: Bank = 0 Row = 948, Col = 182, Data = 70ed97e1
|
# Status: Burst-No: 12 Write Address: 003b42a8 WriteData: 70ed97e1
|
# Status: Burst-No: 12 Write Address: 003b42a8 WriteData: 70ed97e1
|
# tb_core.u_sdram32 : at time 51127.0 ns WRITE: Bank = 0 Row = 948, Col = 183, Data = 12ce1125
|
# tb_core.u_sdram32 : at time 52327.0 ns WRITE: Bank = 0 Row = 948, Col = 183, Data = 12ce1125
|
# Status: Burst-No: 13 Write Address: 003b42a8 WriteData: 12ce1125
|
# Status: Burst-No: 13 Write Address: 003b42a8 WriteData: 12ce1125
|
# tb_core.u_sdram32 : at time 51137.0 ns WRITE: Bank = 0 Row = 948, Col = 184, Data = 93ba6027
|
# tb_core.u_sdram32 : at time 52337.0 ns WRITE: Bank = 0 Row = 948, Col = 184, Data = 93ba6027
|
# Status: Burst-No: 14 Write Address: 003b42a8 WriteData: 93ba6027
|
# Status: Burst-No: 14 Write Address: 003b42a8 WriteData: 93ba6027
|
# tb_core.u_sdram32 : at time 51147.0 ns WRITE: Bank = 0 Row = 948, Col = 185, Data = 227eb144
|
# tb_core.u_sdram32 : at time 52347.0 ns WRITE: Bank = 0 Row = 948, Col = 185, Data = 227eb144
|
# Status: Burst-No: 15 Write Address: 003b42a8 WriteData: 227eb144
|
# Status: Burst-No: 15 Write Address: 003b42a8 WriteData: 227eb144
|
# tb_core.u_sdram32 : at time 51157.0 ns WRITE: Bank = 0 Row = 948, Col = 186, Data = bc944679
|
# tb_core.u_sdram32 : at time 52357.0 ns WRITE: Bank = 0 Row = 948, Col = 186, Data = bc944679
|
# Status: Burst-No: 16 Write Address: 003b42a8 WriteData: bc944679
|
# Status: Burst-No: 16 Write Address: 003b42a8 WriteData: bc944679
|
# tb_core.u_sdram32 : at time 51167.0 ns WRITE: Bank = 0 Row = 948, Col = 187, Data = cfb89e9f
|
# tb_core.u_sdram32 : at time 52367.0 ns WRITE: Bank = 0 Row = 948, Col = 187, Data = cfb89e9f
|
# Status: Burst-No: 17 Write Address: 003b42a8 WriteData: cfb89e9f
|
# Status: Burst-No: 17 Write Address: 003b42a8 WriteData: cfb89e9f
|
# tb_core.u_sdram32 : at time 51177.0 ns WRITE: Bank = 0 Row = 948, Col = 188, Data = 545493a8
|
# tb_core.u_sdram32 : at time 52377.0 ns WRITE: Bank = 0 Row = 948, Col = 188, Data = 545493a8
|
# Status: Burst-No: 18 Write Address: 003b42a8 WriteData: 545493a8
|
# Status: Burst-No: 18 Write Address: 003b42a8 WriteData: 545493a8
|
# tb_core.u_sdram32 : at time 51187.0 ns WRITE: Bank = 0 Row = 948, Col = 189, Data = 64d2d3c9
|
# tb_core.u_sdram32 : at time 52387.0 ns WRITE: Bank = 0 Row = 948, Col = 189, Data = 64d2d3c9
|
# Status: Burst-No: 19 Write Address: 003b42a8 WriteData: 64d2d3c9
|
# Status: Burst-No: 19 Write Address: 003b42a8 WriteData: 64d2d3c9
|
# tb_core.u_sdram32 : at time 51197.0 ns WRITE: Bank = 0 Row = 948, Col = 190, Data = 42955d85
|
# tb_core.u_sdram32 : at time 52397.0 ns WRITE: Bank = 0 Row = 948, Col = 190, Data = 42955d85
|
# Status: Burst-No: 20 Write Address: 003b42a8 WriteData: 42955d85
|
# Status: Burst-No: 20 Write Address: 003b42a8 WriteData: 42955d85
|
# tb_core.u_sdram32 : at time 51207.0 ns WRITE: Bank = 0 Row = 948, Col = 191, Data = 42e39d85
|
# tb_core.u_sdram32 : at time 52407.0 ns WRITE: Bank = 0 Row = 948, Col = 191, Data = 42e39d85
|
# Status: Burst-No: 21 Write Address: 003b42a8 WriteData: 42e39d85
|
# Status: Burst-No: 21 Write Address: 003b42a8 WriteData: 42e39d85
|
# tb_core.u_sdram32 : at time 51217.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 52417.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 51357.0 ns ACT : Bank = 0 Row = 282
|
# tb_core.u_sdram32 : at time 52557.0 ns ACT : Bank = 0 Row = 282
|
# tb_core.u_sdram32 : at time 51413.0 ns READ : Bank = 0 Row = 282, Col = 203, Data = 2f36c55e
|
# tb_core.u_sdram32 : at time 52613.0 ns READ : Bank = 0 Row = 282, Col = 203, Data = 2f36c55e
|
# tb_core.u_sdram32 : at time 51423.0 ns READ : Bank = 0 Row = 282, Col = 204, Data = 5a0f27b4
|
# tb_core.u_sdram32 : at time 52623.0 ns READ : Bank = 0 Row = 282, Col = 204, Data = 5a0f27b4
|
# READ STATUS: Burst-No: 0 Addr: 0011a32d Rxd: 2f36c55e
|
# READ STATUS: Burst-No: 0 Addr: 0011a32d Rxd: 2f36c55e
|
# tb_core.u_sdram32 : at time 51433.0 ns READ : Bank = 0 Row = 282, Col = 205, Data = 073a730e
|
# tb_core.u_sdram32 : at time 52633.0 ns READ : Bank = 0 Row = 282, Col = 205, Data = 073a730e
|
# READ STATUS: Burst-No: 1 Addr: 0011a32f Rxd: 5a0f27b4
|
# READ STATUS: Burst-No: 1 Addr: 0011a32f Rxd: 5a0f27b4
|
# tb_core.u_sdram32 : at time 51443.0 ns READ : Bank = 0 Row = 282, Col = 206, Data = 322cc164
|
# tb_core.u_sdram32 : at time 52643.0 ns READ : Bank = 0 Row = 282, Col = 206, Data = 322cc164
|
# READ STATUS: Burst-No: 2 Addr: 0011a331 Rxd: 073a730e
|
# READ STATUS: Burst-No: 2 Addr: 0011a331 Rxd: 073a730e
|
# tb_core.u_sdram32 : at time 51453.0 ns READ : Bank = 0 Row = 282, Col = 207, Data = 320a8b64
|
# tb_core.u_sdram32 : at time 52653.0 ns READ : Bank = 0 Row = 282, Col = 207, Data = 320a8b64
|
# READ STATUS: Burst-No: 3 Addr: 0011a333 Rxd: 322cc164
|
# READ STATUS: Burst-No: 3 Addr: 0011a333 Rxd: 322cc164
|
# tb_core.u_sdram32 : at time 51463.0 ns READ : Bank = 0 Row = 282, Col = 208, Data = 2416b948
|
# tb_core.u_sdram32 : at time 52663.0 ns READ : Bank = 0 Row = 282, Col = 208, Data = 2416b948
|
# READ STATUS: Burst-No: 4 Addr: 0011a335 Rxd: 320a8b64
|
# READ STATUS: Burst-No: 4 Addr: 0011a335 Rxd: 320a8b64
|
# tb_core.u_sdram32 : at time 51473.0 ns READ : Bank = 0 Row = 282, Col = 209, Data = c544d88a
|
# tb_core.u_sdram32 : at time 52673.0 ns READ : Bank = 0 Row = 282, Col = 209, Data = c544d88a
|
# READ STATUS: Burst-No: 5 Addr: 0011a337 Rxd: 2416b948
|
# READ STATUS: Burst-No: 5 Addr: 0011a337 Rxd: 2416b948
|
# tb_core.u_sdram32 : at time 51483.0 ns READ : Bank = 0 Row = 282, Col = 210, Data = 4dfe879b
|
# tb_core.u_sdram32 : at time 52683.0 ns READ : Bank = 0 Row = 282, Col = 210, Data = 4dfe879b
|
# READ STATUS: Burst-No: 6 Addr: 0011a339 Rxd: c544d88a
|
# READ STATUS: Burst-No: 6 Addr: 0011a339 Rxd: c544d88a
|
# tb_core.u_sdram32 : at time 51493.0 ns READ : Bank = 0 Row = 282, Col = 211, Data = e6fbf4cd
|
# tb_core.u_sdram32 : at time 52693.0 ns READ : Bank = 0 Row = 282, Col = 211, Data = e6fbf4cd
|
# READ STATUS: Burst-No: 7 Addr: 0011a33b Rxd: 4dfe879b
|
# READ STATUS: Burst-No: 7 Addr: 0011a33b Rxd: 4dfe879b
|
# tb_core.u_sdram32 : at time 51503.0 ns READ : Bank = 0 Row = 282, Col = 212, Data = b5f8fa6b
|
# tb_core.u_sdram32 : at time 52703.0 ns READ : Bank = 0 Row = 282, Col = 212, Data = b5f8fa6b
|
# READ STATUS: Burst-No: 8 Addr: 0011a33d Rxd: e6fbf4cd
|
# READ STATUS: Burst-No: 8 Addr: 0011a33d Rxd: e6fbf4cd
|
# tb_core.u_sdram32 : at time 51513.0 ns READ : Bank = 0 Row = 282, Col = 213, Data = 55ff23ab
|
# tb_core.u_sdram32 : at time 52713.0 ns READ : Bank = 0 Row = 282, Col = 213, Data = 55ff23ab
|
# READ STATUS: Burst-No: 9 Addr: 0011a33f Rxd: b5f8fa6b
|
# READ STATUS: Burst-No: 9 Addr: 0011a33f Rxd: b5f8fa6b
|
# tb_core.u_sdram32 : at time 51523.0 ns READ : Bank = 0 Row = 282, Col = 214, Data = f1eca2e3
|
# tb_core.u_sdram32 : at time 52723.0 ns READ : Bank = 0 Row = 282, Col = 214, Data = f1eca2e3
|
# READ STATUS: Burst-No: 10 Addr: 0011a341 Rxd: 55ff23ab
|
# READ STATUS: Burst-No: 10 Addr: 0011a341 Rxd: 55ff23ab
|
# tb_core.u_sdram32 : at time 51533.0 ns READ : Bank = 0 Row = 282, Col = 215, Data = 5e9d2fbd
|
# tb_core.u_sdram32 : at time 52733.0 ns READ : Bank = 0 Row = 282, Col = 215, Data = 5e9d2fbd
|
# READ STATUS: Burst-No: 11 Addr: 0011a343 Rxd: f1eca2e3
|
# READ STATUS: Burst-No: 11 Addr: 0011a343 Rxd: f1eca2e3
|
# tb_core.u_sdram32 : at time 51543.0 ns READ : Bank = 0 Row = 282, Col = 216, Data = ecff24d9
|
# tb_core.u_sdram32 : at time 52743.0 ns READ : Bank = 0 Row = 282, Col = 216, Data = ecff24d9
|
# READ STATUS: Burst-No: 12 Addr: 0011a345 Rxd: 5e9d2fbd
|
# READ STATUS: Burst-No: 12 Addr: 0011a345 Rxd: 5e9d2fbd
|
# tb_core.u_sdram32 : at time 51553.0 ns READ : Bank = 0 Row = 282, Col = 217, Data = e11a58c2
|
# tb_core.u_sdram32 : at time 52753.0 ns READ : Bank = 0 Row = 282, Col = 217, Data = e11a58c2
|
# READ STATUS: Burst-No: 13 Addr: 0011a347 Rxd: ecff24d9
|
# READ STATUS: Burst-No: 13 Addr: 0011a347 Rxd: ecff24d9
|
# tb_core.u_sdram32 : at time 51563.0 ns READ : Bank = 0 Row = 282, Col = 218, Data = f059ace0
|
# tb_core.u_sdram32 : at time 52763.0 ns READ : Bank = 0 Row = 282, Col = 218, Data = f059ace0
|
# READ STATUS: Burst-No: 14 Addr: 0011a349 Rxd: e11a58c2
|
# READ STATUS: Burst-No: 14 Addr: 0011a349 Rxd: e11a58c2
|
# tb_core.u_sdram32 : at time 51573.0 ns READ : Bank = 0 Row = 282, Col = 219, Data = afd1265f
|
# tb_core.u_sdram32 : at time 52773.0 ns READ : Bank = 0 Row = 282, Col = 219, Data = afd1265f
|
# READ STATUS: Burst-No: 15 Addr: 0011a34b Rxd: f059ace0
|
# READ STATUS: Burst-No: 15 Addr: 0011a34b Rxd: f059ace0
|
# tb_core.u_sdram32 : at time 51583.0 ns READ : Bank = 0 Row = 282, Col = 220, Data = 8edc361d
|
# tb_core.u_sdram32 : at time 52783.0 ns READ : Bank = 0 Row = 282, Col = 220, Data = 8edc361d
|
# READ STATUS: Burst-No: 16 Addr: 0011a34d Rxd: afd1265f
|
# READ STATUS: Burst-No: 16 Addr: 0011a34d Rxd: afd1265f
|
# tb_core.u_sdram32 : at time 51593.0 ns READ : Bank = 0 Row = 282, Col = 221, Data = c9b64c93
|
# tb_core.u_sdram32 : at time 52793.0 ns READ : Bank = 0 Row = 282, Col = 221, Data = c9b64c93
|
# READ STATUS: Burst-No: 17 Addr: 0011a34f Rxd: 8edc361d
|
# READ STATUS: Burst-No: 17 Addr: 0011a34f Rxd: 8edc361d
|
# tb_core.u_sdram32 : at time 51603.0 ns READ : Bank = 0 Row = 282, Col = 222, Data = 13180326
|
# tb_core.u_sdram32 : at time 52803.0 ns READ : Bank = 0 Row = 282, Col = 222, Data = 13180326
|
# READ STATUS: Burst-No: 18 Addr: 0011a351 Rxd: c9b64c93
|
# READ STATUS: Burst-No: 18 Addr: 0011a351 Rxd: c9b64c93
|
# tb_core.u_sdram32 : at time 51613.0 ns READ : Bank = 0 Row = 282, Col = 223, Data = 82b78605
|
# tb_core.u_sdram32 : at time 52813.0 ns READ : Bank = 0 Row = 282, Col = 223, Data = 82b78605
|
# READ STATUS: Burst-No: 19 Addr: 0011a353 Rxd: 13180326
|
# READ STATUS: Burst-No: 19 Addr: 0011a353 Rxd: 13180326
|
# tb_core.u_sdram32 : at time 51623.0 ns READ : Bank = 0 Row = 282, Col = 224, Data = 84a8e809
|
# tb_core.u_sdram32 : at time 52823.0 ns READ : Bank = 0 Row = 282, Col = 224, Data = 84a8e809
|
# READ STATUS: Burst-No: 20 Addr: 0011a355 Rxd: 82b78605
|
# READ STATUS: Burst-No: 20 Addr: 0011a355 Rxd: 82b78605
|
# tb_core.u_sdram32 : at time 51633.0 ns READ : Bank = 0 Row = 282, Col = 225, Data = b62d846c
|
# tb_core.u_sdram32 : at time 52833.0 ns READ : Bank = 0 Row = 282, Col = 225, Data = b62d846c
|
# READ STATUS: Burst-No: 21 Addr: 0011a357 Rxd: 84a8e809
|
# READ STATUS: Burst-No: 21 Addr: 0011a357 Rxd: 84a8e809
|
# tb_core.u_sdram32 : at time 51643.0 ns READ : Bank = 0 Row = 282, Col = 226, Data = b5c5c06b
|
# tb_core.u_sdram32 : at time 52843.0 ns READ : Bank = 0 Row = 282, Col = 226, Data = b5c5c06b
|
# READ STATUS: Burst-No: 22 Addr: 0011a359 Rxd: b62d846c
|
# READ STATUS: Burst-No: 22 Addr: 0011a359 Rxd: b62d846c
|
# tb_core.u_sdram32 : at time 51653.0 ns READ : Bank = 0 Row = 282, Col = 227, Data = 5858bdb0
|
# tb_core.u_sdram32 : at time 52853.0 ns READ : Bank = 0 Row = 282, Col = 227, Data = 5858bdb0
|
# READ STATUS: Burst-No: 23 Addr: 0011a35b Rxd: b5c5c06b
|
# READ STATUS: Burst-No: 23 Addr: 0011a35b Rxd: b5c5c06b
|
# tb_core.u_sdram32 : at time 51663.0 ns READ : Bank = 0 Row = 282, Col = 228, Data = fb9fb8f7
|
# tb_core.u_sdram32 : at time 52863.0 ns READ : Bank = 0 Row = 282, Col = 228, Data = fb9fb8f7
|
# READ STATUS: Burst-No: 24 Addr: 0011a35d Rxd: 5858bdb0
|
# READ STATUS: Burst-No: 24 Addr: 0011a35d Rxd: 5858bdb0
|
# tb_core.u_sdram32 : at time 51673.0 ns READ : Bank = 0 Row = 282, Col = 229, Data = 52a151a5
|
# tb_core.u_sdram32 : at time 52873.0 ns READ : Bank = 0 Row = 282, Col = 229, Data = 52a151a5
|
# READ STATUS: Burst-No: 25 Addr: 0011a35f Rxd: fb9fb8f7
|
# READ STATUS: Burst-No: 25 Addr: 0011a35f Rxd: fb9fb8f7
|
# tb_core.u_sdram32 : at time 51683.0 ns READ : Bank = 0 Row = 282, Col = 230, Data = abe8c057
|
# tb_core.u_sdram32 : at time 52883.0 ns READ : Bank = 0 Row = 282, Col = 230, Data = abe8c057
|
# READ STATUS: Burst-No: 26 Addr: 0011a361 Rxd: 52a151a5
|
# READ STATUS: Burst-No: 26 Addr: 0011a361 Rxd: 52a151a5
|
# tb_core.u_sdram32 : at time 51693.0 ns READ : Bank = 0 Row = 282, Col = 231, Data = 3b11f376
|
# tb_core.u_sdram32 : at time 52893.0 ns READ : Bank = 0 Row = 282, Col = 231, Data = 3b11f376
|
# READ STATUS: Burst-No: 27 Addr: 0011a363 Rxd: abe8c057
|
# READ STATUS: Burst-No: 27 Addr: 0011a363 Rxd: abe8c057
|
# tb_core.u_sdram32 : at time 51703.0 ns READ : Bank = 0 Row = 282, Col = 232, Data = 2798e34f
|
# tb_core.u_sdram32 : at time 52903.0 ns READ : Bank = 0 Row = 282, Col = 232, Data = 2798e34f
|
# READ STATUS: Burst-No: 28 Addr: 0011a365 Rxd: 3b11f376
|
# READ STATUS: Burst-No: 28 Addr: 0011a365 Rxd: 3b11f376
|
# tb_core.u_sdram32 : at time 51713.0 ns READ : Bank = 0 Row = 282, Col = 233, Data = 5a45bdb4
|
# tb_core.u_sdram32 : at time 52913.0 ns READ : Bank = 0 Row = 282, Col = 233, Data = 5a45bdb4
|
# READ STATUS: Burst-No: 29 Addr: 0011a367 Rxd: 2798e34f
|
# READ STATUS: Burst-No: 29 Addr: 0011a367 Rxd: 2798e34f
|
# tb_core.u_sdram32 : at time 51723.0 ns READ : Bank = 0 Row = 282, Col = 234, Data = 8ecaa21d
|
# tb_core.u_sdram32 : at time 52923.0 ns READ : Bank = 0 Row = 282, Col = 234, Data = 8ecaa21d
|
# READ STATUS: Burst-No: 30 Addr: 0011a369 Rxd: 5a45bdb4
|
# READ STATUS: Burst-No: 30 Addr: 0011a369 Rxd: 5a45bdb4
|
# tb_core.u_sdram32 : at time 51733.0 ns READ : Bank = 0 Row = 282, Col = 235, Data = 43c11587
|
# tb_core.u_sdram32 : at time 52933.0 ns READ : Bank = 0 Row = 282, Col = 235, Data = 43c11587
|
# READ STATUS: Burst-No: 31 Addr: 0011a36b Rxd: 8ecaa21d
|
# READ STATUS: Burst-No: 31 Addr: 0011a36b Rxd: 8ecaa21d
|
# tb_core.u_sdram32 : at time 51743.0 ns READ : Bank = 0 Row = 282, Col = 236, Data = 23466346
|
# tb_core.u_sdram32 : at time 52943.0 ns READ : Bank = 0 Row = 282, Col = 236, Data = 23466346
|
# READ STATUS: Burst-No: 32 Addr: 0011a36d Rxd: 43c11587
|
# READ STATUS: Burst-No: 32 Addr: 0011a36d Rxd: 43c11587
|
# tb_core.u_sdram32 : at time 51753.0 ns READ : Bank = 0 Row = 282, Col = 237, Data = 336d9366
|
# tb_core.u_sdram32 : at time 52953.0 ns READ : Bank = 0 Row = 282, Col = 237, Data = 336d9366
|
# READ STATUS: Burst-No: 33 Addr: 0011a36f Rxd: 23466346
|
# READ STATUS: Burst-No: 33 Addr: 0011a36f Rxd: 23466346
|
# tb_core.u_sdram32 : at time 51763.0 ns READ : Bank = 0 Row = 282, Col = 238, Data = 4f14c19e
|
# tb_core.u_sdram32 : at time 52963.0 ns READ : Bank = 0 Row = 282, Col = 238, Data = 4f14c19e
|
# READ STATUS: Burst-No: 34 Addr: 0011a371 Rxd: 336d9366
|
# READ STATUS: Burst-No: 34 Addr: 0011a371 Rxd: 336d9366
|
# tb_core.u_sdram32 : at time 51773.0 ns READ : Bank = 0 Row = 282, Col = 239, Data = 1fb0d13f
|
# tb_core.u_sdram32 : at time 52973.0 ns READ : Bank = 0 Row = 282, Col = 239, Data = 1fb0d13f
|
# READ STATUS: Burst-No: 35 Addr: 0011a373 Rxd: 4f14c19e
|
# READ STATUS: Burst-No: 35 Addr: 0011a373 Rxd: 4f14c19e
|
# tb_core.u_sdram32 : at time 51783.0 ns READ : Bank = 0 Row = 282, Col = 240, Data = 2a2ff554
|
# tb_core.u_sdram32 : at time 52983.0 ns READ : Bank = 0 Row = 282, Col = 240, Data = 2a2ff554
|
# READ STATUS: Burst-No: 36 Addr: 0011a375 Rxd: 1fb0d13f
|
# READ STATUS: Burst-No: 36 Addr: 0011a375 Rxd: 1fb0d13f
|
# tb_core.u_sdram32 : at time 51793.0 ns READ : Bank = 0 Row = 282, Col = 241, Data = 2a565f54
|
# tb_core.u_sdram32 : at time 52993.0 ns READ : Bank = 0 Row = 282, Col = 241, Data = 2a565f54
|
# READ STATUS: Burst-No: 37 Addr: 0011a377 Rxd: 2a2ff554
|
# READ STATUS: Burst-No: 37 Addr: 0011a377 Rxd: 2a2ff554
|
# tb_core.u_sdram32 : at time 51803.0 ns READ : Bank = 0 Row = 282, Col = 242, Data = a62c344c
|
# tb_core.u_sdram32 : at time 53003.0 ns READ : Bank = 0 Row = 282, Col = 242, Data = a62c344c
|
# READ STATUS: Burst-No: 38 Addr: 0011a379 Rxd: 2a565f54
|
# READ STATUS: Burst-No: 38 Addr: 0011a379 Rxd: 2a565f54
|
# tb_core.u_sdram32 : at time 51813.0 ns READ : Bank = 0 Row = 282, Col = 243, Data = 83449006
|
# tb_core.u_sdram32 : at time 53013.0 ns READ : Bank = 0 Row = 282, Col = 243, Data = 83449006
|
# READ STATUS: Burst-No: 39 Addr: 0011a37b Rxd: a62c344c
|
# READ STATUS: Burst-No: 39 Addr: 0011a37b Rxd: a62c344c
|
# tb_core.u_sdram32 : at time 51823.0 ns READ : Bank = 0 Row = 282, Col = 244, Data = 286f1350
|
# tb_core.u_sdram32 : at time 53023.0 ns READ : Bank = 0 Row = 282, Col = 244, Data = 286f1350
|
# READ STATUS: Burst-No: 40 Addr: 0011a37d Rxd: 83449006
|
# READ STATUS: Burst-No: 40 Addr: 0011a37d Rxd: 83449006
|
# tb_core.u_sdram32 : at time 51833.0 ns READ : Bank = 0 Row = 282, Col = 245, Data = 16b46d2d
|
# tb_core.u_sdram32 : at time 53033.0 ns READ : Bank = 0 Row = 282, Col = 245, Data = 16b46d2d
|
# READ STATUS: Burst-No: 41 Addr: 0011a37f Rxd: 286f1350
|
# READ STATUS: Burst-No: 41 Addr: 0011a37f Rxd: 286f1350
|
# tb_core.u_sdram32 : at time 51843.0 ns READ : Bank = 0 Row = 282, Col = 246, Data = c34ddc86
|
# tb_core.u_sdram32 : at time 53043.0 ns READ : Bank = 0 Row = 282, Col = 246, Data = c34ddc86
|
# READ STATUS: Burst-No: 42 Addr: 0011a381 Rxd: 16b46d2d
|
# READ STATUS: Burst-No: 42 Addr: 0011a381 Rxd: 16b46d2d
|
# tb_core.u_sdram32 : at time 51853.0 ns READ : Bank = 0 Row = 282, Col = 247, Data = 3564836a
|
# tb_core.u_sdram32 : at time 53053.0 ns READ : Bank = 0 Row = 282, Col = 247, Data = 3564836a
|
# READ STATUS: Burst-No: 43 Addr: 0011a383 Rxd: c34ddc86
|
# READ STATUS: Burst-No: 43 Addr: 0011a383 Rxd: c34ddc86
|
# tb_core.u_sdram32 : at time 51863.0 ns READ : Bank = 0 Row = 282, Col = 248, Data = 5c2afdb8
|
# tb_core.u_sdram32 : at time 53063.0 ns READ : Bank = 0 Row = 282, Col = 248, Data = 5c2afdb8
|
# READ STATUS: Burst-No: 44 Addr: 0011a385 Rxd: 3564836a
|
# READ STATUS: Burst-No: 44 Addr: 0011a385 Rxd: 3564836a
|
# tb_core.u_sdram32 : at time 51873.0 ns READ : Bank = 0 Row = 282, Col = 249, Data = f7fecaef
|
# tb_core.u_sdram32 : at time 53073.0 ns READ : Bank = 0 Row = 282, Col = 249, Data = f7fecaef
|
# READ STATUS: Burst-No: 45 Addr: 0011a387 Rxd: 5c2afdb8
|
# READ STATUS: Burst-No: 45 Addr: 0011a387 Rxd: 5c2afdb8
|
# tb_core.u_sdram32 : at time 51883.0 ns READ : Bank = 0 Row = 282, Col = 250, Data = 506a57a0
|
# tb_core.u_sdram32 : at time 53083.0 ns READ : Bank = 0 Row = 282, Col = 250, Data = 506a57a0
|
# tb_core.u_sdram32 : at time 51887.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 53087.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 46 Addr: 0011a389 Rxd: f7fecaef
|
# READ STATUS: Burst-No: 46 Addr: 0011a389 Rxd: f7fecaef
|
# tb_core.u_sdram32 : at time 51893.0 ns READ : Bank = 0 Row = 282, Col = 251, Data = 1fa98f3f
|
# tb_core.u_sdram32 : at time 53093.0 ns READ : Bank = 0 Row = 282, Col = 251, Data = 1fa98f3f
|
# READ STATUS: Burst-No: 47 Addr: 0011a38b Rxd: 506a57a0
|
# READ STATUS: Burst-No: 47 Addr: 0011a38b Rxd: 506a57a0
|
# tb_core.u_sdram32 : at time 51903.0 ns READ : Bank = 0 Row = 282, Col = 252, Data = 84d4aa09
|
# tb_core.u_sdram32 : at time 53103.0 ns READ : Bank = 0 Row = 282, Col = 252, Data = 84d4aa09
|
# READ STATUS: Burst-No: 48 Addr: 0011a38d Rxd: 1fa98f3f
|
# READ STATUS: Burst-No: 48 Addr: 0011a38d Rxd: 1fa98f3f
|
# READ STATUS: Burst-No: 49 Addr: 0011a38f Rxd: 84d4aa09
|
# READ STATUS: Burst-No: 49 Addr: 0011a38f Rxd: 84d4aa09
|
# tb_core.u_sdram32 : at time 52077.0 ns ACT : Bank = 0 Row = 948
|
# tb_core.u_sdram32 : at time 53277.0 ns ACT : Bank = 0 Row = 948
|
# tb_core.u_sdram32 : at time 52133.0 ns READ : Bank = 0 Row = 948, Col = 170, Data = 8f49661e
|
# tb_core.u_sdram32 : at time 53333.0 ns READ : Bank = 0 Row = 948, Col = 170, Data = 8f49661e
|
# tb_core.u_sdram32 : at time 52143.0 ns READ : Bank = 0 Row = 948, Col = 171, Data = dc22dcb8
|
# tb_core.u_sdram32 : at time 53343.0 ns READ : Bank = 0 Row = 948, Col = 171, Data = dc22dcb8
|
# READ STATUS: Burst-No: 0 Addr: 003b42a8 Rxd: 8f49661e
|
# READ STATUS: Burst-No: 0 Addr: 003b42a8 Rxd: 8f49661e
|
# tb_core.u_sdram32 : at time 52153.0 ns READ : Bank = 0 Row = 948, Col = 172, Data = e70a62ce
|
# tb_core.u_sdram32 : at time 53353.0 ns READ : Bank = 0 Row = 948, Col = 172, Data = e70a62ce
|
# READ STATUS: Burst-No: 1 Addr: 003b42aa Rxd: dc22dcb8
|
# READ STATUS: Burst-No: 1 Addr: 003b42aa Rxd: dc22dcb8
|
# tb_core.u_sdram32 : at time 52163.0 ns READ : Bank = 0 Row = 948, Col = 173, Data = eb40e6d6
|
# tb_core.u_sdram32 : at time 53363.0 ns READ : Bank = 0 Row = 948, Col = 173, Data = eb40e6d6
|
# READ STATUS: Burst-No: 2 Addr: 003b42ac Rxd: e70a62ce
|
# READ STATUS: Burst-No: 2 Addr: 003b42ac Rxd: e70a62ce
|
# tb_core.u_sdram32 : at time 52173.0 ns READ : Bank = 0 Row = 948, Col = 174, Data = 92c27025
|
# tb_core.u_sdram32 : at time 53373.0 ns READ : Bank = 0 Row = 948, Col = 174, Data = 92c27025
|
# READ STATUS: Burst-No: 3 Addr: 003b42ae Rxd: eb40e6d6
|
# READ STATUS: Burst-No: 3 Addr: 003b42ae Rxd: eb40e6d6
|
# tb_core.u_sdram32 : at time 52183.0 ns READ : Bank = 0 Row = 948, Col = 175, Data = d4ce0aa9
|
# tb_core.u_sdram32 : at time 53383.0 ns READ : Bank = 0 Row = 948, Col = 175, Data = d4ce0aa9
|
# READ STATUS: Burst-No: 4 Addr: 003b42b0 Rxd: 92c27025
|
# READ STATUS: Burst-No: 4 Addr: 003b42b0 Rxd: 92c27025
|
# tb_core.u_sdram32 : at time 52193.0 ns READ : Bank = 0 Row = 948, Col = 176, Data = e7b374cf
|
# tb_core.u_sdram32 : at time 53393.0 ns READ : Bank = 0 Row = 948, Col = 176, Data = e7b374cf
|
# READ STATUS: Burst-No: 5 Addr: 003b42b2 Rxd: d4ce0aa9
|
# READ STATUS: Burst-No: 5 Addr: 003b42b2 Rxd: d4ce0aa9
|
# tb_core.u_sdram32 : at time 52203.0 ns READ : Bank = 0 Row = 948, Col = 177, Data = 1a9af535
|
# tb_core.u_sdram32 : at time 53403.0 ns READ : Bank = 0 Row = 948, Col = 177, Data = 1a9af535
|
# READ STATUS: Burst-No: 6 Addr: 003b42b4 Rxd: e7b374cf
|
# READ STATUS: Burst-No: 6 Addr: 003b42b4 Rxd: e7b374cf
|
# tb_core.u_sdram32 : at time 52213.0 ns READ : Bank = 0 Row = 948, Col = 178, Data = 2047dd40
|
# tb_core.u_sdram32 : at time 53413.0 ns READ : Bank = 0 Row = 948, Col = 178, Data = 2047dd40
|
# READ STATUS: Burst-No: 7 Addr: 003b42b6 Rxd: 1a9af535
|
# READ STATUS: Burst-No: 7 Addr: 003b42b6 Rxd: 1a9af535
|
# tb_core.u_sdram32 : at time 52223.0 ns READ : Bank = 0 Row = 948, Col = 179, Data = 5b0c73b6
|
# tb_core.u_sdram32 : at time 53423.0 ns READ : Bank = 0 Row = 948, Col = 179, Data = 5b0c73b6
|
# READ STATUS: Burst-No: 8 Addr: 003b42b8 Rxd: 2047dd40
|
# READ STATUS: Burst-No: 8 Addr: 003b42b8 Rxd: 2047dd40
|
# tb_core.u_sdram32 : at time 52233.0 ns READ : Bank = 0 Row = 948, Col = 180, Data = faf084f5
|
# tb_core.u_sdram32 : at time 53433.0 ns READ : Bank = 0 Row = 948, Col = 180, Data = faf084f5
|
# READ STATUS: Burst-No: 9 Addr: 003b42ba Rxd: 5b0c73b6
|
# READ STATUS: Burst-No: 9 Addr: 003b42ba Rxd: 5b0c73b6
|
# tb_core.u_sdram32 : at time 52243.0 ns READ : Bank = 0 Row = 948, Col = 181, Data = ad27c45a
|
# tb_core.u_sdram32 : at time 53443.0 ns READ : Bank = 0 Row = 948, Col = 181, Data = ad27c45a
|
# READ STATUS: Burst-No: 10 Addr: 003b42bc Rxd: faf084f5
|
# READ STATUS: Burst-No: 10 Addr: 003b42bc Rxd: faf084f5
|
# tb_core.u_sdram32 : at time 52253.0 ns READ : Bank = 0 Row = 948, Col = 182, Data = 70ed97e1
|
# tb_core.u_sdram32 : at time 53453.0 ns READ : Bank = 0 Row = 948, Col = 182, Data = 70ed97e1
|
# READ STATUS: Burst-No: 11 Addr: 003b42be Rxd: ad27c45a
|
# READ STATUS: Burst-No: 11 Addr: 003b42be Rxd: ad27c45a
|
# tb_core.u_sdram32 : at time 52263.0 ns READ : Bank = 0 Row = 948, Col = 183, Data = 12ce1125
|
# tb_core.u_sdram32 : at time 53463.0 ns READ : Bank = 0 Row = 948, Col = 183, Data = 12ce1125
|
# READ STATUS: Burst-No: 12 Addr: 003b42c0 Rxd: 70ed97e1
|
# READ STATUS: Burst-No: 12 Addr: 003b42c0 Rxd: 70ed97e1
|
# tb_core.u_sdram32 : at time 52273.0 ns READ : Bank = 0 Row = 948, Col = 184, Data = 93ba6027
|
# tb_core.u_sdram32 : at time 53473.0 ns READ : Bank = 0 Row = 948, Col = 184, Data = 93ba6027
|
# READ STATUS: Burst-No: 13 Addr: 003b42c2 Rxd: 12ce1125
|
# READ STATUS: Burst-No: 13 Addr: 003b42c2 Rxd: 12ce1125
|
# tb_core.u_sdram32 : at time 52283.0 ns READ : Bank = 0 Row = 948, Col = 185, Data = 227eb144
|
# tb_core.u_sdram32 : at time 53483.0 ns READ : Bank = 0 Row = 948, Col = 185, Data = 227eb144
|
# READ STATUS: Burst-No: 14 Addr: 003b42c4 Rxd: 93ba6027
|
# READ STATUS: Burst-No: 14 Addr: 003b42c4 Rxd: 93ba6027
|
# tb_core.u_sdram32 : at time 52293.0 ns READ : Bank = 0 Row = 948, Col = 186, Data = bc944679
|
# tb_core.u_sdram32 : at time 53493.0 ns READ : Bank = 0 Row = 948, Col = 186, Data = bc944679
|
# READ STATUS: Burst-No: 15 Addr: 003b42c6 Rxd: 227eb144
|
# READ STATUS: Burst-No: 15 Addr: 003b42c6 Rxd: 227eb144
|
# tb_core.u_sdram32 : at time 52303.0 ns READ : Bank = 0 Row = 948, Col = 187, Data = cfb89e9f
|
# tb_core.u_sdram32 : at time 53503.0 ns READ : Bank = 0 Row = 948, Col = 187, Data = cfb89e9f
|
# READ STATUS: Burst-No: 16 Addr: 003b42c8 Rxd: bc944679
|
# READ STATUS: Burst-No: 16 Addr: 003b42c8 Rxd: bc944679
|
# tb_core.u_sdram32 : at time 52313.0 ns READ : Bank = 0 Row = 948, Col = 188, Data = 545493a8
|
# tb_core.u_sdram32 : at time 53513.0 ns READ : Bank = 0 Row = 948, Col = 188, Data = 545493a8
|
# READ STATUS: Burst-No: 17 Addr: 003b42ca Rxd: cfb89e9f
|
# READ STATUS: Burst-No: 17 Addr: 003b42ca Rxd: cfb89e9f
|
# tb_core.u_sdram32 : at time 52323.0 ns READ : Bank = 0 Row = 948, Col = 189, Data = 64d2d3c9
|
# tb_core.u_sdram32 : at time 53523.0 ns READ : Bank = 0 Row = 948, Col = 189, Data = 64d2d3c9
|
# tb_core.u_sdram32 : at time 52327.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 53527.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 18 Addr: 003b42cc Rxd: 545493a8
|
# READ STATUS: Burst-No: 18 Addr: 003b42cc Rxd: 545493a8
|
# tb_core.u_sdram32 : at time 52333.0 ns READ : Bank = 0 Row = 948, Col = 190, Data = 42955d85
|
# tb_core.u_sdram32 : at time 53533.0 ns READ : Bank = 0 Row = 948, Col = 190, Data = 42955d85
|
# READ STATUS: Burst-No: 19 Addr: 003b42ce Rxd: 64d2d3c9
|
# READ STATUS: Burst-No: 19 Addr: 003b42ce Rxd: 64d2d3c9
|
# tb_core.u_sdram32 : at time 52343.0 ns READ : Bank = 0 Row = 948, Col = 191, Data = 42e39d85
|
# tb_core.u_sdram32 : at time 53543.0 ns READ : Bank = 0 Row = 948, Col = 191, Data = 42e39d85
|
# READ STATUS: Burst-No: 20 Addr: 003b42d0 Rxd: 42955d85
|
# READ STATUS: Burst-No: 20 Addr: 003b42d0 Rxd: 42955d85
|
# READ STATUS: Burst-No: 21 Addr: 003b42d2 Rxd: 42e39d85
|
# READ STATUS: Burst-No: 21 Addr: 003b42d2 Rxd: 42e39d85
|
# Write Address: 00196873, Burst Size: 9
|
# Write Address: 00196873, Burst Size: 9
|
# tb_core.u_sdram32 : at time 52517.0 ns ACT : Bank = 2 Row = 406
|
# tb_core.u_sdram32 : at time 53717.0 ns ACT : Bank = 2 Row = 406
|
# tb_core.u_sdram32 : at time 52547.0 ns WRITE: Bank = 2 Row = 406, Col = 28, Data = 4b2f0596
|
# tb_core.u_sdram32 : at time 53747.0 ns WRITE: Bank = 2 Row = 406, Col = 28, Data = 4b2f0596
|
# Status: Burst-No: 0 Write Address: 00196873 WriteData: 4b2f0596
|
# Status: Burst-No: 0 Write Address: 00196873 WriteData: 4b2f0596
|
# tb_core.u_sdram32 : at time 52557.0 ns WRITE: Bank = 2 Row = 406, Col = 29, Data = 9a544234
|
# tb_core.u_sdram32 : at time 53757.0 ns WRITE: Bank = 2 Row = 406, Col = 29, Data = 9a544234
|
# Status: Burst-No: 1 Write Address: 00196873 WriteData: 9a544234
|
# Status: Burst-No: 1 Write Address: 00196873 WriteData: 9a544234
|
# tb_core.u_sdram32 : at time 52567.0 ns WRITE: Bank = 2 Row = 406, Col = 30, Data = 1e85ed3d
|
# tb_core.u_sdram32 : at time 53767.0 ns WRITE: Bank = 2 Row = 406, Col = 30, Data = 1e85ed3d
|
# Status: Burst-No: 2 Write Address: 00196873 WriteData: 1e85ed3d
|
# Status: Burst-No: 2 Write Address: 00196873 WriteData: 1e85ed3d
|
# tb_core.u_sdram32 : at time 52577.0 ns WRITE: Bank = 2 Row = 406, Col = 31, Data = 28b1f151
|
# tb_core.u_sdram32 : at time 53777.0 ns WRITE: Bank = 2 Row = 406, Col = 31, Data = 28b1f151
|
# Status: Burst-No: 3 Write Address: 00196873 WriteData: 28b1f151
|
# Status: Burst-No: 3 Write Address: 00196873 WriteData: 28b1f151
|
# tb_core.u_sdram32 : at time 52587.0 ns WRITE: Bank = 2 Row = 406, Col = 32, Data = 8db0281b
|
# tb_core.u_sdram32 : at time 53787.0 ns WRITE: Bank = 2 Row = 406, Col = 32, Data = 8db0281b
|
# Status: Burst-No: 4 Write Address: 00196873 WriteData: 8db0281b
|
# Status: Burst-No: 4 Write Address: 00196873 WriteData: 8db0281b
|
# tb_core.u_sdram32 : at time 52597.0 ns WRITE: Bank = 2 Row = 406, Col = 33, Data = 8e39901c
|
# tb_core.u_sdram32 : at time 53797.0 ns WRITE: Bank = 2 Row = 406, Col = 33, Data = 8e39901c
|
# Status: Burst-No: 5 Write Address: 00196873 WriteData: 8e39901c
|
# Status: Burst-No: 5 Write Address: 00196873 WriteData: 8e39901c
|
# tb_core.u_sdram32 : at time 52607.0 ns WRITE: Bank = 2 Row = 406, Col = 34, Data = 5ec5ebbd
|
# tb_core.u_sdram32 : at time 53807.0 ns WRITE: Bank = 2 Row = 406, Col = 34, Data = 5ec5ebbd
|
# Status: Burst-No: 6 Write Address: 00196873 WriteData: 5ec5ebbd
|
# Status: Burst-No: 6 Write Address: 00196873 WriteData: 5ec5ebbd
|
# tb_core.u_sdram32 : at time 52617.0 ns WRITE: Bank = 2 Row = 406, Col = 35, Data = da69e2b4
|
# tb_core.u_sdram32 : at time 53817.0 ns WRITE: Bank = 2 Row = 406, Col = 35, Data = da69e2b4
|
# Status: Burst-No: 7 Write Address: 00196873 WriteData: da69e2b4
|
# Status: Burst-No: 7 Write Address: 00196873 WriteData: da69e2b4
|
# tb_core.u_sdram32 : at time 52627.0 ns WRITE: Bank = 2 Row = 406, Col = 36, Data = 2764754e
|
# tb_core.u_sdram32 : at time 53827.0 ns WRITE: Bank = 2 Row = 406, Col = 36, Data = 2764754e
|
# Status: Burst-No: 8 Write Address: 00196873 WriteData: 2764754e
|
# Status: Burst-No: 8 Write Address: 00196873 WriteData: 2764754e
|
# tb_core.u_sdram32 : at time 52637.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 53837.0 ns BST : Burst Terminate
|
# Write Address: 00283f2f, Burst Size: 26
|
# Write Address: 00283f2f, Burst Size: 26
|
# tb_core.u_sdram32 : at time 52777.0 ns ACT : Bank = 3 Row = 643
|
# tb_core.u_sdram32 : at time 53977.0 ns ACT : Bank = 3 Row = 643
|
# tb_core.u_sdram32 : at time 52807.0 ns WRITE: Bank = 3 Row = 643, Col = 203, Data = f670fcec
|
# tb_core.u_sdram32 : at time 54007.0 ns WRITE: Bank = 3 Row = 643, Col = 203, Data = f670fcec
|
# Status: Burst-No: 0 Write Address: 00283f2f WriteData: f670fcec
|
# Status: Burst-No: 0 Write Address: 00283f2f WriteData: f670fcec
|
# tb_core.u_sdram32 : at time 52817.0 ns WRITE: Bank = 3 Row = 643, Col = 204, Data = 0f40551e
|
# tb_core.u_sdram32 : at time 54017.0 ns WRITE: Bank = 3 Row = 643, Col = 204, Data = 0f40551e
|
# Status: Burst-No: 1 Write Address: 00283f2f WriteData: 0f40551e
|
# Status: Burst-No: 1 Write Address: 00283f2f WriteData: 0f40551e
|
# tb_core.u_sdram32 : at time 52827.0 ns WRITE: Bank = 3 Row = 643, Col = 205, Data = ce96ca9d
|
# tb_core.u_sdram32 : at time 54027.0 ns WRITE: Bank = 3 Row = 643, Col = 205, Data = ce96ca9d
|
# Status: Burst-No: 2 Write Address: 00283f2f WriteData: ce96ca9d
|
# Status: Burst-No: 2 Write Address: 00283f2f WriteData: ce96ca9d
|
# tb_core.u_sdram32 : at time 52837.0 ns WRITE: Bank = 3 Row = 643, Col = 206, Data = e02148c0
|
# tb_core.u_sdram32 : at time 54037.0 ns WRITE: Bank = 3 Row = 643, Col = 206, Data = e02148c0
|
# Status: Burst-No: 3 Write Address: 00283f2f WriteData: e02148c0
|
# Status: Burst-No: 3 Write Address: 00283f2f WriteData: e02148c0
|
# tb_core.u_sdram32 : at time 52847.0 ns WRITE: Bank = 3 Row = 643, Col = 207, Data = 71a919e3
|
# tb_core.u_sdram32 : at time 54047.0 ns WRITE: Bank = 3 Row = 643, Col = 207, Data = 71a919e3
|
# Status: Burst-No: 4 Write Address: 00283f2f WriteData: 71a919e3
|
# Status: Burst-No: 4 Write Address: 00283f2f WriteData: 71a919e3
|
# tb_core.u_sdram32 : at time 52857.0 ns WRITE: Bank = 3 Row = 643, Col = 208, Data = b24cf664
|
# tb_core.u_sdram32 : at time 54057.0 ns WRITE: Bank = 3 Row = 643, Col = 208, Data = b24cf664
|
# Status: Burst-No: 5 Write Address: 00283f2f WriteData: b24cf664
|
# Status: Burst-No: 5 Write Address: 00283f2f WriteData: b24cf664
|
# tb_core.u_sdram32 : at time 52867.0 ns WRITE: Bank = 3 Row = 643, Col = 209, Data = a5d9704b
|
# tb_core.u_sdram32 : at time 54067.0 ns WRITE: Bank = 3 Row = 643, Col = 209, Data = a5d9704b
|
# Status: Burst-No: 6 Write Address: 00283f2f WriteData: a5d9704b
|
# Status: Burst-No: 6 Write Address: 00283f2f WriteData: a5d9704b
|
# tb_core.u_sdram32 : at time 52877.0 ns WRITE: Bank = 3 Row = 643, Col = 210, Data = 48e9ff91
|
# tb_core.u_sdram32 : at time 54077.0 ns WRITE: Bank = 3 Row = 643, Col = 210, Data = 48e9ff91
|
# Status: Burst-No: 7 Write Address: 00283f2f WriteData: 48e9ff91
|
# Status: Burst-No: 7 Write Address: 00283f2f WriteData: 48e9ff91
|
# tb_core.u_sdram32 : at time 52887.0 ns WRITE: Bank = 3 Row = 643, Col = 211, Data = 4277d784
|
# tb_core.u_sdram32 : at time 54087.0 ns WRITE: Bank = 3 Row = 643, Col = 211, Data = 4277d784
|
# Status: Burst-No: 8 Write Address: 00283f2f WriteData: 4277d784
|
# Status: Burst-No: 8 Write Address: 00283f2f WriteData: 4277d784
|
# tb_core.u_sdram32 : at time 52897.0 ns WRITE: Bank = 3 Row = 643, Col = 212, Data = 24d44749
|
# tb_core.u_sdram32 : at time 54097.0 ns WRITE: Bank = 3 Row = 643, Col = 212, Data = 24d44749
|
# Status: Burst-No: 9 Write Address: 00283f2f WriteData: 24d44749
|
# Status: Burst-No: 9 Write Address: 00283f2f WriteData: 24d44749
|
# tb_core.u_sdram32 : at time 52907.0 ns WRITE: Bank = 3 Row = 643, Col = 213, Data = 89de2c13
|
# tb_core.u_sdram32 : at time 54107.0 ns WRITE: Bank = 3 Row = 643, Col = 213, Data = 89de2c13
|
# Status: Burst-No: 10 Write Address: 00283f2f WriteData: 89de2c13
|
# Status: Burst-No: 10 Write Address: 00283f2f WriteData: 89de2c13
|
# tb_core.u_sdram32 : at time 52917.0 ns WRITE: Bank = 3 Row = 643, Col = 214, Data = d9f8e0b3
|
# tb_core.u_sdram32 : at time 54117.0 ns WRITE: Bank = 3 Row = 643, Col = 214, Data = d9f8e0b3
|
# Status: Burst-No: 11 Write Address: 00283f2f WriteData: d9f8e0b3
|
# Status: Burst-No: 11 Write Address: 00283f2f WriteData: d9f8e0b3
|
# tb_core.u_sdram32 : at time 52927.0 ns WRITE: Bank = 3 Row = 643, Col = 215, Data = 0e62911c
|
# tb_core.u_sdram32 : at time 54127.0 ns WRITE: Bank = 3 Row = 643, Col = 215, Data = 0e62911c
|
# Status: Burst-No: 12 Write Address: 00283f2f WriteData: 0e62911c
|
# Status: Burst-No: 12 Write Address: 00283f2f WriteData: 0e62911c
|
# tb_core.u_sdram32 : at time 52937.0 ns WRITE: Bank = 3 Row = 643, Col = 216, Data = 144ced28
|
# tb_core.u_sdram32 : at time 54137.0 ns WRITE: Bank = 3 Row = 643, Col = 216, Data = 144ced28
|
# Status: Burst-No: 13 Write Address: 00283f2f WriteData: 144ced28
|
# Status: Burst-No: 13 Write Address: 00283f2f WriteData: 144ced28
|
# tb_core.u_sdram32 : at time 52947.0 ns WRITE: Bank = 3 Row = 643, Col = 217, Data = 1568bb2a
|
# tb_core.u_sdram32 : at time 54147.0 ns WRITE: Bank = 3 Row = 643, Col = 217, Data = 1568bb2a
|
# Status: Burst-No: 14 Write Address: 00283f2f WriteData: 1568bb2a
|
# Status: Burst-No: 14 Write Address: 00283f2f WriteData: 1568bb2a
|
# tb_core.u_sdram32 : at time 52957.0 ns WRITE: Bank = 3 Row = 643, Col = 218, Data = 2e97795d
|
# tb_core.u_sdram32 : at time 54157.0 ns WRITE: Bank = 3 Row = 643, Col = 218, Data = 2e97795d
|
# Status: Burst-No: 15 Write Address: 00283f2f WriteData: 2e97795d
|
# Status: Burst-No: 15 Write Address: 00283f2f WriteData: 2e97795d
|
# tb_core.u_sdram32 : at time 52967.0 ns WRITE: Bank = 3 Row = 643, Col = 219, Data = 776a61ee
|
# tb_core.u_sdram32 : at time 54167.0 ns WRITE: Bank = 3 Row = 643, Col = 219, Data = 776a61ee
|
# Status: Burst-No: 16 Write Address: 00283f2f WriteData: 776a61ee
|
# Status: Burst-No: 16 Write Address: 00283f2f WriteData: 776a61ee
|
# tb_core.u_sdram32 : at time 52977.0 ns WRITE: Bank = 3 Row = 643, Col = 220, Data = 66065bcc
|
# tb_core.u_sdram32 : at time 54177.0 ns WRITE: Bank = 3 Row = 643, Col = 220, Data = 66065bcc
|
# Status: Burst-No: 17 Write Address: 00283f2f WriteData: 66065bcc
|
# Status: Burst-No: 17 Write Address: 00283f2f WriteData: 66065bcc
|
# tb_core.u_sdram32 : at time 52987.0 ns WRITE: Bank = 3 Row = 643, Col = 221, Data = 5d8e95bb
|
# tb_core.u_sdram32 : at time 54187.0 ns WRITE: Bank = 3 Row = 643, Col = 221, Data = 5d8e95bb
|
# Status: Burst-No: 18 Write Address: 00283f2f WriteData: 5d8e95bb
|
# Status: Burst-No: 18 Write Address: 00283f2f WriteData: 5d8e95bb
|
# tb_core.u_sdram32 : at time 52997.0 ns WRITE: Bank = 3 Row = 643, Col = 222, Data = bc461478
|
# tb_core.u_sdram32 : at time 54197.0 ns WRITE: Bank = 3 Row = 643, Col = 222, Data = bc461478
|
# Status: Burst-No: 19 Write Address: 00283f2f WriteData: bc461478
|
# Status: Burst-No: 19 Write Address: 00283f2f WriteData: bc461478
|
# tb_core.u_sdram32 : at time 53007.0 ns WRITE: Bank = 3 Row = 643, Col = 223, Data = 652825ca
|
# tb_core.u_sdram32 : at time 54207.0 ns WRITE: Bank = 3 Row = 643, Col = 223, Data = 652825ca
|
# Status: Burst-No: 20 Write Address: 00283f2f WriteData: 652825ca
|
# Status: Burst-No: 20 Write Address: 00283f2f WriteData: 652825ca
|
# tb_core.u_sdram32 : at time 53017.0 ns WRITE: Bank = 3 Row = 643, Col = 224, Data = 2e94b75d
|
# tb_core.u_sdram32 : at time 54217.0 ns WRITE: Bank = 3 Row = 643, Col = 224, Data = 2e94b75d
|
# Status: Burst-No: 21 Write Address: 00283f2f WriteData: 2e94b75d
|
# Status: Burst-No: 21 Write Address: 00283f2f WriteData: 2e94b75d
|
# tb_core.u_sdram32 : at time 53027.0 ns WRITE: Bank = 3 Row = 643, Col = 225, Data = 8f32fa1e
|
# tb_core.u_sdram32 : at time 54227.0 ns WRITE: Bank = 3 Row = 643, Col = 225, Data = 8f32fa1e
|
# Status: Burst-No: 22 Write Address: 00283f2f WriteData: 8f32fa1e
|
# Status: Burst-No: 22 Write Address: 00283f2f WriteData: 8f32fa1e
|
# tb_core.u_sdram32 : at time 53037.0 ns WRITE: Bank = 3 Row = 643, Col = 226, Data = 3b07bd76
|
# tb_core.u_sdram32 : at time 54237.0 ns WRITE: Bank = 3 Row = 643, Col = 226, Data = 3b07bd76
|
# Status: Burst-No: 23 Write Address: 00283f2f WriteData: 3b07bd76
|
# Status: Burst-No: 23 Write Address: 00283f2f WriteData: 3b07bd76
|
# tb_core.u_sdram32 : at time 53047.0 ns WRITE: Bank = 3 Row = 643, Col = 227, Data = 65a879cb
|
# tb_core.u_sdram32 : at time 54247.0 ns WRITE: Bank = 3 Row = 643, Col = 227, Data = 65a879cb
|
# Status: Burst-No: 24 Write Address: 00283f2f WriteData: 65a879cb
|
# Status: Burst-No: 24 Write Address: 00283f2f WriteData: 65a879cb
|
# tb_core.u_sdram32 : at time 53057.0 ns WRITE: Bank = 3 Row = 643, Col = 228, Data = 6dfcf1db
|
# tb_core.u_sdram32 : at time 54257.0 ns WRITE: Bank = 3 Row = 643, Col = 228, Data = 6dfcf1db
|
# Status: Burst-No: 25 Write Address: 00283f2f WriteData: 6dfcf1db
|
# Status: Burst-No: 25 Write Address: 00283f2f WriteData: 6dfcf1db
|
# tb_core.u_sdram32 : at time 53067.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 54267.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 53203.0 ns READ : Bank = 2 Row = 406, Col = 28, Data = 4b2f0596
|
# tb_core.u_sdram32 : at time 54403.0 ns READ : Bank = 2 Row = 406, Col = 28, Data = 4b2f0596
|
# tb_core.u_sdram32 : at time 53213.0 ns READ : Bank = 2 Row = 406, Col = 29, Data = 9a544234
|
# tb_core.u_sdram32 : at time 54413.0 ns READ : Bank = 2 Row = 406, Col = 29, Data = 9a544234
|
# READ STATUS: Burst-No: 0 Addr: 00196873 Rxd: 4b2f0596
|
# READ STATUS: Burst-No: 0 Addr: 00196873 Rxd: 4b2f0596
|
# tb_core.u_sdram32 : at time 53223.0 ns READ : Bank = 2 Row = 406, Col = 30, Data = 1e85ed3d
|
# tb_core.u_sdram32 : at time 54423.0 ns READ : Bank = 2 Row = 406, Col = 30, Data = 1e85ed3d
|
# READ STATUS: Burst-No: 1 Addr: 00196875 Rxd: 9a544234
|
# READ STATUS: Burst-No: 1 Addr: 00196875 Rxd: 9a544234
|
# tb_core.u_sdram32 : at time 53233.0 ns READ : Bank = 2 Row = 406, Col = 31, Data = 28b1f151
|
# tb_core.u_sdram32 : at time 54433.0 ns READ : Bank = 2 Row = 406, Col = 31, Data = 28b1f151
|
# READ STATUS: Burst-No: 2 Addr: 00196877 Rxd: 1e85ed3d
|
# READ STATUS: Burst-No: 2 Addr: 00196877 Rxd: 1e85ed3d
|
# tb_core.u_sdram32 : at time 53243.0 ns READ : Bank = 2 Row = 406, Col = 32, Data = 8db0281b
|
# tb_core.u_sdram32 : at time 54443.0 ns READ : Bank = 2 Row = 406, Col = 32, Data = 8db0281b
|
# READ STATUS: Burst-No: 3 Addr: 00196879 Rxd: 28b1f151
|
# READ STATUS: Burst-No: 3 Addr: 00196879 Rxd: 28b1f151
|
# tb_core.u_sdram32 : at time 53253.0 ns READ : Bank = 2 Row = 406, Col = 33, Data = 8e39901c
|
# tb_core.u_sdram32 : at time 54453.0 ns READ : Bank = 2 Row = 406, Col = 33, Data = 8e39901c
|
# READ STATUS: Burst-No: 4 Addr: 0019687b Rxd: 8db0281b
|
# READ STATUS: Burst-No: 4 Addr: 0019687b Rxd: 8db0281b
|
# tb_core.u_sdram32 : at time 53263.0 ns READ : Bank = 2 Row = 406, Col = 34, Data = 5ec5ebbd
|
# tb_core.u_sdram32 : at time 54463.0 ns READ : Bank = 2 Row = 406, Col = 34, Data = 5ec5ebbd
|
# tb_core.u_sdram32 : at time 53267.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 54467.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 5 Addr: 0019687d Rxd: 8e39901c
|
# READ STATUS: Burst-No: 5 Addr: 0019687d Rxd: 8e39901c
|
# tb_core.u_sdram32 : at time 53273.0 ns READ : Bank = 2 Row = 406, Col = 35, Data = da69e2b4
|
# tb_core.u_sdram32 : at time 54473.0 ns READ : Bank = 2 Row = 406, Col = 35, Data = da69e2b4
|
# READ STATUS: Burst-No: 6 Addr: 0019687f Rxd: 5ec5ebbd
|
# READ STATUS: Burst-No: 6 Addr: 0019687f Rxd: 5ec5ebbd
|
# tb_core.u_sdram32 : at time 53283.0 ns READ : Bank = 2 Row = 406, Col = 36, Data = 2764754e
|
# tb_core.u_sdram32 : at time 54483.0 ns READ : Bank = 2 Row = 406, Col = 36, Data = 2764754e
|
# READ STATUS: Burst-No: 7 Addr: 00196881 Rxd: da69e2b4
|
# READ STATUS: Burst-No: 7 Addr: 00196881 Rxd: da69e2b4
|
# READ STATUS: Burst-No: 8 Addr: 00196883 Rxd: 2764754e
|
# READ STATUS: Burst-No: 8 Addr: 00196883 Rxd: 2764754e
|
# tb_core.u_sdram32 : at time 53453.0 ns READ : Bank = 3 Row = 643, Col = 203, Data = f670fcec
|
# tb_core.u_sdram32 : at time 54653.0 ns READ : Bank = 3 Row = 643, Col = 203, Data = f670fcec
|
# tb_core.u_sdram32 : at time 53463.0 ns READ : Bank = 3 Row = 643, Col = 204, Data = 0f40551e
|
# tb_core.u_sdram32 : at time 54663.0 ns READ : Bank = 3 Row = 643, Col = 204, Data = 0f40551e
|
# READ STATUS: Burst-No: 0 Addr: 00283f2f Rxd: f670fcec
|
# READ STATUS: Burst-No: 0 Addr: 00283f2f Rxd: f670fcec
|
# tb_core.u_sdram32 : at time 53473.0 ns READ : Bank = 3 Row = 643, Col = 205, Data = ce96ca9d
|
# tb_core.u_sdram32 : at time 54673.0 ns READ : Bank = 3 Row = 643, Col = 205, Data = ce96ca9d
|
# READ STATUS: Burst-No: 1 Addr: 00283f31 Rxd: 0f40551e
|
# READ STATUS: Burst-No: 1 Addr: 00283f31 Rxd: 0f40551e
|
# tb_core.u_sdram32 : at time 53483.0 ns READ : Bank = 3 Row = 643, Col = 206, Data = e02148c0
|
# tb_core.u_sdram32 : at time 54683.0 ns READ : Bank = 3 Row = 643, Col = 206, Data = e02148c0
|
# READ STATUS: Burst-No: 2 Addr: 00283f33 Rxd: ce96ca9d
|
# READ STATUS: Burst-No: 2 Addr: 00283f33 Rxd: ce96ca9d
|
# tb_core.u_sdram32 : at time 53493.0 ns READ : Bank = 3 Row = 643, Col = 207, Data = 71a919e3
|
# tb_core.u_sdram32 : at time 54693.0 ns READ : Bank = 3 Row = 643, Col = 207, Data = 71a919e3
|
# READ STATUS: Burst-No: 3 Addr: 00283f35 Rxd: e02148c0
|
# READ STATUS: Burst-No: 3 Addr: 00283f35 Rxd: e02148c0
|
# tb_core.u_sdram32 : at time 53503.0 ns READ : Bank = 3 Row = 643, Col = 208, Data = b24cf664
|
# tb_core.u_sdram32 : at time 54703.0 ns READ : Bank = 3 Row = 643, Col = 208, Data = b24cf664
|
# READ STATUS: Burst-No: 4 Addr: 00283f37 Rxd: 71a919e3
|
# READ STATUS: Burst-No: 4 Addr: 00283f37 Rxd: 71a919e3
|
# tb_core.u_sdram32 : at time 53513.0 ns READ : Bank = 3 Row = 643, Col = 209, Data = a5d9704b
|
# tb_core.u_sdram32 : at time 54713.0 ns READ : Bank = 3 Row = 643, Col = 209, Data = a5d9704b
|
# READ STATUS: Burst-No: 5 Addr: 00283f39 Rxd: b24cf664
|
# READ STATUS: Burst-No: 5 Addr: 00283f39 Rxd: b24cf664
|
# tb_core.u_sdram32 : at time 53523.0 ns READ : Bank = 3 Row = 643, Col = 210, Data = 48e9ff91
|
# tb_core.u_sdram32 : at time 54723.0 ns READ : Bank = 3 Row = 643, Col = 210, Data = 48e9ff91
|
# READ STATUS: Burst-No: 6 Addr: 00283f3b Rxd: a5d9704b
|
# READ STATUS: Burst-No: 6 Addr: 00283f3b Rxd: a5d9704b
|
# tb_core.u_sdram32 : at time 53533.0 ns READ : Bank = 3 Row = 643, Col = 211, Data = 4277d784
|
# tb_core.u_sdram32 : at time 54733.0 ns READ : Bank = 3 Row = 643, Col = 211, Data = 4277d784
|
# READ STATUS: Burst-No: 7 Addr: 00283f3d Rxd: 48e9ff91
|
# READ STATUS: Burst-No: 7 Addr: 00283f3d Rxd: 48e9ff91
|
# tb_core.u_sdram32 : at time 53543.0 ns READ : Bank = 3 Row = 643, Col = 212, Data = 24d44749
|
# tb_core.u_sdram32 : at time 54743.0 ns READ : Bank = 3 Row = 643, Col = 212, Data = 24d44749
|
# READ STATUS: Burst-No: 8 Addr: 00283f3f Rxd: 4277d784
|
# READ STATUS: Burst-No: 8 Addr: 00283f3f Rxd: 4277d784
|
# tb_core.u_sdram32 : at time 53553.0 ns READ : Bank = 3 Row = 643, Col = 213, Data = 89de2c13
|
# tb_core.u_sdram32 : at time 54753.0 ns READ : Bank = 3 Row = 643, Col = 213, Data = 89de2c13
|
# READ STATUS: Burst-No: 9 Addr: 00283f41 Rxd: 24d44749
|
# READ STATUS: Burst-No: 9 Addr: 00283f41 Rxd: 24d44749
|
# tb_core.u_sdram32 : at time 53563.0 ns READ : Bank = 3 Row = 643, Col = 214, Data = d9f8e0b3
|
# tb_core.u_sdram32 : at time 54763.0 ns READ : Bank = 3 Row = 643, Col = 214, Data = d9f8e0b3
|
# READ STATUS: Burst-No: 10 Addr: 00283f43 Rxd: 89de2c13
|
# READ STATUS: Burst-No: 10 Addr: 00283f43 Rxd: 89de2c13
|
# tb_core.u_sdram32 : at time 53573.0 ns READ : Bank = 3 Row = 643, Col = 215, Data = 0e62911c
|
# tb_core.u_sdram32 : at time 54773.0 ns READ : Bank = 3 Row = 643, Col = 215, Data = 0e62911c
|
# READ STATUS: Burst-No: 11 Addr: 00283f45 Rxd: d9f8e0b3
|
# READ STATUS: Burst-No: 11 Addr: 00283f45 Rxd: d9f8e0b3
|
# tb_core.u_sdram32 : at time 53583.0 ns READ : Bank = 3 Row = 643, Col = 216, Data = 144ced28
|
# tb_core.u_sdram32 : at time 54783.0 ns READ : Bank = 3 Row = 643, Col = 216, Data = 144ced28
|
# READ STATUS: Burst-No: 12 Addr: 00283f47 Rxd: 0e62911c
|
# READ STATUS: Burst-No: 12 Addr: 00283f47 Rxd: 0e62911c
|
# tb_core.u_sdram32 : at time 53593.0 ns READ : Bank = 3 Row = 643, Col = 217, Data = 1568bb2a
|
# tb_core.u_sdram32 : at time 54793.0 ns READ : Bank = 3 Row = 643, Col = 217, Data = 1568bb2a
|
# READ STATUS: Burst-No: 13 Addr: 00283f49 Rxd: 144ced28
|
# READ STATUS: Burst-No: 13 Addr: 00283f49 Rxd: 144ced28
|
# tb_core.u_sdram32 : at time 53603.0 ns READ : Bank = 3 Row = 643, Col = 218, Data = 2e97795d
|
# tb_core.u_sdram32 : at time 54803.0 ns READ : Bank = 3 Row = 643, Col = 218, Data = 2e97795d
|
# READ STATUS: Burst-No: 14 Addr: 00283f4b Rxd: 1568bb2a
|
# READ STATUS: Burst-No: 14 Addr: 00283f4b Rxd: 1568bb2a
|
# tb_core.u_sdram32 : at time 53613.0 ns READ : Bank = 3 Row = 643, Col = 219, Data = 776a61ee
|
# tb_core.u_sdram32 : at time 54813.0 ns READ : Bank = 3 Row = 643, Col = 219, Data = 776a61ee
|
# READ STATUS: Burst-No: 15 Addr: 00283f4d Rxd: 2e97795d
|
# READ STATUS: Burst-No: 15 Addr: 00283f4d Rxd: 2e97795d
|
# tb_core.u_sdram32 : at time 53623.0 ns READ : Bank = 3 Row = 643, Col = 220, Data = 66065bcc
|
# tb_core.u_sdram32 : at time 54823.0 ns READ : Bank = 3 Row = 643, Col = 220, Data = 66065bcc
|
# READ STATUS: Burst-No: 16 Addr: 00283f4f Rxd: 776a61ee
|
# READ STATUS: Burst-No: 16 Addr: 00283f4f Rxd: 776a61ee
|
# tb_core.u_sdram32 : at time 53633.0 ns READ : Bank = 3 Row = 643, Col = 221, Data = 5d8e95bb
|
# tb_core.u_sdram32 : at time 54833.0 ns READ : Bank = 3 Row = 643, Col = 221, Data = 5d8e95bb
|
# READ STATUS: Burst-No: 17 Addr: 00283f51 Rxd: 66065bcc
|
# READ STATUS: Burst-No: 17 Addr: 00283f51 Rxd: 66065bcc
|
# tb_core.u_sdram32 : at time 53643.0 ns READ : Bank = 3 Row = 643, Col = 222, Data = bc461478
|
# tb_core.u_sdram32 : at time 54843.0 ns READ : Bank = 3 Row = 643, Col = 222, Data = bc461478
|
# READ STATUS: Burst-No: 18 Addr: 00283f53 Rxd: 5d8e95bb
|
# READ STATUS: Burst-No: 18 Addr: 00283f53 Rxd: 5d8e95bb
|
# tb_core.u_sdram32 : at time 53653.0 ns READ : Bank = 3 Row = 643, Col = 223, Data = 652825ca
|
# tb_core.u_sdram32 : at time 54853.0 ns READ : Bank = 3 Row = 643, Col = 223, Data = 652825ca
|
# READ STATUS: Burst-No: 19 Addr: 00283f55 Rxd: bc461478
|
# READ STATUS: Burst-No: 19 Addr: 00283f55 Rxd: bc461478
|
# tb_core.u_sdram32 : at time 53663.0 ns READ : Bank = 3 Row = 643, Col = 224, Data = 2e94b75d
|
# tb_core.u_sdram32 : at time 54863.0 ns READ : Bank = 3 Row = 643, Col = 224, Data = 2e94b75d
|
# READ STATUS: Burst-No: 20 Addr: 00283f57 Rxd: 652825ca
|
# READ STATUS: Burst-No: 20 Addr: 00283f57 Rxd: 652825ca
|
# tb_core.u_sdram32 : at time 53673.0 ns READ : Bank = 3 Row = 643, Col = 225, Data = 8f32fa1e
|
# tb_core.u_sdram32 : at time 54873.0 ns READ : Bank = 3 Row = 643, Col = 225, Data = 8f32fa1e
|
# READ STATUS: Burst-No: 21 Addr: 00283f59 Rxd: 2e94b75d
|
# READ STATUS: Burst-No: 21 Addr: 00283f59 Rxd: 2e94b75d
|
# tb_core.u_sdram32 : at time 53683.0 ns READ : Bank = 3 Row = 643, Col = 226, Data = 3b07bd76
|
# tb_core.u_sdram32 : at time 54883.0 ns READ : Bank = 3 Row = 643, Col = 226, Data = 3b07bd76
|
# tb_core.u_sdram32 : at time 53687.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 54887.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 22 Addr: 00283f5b Rxd: 8f32fa1e
|
# READ STATUS: Burst-No: 22 Addr: 00283f5b Rxd: 8f32fa1e
|
# tb_core.u_sdram32 : at time 53693.0 ns READ : Bank = 3 Row = 643, Col = 227, Data = 65a879cb
|
# tb_core.u_sdram32 : at time 54893.0 ns READ : Bank = 3 Row = 643, Col = 227, Data = 65a879cb
|
# READ STATUS: Burst-No: 23 Addr: 00283f5d Rxd: 3b07bd76
|
# READ STATUS: Burst-No: 23 Addr: 00283f5d Rxd: 3b07bd76
|
# tb_core.u_sdram32 : at time 53703.0 ns READ : Bank = 3 Row = 643, Col = 228, Data = 6dfcf1db
|
# tb_core.u_sdram32 : at time 54903.0 ns READ : Bank = 3 Row = 643, Col = 228, Data = 6dfcf1db
|
# READ STATUS: Burst-No: 24 Addr: 00283f5f Rxd: 65a879cb
|
# READ STATUS: Burst-No: 24 Addr: 00283f5f Rxd: 65a879cb
|
# READ STATUS: Burst-No: 25 Addr: 00283f61 Rxd: 6dfcf1db
|
# READ STATUS: Burst-No: 25 Addr: 00283f61 Rxd: 6dfcf1db
|
# Write Address: 0002e4b4, Burst Size: 33
|
# Write Address: 0002e4b4, Burst Size: 33
|
# tb_core.u_sdram32 : at time 53877.0 ns ACT : Bank = 1 Row = 46
|
# tb_core.u_sdram32 : at time 55077.0 ns ACT : Bank = 1 Row = 46
|
# tb_core.u_sdram32 : at time 53907.0 ns WRITE: Bank = 1 Row = 46, Col = 45, Data = 0207bb04
|
# tb_core.u_sdram32 : at time 55107.0 ns WRITE: Bank = 1 Row = 46, Col = 45, Data = 0207bb04
|
# Status: Burst-No: 0 Write Address: 0002e4b4 WriteData: 0207bb04
|
# Status: Burst-No: 0 Write Address: 0002e4b4 WriteData: 0207bb04
|
# tb_core.u_sdram32 : at time 53917.0 ns WRITE: Bank = 1 Row = 46, Col = 46, Data = bca0b279
|
# tb_core.u_sdram32 : at time 55117.0 ns WRITE: Bank = 1 Row = 46, Col = 46, Data = bca0b279
|
# Status: Burst-No: 1 Write Address: 0002e4b4 WriteData: bca0b279
|
# Status: Burst-No: 1 Write Address: 0002e4b4 WriteData: bca0b279
|
# tb_core.u_sdram32 : at time 53927.0 ns WRITE: Bank = 1 Row = 46, Col = 47, Data = e6b110cd
|
# tb_core.u_sdram32 : at time 55127.0 ns WRITE: Bank = 1 Row = 46, Col = 47, Data = e6b110cd
|
# Status: Burst-No: 2 Write Address: 0002e4b4 WriteData: e6b110cd
|
# Status: Burst-No: 2 Write Address: 0002e4b4 WriteData: e6b110cd
|
# tb_core.u_sdram32 : at time 53937.0 ns WRITE: Bank = 1 Row = 46, Col = 48, Data = c9662c92
|
# tb_core.u_sdram32 : at time 55137.0 ns WRITE: Bank = 1 Row = 46, Col = 48, Data = c9662c92
|
# Status: Burst-No: 3 Write Address: 0002e4b4 WriteData: c9662c92
|
# Status: Burst-No: 3 Write Address: 0002e4b4 WriteData: c9662c92
|
# tb_core.u_sdram32 : at time 53947.0 ns WRITE: Bank = 1 Row = 46, Col = 49, Data = a2ce0045
|
# tb_core.u_sdram32 : at time 55147.0 ns WRITE: Bank = 1 Row = 46, Col = 49, Data = a2ce0045
|
# Status: Burst-No: 4 Write Address: 0002e4b4 WriteData: a2ce0045
|
# Status: Burst-No: 4 Write Address: 0002e4b4 WriteData: a2ce0045
|
# tb_core.u_sdram32 : at time 53957.0 ns WRITE: Bank = 1 Row = 46, Col = 50, Data = d4ea6aa9
|
# tb_core.u_sdram32 : at time 55157.0 ns WRITE: Bank = 1 Row = 46, Col = 50, Data = d4ea6aa9
|
# Status: Burst-No: 5 Write Address: 0002e4b4 WriteData: d4ea6aa9
|
# Status: Burst-No: 5 Write Address: 0002e4b4 WriteData: d4ea6aa9
|
# tb_core.u_sdram32 : at time 53967.0 ns WRITE: Bank = 1 Row = 46, Col = 51, Data = cf31fc9e
|
# tb_core.u_sdram32 : at time 55167.0 ns WRITE: Bank = 1 Row = 46, Col = 51, Data = cf31fc9e
|
# Status: Burst-No: 6 Write Address: 0002e4b4 WriteData: cf31fc9e
|
# Status: Burst-No: 6 Write Address: 0002e4b4 WriteData: cf31fc9e
|
# tb_core.u_sdram32 : at time 53977.0 ns WRITE: Bank = 1 Row = 46, Col = 52, Data = 6ec2cbdd
|
# tb_core.u_sdram32 : at time 55177.0 ns WRITE: Bank = 1 Row = 46, Col = 52, Data = 6ec2cbdd
|
# Status: Burst-No: 7 Write Address: 0002e4b4 WriteData: 6ec2cbdd
|
# Status: Burst-No: 7 Write Address: 0002e4b4 WriteData: 6ec2cbdd
|
# tb_core.u_sdram32 : at time 53987.0 ns WRITE: Bank = 1 Row = 46, Col = 53, Data = 600b2dc0
|
# tb_core.u_sdram32 : at time 55187.0 ns WRITE: Bank = 1 Row = 46, Col = 53, Data = 600b2dc0
|
# Status: Burst-No: 8 Write Address: 0002e4b4 WriteData: 600b2dc0
|
# Status: Burst-No: 8 Write Address: 0002e4b4 WriteData: 600b2dc0
|
# tb_core.u_sdram32 : at time 53997.0 ns WRITE: Bank = 1 Row = 46, Col = 54, Data = a5b9424b
|
# tb_core.u_sdram32 : at time 55197.0 ns WRITE: Bank = 1 Row = 46, Col = 54, Data = a5b9424b
|
# Status: Burst-No: 9 Write Address: 0002e4b4 WriteData: a5b9424b
|
# Status: Burst-No: 9 Write Address: 0002e4b4 WriteData: a5b9424b
|
# tb_core.u_sdram32 : at time 54007.0 ns WRITE: Bank = 1 Row = 46, Col = 55, Data = 5db7e1bb
|
# tb_core.u_sdram32 : at time 55207.0 ns WRITE: Bank = 1 Row = 46, Col = 55, Data = 5db7e1bb
|
# Status: Burst-No: 10 Write Address: 0002e4b4 WriteData: 5db7e1bb
|
# Status: Burst-No: 10 Write Address: 0002e4b4 WriteData: 5db7e1bb
|
# tb_core.u_sdram32 : at time 54017.0 ns WRITE: Bank = 1 Row = 46, Col = 56, Data = 408a2981
|
# tb_core.u_sdram32 : at time 55217.0 ns WRITE: Bank = 1 Row = 46, Col = 56, Data = 408a2981
|
# Status: Burst-No: 11 Write Address: 0002e4b4 WriteData: 408a2981
|
# Status: Burst-No: 11 Write Address: 0002e4b4 WriteData: 408a2981
|
# tb_core.u_sdram32 : at time 54027.0 ns WRITE: Bank = 1 Row = 46, Col = 57, Data = d932d8b2
|
# tb_core.u_sdram32 : at time 55227.0 ns WRITE: Bank = 1 Row = 46, Col = 57, Data = d932d8b2
|
# Status: Burst-No: 12 Write Address: 0002e4b4 WriteData: d932d8b2
|
# Status: Burst-No: 12 Write Address: 0002e4b4 WriteData: d932d8b2
|
# tb_core.u_sdram32 : at time 54037.0 ns WRITE: Bank = 1 Row = 46, Col = 58, Data = 598d27b3
|
# tb_core.u_sdram32 : at time 55237.0 ns WRITE: Bank = 1 Row = 46, Col = 58, Data = 598d27b3
|
# Status: Burst-No: 13 Write Address: 0002e4b4 WriteData: 598d27b3
|
# Status: Burst-No: 13 Write Address: 0002e4b4 WriteData: 598d27b3
|
# tb_core.u_sdram32 : at time 54047.0 ns WRITE: Bank = 1 Row = 46, Col = 59, Data = 05aeb90b
|
# tb_core.u_sdram32 : at time 55247.0 ns WRITE: Bank = 1 Row = 46, Col = 59, Data = 05aeb90b
|
# Status: Burst-No: 14 Write Address: 0002e4b4 WriteData: 05aeb90b
|
# Status: Burst-No: 14 Write Address: 0002e4b4 WriteData: 05aeb90b
|
# tb_core.u_sdram32 : at time 54057.0 ns WRITE: Bank = 1 Row = 46, Col = 60, Data = 24011148
|
# tb_core.u_sdram32 : at time 55257.0 ns WRITE: Bank = 1 Row = 46, Col = 60, Data = 24011148
|
# Status: Burst-No: 15 Write Address: 0002e4b4 WriteData: 24011148
|
# Status: Burst-No: 15 Write Address: 0002e4b4 WriteData: 24011148
|
# tb_core.u_sdram32 : at time 54067.0 ns WRITE: Bank = 1 Row = 46, Col = 61, Data = f0b860e1
|
# tb_core.u_sdram32 : at time 55267.0 ns WRITE: Bank = 1 Row = 46, Col = 61, Data = f0b860e1
|
# Status: Burst-No: 16 Write Address: 0002e4b4 WriteData: f0b860e1
|
# Status: Burst-No: 16 Write Address: 0002e4b4 WriteData: f0b860e1
|
# tb_core.u_sdram32 : at time 54077.0 ns WRITE: Bank = 1 Row = 46, Col = 62, Data = 7e72c5fc
|
# tb_core.u_sdram32 : at time 55277.0 ns WRITE: Bank = 1 Row = 46, Col = 62, Data = 7e72c5fc
|
# Status: Burst-No: 17 Write Address: 0002e4b4 WriteData: 7e72c5fc
|
# Status: Burst-No: 17 Write Address: 0002e4b4 WriteData: 7e72c5fc
|
# tb_core.u_sdram32 : at time 54087.0 ns WRITE: Bank = 1 Row = 46, Col = 63, Data = d7f844af
|
# tb_core.u_sdram32 : at time 55287.0 ns WRITE: Bank = 1 Row = 46, Col = 63, Data = d7f844af
|
# Status: Burst-No: 18 Write Address: 0002e4b4 WriteData: d7f844af
|
# Status: Burst-No: 18 Write Address: 0002e4b4 WriteData: d7f844af
|
# tb_core.u_sdram32 : at time 54097.0 ns WRITE: Bank = 1 Row = 46, Col = 64, Data = d0770ea0
|
# tb_core.u_sdram32 : at time 55297.0 ns WRITE: Bank = 1 Row = 46, Col = 64, Data = d0770ea0
|
# Status: Burst-No: 19 Write Address: 0002e4b4 WriteData: d0770ea0
|
# Status: Burst-No: 19 Write Address: 0002e4b4 WriteData: d0770ea0
|
# tb_core.u_sdram32 : at time 54107.0 ns WRITE: Bank = 1 Row = 46, Col = 65, Data = 076adf0e
|
# tb_core.u_sdram32 : at time 55307.0 ns WRITE: Bank = 1 Row = 46, Col = 65, Data = 076adf0e
|
# Status: Burst-No: 20 Write Address: 0002e4b4 WriteData: 076adf0e
|
# Status: Burst-No: 20 Write Address: 0002e4b4 WriteData: 076adf0e
|
# tb_core.u_sdram32 : at time 54117.0 ns WRITE: Bank = 1 Row = 46, Col = 66, Data = 3aaf8775
|
# tb_core.u_sdram32 : at time 55317.0 ns WRITE: Bank = 1 Row = 46, Col = 66, Data = 3aaf8775
|
# Status: Burst-No: 21 Write Address: 0002e4b4 WriteData: 3aaf8775
|
# Status: Burst-No: 21 Write Address: 0002e4b4 WriteData: 3aaf8775
|
# tb_core.u_sdram32 : at time 54127.0 ns WRITE: Bank = 1 Row = 46, Col = 67, Data = 6ca7ffd9
|
# tb_core.u_sdram32 : at time 55327.0 ns WRITE: Bank = 1 Row = 46, Col = 67, Data = 6ca7ffd9
|
# Status: Burst-No: 22 Write Address: 0002e4b4 WriteData: 6ca7ffd9
|
# Status: Burst-No: 22 Write Address: 0002e4b4 WriteData: 6ca7ffd9
|
# tb_core.u_sdram32 : at time 54137.0 ns WRITE: Bank = 1 Row = 46, Col = 68, Data = 86d26e0d
|
# tb_core.u_sdram32 : at time 55337.0 ns WRITE: Bank = 1 Row = 46, Col = 68, Data = 86d26e0d
|
# Status: Burst-No: 23 Write Address: 0002e4b4 WriteData: 86d26e0d
|
# Status: Burst-No: 23 Write Address: 0002e4b4 WriteData: 86d26e0d
|
# tb_core.u_sdram32 : at time 54147.0 ns WRITE: Bank = 1 Row = 46, Col = 69, Data = 13913127
|
# tb_core.u_sdram32 : at time 55347.0 ns WRITE: Bank = 1 Row = 46, Col = 69, Data = 13913127
|
# Status: Burst-No: 24 Write Address: 0002e4b4 WriteData: 13913127
|
# Status: Burst-No: 24 Write Address: 0002e4b4 WriteData: 13913127
|
# tb_core.u_sdram32 : at time 54157.0 ns WRITE: Bank = 1 Row = 46, Col = 70, Data = 3a2d9974
|
# tb_core.u_sdram32 : at time 55357.0 ns WRITE: Bank = 1 Row = 46, Col = 70, Data = 3a2d9974
|
# Status: Burst-No: 25 Write Address: 0002e4b4 WriteData: 3a2d9974
|
# Status: Burst-No: 25 Write Address: 0002e4b4 WriteData: 3a2d9974
|
# tb_core.u_sdram32 : at time 54167.0 ns WRITE: Bank = 1 Row = 46, Col = 71, Data = 7e7f21fc
|
# tb_core.u_sdram32 : at time 55367.0 ns WRITE: Bank = 1 Row = 46, Col = 71, Data = 7e7f21fc
|
# Status: Burst-No: 26 Write Address: 0002e4b4 WriteData: 7e7f21fc
|
# Status: Burst-No: 26 Write Address: 0002e4b4 WriteData: 7e7f21fc
|
# tb_core.u_sdram32 : at time 54177.0 ns WRITE: Bank = 1 Row = 46, Col = 72, Data = dfdc3ebf
|
# tb_core.u_sdram32 : at time 55377.0 ns WRITE: Bank = 1 Row = 46, Col = 72, Data = dfdc3ebf
|
# Status: Burst-No: 27 Write Address: 0002e4b4 WriteData: dfdc3ebf
|
# Status: Burst-No: 27 Write Address: 0002e4b4 WriteData: dfdc3ebf
|
# tb_core.u_sdram32 : at time 54187.0 ns WRITE: Bank = 1 Row = 46, Col = 73, Data = afc5f25f
|
# tb_core.u_sdram32 : at time 55387.0 ns WRITE: Bank = 1 Row = 46, Col = 73, Data = afc5f25f
|
# Status: Burst-No: 28 Write Address: 0002e4b4 WriteData: afc5f25f
|
# Status: Burst-No: 28 Write Address: 0002e4b4 WriteData: afc5f25f
|
# tb_core.u_sdram32 : at time 54197.0 ns WRITE: Bank = 1 Row = 46, Col = 74, Data = c0a7e881
|
# tb_core.u_sdram32 : at time 55397.0 ns WRITE: Bank = 1 Row = 46, Col = 74, Data = c0a7e881
|
# Status: Burst-No: 29 Write Address: 0002e4b4 WriteData: c0a7e881
|
# Status: Burst-No: 29 Write Address: 0002e4b4 WriteData: c0a7e881
|
# tb_core.u_sdram32 : at time 54207.0 ns WRITE: Bank = 1 Row = 46, Col = 75, Data = b428aa68
|
# tb_core.u_sdram32 : at time 55407.0 ns WRITE: Bank = 1 Row = 46, Col = 75, Data = b428aa68
|
# Status: Burst-No: 30 Write Address: 0002e4b4 WriteData: b428aa68
|
# Status: Burst-No: 30 Write Address: 0002e4b4 WriteData: b428aa68
|
# tb_core.u_sdram32 : at time 54217.0 ns WRITE: Bank = 1 Row = 46, Col = 76, Data = fd4c48fa
|
# tb_core.u_sdram32 : at time 55417.0 ns WRITE: Bank = 1 Row = 46, Col = 76, Data = fd4c48fa
|
# Status: Burst-No: 31 Write Address: 0002e4b4 WriteData: fd4c48fa
|
# Status: Burst-No: 31 Write Address: 0002e4b4 WriteData: fd4c48fa
|
# tb_core.u_sdram32 : at time 54227.0 ns WRITE: Bank = 1 Row = 46, Col = 77, Data = fd9380fb
|
# tb_core.u_sdram32 : at time 55427.0 ns WRITE: Bank = 1 Row = 46, Col = 77, Data = fd9380fb
|
# Status: Burst-No: 32 Write Address: 0002e4b4 WriteData: fd9380fb
|
# Status: Burst-No: 32 Write Address: 0002e4b4 WriteData: fd9380fb
|
# tb_core.u_sdram32 : at time 54237.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 55437.0 ns BST : Burst Terminate
|
# Write Address: 00162119, Burst Size: 39
|
# Write Address: 00162119, Burst Size: 39
|
# tb_core.u_sdram32 : at time 54377.0 ns ACT : Bank = 0 Row = 354
|
# tb_core.u_sdram32 : at time 55577.0 ns ACT : Bank = 0 Row = 354
|
# tb_core.u_sdram32 : at time 54407.0 ns WRITE: Bank = 0 Row = 354, Col = 70, Data = 29951b53
|
# tb_core.u_sdram32 : at time 55607.0 ns WRITE: Bank = 0 Row = 354, Col = 70, Data = 29951b53
|
# Status: Burst-No: 0 Write Address: 00162119 WriteData: 29951b53
|
# Status: Burst-No: 0 Write Address: 00162119 WriteData: 29951b53
|
# tb_core.u_sdram32 : at time 54417.0 ns WRITE: Bank = 0 Row = 354, Col = 71, Data = f7cff6ef
|
# tb_core.u_sdram32 : at time 55617.0 ns WRITE: Bank = 0 Row = 354, Col = 71, Data = f7cff6ef
|
# Status: Burst-No: 1 Write Address: 00162119 WriteData: f7cff6ef
|
# Status: Burst-No: 1 Write Address: 00162119 WriteData: f7cff6ef
|
# tb_core.u_sdram32 : at time 54427.0 ns WRITE: Bank = 0 Row = 354, Col = 72, Data = f6d8aeed
|
# tb_core.u_sdram32 : at time 55627.0 ns WRITE: Bank = 0 Row = 354, Col = 72, Data = f6d8aeed
|
# Status: Burst-No: 2 Write Address: 00162119 WriteData: f6d8aeed
|
# Status: Burst-No: 2 Write Address: 00162119 WriteData: f6d8aeed
|
# tb_core.u_sdram32 : at time 54437.0 ns WRITE: Bank = 0 Row = 354, Col = 73, Data = 58d79db1
|
# tb_core.u_sdram32 : at time 55637.0 ns WRITE: Bank = 0 Row = 354, Col = 73, Data = 58d79db1
|
# Status: Burst-No: 3 Write Address: 00162119 WriteData: 58d79db1
|
# Status: Burst-No: 3 Write Address: 00162119 WriteData: 58d79db1
|
# tb_core.u_sdram32 : at time 54447.0 ns WRITE: Bank = 0 Row = 354, Col = 74, Data = b26ffe64
|
# tb_core.u_sdram32 : at time 55647.0 ns WRITE: Bank = 0 Row = 354, Col = 74, Data = b26ffe64
|
# Status: Burst-No: 4 Write Address: 00162119 WriteData: b26ffe64
|
# Status: Burst-No: 4 Write Address: 00162119 WriteData: b26ffe64
|
# tb_core.u_sdram32 : at time 54457.0 ns WRITE: Bank = 0 Row = 354, Col = 75, Data = 90b93021
|
# tb_core.u_sdram32 : at time 55657.0 ns WRITE: Bank = 0 Row = 354, Col = 75, Data = 90b93021
|
# Status: Burst-No: 5 Write Address: 00162119 WriteData: 90b93021
|
# Status: Burst-No: 5 Write Address: 00162119 WriteData: 90b93021
|
# tb_core.u_sdram32 : at time 54467.0 ns WRITE: Bank = 0 Row = 354, Col = 76, Data = 7b24bdf6
|
# tb_core.u_sdram32 : at time 55667.0 ns WRITE: Bank = 0 Row = 354, Col = 76, Data = 7b24bdf6
|
# Status: Burst-No: 6 Write Address: 00162119 WriteData: 7b24bdf6
|
# Status: Burst-No: 6 Write Address: 00162119 WriteData: 7b24bdf6
|
# tb_core.u_sdram32 : at time 54477.0 ns WRITE: Bank = 0 Row = 354, Col = 77, Data = 345fbf68
|
# tb_core.u_sdram32 : at time 55677.0 ns WRITE: Bank = 0 Row = 354, Col = 77, Data = 345fbf68
|
# Status: Burst-No: 7 Write Address: 00162119 WriteData: 345fbf68
|
# Status: Burst-No: 7 Write Address: 00162119 WriteData: 345fbf68
|
# tb_core.u_sdram32 : at time 54487.0 ns WRITE: Bank = 0 Row = 354, Col = 78, Data = 8a290014
|
# tb_core.u_sdram32 : at time 55687.0 ns WRITE: Bank = 0 Row = 354, Col = 78, Data = 8a290014
|
# Status: Burst-No: 8 Write Address: 00162119 WriteData: 8a290014
|
# Status: Burst-No: 8 Write Address: 00162119 WriteData: 8a290014
|
# tb_core.u_sdram32 : at time 54497.0 ns WRITE: Bank = 0 Row = 354, Col = 79, Data = b7d0ca6f
|
# tb_core.u_sdram32 : at time 55697.0 ns WRITE: Bank = 0 Row = 354, Col = 79, Data = b7d0ca6f
|
# Status: Burst-No: 9 Write Address: 00162119 WriteData: b7d0ca6f
|
# Status: Burst-No: 9 Write Address: 00162119 WriteData: b7d0ca6f
|
# tb_core.u_sdram32 : at time 54507.0 ns WRITE: Bank = 0 Row = 354, Col = 80, Data = 9530362a
|
# tb_core.u_sdram32 : at time 55707.0 ns WRITE: Bank = 0 Row = 354, Col = 80, Data = 9530362a
|
# Status: Burst-No: 10 Write Address: 00162119 WriteData: 9530362a
|
# Status: Burst-No: 10 Write Address: 00162119 WriteData: 9530362a
|
# tb_core.u_sdram32 : at time 54517.0 ns WRITE: Bank = 0 Row = 354, Col = 81, Data = 1f77b73e
|
# tb_core.u_sdram32 : at time 55717.0 ns WRITE: Bank = 0 Row = 354, Col = 81, Data = 1f77b73e
|
# Status: Burst-No: 11 Write Address: 00162119 WriteData: 1f77b73e
|
# Status: Burst-No: 11 Write Address: 00162119 WriteData: 1f77b73e
|
# tb_core.u_sdram32 : at time 54527.0 ns WRITE: Bank = 0 Row = 354, Col = 82, Data = fbaaeef7
|
# tb_core.u_sdram32 : at time 55727.0 ns WRITE: Bank = 0 Row = 354, Col = 82, Data = fbaaeef7
|
# Status: Burst-No: 12 Write Address: 00162119 WriteData: fbaaeef7
|
# Status: Burst-No: 12 Write Address: 00162119 WriteData: fbaaeef7
|
# tb_core.u_sdram32 : at time 54537.0 ns WRITE: Bank = 0 Row = 354, Col = 83, Data = 23781f46
|
# tb_core.u_sdram32 : at time 55737.0 ns WRITE: Bank = 0 Row = 354, Col = 83, Data = 23781f46
|
# Status: Burst-No: 13 Write Address: 00162119 WriteData: 23781f46
|
# Status: Burst-No: 13 Write Address: 00162119 WriteData: 23781f46
|
# tb_core.u_sdram32 : at time 54547.0 ns WRITE: Bank = 0 Row = 354, Col = 84, Data = 9e9dca3d
|
# tb_core.u_sdram32 : at time 55747.0 ns WRITE: Bank = 0 Row = 354, Col = 84, Data = 9e9dca3d
|
# Status: Burst-No: 14 Write Address: 00162119 WriteData: 9e9dca3d
|
# Status: Burst-No: 14 Write Address: 00162119 WriteData: 9e9dca3d
|
# tb_core.u_sdram32 : at time 54557.0 ns WRITE: Bank = 0 Row = 354, Col = 85, Data = d01f40a0
|
# tb_core.u_sdram32 : at time 55757.0 ns WRITE: Bank = 0 Row = 354, Col = 85, Data = d01f40a0
|
# Status: Burst-No: 15 Write Address: 00162119 WriteData: d01f40a0
|
# Status: Burst-No: 15 Write Address: 00162119 WriteData: d01f40a0
|
# tb_core.u_sdram32 : at time 54567.0 ns WRITE: Bank = 0 Row = 354, Col = 86, Data = 7d4b53fa
|
# tb_core.u_sdram32 : at time 55767.0 ns WRITE: Bank = 0 Row = 354, Col = 86, Data = 7d4b53fa
|
# Status: Burst-No: 16 Write Address: 00162119 WriteData: 7d4b53fa
|
# Status: Burst-No: 16 Write Address: 00162119 WriteData: 7d4b53fa
|
# tb_core.u_sdram32 : at time 54577.0 ns WRITE: Bank = 0 Row = 354, Col = 87, Data = 7a4c4df4
|
# tb_core.u_sdram32 : at time 55777.0 ns WRITE: Bank = 0 Row = 354, Col = 87, Data = 7a4c4df4
|
# Status: Burst-No: 17 Write Address: 00162119 WriteData: 7a4c4df4
|
# Status: Burst-No: 17 Write Address: 00162119 WriteData: 7a4c4df4
|
# tb_core.u_sdram32 : at time 54587.0 ns WRITE: Bank = 0 Row = 354, Col = 88, Data = 19a8e333
|
# tb_core.u_sdram32 : at time 55787.0 ns WRITE: Bank = 0 Row = 354, Col = 88, Data = 19a8e333
|
# Status: Burst-No: 18 Write Address: 00162119 WriteData: 19a8e333
|
# Status: Burst-No: 18 Write Address: 00162119 WriteData: 19a8e333
|
# tb_core.u_sdram32 : at time 54597.0 ns WRITE: Bank = 0 Row = 354, Col = 89, Data = 0067d700
|
# tb_core.u_sdram32 : at time 55797.0 ns WRITE: Bank = 0 Row = 354, Col = 89, Data = 0067d700
|
# Status: Burst-No: 19 Write Address: 00162119 WriteData: 0067d700
|
# Status: Burst-No: 19 Write Address: 00162119 WriteData: 0067d700
|
# tb_core.u_sdram32 : at time 54607.0 ns WRITE: Bank = 0 Row = 354, Col = 90, Data = 6e567bdc
|
# tb_core.u_sdram32 : at time 55807.0 ns WRITE: Bank = 0 Row = 354, Col = 90, Data = 6e567bdc
|
# Status: Burst-No: 20 Write Address: 00162119 WriteData: 6e567bdc
|
# Status: Burst-No: 20 Write Address: 00162119 WriteData: 6e567bdc
|
# tb_core.u_sdram32 : at time 54617.0 ns WRITE: Bank = 0 Row = 354, Col = 91, Data = 38422d70
|
# tb_core.u_sdram32 : at time 55817.0 ns WRITE: Bank = 0 Row = 354, Col = 91, Data = 38422d70
|
# Status: Burst-No: 21 Write Address: 00162119 WriteData: 38422d70
|
# Status: Burst-No: 21 Write Address: 00162119 WriteData: 38422d70
|
# tb_core.u_sdram32 : at time 54627.0 ns WRITE: Bank = 0 Row = 354, Col = 92, Data = 9491aa29
|
# tb_core.u_sdram32 : at time 55827.0 ns WRITE: Bank = 0 Row = 354, Col = 92, Data = 9491aa29
|
# Status: Burst-No: 22 Write Address: 00162119 WriteData: 9491aa29
|
# Status: Burst-No: 22 Write Address: 00162119 WriteData: 9491aa29
|
# tb_core.u_sdram32 : at time 54637.0 ns WRITE: Bank = 0 Row = 354, Col = 93, Data = 07f0b90f
|
# tb_core.u_sdram32 : at time 55837.0 ns WRITE: Bank = 0 Row = 354, Col = 93, Data = 07f0b90f
|
# Status: Burst-No: 23 Write Address: 00162119 WriteData: 07f0b90f
|
# Status: Burst-No: 23 Write Address: 00162119 WriteData: 07f0b90f
|
# tb_core.u_sdram32 : at time 54647.0 ns WRITE: Bank = 0 Row = 354, Col = 94, Data = 4b5b7196
|
# tb_core.u_sdram32 : at time 55847.0 ns WRITE: Bank = 0 Row = 354, Col = 94, Data = 4b5b7196
|
# Status: Burst-No: 24 Write Address: 00162119 WriteData: 4b5b7196
|
# Status: Burst-No: 24 Write Address: 00162119 WriteData: 4b5b7196
|
# tb_core.u_sdram32 : at time 54657.0 ns WRITE: Bank = 0 Row = 354, Col = 95, Data = 6b825dd7
|
# tb_core.u_sdram32 : at time 55857.0 ns WRITE: Bank = 0 Row = 354, Col = 95, Data = 6b825dd7
|
# Status: Burst-No: 25 Write Address: 00162119 WriteData: 6b825dd7
|
# Status: Burst-No: 25 Write Address: 00162119 WriteData: 6b825dd7
|
# tb_core.u_sdram32 : at time 54667.0 ns WRITE: Bank = 0 Row = 354, Col = 96, Data = 11c91123
|
# tb_core.u_sdram32 : at time 55867.0 ns WRITE: Bank = 0 Row = 354, Col = 96, Data = 11c91123
|
# Status: Burst-No: 26 Write Address: 00162119 WriteData: 11c91123
|
# Status: Burst-No: 26 Write Address: 00162119 WriteData: 11c91123
|
# tb_core.u_sdram32 : at time 54677.0 ns WRITE: Bank = 0 Row = 354, Col = 97, Data = 8322de06
|
# tb_core.u_sdram32 : at time 55877.0 ns WRITE: Bank = 0 Row = 354, Col = 97, Data = 8322de06
|
# Status: Burst-No: 27 Write Address: 00162119 WriteData: 8322de06
|
# Status: Burst-No: 27 Write Address: 00162119 WriteData: 8322de06
|
# tb_core.u_sdram32 : at time 54687.0 ns WRITE: Bank = 0 Row = 354, Col = 98, Data = a538004a
|
# tb_core.u_sdram32 : at time 55887.0 ns WRITE: Bank = 0 Row = 354, Col = 98, Data = a538004a
|
# Status: Burst-No: 28 Write Address: 00162119 WriteData: a538004a
|
# Status: Burst-No: 28 Write Address: 00162119 WriteData: a538004a
|
# tb_core.u_sdram32 : at time 54697.0 ns WRITE: Bank = 0 Row = 354, Col = 99, Data = 2505394a
|
# tb_core.u_sdram32 : at time 55897.0 ns WRITE: Bank = 0 Row = 354, Col = 99, Data = 2505394a
|
# Status: Burst-No: 29 Write Address: 00162119 WriteData: 2505394a
|
# Status: Burst-No: 29 Write Address: 00162119 WriteData: 2505394a
|
# tb_core.u_sdram32 : at time 54707.0 ns WRITE: Bank = 0 Row = 354, Col = 100, Data = 20dcbf41
|
# tb_core.u_sdram32 : at time 55907.0 ns WRITE: Bank = 0 Row = 354, Col = 100, Data = 20dcbf41
|
# Status: Burst-No: 30 Write Address: 00162119 WriteData: 20dcbf41
|
# Status: Burst-No: 30 Write Address: 00162119 WriteData: 20dcbf41
|
# tb_core.u_sdram32 : at time 54717.0 ns WRITE: Bank = 0 Row = 354, Col = 101, Data = 442d0788
|
# tb_core.u_sdram32 : at time 55917.0 ns WRITE: Bank = 0 Row = 354, Col = 101, Data = 442d0788
|
# Status: Burst-No: 31 Write Address: 00162119 WriteData: 442d0788
|
# Status: Burst-No: 31 Write Address: 00162119 WriteData: 442d0788
|
# tb_core.u_sdram32 : at time 54727.0 ns WRITE: Bank = 0 Row = 354, Col = 102, Data = e6e4b8cd
|
# tb_core.u_sdram32 : at time 55927.0 ns WRITE: Bank = 0 Row = 354, Col = 102, Data = e6e4b8cd
|
# Status: Burst-No: 32 Write Address: 00162119 WriteData: e6e4b8cd
|
# Status: Burst-No: 32 Write Address: 00162119 WriteData: e6e4b8cd
|
# tb_core.u_sdram32 : at time 54737.0 ns WRITE: Bank = 0 Row = 354, Col = 103, Data = 38eedd71
|
# tb_core.u_sdram32 : at time 55937.0 ns WRITE: Bank = 0 Row = 354, Col = 103, Data = 38eedd71
|
# Status: Burst-No: 33 Write Address: 00162119 WriteData: 38eedd71
|
# Status: Burst-No: 33 Write Address: 00162119 WriteData: 38eedd71
|
# tb_core.u_sdram32 : at time 54747.0 ns WRITE: Bank = 0 Row = 354, Col = 104, Data = 94232228
|
# tb_core.u_sdram32 : at time 55947.0 ns WRITE: Bank = 0 Row = 354, Col = 104, Data = 94232228
|
# Status: Burst-No: 34 Write Address: 00162119 WriteData: 94232228
|
# Status: Burst-No: 34 Write Address: 00162119 WriteData: 94232228
|
# tb_core.u_sdram32 : at time 54757.0 ns WRITE: Bank = 0 Row = 354, Col = 105, Data = 89bfac13
|
# tb_core.u_sdram32 : at time 55957.0 ns WRITE: Bank = 0 Row = 354, Col = 105, Data = 89bfac13
|
# Status: Burst-No: 35 Write Address: 00162119 WriteData: 89bfac13
|
# Status: Burst-No: 35 Write Address: 00162119 WriteData: 89bfac13
|
# tb_core.u_sdram32 : at time 54767.0 ns WRITE: Bank = 0 Row = 354, Col = 106, Data = b600e26c
|
# tb_core.u_sdram32 : at time 55967.0 ns WRITE: Bank = 0 Row = 354, Col = 106, Data = b600e26c
|
# Status: Burst-No: 36 Write Address: 00162119 WriteData: b600e26c
|
# Status: Burst-No: 36 Write Address: 00162119 WriteData: b600e26c
|
# tb_core.u_sdram32 : at time 54777.0 ns WRITE: Bank = 0 Row = 354, Col = 107, Data = aaab2455
|
# tb_core.u_sdram32 : at time 55977.0 ns WRITE: Bank = 0 Row = 354, Col = 107, Data = aaab2455
|
# Status: Burst-No: 37 Write Address: 00162119 WriteData: aaab2455
|
# Status: Burst-No: 37 Write Address: 00162119 WriteData: aaab2455
|
# tb_core.u_sdram32 : at time 54787.0 ns WRITE: Bank = 0 Row = 354, Col = 108, Data = 7f2767fe
|
# tb_core.u_sdram32 : at time 55987.0 ns WRITE: Bank = 0 Row = 354, Col = 108, Data = 7f2767fe
|
# Status: Burst-No: 38 Write Address: 00162119 WriteData: 7f2767fe
|
# Status: Burst-No: 38 Write Address: 00162119 WriteData: 7f2767fe
|
# tb_core.u_sdram32 : at time 54797.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 55997.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 54933.0 ns READ : Bank = 1 Row = 46, Col = 45, Data = 0207bb04
|
# tb_core.u_sdram32 : at time 56133.0 ns READ : Bank = 1 Row = 46, Col = 45, Data = 0207bb04
|
# tb_core.u_sdram32 : at time 54943.0 ns READ : Bank = 1 Row = 46, Col = 46, Data = bca0b279
|
# tb_core.u_sdram32 : at time 56143.0 ns READ : Bank = 1 Row = 46, Col = 46, Data = bca0b279
|
# READ STATUS: Burst-No: 0 Addr: 0002e4b4 Rxd: 0207bb04
|
# READ STATUS: Burst-No: 0 Addr: 0002e4b4 Rxd: 0207bb04
|
# tb_core.u_sdram32 : at time 54953.0 ns READ : Bank = 1 Row = 46, Col = 47, Data = e6b110cd
|
# tb_core.u_sdram32 : at time 56153.0 ns READ : Bank = 1 Row = 46, Col = 47, Data = e6b110cd
|
# READ STATUS: Burst-No: 1 Addr: 0002e4b6 Rxd: bca0b279
|
# READ STATUS: Burst-No: 1 Addr: 0002e4b6 Rxd: bca0b279
|
# tb_core.u_sdram32 : at time 54963.0 ns READ : Bank = 1 Row = 46, Col = 48, Data = c9662c92
|
# tb_core.u_sdram32 : at time 56163.0 ns READ : Bank = 1 Row = 46, Col = 48, Data = c9662c92
|
# READ STATUS: Burst-No: 2 Addr: 0002e4b8 Rxd: e6b110cd
|
# READ STATUS: Burst-No: 2 Addr: 0002e4b8 Rxd: e6b110cd
|
# tb_core.u_sdram32 : at time 54973.0 ns READ : Bank = 1 Row = 46, Col = 49, Data = a2ce0045
|
# tb_core.u_sdram32 : at time 56173.0 ns READ : Bank = 1 Row = 46, Col = 49, Data = a2ce0045
|
# READ STATUS: Burst-No: 3 Addr: 0002e4ba Rxd: c9662c92
|
# READ STATUS: Burst-No: 3 Addr: 0002e4ba Rxd: c9662c92
|
# tb_core.u_sdram32 : at time 54983.0 ns READ : Bank = 1 Row = 46, Col = 50, Data = d4ea6aa9
|
# tb_core.u_sdram32 : at time 56183.0 ns READ : Bank = 1 Row = 46, Col = 50, Data = d4ea6aa9
|
# READ STATUS: Burst-No: 4 Addr: 0002e4bc Rxd: a2ce0045
|
# READ STATUS: Burst-No: 4 Addr: 0002e4bc Rxd: a2ce0045
|
# tb_core.u_sdram32 : at time 54993.0 ns READ : Bank = 1 Row = 46, Col = 51, Data = cf31fc9e
|
# tb_core.u_sdram32 : at time 56193.0 ns READ : Bank = 1 Row = 46, Col = 51, Data = cf31fc9e
|
# READ STATUS: Burst-No: 5 Addr: 0002e4be Rxd: d4ea6aa9
|
# READ STATUS: Burst-No: 5 Addr: 0002e4be Rxd: d4ea6aa9
|
# tb_core.u_sdram32 : at time 55003.0 ns READ : Bank = 1 Row = 46, Col = 52, Data = 6ec2cbdd
|
# tb_core.u_sdram32 : at time 56203.0 ns READ : Bank = 1 Row = 46, Col = 52, Data = 6ec2cbdd
|
# READ STATUS: Burst-No: 6 Addr: 0002e4c0 Rxd: cf31fc9e
|
# READ STATUS: Burst-No: 6 Addr: 0002e4c0 Rxd: cf31fc9e
|
# tb_core.u_sdram32 : at time 55013.0 ns READ : Bank = 1 Row = 46, Col = 53, Data = 600b2dc0
|
# tb_core.u_sdram32 : at time 56213.0 ns READ : Bank = 1 Row = 46, Col = 53, Data = 600b2dc0
|
# READ STATUS: Burst-No: 7 Addr: 0002e4c2 Rxd: 6ec2cbdd
|
# READ STATUS: Burst-No: 7 Addr: 0002e4c2 Rxd: 6ec2cbdd
|
# tb_core.u_sdram32 : at time 55023.0 ns READ : Bank = 1 Row = 46, Col = 54, Data = a5b9424b
|
# tb_core.u_sdram32 : at time 56223.0 ns READ : Bank = 1 Row = 46, Col = 54, Data = a5b9424b
|
# READ STATUS: Burst-No: 8 Addr: 0002e4c4 Rxd: 600b2dc0
|
# READ STATUS: Burst-No: 8 Addr: 0002e4c4 Rxd: 600b2dc0
|
# tb_core.u_sdram32 : at time 55033.0 ns READ : Bank = 1 Row = 46, Col = 55, Data = 5db7e1bb
|
# tb_core.u_sdram32 : at time 56233.0 ns READ : Bank = 1 Row = 46, Col = 55, Data = 5db7e1bb
|
# READ STATUS: Burst-No: 9 Addr: 0002e4c6 Rxd: a5b9424b
|
# READ STATUS: Burst-No: 9 Addr: 0002e4c6 Rxd: a5b9424b
|
# tb_core.u_sdram32 : at time 55043.0 ns READ : Bank = 1 Row = 46, Col = 56, Data = 408a2981
|
# tb_core.u_sdram32 : at time 56243.0 ns READ : Bank = 1 Row = 46, Col = 56, Data = 408a2981
|
# READ STATUS: Burst-No: 10 Addr: 0002e4c8 Rxd: 5db7e1bb
|
# READ STATUS: Burst-No: 10 Addr: 0002e4c8 Rxd: 5db7e1bb
|
# tb_core.u_sdram32 : at time 55053.0 ns READ : Bank = 1 Row = 46, Col = 57, Data = d932d8b2
|
# tb_core.u_sdram32 : at time 56253.0 ns READ : Bank = 1 Row = 46, Col = 57, Data = d932d8b2
|
# READ STATUS: Burst-No: 11 Addr: 0002e4ca Rxd: 408a2981
|
# READ STATUS: Burst-No: 11 Addr: 0002e4ca Rxd: 408a2981
|
# tb_core.u_sdram32 : at time 55063.0 ns READ : Bank = 1 Row = 46, Col = 58, Data = 598d27b3
|
# tb_core.u_sdram32 : at time 56263.0 ns READ : Bank = 1 Row = 46, Col = 58, Data = 598d27b3
|
# READ STATUS: Burst-No: 12 Addr: 0002e4cc Rxd: d932d8b2
|
# READ STATUS: Burst-No: 12 Addr: 0002e4cc Rxd: d932d8b2
|
# tb_core.u_sdram32 : at time 55073.0 ns READ : Bank = 1 Row = 46, Col = 59, Data = 05aeb90b
|
# tb_core.u_sdram32 : at time 56273.0 ns READ : Bank = 1 Row = 46, Col = 59, Data = 05aeb90b
|
# READ STATUS: Burst-No: 13 Addr: 0002e4ce Rxd: 598d27b3
|
# READ STATUS: Burst-No: 13 Addr: 0002e4ce Rxd: 598d27b3
|
# tb_core.u_sdram32 : at time 55083.0 ns READ : Bank = 1 Row = 46, Col = 60, Data = 24011148
|
# tb_core.u_sdram32 : at time 56283.0 ns READ : Bank = 1 Row = 46, Col = 60, Data = 24011148
|
# READ STATUS: Burst-No: 14 Addr: 0002e4d0 Rxd: 05aeb90b
|
# READ STATUS: Burst-No: 14 Addr: 0002e4d0 Rxd: 05aeb90b
|
# tb_core.u_sdram32 : at time 55093.0 ns READ : Bank = 1 Row = 46, Col = 61, Data = f0b860e1
|
# tb_core.u_sdram32 : at time 56293.0 ns READ : Bank = 1 Row = 46, Col = 61, Data = f0b860e1
|
# READ STATUS: Burst-No: 15 Addr: 0002e4d2 Rxd: 24011148
|
# READ STATUS: Burst-No: 15 Addr: 0002e4d2 Rxd: 24011148
|
# tb_core.u_sdram32 : at time 55103.0 ns READ : Bank = 1 Row = 46, Col = 62, Data = 7e72c5fc
|
# tb_core.u_sdram32 : at time 56303.0 ns READ : Bank = 1 Row = 46, Col = 62, Data = 7e72c5fc
|
# READ STATUS: Burst-No: 16 Addr: 0002e4d4 Rxd: f0b860e1
|
# READ STATUS: Burst-No: 16 Addr: 0002e4d4 Rxd: f0b860e1
|
# tb_core.u_sdram32 : at time 55113.0 ns READ : Bank = 1 Row = 46, Col = 63, Data = d7f844af
|
# tb_core.u_sdram32 : at time 56313.0 ns READ : Bank = 1 Row = 46, Col = 63, Data = d7f844af
|
# READ STATUS: Burst-No: 17 Addr: 0002e4d6 Rxd: 7e72c5fc
|
# READ STATUS: Burst-No: 17 Addr: 0002e4d6 Rxd: 7e72c5fc
|
# tb_core.u_sdram32 : at time 55123.0 ns READ : Bank = 1 Row = 46, Col = 64, Data = d0770ea0
|
# tb_core.u_sdram32 : at time 56323.0 ns READ : Bank = 1 Row = 46, Col = 64, Data = d0770ea0
|
# READ STATUS: Burst-No: 18 Addr: 0002e4d8 Rxd: d7f844af
|
# READ STATUS: Burst-No: 18 Addr: 0002e4d8 Rxd: d7f844af
|
# tb_core.u_sdram32 : at time 55133.0 ns READ : Bank = 1 Row = 46, Col = 65, Data = 076adf0e
|
# tb_core.u_sdram32 : at time 56333.0 ns READ : Bank = 1 Row = 46, Col = 65, Data = 076adf0e
|
# READ STATUS: Burst-No: 19 Addr: 0002e4da Rxd: d0770ea0
|
# READ STATUS: Burst-No: 19 Addr: 0002e4da Rxd: d0770ea0
|
# tb_core.u_sdram32 : at time 55143.0 ns READ : Bank = 1 Row = 46, Col = 66, Data = 3aaf8775
|
# tb_core.u_sdram32 : at time 56343.0 ns READ : Bank = 1 Row = 46, Col = 66, Data = 3aaf8775
|
# READ STATUS: Burst-No: 20 Addr: 0002e4dc Rxd: 076adf0e
|
# READ STATUS: Burst-No: 20 Addr: 0002e4dc Rxd: 076adf0e
|
# tb_core.u_sdram32 : at time 55153.0 ns READ : Bank = 1 Row = 46, Col = 67, Data = 6ca7ffd9
|
# tb_core.u_sdram32 : at time 56353.0 ns READ : Bank = 1 Row = 46, Col = 67, Data = 6ca7ffd9
|
# READ STATUS: Burst-No: 21 Addr: 0002e4de Rxd: 3aaf8775
|
# READ STATUS: Burst-No: 21 Addr: 0002e4de Rxd: 3aaf8775
|
# tb_core.u_sdram32 : at time 55163.0 ns READ : Bank = 1 Row = 46, Col = 68, Data = 86d26e0d
|
# tb_core.u_sdram32 : at time 56363.0 ns READ : Bank = 1 Row = 46, Col = 68, Data = 86d26e0d
|
# READ STATUS: Burst-No: 22 Addr: 0002e4e0 Rxd: 6ca7ffd9
|
# READ STATUS: Burst-No: 22 Addr: 0002e4e0 Rxd: 6ca7ffd9
|
# tb_core.u_sdram32 : at time 55173.0 ns READ : Bank = 1 Row = 46, Col = 69, Data = 13913127
|
# tb_core.u_sdram32 : at time 56373.0 ns READ : Bank = 1 Row = 46, Col = 69, Data = 13913127
|
# READ STATUS: Burst-No: 23 Addr: 0002e4e2 Rxd: 86d26e0d
|
# READ STATUS: Burst-No: 23 Addr: 0002e4e2 Rxd: 86d26e0d
|
# tb_core.u_sdram32 : at time 55183.0 ns READ : Bank = 1 Row = 46, Col = 70, Data = 3a2d9974
|
# tb_core.u_sdram32 : at time 56383.0 ns READ : Bank = 1 Row = 46, Col = 70, Data = 3a2d9974
|
# READ STATUS: Burst-No: 24 Addr: 0002e4e4 Rxd: 13913127
|
# READ STATUS: Burst-No: 24 Addr: 0002e4e4 Rxd: 13913127
|
# tb_core.u_sdram32 : at time 55193.0 ns READ : Bank = 1 Row = 46, Col = 71, Data = 7e7f21fc
|
# tb_core.u_sdram32 : at time 56393.0 ns READ : Bank = 1 Row = 46, Col = 71, Data = 7e7f21fc
|
# READ STATUS: Burst-No: 25 Addr: 0002e4e6 Rxd: 3a2d9974
|
# READ STATUS: Burst-No: 25 Addr: 0002e4e6 Rxd: 3a2d9974
|
# tb_core.u_sdram32 : at time 55203.0 ns READ : Bank = 1 Row = 46, Col = 72, Data = dfdc3ebf
|
# tb_core.u_sdram32 : at time 56403.0 ns READ : Bank = 1 Row = 46, Col = 72, Data = dfdc3ebf
|
# READ STATUS: Burst-No: 26 Addr: 0002e4e8 Rxd: 7e7f21fc
|
# READ STATUS: Burst-No: 26 Addr: 0002e4e8 Rxd: 7e7f21fc
|
# tb_core.u_sdram32 : at time 55213.0 ns READ : Bank = 1 Row = 46, Col = 73, Data = afc5f25f
|
# tb_core.u_sdram32 : at time 56413.0 ns READ : Bank = 1 Row = 46, Col = 73, Data = afc5f25f
|
# READ STATUS: Burst-No: 27 Addr: 0002e4ea Rxd: dfdc3ebf
|
# READ STATUS: Burst-No: 27 Addr: 0002e4ea Rxd: dfdc3ebf
|
# tb_core.u_sdram32 : at time 55223.0 ns READ : Bank = 1 Row = 46, Col = 74, Data = c0a7e881
|
# tb_core.u_sdram32 : at time 56423.0 ns READ : Bank = 1 Row = 46, Col = 74, Data = c0a7e881
|
# READ STATUS: Burst-No: 28 Addr: 0002e4ec Rxd: afc5f25f
|
# READ STATUS: Burst-No: 28 Addr: 0002e4ec Rxd: afc5f25f
|
# tb_core.u_sdram32 : at time 55233.0 ns READ : Bank = 1 Row = 46, Col = 75, Data = b428aa68
|
# tb_core.u_sdram32 : at time 56433.0 ns READ : Bank = 1 Row = 46, Col = 75, Data = b428aa68
|
# tb_core.u_sdram32 : at time 55237.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 56437.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 29 Addr: 0002e4ee Rxd: c0a7e881
|
# READ STATUS: Burst-No: 29 Addr: 0002e4ee Rxd: c0a7e881
|
# tb_core.u_sdram32 : at time 55243.0 ns READ : Bank = 1 Row = 46, Col = 76, Data = fd4c48fa
|
# tb_core.u_sdram32 : at time 56443.0 ns READ : Bank = 1 Row = 46, Col = 76, Data = fd4c48fa
|
# READ STATUS: Burst-No: 30 Addr: 0002e4f0 Rxd: b428aa68
|
# READ STATUS: Burst-No: 30 Addr: 0002e4f0 Rxd: b428aa68
|
# tb_core.u_sdram32 : at time 55253.0 ns READ : Bank = 1 Row = 46, Col = 77, Data = fd9380fb
|
# tb_core.u_sdram32 : at time 56453.0 ns READ : Bank = 1 Row = 46, Col = 77, Data = fd9380fb
|
# READ STATUS: Burst-No: 31 Addr: 0002e4f2 Rxd: fd4c48fa
|
# READ STATUS: Burst-No: 31 Addr: 0002e4f2 Rxd: fd4c48fa
|
# READ STATUS: Burst-No: 32 Addr: 0002e4f4 Rxd: fd9380fb
|
# READ STATUS: Burst-No: 32 Addr: 0002e4f4 Rxd: fd9380fb
|
# tb_core.u_sdram32 : at time 55423.0 ns READ : Bank = 0 Row = 354, Col = 70, Data = 29951b53
|
# tb_core.u_sdram32 : at time 56487.0 ns AREF : Auto Refresh
|
# tb_core.u_sdram32 : at time 55433.0 ns READ : Bank = 0 Row = 354, Col = 71, Data = f7cff6ef
|
# tb_core.u_sdram32 : at time 56577.0 ns AREF : Auto Refresh
|
|
# tb_core.u_sdram32 : at time 56667.0 ns AREF : Auto Refresh
|
|
# tb_core.u_sdram32 : at time 56757.0 ns AREF : Auto Refresh
|
|
# tb_core.u_sdram32 : at time 56847.0 ns AREF : Auto Refresh
|
|
# tb_core.u_sdram32 : at time 56937.0 ns AREF : Auto Refresh
|
|
# tb_core.u_sdram32 : at time 57057.0 ns ACT : Bank = 0 Row = 354
|
|
# tb_core.u_sdram32 : at time 57113.0 ns READ : Bank = 0 Row = 354, Col = 70, Data = 29951b53
|
|
# tb_core.u_sdram32 : at time 57123.0 ns READ : Bank = 0 Row = 354, Col = 71, Data = f7cff6ef
|
# READ STATUS: Burst-No: 0 Addr: 00162119 Rxd: 29951b53
|
# READ STATUS: Burst-No: 0 Addr: 00162119 Rxd: 29951b53
|
# tb_core.u_sdram32 : at time 55443.0 ns READ : Bank = 0 Row = 354, Col = 72, Data = f6d8aeed
|
# tb_core.u_sdram32 : at time 57133.0 ns READ : Bank = 0 Row = 354, Col = 72, Data = f6d8aeed
|
# READ STATUS: Burst-No: 1 Addr: 0016211b Rxd: f7cff6ef
|
# READ STATUS: Burst-No: 1 Addr: 0016211b Rxd: f7cff6ef
|
# tb_core.u_sdram32 : at time 55453.0 ns READ : Bank = 0 Row = 354, Col = 73, Data = 58d79db1
|
# tb_core.u_sdram32 : at time 57143.0 ns READ : Bank = 0 Row = 354, Col = 73, Data = 58d79db1
|
# READ STATUS: Burst-No: 2 Addr: 0016211d Rxd: f6d8aeed
|
# READ STATUS: Burst-No: 2 Addr: 0016211d Rxd: f6d8aeed
|
# tb_core.u_sdram32 : at time 55463.0 ns READ : Bank = 0 Row = 354, Col = 74, Data = b26ffe64
|
# tb_core.u_sdram32 : at time 57153.0 ns READ : Bank = 0 Row = 354, Col = 74, Data = b26ffe64
|
# READ STATUS: Burst-No: 3 Addr: 0016211f Rxd: 58d79db1
|
# READ STATUS: Burst-No: 3 Addr: 0016211f Rxd: 58d79db1
|
# tb_core.u_sdram32 : at time 55473.0 ns READ : Bank = 0 Row = 354, Col = 75, Data = 90b93021
|
# tb_core.u_sdram32 : at time 57163.0 ns READ : Bank = 0 Row = 354, Col = 75, Data = 90b93021
|
# READ STATUS: Burst-No: 4 Addr: 00162121 Rxd: b26ffe64
|
# READ STATUS: Burst-No: 4 Addr: 00162121 Rxd: b26ffe64
|
# tb_core.u_sdram32 : at time 55483.0 ns READ : Bank = 0 Row = 354, Col = 76, Data = 7b24bdf6
|
# tb_core.u_sdram32 : at time 57173.0 ns READ : Bank = 0 Row = 354, Col = 76, Data = 7b24bdf6
|
# READ STATUS: Burst-No: 5 Addr: 00162123 Rxd: 90b93021
|
# READ STATUS: Burst-No: 5 Addr: 00162123 Rxd: 90b93021
|
# tb_core.u_sdram32 : at time 55493.0 ns READ : Bank = 0 Row = 354, Col = 77, Data = 345fbf68
|
# tb_core.u_sdram32 : at time 57183.0 ns READ : Bank = 0 Row = 354, Col = 77, Data = 345fbf68
|
# READ STATUS: Burst-No: 6 Addr: 00162125 Rxd: 7b24bdf6
|
# READ STATUS: Burst-No: 6 Addr: 00162125 Rxd: 7b24bdf6
|
# tb_core.u_sdram32 : at time 55503.0 ns READ : Bank = 0 Row = 354, Col = 78, Data = 8a290014
|
# tb_core.u_sdram32 : at time 57193.0 ns READ : Bank = 0 Row = 354, Col = 78, Data = 8a290014
|
# READ STATUS: Burst-No: 7 Addr: 00162127 Rxd: 345fbf68
|
# READ STATUS: Burst-No: 7 Addr: 00162127 Rxd: 345fbf68
|
# tb_core.u_sdram32 : at time 55513.0 ns READ : Bank = 0 Row = 354, Col = 79, Data = b7d0ca6f
|
# tb_core.u_sdram32 : at time 57203.0 ns READ : Bank = 0 Row = 354, Col = 79, Data = b7d0ca6f
|
# READ STATUS: Burst-No: 8 Addr: 00162129 Rxd: 8a290014
|
# READ STATUS: Burst-No: 8 Addr: 00162129 Rxd: 8a290014
|
# tb_core.u_sdram32 : at time 55523.0 ns READ : Bank = 0 Row = 354, Col = 80, Data = 9530362a
|
# tb_core.u_sdram32 : at time 57213.0 ns READ : Bank = 0 Row = 354, Col = 80, Data = 9530362a
|
# READ STATUS: Burst-No: 9 Addr: 0016212b Rxd: b7d0ca6f
|
# READ STATUS: Burst-No: 9 Addr: 0016212b Rxd: b7d0ca6f
|
# tb_core.u_sdram32 : at time 55533.0 ns READ : Bank = 0 Row = 354, Col = 81, Data = 1f77b73e
|
# tb_core.u_sdram32 : at time 57223.0 ns READ : Bank = 0 Row = 354, Col = 81, Data = 1f77b73e
|
# READ STATUS: Burst-No: 10 Addr: 0016212d Rxd: 9530362a
|
# READ STATUS: Burst-No: 10 Addr: 0016212d Rxd: 9530362a
|
# tb_core.u_sdram32 : at time 55543.0 ns READ : Bank = 0 Row = 354, Col = 82, Data = fbaaeef7
|
# tb_core.u_sdram32 : at time 57233.0 ns READ : Bank = 0 Row = 354, Col = 82, Data = fbaaeef7
|
# READ STATUS: Burst-No: 11 Addr: 0016212f Rxd: 1f77b73e
|
# READ STATUS: Burst-No: 11 Addr: 0016212f Rxd: 1f77b73e
|
# tb_core.u_sdram32 : at time 55553.0 ns READ : Bank = 0 Row = 354, Col = 83, Data = 23781f46
|
# tb_core.u_sdram32 : at time 57243.0 ns READ : Bank = 0 Row = 354, Col = 83, Data = 23781f46
|
# READ STATUS: Burst-No: 12 Addr: 00162131 Rxd: fbaaeef7
|
# READ STATUS: Burst-No: 12 Addr: 00162131 Rxd: fbaaeef7
|
# tb_core.u_sdram32 : at time 55563.0 ns READ : Bank = 0 Row = 354, Col = 84, Data = 9e9dca3d
|
# tb_core.u_sdram32 : at time 57253.0 ns READ : Bank = 0 Row = 354, Col = 84, Data = 9e9dca3d
|
# READ STATUS: Burst-No: 13 Addr: 00162133 Rxd: 23781f46
|
# READ STATUS: Burst-No: 13 Addr: 00162133 Rxd: 23781f46
|
# tb_core.u_sdram32 : at time 55573.0 ns READ : Bank = 0 Row = 354, Col = 85, Data = d01f40a0
|
# tb_core.u_sdram32 : at time 57263.0 ns READ : Bank = 0 Row = 354, Col = 85, Data = d01f40a0
|
# READ STATUS: Burst-No: 14 Addr: 00162135 Rxd: 9e9dca3d
|
# READ STATUS: Burst-No: 14 Addr: 00162135 Rxd: 9e9dca3d
|
# tb_core.u_sdram32 : at time 55583.0 ns READ : Bank = 0 Row = 354, Col = 86, Data = 7d4b53fa
|
# tb_core.u_sdram32 : at time 57273.0 ns READ : Bank = 0 Row = 354, Col = 86, Data = 7d4b53fa
|
# READ STATUS: Burst-No: 15 Addr: 00162137 Rxd: d01f40a0
|
# READ STATUS: Burst-No: 15 Addr: 00162137 Rxd: d01f40a0
|
# tb_core.u_sdram32 : at time 55593.0 ns READ : Bank = 0 Row = 354, Col = 87, Data = 7a4c4df4
|
# tb_core.u_sdram32 : at time 57283.0 ns READ : Bank = 0 Row = 354, Col = 87, Data = 7a4c4df4
|
# READ STATUS: Burst-No: 16 Addr: 00162139 Rxd: 7d4b53fa
|
# READ STATUS: Burst-No: 16 Addr: 00162139 Rxd: 7d4b53fa
|
# tb_core.u_sdram32 : at time 55603.0 ns READ : Bank = 0 Row = 354, Col = 88, Data = 19a8e333
|
# tb_core.u_sdram32 : at time 57293.0 ns READ : Bank = 0 Row = 354, Col = 88, Data = 19a8e333
|
# READ STATUS: Burst-No: 17 Addr: 0016213b Rxd: 7a4c4df4
|
# READ STATUS: Burst-No: 17 Addr: 0016213b Rxd: 7a4c4df4
|
# tb_core.u_sdram32 : at time 55613.0 ns READ : Bank = 0 Row = 354, Col = 89, Data = 0067d700
|
# tb_core.u_sdram32 : at time 57303.0 ns READ : Bank = 0 Row = 354, Col = 89, Data = 0067d700
|
# READ STATUS: Burst-No: 18 Addr: 0016213d Rxd: 19a8e333
|
# READ STATUS: Burst-No: 18 Addr: 0016213d Rxd: 19a8e333
|
# tb_core.u_sdram32 : at time 55623.0 ns READ : Bank = 0 Row = 354, Col = 90, Data = 6e567bdc
|
# tb_core.u_sdram32 : at time 57313.0 ns READ : Bank = 0 Row = 354, Col = 90, Data = 6e567bdc
|
# READ STATUS: Burst-No: 19 Addr: 0016213f Rxd: 0067d700
|
# READ STATUS: Burst-No: 19 Addr: 0016213f Rxd: 0067d700
|
# tb_core.u_sdram32 : at time 55633.0 ns READ : Bank = 0 Row = 354, Col = 91, Data = 38422d70
|
# tb_core.u_sdram32 : at time 57323.0 ns READ : Bank = 0 Row = 354, Col = 91, Data = 38422d70
|
# READ STATUS: Burst-No: 20 Addr: 00162141 Rxd: 6e567bdc
|
# READ STATUS: Burst-No: 20 Addr: 00162141 Rxd: 6e567bdc
|
# tb_core.u_sdram32 : at time 55643.0 ns READ : Bank = 0 Row = 354, Col = 92, Data = 9491aa29
|
# tb_core.u_sdram32 : at time 57333.0 ns READ : Bank = 0 Row = 354, Col = 92, Data = 9491aa29
|
# READ STATUS: Burst-No: 21 Addr: 00162143 Rxd: 38422d70
|
# READ STATUS: Burst-No: 21 Addr: 00162143 Rxd: 38422d70
|
# tb_core.u_sdram32 : at time 55653.0 ns READ : Bank = 0 Row = 354, Col = 93, Data = 07f0b90f
|
# tb_core.u_sdram32 : at time 57343.0 ns READ : Bank = 0 Row = 354, Col = 93, Data = 07f0b90f
|
# READ STATUS: Burst-No: 22 Addr: 00162145 Rxd: 9491aa29
|
# READ STATUS: Burst-No: 22 Addr: 00162145 Rxd: 9491aa29
|
# tb_core.u_sdram32 : at time 55663.0 ns READ : Bank = 0 Row = 354, Col = 94, Data = 4b5b7196
|
# tb_core.u_sdram32 : at time 57353.0 ns READ : Bank = 0 Row = 354, Col = 94, Data = 4b5b7196
|
# READ STATUS: Burst-No: 23 Addr: 00162147 Rxd: 07f0b90f
|
# READ STATUS: Burst-No: 23 Addr: 00162147 Rxd: 07f0b90f
|
# tb_core.u_sdram32 : at time 55673.0 ns READ : Bank = 0 Row = 354, Col = 95, Data = 6b825dd7
|
# tb_core.u_sdram32 : at time 57363.0 ns READ : Bank = 0 Row = 354, Col = 95, Data = 6b825dd7
|
# READ STATUS: Burst-No: 24 Addr: 00162149 Rxd: 4b5b7196
|
# READ STATUS: Burst-No: 24 Addr: 00162149 Rxd: 4b5b7196
|
# tb_core.u_sdram32 : at time 55683.0 ns READ : Bank = 0 Row = 354, Col = 96, Data = 11c91123
|
# tb_core.u_sdram32 : at time 57373.0 ns READ : Bank = 0 Row = 354, Col = 96, Data = 11c91123
|
# READ STATUS: Burst-No: 25 Addr: 0016214b Rxd: 6b825dd7
|
# READ STATUS: Burst-No: 25 Addr: 0016214b Rxd: 6b825dd7
|
# tb_core.u_sdram32 : at time 55693.0 ns READ : Bank = 0 Row = 354, Col = 97, Data = 8322de06
|
# tb_core.u_sdram32 : at time 57383.0 ns READ : Bank = 0 Row = 354, Col = 97, Data = 8322de06
|
# READ STATUS: Burst-No: 26 Addr: 0016214d Rxd: 11c91123
|
# READ STATUS: Burst-No: 26 Addr: 0016214d Rxd: 11c91123
|
# tb_core.u_sdram32 : at time 55703.0 ns READ : Bank = 0 Row = 354, Col = 98, Data = a538004a
|
# tb_core.u_sdram32 : at time 57393.0 ns READ : Bank = 0 Row = 354, Col = 98, Data = a538004a
|
# READ STATUS: Burst-No: 27 Addr: 0016214f Rxd: 8322de06
|
# READ STATUS: Burst-No: 27 Addr: 0016214f Rxd: 8322de06
|
# tb_core.u_sdram32 : at time 55713.0 ns READ : Bank = 0 Row = 354, Col = 99, Data = 2505394a
|
# tb_core.u_sdram32 : at time 57403.0 ns READ : Bank = 0 Row = 354, Col = 99, Data = 2505394a
|
# READ STATUS: Burst-No: 28 Addr: 00162151 Rxd: a538004a
|
# READ STATUS: Burst-No: 28 Addr: 00162151 Rxd: a538004a
|
# tb_core.u_sdram32 : at time 55723.0 ns READ : Bank = 0 Row = 354, Col = 100, Data = 20dcbf41
|
# tb_core.u_sdram32 : at time 57413.0 ns READ : Bank = 0 Row = 354, Col = 100, Data = 20dcbf41
|
# READ STATUS: Burst-No: 29 Addr: 00162153 Rxd: 2505394a
|
# READ STATUS: Burst-No: 29 Addr: 00162153 Rxd: 2505394a
|
# tb_core.u_sdram32 : at time 55733.0 ns READ : Bank = 0 Row = 354, Col = 101, Data = 442d0788
|
# tb_core.u_sdram32 : at time 57423.0 ns READ : Bank = 0 Row = 354, Col = 101, Data = 442d0788
|
# READ STATUS: Burst-No: 30 Addr: 00162155 Rxd: 20dcbf41
|
# READ STATUS: Burst-No: 30 Addr: 00162155 Rxd: 20dcbf41
|
# tb_core.u_sdram32 : at time 55743.0 ns READ : Bank = 0 Row = 354, Col = 102, Data = e6e4b8cd
|
# tb_core.u_sdram32 : at time 57433.0 ns READ : Bank = 0 Row = 354, Col = 102, Data = e6e4b8cd
|
# READ STATUS: Burst-No: 31 Addr: 00162157 Rxd: 442d0788
|
# READ STATUS: Burst-No: 31 Addr: 00162157 Rxd: 442d0788
|
# tb_core.u_sdram32 : at time 55753.0 ns READ : Bank = 0 Row = 354, Col = 103, Data = 38eedd71
|
# tb_core.u_sdram32 : at time 57443.0 ns READ : Bank = 0 Row = 354, Col = 103, Data = 38eedd71
|
# READ STATUS: Burst-No: 32 Addr: 00162159 Rxd: e6e4b8cd
|
# READ STATUS: Burst-No: 32 Addr: 00162159 Rxd: e6e4b8cd
|
# tb_core.u_sdram32 : at time 55763.0 ns READ : Bank = 0 Row = 354, Col = 104, Data = 94232228
|
# tb_core.u_sdram32 : at time 57453.0 ns READ : Bank = 0 Row = 354, Col = 104, Data = 94232228
|
# READ STATUS: Burst-No: 33 Addr: 0016215b Rxd: 38eedd71
|
# READ STATUS: Burst-No: 33 Addr: 0016215b Rxd: 38eedd71
|
# tb_core.u_sdram32 : at time 55773.0 ns READ : Bank = 0 Row = 354, Col = 105, Data = 89bfac13
|
# tb_core.u_sdram32 : at time 57463.0 ns READ : Bank = 0 Row = 354, Col = 105, Data = 89bfac13
|
# READ STATUS: Burst-No: 34 Addr: 0016215d Rxd: 94232228
|
# READ STATUS: Burst-No: 34 Addr: 0016215d Rxd: 94232228
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# tb_core.u_sdram32 : at time 55783.0 ns READ : Bank = 0 Row = 354, Col = 106, Data = b600e26c
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# tb_core.u_sdram32 : at time 57473.0 ns READ : Bank = 0 Row = 354, Col = 106, Data = b600e26c
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# tb_core.u_sdram32 : at time 55787.0 ns BST : Burst Terminate
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# tb_core.u_sdram32 : at time 57477.0 ns BST : Burst Terminate
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# READ STATUS: Burst-No: 35 Addr: 0016215f Rxd: 89bfac13
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# READ STATUS: Burst-No: 35 Addr: 0016215f Rxd: 89bfac13
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# tb_core.u_sdram32 : at time 55793.0 ns READ : Bank = 0 Row = 354, Col = 107, Data = aaab2455
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# tb_core.u_sdram32 : at time 57483.0 ns READ : Bank = 0 Row = 354, Col = 107, Data = aaab2455
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# READ STATUS: Burst-No: 36 Addr: 00162161 Rxd: b600e26c
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# READ STATUS: Burst-No: 36 Addr: 00162161 Rxd: b600e26c
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# tb_core.u_sdram32 : at time 55803.0 ns READ : Bank = 0 Row = 354, Col = 108, Data = 7f2767fe
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# tb_core.u_sdram32 : at time 57493.0 ns READ : Bank = 0 Row = 354, Col = 108, Data = 7f2767fe
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# READ STATUS: Burst-No: 37 Addr: 00162163 Rxd: aaab2455
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# READ STATUS: Burst-No: 37 Addr: 00162163 Rxd: aaab2455
|
# READ STATUS: Burst-No: 38 Addr: 00162165 Rxd: 7f2767fe
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# READ STATUS: Burst-No: 38 Addr: 00162165 Rxd: 7f2767fe
|
###############################
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###############################
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# STATUS: SDRAM Write/Read TEST PASSED
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# STATUS: SDRAM Write/Read TEST PASSED
|
###############################
|
###############################
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# ** Note: $finish : ../tb/tb_core.sv(320)
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# ** Note: $finish : ../tb/tb_core.sv(320)
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# Time: 65930 ns Iteration: 0 Instance: /tb_core
|
# Time: 67620 ns Iteration: 0 Instance: /tb_core
|
### test 1: basic_test1 --> PASSED
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### test 1: basic_test1 --> PASSED
|
###########################################
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###########################################
|
|
|
###########################################
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###########################################
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### Test Logs
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### Test Logs
|
