| Line 103... |
Line 103... |
# tb_core.u_sdram32 : at time 13907.0 ns WRITE: Bank = 0 Row = 64, Col = 2, Data = b2c28465
|
# tb_core.u_sdram32 : at time 13907.0 ns WRITE: Bank = 0 Row = 64, Col = 2, Data = b2c28465
|
# Status: Burst-No: 2 Write Address: 00040000 WriteData: b2c28465
|
# Status: Burst-No: 2 Write Address: 00040000 WriteData: b2c28465
|
# tb_core.u_sdram32 : at time 13917.0 ns WRITE: Bank = 0 Row = 64, Col = 3, Data = 89375212
|
# tb_core.u_sdram32 : at time 13917.0 ns WRITE: Bank = 0 Row = 64, Col = 3, Data = 89375212
|
# Status: Burst-No: 3 Write Address: 00040000 WriteData: 89375212
|
# Status: Burst-No: 3 Write Address: 00040000 WriteData: 89375212
|
# tb_core.u_sdram32 : at time 13927.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 13927.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 13973.0 ns READ : Bank = 0 Row = 64, Col = 0, Data = 06b97b0d
|
# tb_core.u_sdram32 : at time 13983.0 ns READ : Bank = 0 Row = 64, Col = 0, Data = 06b97b0d
|
# tb_core.u_sdram32 : at time 13983.0 ns READ : Bank = 0 Row = 64, Col = 1, Data = 46df998d
|
# tb_core.u_sdram32 : at time 13993.0 ns READ : Bank = 0 Row = 64, Col = 1, Data = 46df998d
|
# READ STATUS: Burst-No: 0 Addr: 00040000 Rxd: 06b97b0d
|
# READ STATUS: Burst-No: 0 Addr: 00040000 Rxd: 06b97b0d
|
# tb_core.u_sdram32 : at time 13987.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 13997.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 13993.0 ns READ : Bank = 0 Row = 64, Col = 2, Data = b2c28465
|
# tb_core.u_sdram32 : at time 14003.0 ns READ : Bank = 0 Row = 64, Col = 2, Data = b2c28465
|
# READ STATUS: Burst-No: 1 Addr: 00040002 Rxd: 46df998d
|
# READ STATUS: Burst-No: 1 Addr: 00040002 Rxd: 46df998d
|
# tb_core.u_sdram32 : at time 14003.0 ns READ : Bank = 0 Row = 64, Col = 3, Data = 89375212
|
# tb_core.u_sdram32 : at time 14013.0 ns READ : Bank = 0 Row = 64, Col = 3, Data = 89375212
|
# READ STATUS: Burst-No: 2 Addr: 00040004 Rxd: b2c28465
|
# READ STATUS: Burst-No: 2 Addr: 00040004 Rxd: b2c28465
|
# READ STATUS: Burst-No: 3 Addr: 00040006 Rxd: 89375212
|
# READ STATUS: Burst-No: 3 Addr: 00040006 Rxd: 89375212
|
# Write Address: 00400000, Burst Size: 5
|
# Write Address: 00400000, Burst Size: 5
|
# tb_core.u_sdram32 : at time 14107.0 ns ACT : Bank = 0 Row = 1024
|
# tb_core.u_sdram32 : at time 14117.0 ns ACT : Bank = 0 Row = 1024
|
# tb_core.u_sdram32 : at time 14147.0 ns WRITE: Bank = 0 Row = 1024, Col = 0, Data = 00f3e301
|
# tb_core.u_sdram32 : at time 14157.0 ns WRITE: Bank = 0 Row = 1024, Col = 0, Data = 00f3e301
|
# Status: Burst-No: 0 Write Address: 00400000 WriteData: 00f3e301
|
# Status: Burst-No: 0 Write Address: 00400000 WriteData: 00f3e301
|
# tb_core.u_sdram32 : at time 14157.0 ns WRITE: Bank = 0 Row = 1024, Col = 1, Data = 06d7cd0d
|
# tb_core.u_sdram32 : at time 14167.0 ns WRITE: Bank = 0 Row = 1024, Col = 1, Data = 06d7cd0d
|
# Status: Burst-No: 1 Write Address: 00400000 WriteData: 06d7cd0d
|
# Status: Burst-No: 1 Write Address: 00400000 WriteData: 06d7cd0d
|
# tb_core.u_sdram32 : at time 14167.0 ns WRITE: Bank = 0 Row = 1024, Col = 2, Data = 3b23f176
|
# tb_core.u_sdram32 : at time 14177.0 ns WRITE: Bank = 0 Row = 1024, Col = 2, Data = 3b23f176
|
# Status: Burst-No: 2 Write Address: 00400000 WriteData: 3b23f176
|
# Status: Burst-No: 2 Write Address: 00400000 WriteData: 3b23f176
|
# tb_core.u_sdram32 : at time 14177.0 ns WRITE: Bank = 0 Row = 1024, Col = 3, Data = 1e8dcd3d
|
# tb_core.u_sdram32 : at time 14187.0 ns WRITE: Bank = 0 Row = 1024, Col = 3, Data = 1e8dcd3d
|
# Status: Burst-No: 3 Write Address: 00400000 WriteData: 1e8dcd3d
|
# Status: Burst-No: 3 Write Address: 00400000 WriteData: 1e8dcd3d
|
# tb_core.u_sdram32 : at time 14187.0 ns WRITE: Bank = 0 Row = 1024, Col = 4, Data = 76d457ed
|
# tb_core.u_sdram32 : at time 14197.0 ns WRITE: Bank = 0 Row = 1024, Col = 4, Data = 76d457ed
|
# Status: Burst-No: 4 Write Address: 00400000 WriteData: 76d457ed
|
# Status: Burst-No: 4 Write Address: 00400000 WriteData: 76d457ed
|
# tb_core.u_sdram32 : at time 14197.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 14207.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 14243.0 ns READ : Bank = 0 Row = 1024, Col = 0, Data = 00f3e301
|
# tb_core.u_sdram32 : at time 14263.0 ns READ : Bank = 0 Row = 1024, Col = 0, Data = 00f3e301
|
# tb_core.u_sdram32 : at time 14253.0 ns READ : Bank = 0 Row = 1024, Col = 1, Data = 06d7cd0d
|
# tb_core.u_sdram32 : at time 14273.0 ns READ : Bank = 0 Row = 1024, Col = 1, Data = 06d7cd0d
|
# READ STATUS: Burst-No: 0 Addr: 00400000 Rxd: 00f3e301
|
# READ STATUS: Burst-No: 0 Addr: 00400000 Rxd: 00f3e301
|
# tb_core.u_sdram32 : at time 14263.0 ns READ : Bank = 0 Row = 1024, Col = 2, Data = 3b23f176
|
# tb_core.u_sdram32 : at time 14283.0 ns READ : Bank = 0 Row = 1024, Col = 2, Data = 3b23f176
|
# tb_core.u_sdram32 : at time 14267.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 14287.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 1 Addr: 00400002 Rxd: 06d7cd0d
|
# READ STATUS: Burst-No: 1 Addr: 00400002 Rxd: 06d7cd0d
|
# tb_core.u_sdram32 : at time 14273.0 ns READ : Bank = 0 Row = 1024, Col = 3, Data = 1e8dcd3d
|
# tb_core.u_sdram32 : at time 14293.0 ns READ : Bank = 0 Row = 1024, Col = 3, Data = 1e8dcd3d
|
# READ STATUS: Burst-No: 2 Addr: 00400004 Rxd: 3b23f176
|
# READ STATUS: Burst-No: 2 Addr: 00400004 Rxd: 3b23f176
|
# tb_core.u_sdram32 : at time 14283.0 ns READ : Bank = 0 Row = 1024, Col = 4, Data = 76d457ed
|
# tb_core.u_sdram32 : at time 14303.0 ns READ : Bank = 0 Row = 1024, Col = 4, Data = 76d457ed
|
# READ STATUS: Burst-No: 3 Addr: 00400006 Rxd: 1e8dcd3d
|
# READ STATUS: Burst-No: 3 Addr: 00400006 Rxd: 1e8dcd3d
|
# READ STATUS: Burst-No: 4 Addr: 00400008 Rxd: 76d457ed
|
# READ STATUS: Burst-No: 4 Addr: 00400008 Rxd: 76d457ed
|
# ----------------------------------------
|
# ----------------------------------------
|
# Case-3 Create a Page Cross Over
|
# Case-3 Create a Page Cross Over
|
# ----------------------------------------
|
# ----------------------------------------
|
# Write Address: 00000ff0, Burst Size: 8
|
# Write Address: 00000ff0, Burst Size: 8
|
# tb_core.u_sdram32 : at time 14387.0 ns ACT : Bank = 3 Row = 0
|
# tb_core.u_sdram32 : at time 14407.0 ns ACT : Bank = 3 Row = 0
|
# tb_core.u_sdram32 : at time 14397.0 ns ACT : Bank = 0 Row = 1
|
# tb_core.u_sdram32 : at time 14447.0 ns WRITE: Bank = 3 Row = 0, Col = 252, Data = 462df78c
|
# tb_core.u_sdram32 : at time 14397.0 ns ERROR: tRRD violation during Activate bank = 0
|
|
# tb_core.u_sdram32 : at time 14427.0 ns WRITE: Bank = 3 Row = 0, Col = 252, Data = 462df78c
|
|
# Status: Burst-No: 0 Write Address: 00000ff0 WriteData: 462df78c
|
# Status: Burst-No: 0 Write Address: 00000ff0 WriteData: 462df78c
|
# tb_core.u_sdram32 : at time 14437.0 ns WRITE: Bank = 3 Row = 0, Col = 253, Data = 7cfde9f9
|
# tb_core.u_sdram32 : at time 14457.0 ns WRITE: Bank = 3 Row = 0, Col = 253, Data = 7cfde9f9
|
# Status: Burst-No: 1 Write Address: 00000ff0 WriteData: 7cfde9f9
|
# Status: Burst-No: 1 Write Address: 00000ff0 WriteData: 7cfde9f9
|
# tb_core.u_sdram32 : at time 14447.0 ns WRITE: Bank = 3 Row = 0, Col = 254, Data = e33724c6
|
# tb_core.u_sdram32 : at time 14467.0 ns WRITE: Bank = 3 Row = 0, Col = 254, Data = e33724c6
|
# Status: Burst-No: 2 Write Address: 00000ff0 WriteData: e33724c6
|
# Status: Burst-No: 2 Write Address: 00000ff0 WriteData: e33724c6
|
# tb_core.u_sdram32 : at time 14457.0 ns WRITE: Bank = 3 Row = 0, Col = 255, Data = e2f784c5
|
# tb_core.u_sdram32 : at time 14477.0 ns WRITE: Bank = 3 Row = 0, Col = 255, Data = e2f784c5
|
# Status: Burst-No: 3 Write Address: 00000ff0 WriteData: e2f784c5
|
# Status: Burst-No: 3 Write Address: 00000ff0 WriteData: e2f784c5
|
# tb_core.u_sdram32 : at time 14467.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 14487.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 14477.0 ns WRITE: Bank = 0 Row = 1, Col = 0, Data = d513d2aa
|
# tb_core.u_sdram32 : at time 14497.0 ns ACT : Bank = 0 Row = 1
|
|
# tb_core.u_sdram32 : at time 14537.0 ns WRITE: Bank = 0 Row = 1, Col = 0, Data = d513d2aa
|
# Status: Burst-No: 4 Write Address: 00000ff0 WriteData: d513d2aa
|
# Status: Burst-No: 4 Write Address: 00000ff0 WriteData: d513d2aa
|
# tb_core.u_sdram32 : at time 14487.0 ns WRITE: Bank = 0 Row = 1, Col = 1, Data = 72aff7e5
|
# tb_core.u_sdram32 : at time 14547.0 ns WRITE: Bank = 0 Row = 1, Col = 1, Data = 72aff7e5
|
# Status: Burst-No: 5 Write Address: 00000ff0 WriteData: 72aff7e5
|
# Status: Burst-No: 5 Write Address: 00000ff0 WriteData: 72aff7e5
|
# tb_core.u_sdram32 : at time 14497.0 ns WRITE: Bank = 0 Row = 1, Col = 2, Data = bbd27277
|
# tb_core.u_sdram32 : at time 14557.0 ns WRITE: Bank = 0 Row = 1, Col = 2, Data = bbd27277
|
# Status: Burst-No: 6 Write Address: 00000ff0 WriteData: bbd27277
|
# Status: Burst-No: 6 Write Address: 00000ff0 WriteData: bbd27277
|
# tb_core.u_sdram32 : at time 14507.0 ns WRITE: Bank = 0 Row = 1, Col = 3, Data = 8932d612
|
# tb_core.u_sdram32 : at time 14567.0 ns WRITE: Bank = 0 Row = 1, Col = 3, Data = 8932d612
|
# Status: Burst-No: 7 Write Address: 00000ff0 WriteData: 8932d612
|
# Status: Burst-No: 7 Write Address: 00000ff0 WriteData: 8932d612
|
# tb_core.u_sdram32 : at time 14517.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 14577.0 ns BST : Burst Terminate
|
# Write Address: 00010ff4, Burst Size: 15
|
# Write Address: 00010ff4, Burst Size: 15
|
# tb_core.u_sdram32 : at time 14587.0 ns ACT : Bank = 3 Row = 16
|
# tb_core.u_sdram32 : at time 14647.0 ns ACT : Bank = 3 Row = 16
|
# tb_core.u_sdram32 : at time 14597.0 ns ACT : Bank = 0 Row = 17
|
# tb_core.u_sdram32 : at time 14687.0 ns WRITE: Bank = 3 Row = 16, Col = 253, Data = 47ecdb8f
|
# tb_core.u_sdram32 : at time 14597.0 ns ERROR: tRRD violation during Activate bank = 0
|
|
# tb_core.u_sdram32 : at time 14627.0 ns WRITE: Bank = 3 Row = 16, Col = 253, Data = 47ecdb8f
|
|
# Status: Burst-No: 0 Write Address: 00010ff4 WriteData: 47ecdb8f
|
# Status: Burst-No: 0 Write Address: 00010ff4 WriteData: 47ecdb8f
|
# tb_core.u_sdram32 : at time 14637.0 ns WRITE: Bank = 3 Row = 16, Col = 254, Data = 793069f2
|
# tb_core.u_sdram32 : at time 14697.0 ns WRITE: Bank = 3 Row = 16, Col = 254, Data = 793069f2
|
# Status: Burst-No: 1 Write Address: 00010ff4 WriteData: 793069f2
|
# Status: Burst-No: 1 Write Address: 00010ff4 WriteData: 793069f2
|
# tb_core.u_sdram32 : at time 14647.0 ns WRITE: Bank = 3 Row = 16, Col = 255, Data = e77696ce
|
# tb_core.u_sdram32 : at time 14707.0 ns WRITE: Bank = 3 Row = 16, Col = 255, Data = e77696ce
|
# Status: Burst-No: 2 Write Address: 00010ff4 WriteData: e77696ce
|
# Status: Burst-No: 2 Write Address: 00010ff4 WriteData: e77696ce
|
# tb_core.u_sdram32 : at time 14657.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 14717.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 14667.0 ns WRITE: Bank = 0 Row = 17, Col = 0, Data = f4007ae8
|
# tb_core.u_sdram32 : at time 14737.0 ns ACT : Bank = 0 Row = 17
|
|
# tb_core.u_sdram32 : at time 14777.0 ns WRITE: Bank = 0 Row = 17, Col = 0, Data = f4007ae8
|
# Status: Burst-No: 3 Write Address: 00010ff4 WriteData: f4007ae8
|
# Status: Burst-No: 3 Write Address: 00010ff4 WriteData: f4007ae8
|
# tb_core.u_sdram32 : at time 14677.0 ns WRITE: Bank = 0 Row = 17, Col = 1, Data = e2ca4ec5
|
# tb_core.u_sdram32 : at time 14787.0 ns WRITE: Bank = 0 Row = 17, Col = 1, Data = e2ca4ec5
|
# Status: Burst-No: 4 Write Address: 00010ff4 WriteData: e2ca4ec5
|
# Status: Burst-No: 4 Write Address: 00010ff4 WriteData: e2ca4ec5
|
# tb_core.u_sdram32 : at time 14687.0 ns WRITE: Bank = 0 Row = 17, Col = 2, Data = 2e58495c
|
# tb_core.u_sdram32 : at time 14797.0 ns WRITE: Bank = 0 Row = 17, Col = 2, Data = 2e58495c
|
# Status: Burst-No: 5 Write Address: 00010ff4 WriteData: 2e58495c
|
# Status: Burst-No: 5 Write Address: 00010ff4 WriteData: 2e58495c
|
# tb_core.u_sdram32 : at time 14697.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 14807.0 ns WRITE: Bank = 0 Row = 17, Col = 3, Data = de8e28bd
|
# tb_core.u_sdram32 : at time 14707.0 ns WRITE: Bank = 0 Row = 17, Col = 3, Data = de8e28bd
|
|
# Status: Burst-No: 6 Write Address: 00010ff4 WriteData: de8e28bd
|
# Status: Burst-No: 6 Write Address: 00010ff4 WriteData: de8e28bd
|
# tb_core.u_sdram32 : at time 14717.0 ns WRITE: Bank = 0 Row = 17, Col = 4, Data = 96ab582d
|
# tb_core.u_sdram32 : at time 14817.0 ns WRITE: Bank = 0 Row = 17, Col = 4, Data = 96ab582d
|
# Status: Burst-No: 7 Write Address: 00010ff4 WriteData: 96ab582d
|
# Status: Burst-No: 7 Write Address: 00010ff4 WriteData: 96ab582d
|
# tb_core.u_sdram32 : at time 14727.0 ns WRITE: Bank = 0 Row = 17, Col = 5, Data = b2a72665
|
# tb_core.u_sdram32 : at time 14827.0 ns WRITE: Bank = 0 Row = 17, Col = 5, Data = b2a72665
|
# Status: Burst-No: 8 Write Address: 00010ff4 WriteData: b2a72665
|
# Status: Burst-No: 8 Write Address: 00010ff4 WriteData: b2a72665
|
# tb_core.u_sdram32 : at time 14737.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 14837.0 ns WRITE: Bank = 0 Row = 17, Col = 6, Data = b1ef6263
|
# tb_core.u_sdram32 : at time 14747.0 ns WRITE: Bank = 0 Row = 17, Col = 6, Data = b1ef6263
|
|
# Status: Burst-No: 9 Write Address: 00010ff4 WriteData: b1ef6263
|
# Status: Burst-No: 9 Write Address: 00010ff4 WriteData: b1ef6263
|
# tb_core.u_sdram32 : at time 14757.0 ns WRITE: Bank = 0 Row = 17, Col = 7, Data = 0573870a
|
# tb_core.u_sdram32 : at time 14847.0 ns WRITE: Bank = 0 Row = 17, Col = 7, Data = 0573870a
|
# Status: Burst-No: 10 Write Address: 00010ff4 WriteData: 0573870a
|
# Status: Burst-No: 10 Write Address: 00010ff4 WriteData: 0573870a
|
# tb_core.u_sdram32 : at time 14767.0 ns WRITE: Bank = 0 Row = 17, Col = 8, Data = c03b2280
|
# tb_core.u_sdram32 : at time 14857.0 ns WRITE: Bank = 0 Row = 17, Col = 8, Data = c03b2280
|
# Status: Burst-No: 11 Write Address: 00010ff4 WriteData: c03b2280
|
# Status: Burst-No: 11 Write Address: 00010ff4 WriteData: c03b2280
|
# tb_core.u_sdram32 : at time 14777.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 14867.0 ns WRITE: Bank = 0 Row = 17, Col = 9, Data = 10642120
|
# tb_core.u_sdram32 : at time 14787.0 ns WRITE: Bank = 0 Row = 17, Col = 9, Data = 10642120
|
|
# Status: Burst-No: 12 Write Address: 00010ff4 WriteData: 10642120
|
# Status: Burst-No: 12 Write Address: 00010ff4 WriteData: 10642120
|
# tb_core.u_sdram32 : at time 14797.0 ns WRITE: Bank = 0 Row = 17, Col = 10, Data = 557845aa
|
# tb_core.u_sdram32 : at time 14877.0 ns WRITE: Bank = 0 Row = 17, Col = 10, Data = 557845aa
|
# Status: Burst-No: 13 Write Address: 00010ff4 WriteData: 557845aa
|
# Status: Burst-No: 13 Write Address: 00010ff4 WriteData: 557845aa
|
# tb_core.u_sdram32 : at time 14807.0 ns WRITE: Bank = 0 Row = 17, Col = 11, Data = cecccc9d
|
# tb_core.u_sdram32 : at time 14887.0 ns WRITE: Bank = 0 Row = 17, Col = 11, Data = cecccc9d
|
# Status: Burst-No: 14 Write Address: 00010ff4 WriteData: cecccc9d
|
# Status: Burst-No: 14 Write Address: 00010ff4 WriteData: cecccc9d
|
# tb_core.u_sdram32 : at time 14817.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 14897.0 ns BST : Burst Terminate
|
# Write Address: 00020ff8, Burst Size: 15
|
# Write Address: 00020ff8, Burst Size: 15
|
# tb_core.u_sdram32 : at time 14887.0 ns ACT : Bank = 3 Row = 32
|
# tb_core.u_sdram32 : at time 14967.0 ns ACT : Bank = 3 Row = 32
|
# tb_core.u_sdram32 : at time 14897.0 ns ACT : Bank = 0 Row = 33
|
# tb_core.u_sdram32 : at time 15007.0 ns WRITE: Bank = 3 Row = 32, Col = 254, Data = cb203e96
|
# tb_core.u_sdram32 : at time 14897.0 ns ERROR: tRRD violation during Activate bank = 0
|
|
# tb_core.u_sdram32 : at time 14927.0 ns WRITE: Bank = 3 Row = 32, Col = 254, Data = cb203e96
|
|
# Status: Burst-No: 0 Write Address: 00020ff8 WriteData: cb203e96
|
# Status: Burst-No: 0 Write Address: 00020ff8 WriteData: cb203e96
|
# tb_core.u_sdram32 : at time 14937.0 ns WRITE: Bank = 3 Row = 32, Col = 255, Data = 8983b813
|
# tb_core.u_sdram32 : at time 15017.0 ns WRITE: Bank = 3 Row = 32, Col = 255, Data = 8983b813
|
# Status: Burst-No: 1 Write Address: 00020ff8 WriteData: 8983b813
|
# Status: Burst-No: 1 Write Address: 00020ff8 WriteData: 8983b813
|
# tb_core.u_sdram32 : at time 14947.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 15027.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 14957.0 ns WRITE: Bank = 0 Row = 33, Col = 0, Data = 86bc380d
|
# tb_core.u_sdram32 : at time 15057.0 ns ACT : Bank = 0 Row = 33
|
|
# tb_core.u_sdram32 : at time 15097.0 ns WRITE: Bank = 0 Row = 33, Col = 0, Data = 86bc380d
|
# Status: Burst-No: 2 Write Address: 00020ff8 WriteData: 86bc380d
|
# Status: Burst-No: 2 Write Address: 00020ff8 WriteData: 86bc380d
|
# tb_core.u_sdram32 : at time 14967.0 ns WRITE: Bank = 0 Row = 33, Col = 1, Data = a9a7d653
|
# tb_core.u_sdram32 : at time 15107.0 ns WRITE: Bank = 0 Row = 33, Col = 1, Data = a9a7d653
|
# Status: Burst-No: 3 Write Address: 00020ff8 WriteData: a9a7d653
|
# Status: Burst-No: 3 Write Address: 00020ff8 WriteData: a9a7d653
|
# tb_core.u_sdram32 : at time 14977.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 15117.0 ns WRITE: Bank = 0 Row = 33, Col = 2, Data = 359fdd6b
|
# tb_core.u_sdram32 : at time 14987.0 ns WRITE: Bank = 0 Row = 33, Col = 2, Data = 359fdd6b
|
|
# Status: Burst-No: 4 Write Address: 00020ff8 WriteData: 359fdd6b
|
# Status: Burst-No: 4 Write Address: 00020ff8 WriteData: 359fdd6b
|
# tb_core.u_sdram32 : at time 14997.0 ns WRITE: Bank = 0 Row = 33, Col = 3, Data = eaa62ad5
|
# tb_core.u_sdram32 : at time 15127.0 ns WRITE: Bank = 0 Row = 33, Col = 3, Data = eaa62ad5
|
# Status: Burst-No: 5 Write Address: 00020ff8 WriteData: eaa62ad5
|
# Status: Burst-No: 5 Write Address: 00020ff8 WriteData: eaa62ad5
|
# tb_core.u_sdram32 : at time 15007.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 15137.0 ns WRITE: Bank = 0 Row = 33, Col = 4, Data = 81174a02
|
# tb_core.u_sdram32 : at time 15017.0 ns WRITE: Bank = 0 Row = 33, Col = 4, Data = 81174a02
|
|
# Status: Burst-No: 6 Write Address: 00020ff8 WriteData: 81174a02
|
# Status: Burst-No: 6 Write Address: 00020ff8 WriteData: 81174a02
|
# tb_core.u_sdram32 : at time 15027.0 ns WRITE: Bank = 0 Row = 33, Col = 5, Data = d7563eae
|
# tb_core.u_sdram32 : at time 15147.0 ns WRITE: Bank = 0 Row = 33, Col = 5, Data = d7563eae
|
# Status: Burst-No: 7 Write Address: 00020ff8 WriteData: d7563eae
|
# Status: Burst-No: 7 Write Address: 00020ff8 WriteData: d7563eae
|
# tb_core.u_sdram32 : at time 15037.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 15157.0 ns WRITE: Bank = 0 Row = 33, Col = 6, Data = 0effe91d
|
# tb_core.u_sdram32 : at time 15047.0 ns WRITE: Bank = 0 Row = 33, Col = 6, Data = 0effe91d
|
|
# Status: Burst-No: 8 Write Address: 00020ff8 WriteData: 0effe91d
|
# Status: Burst-No: 8 Write Address: 00020ff8 WriteData: 0effe91d
|
# tb_core.u_sdram32 : at time 15057.0 ns WRITE: Bank = 0 Row = 33, Col = 7, Data = e7c572cf
|
# tb_core.u_sdram32 : at time 15167.0 ns WRITE: Bank = 0 Row = 33, Col = 7, Data = e7c572cf
|
# Status: Burst-No: 9 Write Address: 00020ff8 WriteData: e7c572cf
|
# Status: Burst-No: 9 Write Address: 00020ff8 WriteData: e7c572cf
|
# tb_core.u_sdram32 : at time 15067.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 15177.0 ns WRITE: Bank = 0 Row = 33, Col = 8, Data = 11844923
|
# tb_core.u_sdram32 : at time 15077.0 ns WRITE: Bank = 0 Row = 33, Col = 8, Data = 11844923
|
|
# Status: Burst-No: 10 Write Address: 00020ff8 WriteData: 11844923
|
# Status: Burst-No: 10 Write Address: 00020ff8 WriteData: 11844923
|
# tb_core.u_sdram32 : at time 15087.0 ns WRITE: Bank = 0 Row = 33, Col = 9, Data = 0509650a
|
# tb_core.u_sdram32 : at time 15187.0 ns WRITE: Bank = 0 Row = 33, Col = 9, Data = 0509650a
|
# Status: Burst-No: 11 Write Address: 00020ff8 WriteData: 0509650a
|
# Status: Burst-No: 11 Write Address: 00020ff8 WriteData: 0509650a
|
# tb_core.u_sdram32 : at time 15097.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 15197.0 ns WRITE: Bank = 0 Row = 33, Col = 10, Data = e5730aca
|
# tb_core.u_sdram32 : at time 15107.0 ns WRITE: Bank = 0 Row = 33, Col = 10, Data = e5730aca
|
|
# Status: Burst-No: 12 Write Address: 00020ff8 WriteData: e5730aca
|
# Status: Burst-No: 12 Write Address: 00020ff8 WriteData: e5730aca
|
# tb_core.u_sdram32 : at time 15117.0 ns WRITE: Bank = 0 Row = 33, Col = 11, Data = 9e314c3c
|
# tb_core.u_sdram32 : at time 15207.0 ns WRITE: Bank = 0 Row = 33, Col = 11, Data = 9e314c3c
|
# Status: Burst-No: 13 Write Address: 00020ff8 WriteData: 9e314c3c
|
# Status: Burst-No: 13 Write Address: 00020ff8 WriteData: 9e314c3c
|
# tb_core.u_sdram32 : at time 15127.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 15217.0 ns WRITE: Bank = 0 Row = 33, Col = 12, Data = 7968bdf2
|
# tb_core.u_sdram32 : at time 15137.0 ns WRITE: Bank = 0 Row = 33, Col = 12, Data = 7968bdf2
|
|
# Status: Burst-No: 14 Write Address: 00020ff8 WriteData: 7968bdf2
|
# Status: Burst-No: 14 Write Address: 00020ff8 WriteData: 7968bdf2
|
# tb_core.u_sdram32 : at time 15147.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 15227.0 ns BST : Burst Terminate
|
# Write Address: 00030ffc, Burst Size: 15
|
# Write Address: 00030ffc, Burst Size: 15
|
# tb_core.u_sdram32 : at time 15217.0 ns ACT : Bank = 3 Row = 48
|
# tb_core.u_sdram32 : at time 15297.0 ns ACT : Bank = 3 Row = 48
|
# tb_core.u_sdram32 : at time 15227.0 ns ACT : Bank = 0 Row = 49
|
# tb_core.u_sdram32 : at time 15337.0 ns WRITE: Bank = 3 Row = 48, Col = 255, Data = 452e618a
|
# tb_core.u_sdram32 : at time 15227.0 ns ERROR: tRRD violation during Activate bank = 0
|
|
# tb_core.u_sdram32 : at time 15257.0 ns WRITE: Bank = 3 Row = 48, Col = 255, Data = 452e618a
|
|
# Status: Burst-No: 0 Write Address: 00030ffc WriteData: 452e618a
|
# Status: Burst-No: 0 Write Address: 00030ffc WriteData: 452e618a
|
# tb_core.u_sdram32 : at time 15267.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 15347.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 15277.0 ns WRITE: Bank = 0 Row = 49, Col = 0, Data = 20c4b341
|
# tb_core.u_sdram32 : at time 15407.0 ns ACT : Bank = 0 Row = 49
|
|
# tb_core.u_sdram32 : at time 15447.0 ns WRITE: Bank = 0 Row = 49, Col = 0, Data = 20c4b341
|
# Status: Burst-No: 1 Write Address: 00030ffc WriteData: 20c4b341
|
# Status: Burst-No: 1 Write Address: 00030ffc WriteData: 20c4b341
|
# tb_core.u_sdram32 : at time 15287.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 15457.0 ns WRITE: Bank = 0 Row = 49, Col = 1, Data = ec4b34d8
|
# tb_core.u_sdram32 : at time 15297.0 ns WRITE: Bank = 0 Row = 49, Col = 1, Data = ec4b34d8
|
|
# Status: Burst-No: 2 Write Address: 00030ffc WriteData: ec4b34d8
|
# Status: Burst-No: 2 Write Address: 00030ffc WriteData: ec4b34d8
|
# tb_core.u_sdram32 : at time 15307.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 15467.0 ns WRITE: Bank = 0 Row = 49, Col = 2, Data = 3c20f378
|
# tb_core.u_sdram32 : at time 15317.0 ns WRITE: Bank = 0 Row = 49, Col = 2, Data = 3c20f378
|
|
# Status: Burst-No: 3 Write Address: 00030ffc WriteData: 3c20f378
|
# Status: Burst-No: 3 Write Address: 00030ffc WriteData: 3c20f378
|
# tb_core.u_sdram32 : at time 15327.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 15477.0 ns WRITE: Bank = 0 Row = 49, Col = 3, Data = c48a1289
|
# tb_core.u_sdram32 : at time 15337.0 ns WRITE: Bank = 0 Row = 49, Col = 3, Data = c48a1289
|
|
# Status: Burst-No: 4 Write Address: 00030ffc WriteData: c48a1289
|
# Status: Burst-No: 4 Write Address: 00030ffc WriteData: c48a1289
|
# tb_core.u_sdram32 : at time 15347.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 15487.0 ns WRITE: Bank = 0 Row = 49, Col = 4, Data = 75c50deb
|
# tb_core.u_sdram32 : at time 15357.0 ns WRITE: Bank = 0 Row = 49, Col = 4, Data = 75c50deb
|
|
# Status: Burst-No: 5 Write Address: 00030ffc WriteData: 75c50deb
|
# Status: Burst-No: 5 Write Address: 00030ffc WriteData: 75c50deb
|
# tb_core.u_sdram32 : at time 15367.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 15497.0 ns WRITE: Bank = 0 Row = 49, Col = 5, Data = 5b0265b6
|
# tb_core.u_sdram32 : at time 15377.0 ns WRITE: Bank = 0 Row = 49, Col = 5, Data = 5b0265b6
|
|
# Status: Burst-No: 6 Write Address: 00030ffc WriteData: 5b0265b6
|
# Status: Burst-No: 6 Write Address: 00030ffc WriteData: 5b0265b6
|
# tb_core.u_sdram32 : at time 15387.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 15507.0 ns WRITE: Bank = 0 Row = 49, Col = 6, Data = 634bf9c6
|
# tb_core.u_sdram32 : at time 15397.0 ns WRITE: Bank = 0 Row = 49, Col = 6, Data = 634bf9c6
|
|
# Status: Burst-No: 7 Write Address: 00030ffc WriteData: 634bf9c6
|
# Status: Burst-No: 7 Write Address: 00030ffc WriteData: 634bf9c6
|
# tb_core.u_sdram32 : at time 15407.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 15517.0 ns WRITE: Bank = 0 Row = 49, Col = 7, Data = 571513ae
|
# tb_core.u_sdram32 : at time 15417.0 ns WRITE: Bank = 0 Row = 49, Col = 7, Data = 571513ae
|
|
# Status: Burst-No: 8 Write Address: 00030ffc WriteData: 571513ae
|
# Status: Burst-No: 8 Write Address: 00030ffc WriteData: 571513ae
|
# tb_core.u_sdram32 : at time 15427.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 15527.0 ns WRITE: Bank = 0 Row = 49, Col = 8, Data = de7502bc
|
# tb_core.u_sdram32 : at time 15437.0 ns WRITE: Bank = 0 Row = 49, Col = 8, Data = de7502bc
|
|
# Status: Burst-No: 9 Write Address: 00030ffc WriteData: de7502bc
|
# Status: Burst-No: 9 Write Address: 00030ffc WriteData: de7502bc
|
# tb_core.u_sdram32 : at time 15447.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 15537.0 ns WRITE: Bank = 0 Row = 49, Col = 9, Data = 150fdd2a
|
# tb_core.u_sdram32 : at time 15457.0 ns WRITE: Bank = 0 Row = 49, Col = 9, Data = 150fdd2a
|
|
# Status: Burst-No: 10 Write Address: 00030ffc WriteData: 150fdd2a
|
# Status: Burst-No: 10 Write Address: 00030ffc WriteData: 150fdd2a
|
# tb_core.u_sdram32 : at time 15467.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 15547.0 ns WRITE: Bank = 0 Row = 49, Col = 10, Data = 85d79a0b
|
# tb_core.u_sdram32 : at time 15477.0 ns WRITE: Bank = 0 Row = 49, Col = 10, Data = 85d79a0b
|
|
# Status: Burst-No: 11 Write Address: 00030ffc WriteData: 85d79a0b
|
# Status: Burst-No: 11 Write Address: 00030ffc WriteData: 85d79a0b
|
# tb_core.u_sdram32 : at time 15487.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 15557.0 ns WRITE: Bank = 0 Row = 49, Col = 11, Data = b897be71
|
# tb_core.u_sdram32 : at time 15497.0 ns WRITE: Bank = 0 Row = 49, Col = 11, Data = b897be71
|
|
# Status: Burst-No: 12 Write Address: 00030ffc WriteData: b897be71
|
# Status: Burst-No: 12 Write Address: 00030ffc WriteData: b897be71
|
# tb_core.u_sdram32 : at time 15507.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 15567.0 ns WRITE: Bank = 0 Row = 49, Col = 12, Data = 42f24185
|
# tb_core.u_sdram32 : at time 15517.0 ns WRITE: Bank = 0 Row = 49, Col = 12, Data = 42f24185
|
|
# Status: Burst-No: 13 Write Address: 00030ffc WriteData: 42f24185
|
# Status: Burst-No: 13 Write Address: 00030ffc WriteData: 42f24185
|
# tb_core.u_sdram32 : at time 15527.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 15577.0 ns WRITE: Bank = 0 Row = 49, Col = 13, Data = 27f2554f
|
# tb_core.u_sdram32 : at time 15537.0 ns WRITE: Bank = 0 Row = 49, Col = 13, Data = 27f2554f
|
|
# Status: Burst-No: 14 Write Address: 00030ffc WriteData: 27f2554f
|
# Status: Burst-No: 14 Write Address: 00030ffc WriteData: 27f2554f
|
# tb_core.u_sdram32 : at time 15547.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 15587.0 ns BST : Burst Terminate
|
# Write Address: 00040fe0, Burst Size: 15
|
# Write Address: 00040fe0, Burst Size: 15
|
# tb_core.u_sdram32 : at time 15617.0 ns ACT : Bank = 3 Row = 64
|
# tb_core.u_sdram32 : at time 15657.0 ns ACT : Bank = 3 Row = 64
|
# tb_core.u_sdram32 : at time 15627.0 ns ACT : Bank = 0 Row = 65
|
# tb_core.u_sdram32 : at time 15697.0 ns WRITE: Bank = 3 Row = 64, Col = 248, Data = 9dcc603b
|
# tb_core.u_sdram32 : at time 15627.0 ns ERROR: tRRD violation during Activate bank = 0
|
|
# tb_core.u_sdram32 : at time 15657.0 ns WRITE: Bank = 3 Row = 64, Col = 248, Data = 9dcc603b
|
|
# Status: Burst-No: 0 Write Address: 00040fe0 WriteData: 9dcc603b
|
# Status: Burst-No: 0 Write Address: 00040fe0 WriteData: 9dcc603b
|
# tb_core.u_sdram32 : at time 15667.0 ns WRITE: Bank = 3 Row = 64, Col = 249, Data = 1d06333a
|
# tb_core.u_sdram32 : at time 15707.0 ns WRITE: Bank = 3 Row = 64, Col = 249, Data = 1d06333a
|
# Status: Burst-No: 1 Write Address: 00040fe0 WriteData: 1d06333a
|
# Status: Burst-No: 1 Write Address: 00040fe0 WriteData: 1d06333a
|
# tb_core.u_sdram32 : at time 15677.0 ns WRITE: Bank = 3 Row = 64, Col = 250, Data = bf23327e
|
# tb_core.u_sdram32 : at time 15717.0 ns WRITE: Bank = 3 Row = 64, Col = 250, Data = bf23327e
|
# Status: Burst-No: 2 Write Address: 00040fe0 WriteData: bf23327e
|
# Status: Burst-No: 2 Write Address: 00040fe0 WriteData: bf23327e
|
# tb_core.u_sdram32 : at time 15687.0 ns WRITE: Bank = 3 Row = 64, Col = 251, Data = 0aaa4b15
|
# tb_core.u_sdram32 : at time 15727.0 ns WRITE: Bank = 3 Row = 64, Col = 251, Data = 0aaa4b15
|
# Status: Burst-No: 3 Write Address: 00040fe0 WriteData: 0aaa4b15
|
# Status: Burst-No: 3 Write Address: 00040fe0 WriteData: 0aaa4b15
|
# tb_core.u_sdram32 : at time 15697.0 ns WRITE: Bank = 3 Row = 64, Col = 252, Data = 78d99bf1
|
# tb_core.u_sdram32 : at time 15737.0 ns WRITE: Bank = 3 Row = 64, Col = 252, Data = 78d99bf1
|
# Status: Burst-No: 4 Write Address: 00040fe0 WriteData: 78d99bf1
|
# Status: Burst-No: 4 Write Address: 00040fe0 WriteData: 78d99bf1
|
# tb_core.u_sdram32 : at time 15707.0 ns WRITE: Bank = 3 Row = 64, Col = 253, Data = 6c9c4bd9
|
# tb_core.u_sdram32 : at time 15747.0 ns ACT : Bank = 0 Row = 65
|
|
# tb_core.u_sdram32 : at time 15747.0 ns WRITE: Bank = 3 Row = 64, Col = 253, Data = 6c9c4bd9
|
# Status: Burst-No: 5 Write Address: 00040fe0 WriteData: 6c9c4bd9
|
# Status: Burst-No: 5 Write Address: 00040fe0 WriteData: 6c9c4bd9
|
# tb_core.u_sdram32 : at time 15717.0 ns WRITE: Bank = 3 Row = 64, Col = 254, Data = 31230762
|
# tb_core.u_sdram32 : at time 15757.0 ns WRITE: Bank = 3 Row = 64, Col = 254, Data = 31230762
|
# Status: Burst-No: 6 Write Address: 00040fe0 WriteData: 31230762
|
# Status: Burst-No: 6 Write Address: 00040fe0 WriteData: 31230762
|
# tb_core.u_sdram32 : at time 15727.0 ns WRITE: Bank = 3 Row = 64, Col = 255, Data = 2635fb4c
|
# tb_core.u_sdram32 : at time 15767.0 ns WRITE: Bank = 3 Row = 64, Col = 255, Data = 2635fb4c
|
# Status: Burst-No: 7 Write Address: 00040fe0 WriteData: 2635fb4c
|
# Status: Burst-No: 7 Write Address: 00040fe0 WriteData: 2635fb4c
|
# tb_core.u_sdram32 : at time 15737.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 15777.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 15747.0 ns WRITE: Bank = 0 Row = 65, Col = 0, Data = 4fa1559f
|
# tb_core.u_sdram32 : at time 15787.0 ns WRITE: Bank = 0 Row = 65, Col = 0, Data = 4fa1559f
|
# Status: Burst-No: 8 Write Address: 00040fe0 WriteData: 4fa1559f
|
# Status: Burst-No: 8 Write Address: 00040fe0 WriteData: 4fa1559f
|
# tb_core.u_sdram32 : at time 15757.0 ns WRITE: Bank = 0 Row = 65, Col = 1, Data = 47b9a18f
|
# tb_core.u_sdram32 : at time 15797.0 ns WRITE: Bank = 0 Row = 65, Col = 1, Data = 47b9a18f
|
# Status: Burst-No: 9 Write Address: 00040fe0 WriteData: 47b9a18f
|
# Status: Burst-No: 9 Write Address: 00040fe0 WriteData: 47b9a18f
|
# tb_core.u_sdram32 : at time 15767.0 ns WRITE: Bank = 0 Row = 65, Col = 2, Data = 7c6da9f8
|
# tb_core.u_sdram32 : at time 15807.0 ns WRITE: Bank = 0 Row = 65, Col = 2, Data = 7c6da9f8
|
# Status: Burst-No: 10 Write Address: 00040fe0 WriteData: 7c6da9f8
|
# Status: Burst-No: 10 Write Address: 00040fe0 WriteData: 7c6da9f8
|
# tb_core.u_sdram32 : at time 15777.0 ns WRITE: Bank = 0 Row = 65, Col = 3, Data = dbcd60b7
|
# tb_core.u_sdram32 : at time 15817.0 ns WRITE: Bank = 0 Row = 65, Col = 3, Data = dbcd60b7
|
# Status: Burst-No: 11 Write Address: 00040fe0 WriteData: dbcd60b7
|
# Status: Burst-No: 11 Write Address: 00040fe0 WriteData: dbcd60b7
|
# tb_core.u_sdram32 : at time 15787.0 ns WRITE: Bank = 0 Row = 65, Col = 4, Data = cfc4569f
|
# tb_core.u_sdram32 : at time 15827.0 ns WRITE: Bank = 0 Row = 65, Col = 4, Data = cfc4569f
|
# Status: Burst-No: 12 Write Address: 00040fe0 WriteData: cfc4569f
|
# Status: Burst-No: 12 Write Address: 00040fe0 WriteData: cfc4569f
|
# tb_core.u_sdram32 : at time 15797.0 ns WRITE: Bank = 0 Row = 65, Col = 5, Data = ae7d945c
|
# tb_core.u_sdram32 : at time 15837.0 ns WRITE: Bank = 0 Row = 65, Col = 5, Data = ae7d945c
|
# Status: Burst-No: 13 Write Address: 00040fe0 WriteData: ae7d945c
|
# Status: Burst-No: 13 Write Address: 00040fe0 WriteData: ae7d945c
|
# tb_core.u_sdram32 : at time 15807.0 ns WRITE: Bank = 0 Row = 65, Col = 6, Data = adcbc05b
|
# tb_core.u_sdram32 : at time 15847.0 ns WRITE: Bank = 0 Row = 65, Col = 6, Data = adcbc05b
|
# Status: Burst-No: 14 Write Address: 00040fe0 WriteData: adcbc05b
|
# Status: Burst-No: 14 Write Address: 00040fe0 WriteData: adcbc05b
|
# tb_core.u_sdram32 : at time 15817.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 15857.0 ns BST : Burst Terminate
|
# Write Address: 00050fe4, Burst Size: 15
|
# Write Address: 00050fe4, Burst Size: 15
|
# tb_core.u_sdram32 : at time 15887.0 ns ACT : Bank = 3 Row = 80
|
# tb_core.u_sdram32 : at time 15927.0 ns ACT : Bank = 3 Row = 80
|
# tb_core.u_sdram32 : at time 15897.0 ns ACT : Bank = 0 Row = 81
|
# tb_core.u_sdram32 : at time 15967.0 ns WRITE: Bank = 3 Row = 80, Col = 249, Data = 44de3789
|
# tb_core.u_sdram32 : at time 15897.0 ns ERROR: tRRD violation during Activate bank = 0
|
|
# tb_core.u_sdram32 : at time 15927.0 ns WRITE: Bank = 3 Row = 80, Col = 249, Data = 44de3789
|
|
# Status: Burst-No: 0 Write Address: 00050fe4 WriteData: 44de3789
|
# Status: Burst-No: 0 Write Address: 00050fe4 WriteData: 44de3789
|
# tb_core.u_sdram32 : at time 15937.0 ns WRITE: Bank = 3 Row = 80, Col = 250, Data = a4ae3249
|
# tb_core.u_sdram32 : at time 15977.0 ns WRITE: Bank = 3 Row = 80, Col = 250, Data = a4ae3249
|
# Status: Burst-No: 1 Write Address: 00050fe4 WriteData: a4ae3249
|
# Status: Burst-No: 1 Write Address: 00050fe4 WriteData: a4ae3249
|
# tb_core.u_sdram32 : at time 15947.0 ns WRITE: Bank = 3 Row = 80, Col = 251, Data = e8233ed0
|
# tb_core.u_sdram32 : at time 15987.0 ns WRITE: Bank = 3 Row = 80, Col = 251, Data = e8233ed0
|
# Status: Burst-No: 2 Write Address: 00050fe4 WriteData: e8233ed0
|
# Status: Burst-No: 2 Write Address: 00050fe4 WriteData: e8233ed0
|
# tb_core.u_sdram32 : at time 15957.0 ns WRITE: Bank = 3 Row = 80, Col = 252, Data = ebfec0d7
|
# tb_core.u_sdram32 : at time 15997.0 ns WRITE: Bank = 3 Row = 80, Col = 252, Data = ebfec0d7
|
# Status: Burst-No: 3 Write Address: 00050fe4 WriteData: ebfec0d7
|
# Status: Burst-No: 3 Write Address: 00050fe4 WriteData: ebfec0d7
|
# tb_core.u_sdram32 : at time 15967.0 ns WRITE: Bank = 3 Row = 80, Col = 253, Data = a8c7fc51
|
# tb_core.u_sdram32 : at time 16007.0 ns WRITE: Bank = 3 Row = 80, Col = 253, Data = a8c7fc51
|
# Status: Burst-No: 4 Write Address: 00050fe4 WriteData: a8c7fc51
|
# Status: Burst-No: 4 Write Address: 00050fe4 WriteData: a8c7fc51
|
# tb_core.u_sdram32 : at time 15977.0 ns WRITE: Bank = 3 Row = 80, Col = 254, Data = 4b212f96
|
# tb_core.u_sdram32 : at time 16017.0 ns ACT : Bank = 0 Row = 81
|
|
# tb_core.u_sdram32 : at time 16017.0 ns WRITE: Bank = 3 Row = 80, Col = 254, Data = 4b212f96
|
# Status: Burst-No: 5 Write Address: 00050fe4 WriteData: 4b212f96
|
# Status: Burst-No: 5 Write Address: 00050fe4 WriteData: 4b212f96
|
# tb_core.u_sdram32 : at time 15987.0 ns WRITE: Bank = 3 Row = 80, Col = 255, Data = 061d7f0c
|
# tb_core.u_sdram32 : at time 16027.0 ns WRITE: Bank = 3 Row = 80, Col = 255, Data = 061d7f0c
|
# Status: Burst-No: 6 Write Address: 00050fe4 WriteData: 061d7f0c
|
# Status: Burst-No: 6 Write Address: 00050fe4 WriteData: 061d7f0c
|
# tb_core.u_sdram32 : at time 15997.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 16037.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 16007.0 ns WRITE: Bank = 0 Row = 81, Col = 0, Data = e12ccec2
|
# tb_core.u_sdram32 : at time 16057.0 ns WRITE: Bank = 0 Row = 81, Col = 0, Data = e12ccec2
|
# Status: Burst-No: 7 Write Address: 00050fe4 WriteData: e12ccec2
|
# Status: Burst-No: 7 Write Address: 00050fe4 WriteData: e12ccec2
|
# tb_core.u_sdram32 : at time 16017.0 ns WRITE: Bank = 0 Row = 81, Col = 1, Data = 6457edc8
|
# tb_core.u_sdram32 : at time 16067.0 ns WRITE: Bank = 0 Row = 81, Col = 1, Data = 6457edc8
|
# Status: Burst-No: 8 Write Address: 00050fe4 WriteData: 6457edc8
|
# Status: Burst-No: 8 Write Address: 00050fe4 WriteData: 6457edc8
|
# tb_core.u_sdram32 : at time 16027.0 ns WRITE: Bank = 0 Row = 81, Col = 2, Data = bb825a77
|
# tb_core.u_sdram32 : at time 16077.0 ns WRITE: Bank = 0 Row = 81, Col = 2, Data = bb825a77
|
# Status: Burst-No: 9 Write Address: 00050fe4 WriteData: bb825a77
|
# Status: Burst-No: 9 Write Address: 00050fe4 WriteData: bb825a77
|
# tb_core.u_sdram32 : at time 16037.0 ns WRITE: Bank = 0 Row = 81, Col = 3, Data = 1ef2ed3d
|
# tb_core.u_sdram32 : at time 16087.0 ns WRITE: Bank = 0 Row = 81, Col = 3, Data = 1ef2ed3d
|
# Status: Burst-No: 10 Write Address: 00050fe4 WriteData: 1ef2ed3d
|
# Status: Burst-No: 10 Write Address: 00050fe4 WriteData: 1ef2ed3d
|
# tb_core.u_sdram32 : at time 16047.0 ns WRITE: Bank = 0 Row = 81, Col = 4, Data = 090cdb12
|
# tb_core.u_sdram32 : at time 16097.0 ns WRITE: Bank = 0 Row = 81, Col = 4, Data = 090cdb12
|
# Status: Burst-No: 11 Write Address: 00050fe4 WriteData: 090cdb12
|
# Status: Burst-No: 11 Write Address: 00050fe4 WriteData: 090cdb12
|
# tb_core.u_sdram32 : at time 16057.0 ns WRITE: Bank = 0 Row = 81, Col = 5, Data = bf05007e
|
# tb_core.u_sdram32 : at time 16107.0 ns WRITE: Bank = 0 Row = 81, Col = 5, Data = bf05007e
|
# Status: Burst-No: 12 Write Address: 00050fe4 WriteData: bf05007e
|
# Status: Burst-No: 12 Write Address: 00050fe4 WriteData: bf05007e
|
# tb_core.u_sdram32 : at time 16067.0 ns WRITE: Bank = 0 Row = 81, Col = 6, Data = 36e5816d
|
# tb_core.u_sdram32 : at time 16117.0 ns WRITE: Bank = 0 Row = 81, Col = 6, Data = 36e5816d
|
# Status: Burst-No: 13 Write Address: 00050fe4 WriteData: 36e5816d
|
# Status: Burst-No: 13 Write Address: 00050fe4 WriteData: 36e5816d
|
# tb_core.u_sdram32 : at time 16077.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 16127.0 ns WRITE: Bank = 0 Row = 81, Col = 7, Data = 1cd9e739
|
# tb_core.u_sdram32 : at time 16087.0 ns WRITE: Bank = 0 Row = 81, Col = 7, Data = 1cd9e739
|
|
# Status: Burst-No: 14 Write Address: 00050fe4 WriteData: 1cd9e739
|
# Status: Burst-No: 14 Write Address: 00050fe4 WriteData: 1cd9e739
|
# tb_core.u_sdram32 : at time 16097.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 16137.0 ns BST : Burst Terminate
|
# Write Address: 00060fe8, Burst Size: 15
|
# Write Address: 00060fe8, Burst Size: 15
|
# tb_core.u_sdram32 : at time 16167.0 ns ACT : Bank = 3 Row = 96
|
# tb_core.u_sdram32 : at time 16207.0 ns ACT : Bank = 3 Row = 96
|
# tb_core.u_sdram32 : at time 16177.0 ns ACT : Bank = 0 Row = 97
|
# tb_core.u_sdram32 : at time 16247.0 ns WRITE: Bank = 3 Row = 96, Col = 250, Data = 0fd28f1f
|
# tb_core.u_sdram32 : at time 16177.0 ns ERROR: tRRD violation during Activate bank = 0
|
|
# tb_core.u_sdram32 : at time 16207.0 ns WRITE: Bank = 3 Row = 96, Col = 250, Data = 0fd28f1f
|
|
# Status: Burst-No: 0 Write Address: 00060fe8 WriteData: 0fd28f1f
|
# Status: Burst-No: 0 Write Address: 00060fe8 WriteData: 0fd28f1f
|
# tb_core.u_sdram32 : at time 16217.0 ns WRITE: Bank = 3 Row = 96, Col = 251, Data = e9ebf6d3
|
# tb_core.u_sdram32 : at time 16257.0 ns WRITE: Bank = 3 Row = 96, Col = 251, Data = e9ebf6d3
|
# Status: Burst-No: 1 Write Address: 00060fe8 WriteData: e9ebf6d3
|
# Status: Burst-No: 1 Write Address: 00060fe8 WriteData: e9ebf6d3
|
# tb_core.u_sdram32 : at time 16227.0 ns WRITE: Bank = 3 Row = 96, Col = 252, Data = 42d92f85
|
# tb_core.u_sdram32 : at time 16267.0 ns WRITE: Bank = 3 Row = 96, Col = 252, Data = 42d92f85
|
# Status: Burst-No: 2 Write Address: 00060fe8 WriteData: 42d92f85
|
# Status: Burst-No: 2 Write Address: 00060fe8 WriteData: 42d92f85
|
# tb_core.u_sdram32 : at time 16237.0 ns WRITE: Bank = 3 Row = 96, Col = 253, Data = bc148878
|
# tb_core.u_sdram32 : at time 16277.0 ns WRITE: Bank = 3 Row = 96, Col = 253, Data = bc148878
|
# Status: Burst-No: 3 Write Address: 00060fe8 WriteData: bc148878
|
# Status: Burst-No: 3 Write Address: 00060fe8 WriteData: bc148878
|
# tb_core.u_sdram32 : at time 16247.0 ns WRITE: Bank = 3 Row = 96, Col = 254, Data = 2dda595b
|
# tb_core.u_sdram32 : at time 16287.0 ns WRITE: Bank = 3 Row = 96, Col = 254, Data = 2dda595b
|
# Status: Burst-No: 4 Write Address: 00060fe8 WriteData: 2dda595b
|
# Status: Burst-No: 4 Write Address: 00060fe8 WriteData: 2dda595b
|
# tb_core.u_sdram32 : at time 16257.0 ns WRITE: Bank = 3 Row = 96, Col = 255, Data = 248b4b49
|
# tb_core.u_sdram32 : at time 16297.0 ns ACT : Bank = 0 Row = 97
|
|
# tb_core.u_sdram32 : at time 16297.0 ns WRITE: Bank = 3 Row = 96, Col = 255, Data = 248b4b49
|
# Status: Burst-No: 5 Write Address: 00060fe8 WriteData: 248b4b49
|
# Status: Burst-No: 5 Write Address: 00060fe8 WriteData: 248b4b49
|
# tb_core.u_sdram32 : at time 16267.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 16307.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 16277.0 ns WRITE: Bank = 0 Row = 97, Col = 0, Data = 9ff2ae3f
|
# tb_core.u_sdram32 : at time 16337.0 ns WRITE: Bank = 0 Row = 97, Col = 0, Data = 9ff2ae3f
|
# Status: Burst-No: 6 Write Address: 00060fe8 WriteData: 9ff2ae3f
|
# Status: Burst-No: 6 Write Address: 00060fe8 WriteData: 9ff2ae3f
|
# tb_core.u_sdram32 : at time 16287.0 ns WRITE: Bank = 0 Row = 97, Col = 1, Data = 150caf2a
|
# tb_core.u_sdram32 : at time 16347.0 ns WRITE: Bank = 0 Row = 97, Col = 1, Data = 150caf2a
|
# Status: Burst-No: 7 Write Address: 00060fe8 WriteData: 150caf2a
|
# Status: Burst-No: 7 Write Address: 00060fe8 WriteData: 150caf2a
|
# tb_core.u_sdram32 : at time 16297.0 ns WRITE: Bank = 0 Row = 97, Col = 2, Data = 2c156358
|
# tb_core.u_sdram32 : at time 16357.0 ns WRITE: Bank = 0 Row = 97, Col = 2, Data = 2c156358
|
# Status: Burst-No: 8 Write Address: 00060fe8 WriteData: 2c156358
|
# Status: Burst-No: 8 Write Address: 00060fe8 WriteData: 2c156358
|
# tb_core.u_sdram32 : at time 16307.0 ns WRITE: Bank = 0 Row = 97, Col = 3, Data = c33f3886
|
# tb_core.u_sdram32 : at time 16367.0 ns WRITE: Bank = 0 Row = 97, Col = 3, Data = c33f3886
|
# Status: Burst-No: 9 Write Address: 00060fe8 WriteData: c33f3886
|
# Status: Burst-No: 9 Write Address: 00060fe8 WriteData: c33f3886
|
# tb_core.u_sdram32 : at time 16317.0 ns WRITE: Bank = 0 Row = 97, Col = 4, Data = c71a0c8e
|
# tb_core.u_sdram32 : at time 16377.0 ns WRITE: Bank = 0 Row = 97, Col = 4, Data = c71a0c8e
|
# Status: Burst-No: 10 Write Address: 00060fe8 WriteData: c71a0c8e
|
# Status: Burst-No: 10 Write Address: 00060fe8 WriteData: c71a0c8e
|
# tb_core.u_sdram32 : at time 16327.0 ns WRITE: Bank = 0 Row = 97, Col = 5, Data = ce2ff29c
|
# tb_core.u_sdram32 : at time 16387.0 ns WRITE: Bank = 0 Row = 97, Col = 5, Data = ce2ff29c
|
# Status: Burst-No: 11 Write Address: 00060fe8 WriteData: ce2ff29c
|
# Status: Burst-No: 11 Write Address: 00060fe8 WriteData: ce2ff29c
|
# tb_core.u_sdram32 : at time 16337.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 16397.0 ns WRITE: Bank = 0 Row = 97, Col = 6, Data = 7d3599fa
|
# tb_core.u_sdram32 : at time 16347.0 ns WRITE: Bank = 0 Row = 97, Col = 6, Data = 7d3599fa
|
|
# Status: Burst-No: 12 Write Address: 00060fe8 WriteData: 7d3599fa
|
# Status: Burst-No: 12 Write Address: 00060fe8 WriteData: 7d3599fa
|
# tb_core.u_sdram32 : at time 16357.0 ns WRITE: Bank = 0 Row = 97, Col = 7, Data = 937dbc26
|
# tb_core.u_sdram32 : at time 16407.0 ns WRITE: Bank = 0 Row = 97, Col = 7, Data = 937dbc26
|
# Status: Burst-No: 13 Write Address: 00060fe8 WriteData: 937dbc26
|
# Status: Burst-No: 13 Write Address: 00060fe8 WriteData: 937dbc26
|
# tb_core.u_sdram32 : at time 16367.0 ns WRITE: Bank = 0 Row = 97, Col = 8, Data = 39961773
|
# tb_core.u_sdram32 : at time 16417.0 ns WRITE: Bank = 0 Row = 97, Col = 8, Data = 39961773
|
# Status: Burst-No: 14 Write Address: 00060fe8 WriteData: 39961773
|
# Status: Burst-No: 14 Write Address: 00060fe8 WriteData: 39961773
|
# tb_core.u_sdram32 : at time 16377.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 16427.0 ns BST : Burst Terminate
|
# Write Address: 00070fec, Burst Size: 15
|
# Write Address: 00070fec, Burst Size: 15
|
# tb_core.u_sdram32 : at time 16447.0 ns ACT : Bank = 3 Row = 112
|
# tb_core.u_sdram32 : at time 16497.0 ns ACT : Bank = 3 Row = 112
|
# tb_core.u_sdram32 : at time 16457.0 ns ACT : Bank = 0 Row = 113
|
# tb_core.u_sdram32 : at time 16537.0 ns WRITE: Bank = 3 Row = 112, Col = 251, Data = d18bb4a3
|
# tb_core.u_sdram32 : at time 16457.0 ns ERROR: tRRD violation during Activate bank = 0
|
|
# tb_core.u_sdram32 : at time 16487.0 ns WRITE: Bank = 3 Row = 112, Col = 251, Data = d18bb4a3
|
|
# Status: Burst-No: 0 Write Address: 00070fec WriteData: d18bb4a3
|
# Status: Burst-No: 0 Write Address: 00070fec WriteData: d18bb4a3
|
# tb_core.u_sdram32 : at time 16497.0 ns WRITE: Bank = 3 Row = 112, Col = 252, Data = 9799a82f
|
# tb_core.u_sdram32 : at time 16547.0 ns WRITE: Bank = 3 Row = 112, Col = 252, Data = 9799a82f
|
# Status: Burst-No: 1 Write Address: 00070fec WriteData: 9799a82f
|
# Status: Burst-No: 1 Write Address: 00070fec WriteData: 9799a82f
|
# tb_core.u_sdram32 : at time 16507.0 ns WRITE: Bank = 3 Row = 112, Col = 253, Data = d9d292b3
|
# tb_core.u_sdram32 : at time 16557.0 ns WRITE: Bank = 3 Row = 112, Col = 253, Data = d9d292b3
|
# Status: Burst-No: 2 Write Address: 00070fec WriteData: d9d292b3
|
# Status: Burst-No: 2 Write Address: 00070fec WriteData: d9d292b3
|
# tb_core.u_sdram32 : at time 16517.0 ns WRITE: Bank = 3 Row = 112, Col = 254, Data = afd8565f
|
# tb_core.u_sdram32 : at time 16567.0 ns WRITE: Bank = 3 Row = 112, Col = 254, Data = afd8565f
|
# Status: Burst-No: 3 Write Address: 00070fec WriteData: afd8565f
|
# Status: Burst-No: 3 Write Address: 00070fec WriteData: afd8565f
|
# tb_core.u_sdram32 : at time 16527.0 ns WRITE: Bank = 3 Row = 112, Col = 255, Data = 22290d44
|
# tb_core.u_sdram32 : at time 16577.0 ns WRITE: Bank = 3 Row = 112, Col = 255, Data = 22290d44
|
# Status: Burst-No: 4 Write Address: 00070fec WriteData: 22290d44
|
# Status: Burst-No: 4 Write Address: 00070fec WriteData: 22290d44
|
# tb_core.u_sdram32 : at time 16537.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 16587.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 16547.0 ns WRITE: Bank = 0 Row = 113, Col = 0, Data = 7bf8fdf7
|
# tb_core.u_sdram32 : at time 16647.0 ns ACT : Bank = 0 Row = 113
|
|
# tb_core.u_sdram32 : at time 16687.0 ns WRITE: Bank = 0 Row = 113, Col = 0, Data = 7bf8fdf7
|
# Status: Burst-No: 5 Write Address: 00070fec WriteData: 7bf8fdf7
|
# Status: Burst-No: 5 Write Address: 00070fec WriteData: 7bf8fdf7
|
# tb_core.u_sdram32 : at time 16557.0 ns WRITE: Bank = 0 Row = 113, Col = 1, Data = e59b36cb
|
# tb_core.u_sdram32 : at time 16697.0 ns WRITE: Bank = 0 Row = 113, Col = 1, Data = e59b36cb
|
# Status: Burst-No: 6 Write Address: 00070fec WriteData: e59b36cb
|
# Status: Burst-No: 6 Write Address: 00070fec WriteData: e59b36cb
|
# tb_core.u_sdram32 : at time 16567.0 ns WRITE: Bank = 0 Row = 113, Col = 2, Data = f3091ae6
|
# tb_core.u_sdram32 : at time 16707.0 ns WRITE: Bank = 0 Row = 113, Col = 2, Data = f3091ae6
|
# Status: Burst-No: 7 Write Address: 00070fec WriteData: f3091ae6
|
# Status: Burst-No: 7 Write Address: 00070fec WriteData: f3091ae6
|
# tb_core.u_sdram32 : at time 16577.0 ns WRITE: Bank = 0 Row = 113, Col = 3, Data = 2d28db5a
|
# tb_core.u_sdram32 : at time 16717.0 ns WRITE: Bank = 0 Row = 113, Col = 3, Data = 2d28db5a
|
# Status: Burst-No: 8 Write Address: 00070fec WriteData: 2d28db5a
|
# Status: Burst-No: 8 Write Address: 00070fec WriteData: 2d28db5a
|
# tb_core.u_sdram32 : at time 16587.0 ns WRITE: Bank = 0 Row = 113, Col = 4, Data = 14cfc129
|
# tb_core.u_sdram32 : at time 16727.0 ns WRITE: Bank = 0 Row = 113, Col = 4, Data = 14cfc129
|
# Status: Burst-No: 9 Write Address: 00070fec WriteData: 14cfc129
|
# Status: Burst-No: 9 Write Address: 00070fec WriteData: 14cfc129
|
# tb_core.u_sdram32 : at time 16597.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 16737.0 ns WRITE: Bank = 0 Row = 113, Col = 5, Data = f682e2ed
|
# tb_core.u_sdram32 : at time 16607.0 ns WRITE: Bank = 0 Row = 113, Col = 5, Data = f682e2ed
|
|
# Status: Burst-No: 10 Write Address: 00070fec WriteData: f682e2ed
|
# Status: Burst-No: 10 Write Address: 00070fec WriteData: f682e2ed
|
# tb_core.u_sdram32 : at time 16617.0 ns WRITE: Bank = 0 Row = 113, Col = 6, Data = ed536cda
|
# tb_core.u_sdram32 : at time 16747.0 ns WRITE: Bank = 0 Row = 113, Col = 6, Data = ed536cda
|
# Status: Burst-No: 11 Write Address: 00070fec WriteData: ed536cda
|
# Status: Burst-No: 11 Write Address: 00070fec WriteData: ed536cda
|
# tb_core.u_sdram32 : at time 16627.0 ns WRITE: Bank = 0 Row = 113, Col = 7, Data = b29fb665
|
# tb_core.u_sdram32 : at time 16757.0 ns WRITE: Bank = 0 Row = 113, Col = 7, Data = b29fb665
|
# Status: Burst-No: 12 Write Address: 00070fec WriteData: b29fb665
|
# Status: Burst-No: 12 Write Address: 00070fec WriteData: b29fb665
|
# tb_core.u_sdram32 : at time 16637.0 ns WRITE: Bank = 0 Row = 113, Col = 8, Data = da8ae2b5
|
# tb_core.u_sdram32 : at time 16767.0 ns WRITE: Bank = 0 Row = 113, Col = 8, Data = da8ae2b5
|
# Status: Burst-No: 13 Write Address: 00070fec WriteData: da8ae2b5
|
# Status: Burst-No: 13 Write Address: 00070fec WriteData: da8ae2b5
|
# tb_core.u_sdram32 : at time 16647.0 ns WRITE: Bank = 0 Row = 113, Col = 9, Data = efbe94df
|
# tb_core.u_sdram32 : at time 16777.0 ns WRITE: Bank = 0 Row = 113, Col = 9, Data = efbe94df
|
# Status: Burst-No: 14 Write Address: 00070fec WriteData: efbe94df
|
# Status: Burst-No: 14 Write Address: 00070fec WriteData: efbe94df
|
# tb_core.u_sdram32 : at time 16657.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 16787.0 ns BST : Burst Terminate
|
# Write Address: 00080fd0, Burst Size: 15
|
# Write Address: 00080fd0, Burst Size: 15
|
# tb_core.u_sdram32 : at time 16727.0 ns ACT : Bank = 3 Row = 128
|
# tb_core.u_sdram32 : at time 16857.0 ns ACT : Bank = 3 Row = 128
|
# tb_core.u_sdram32 : at time 16737.0 ns ACT : Bank = 0 Row = 129
|
# tb_core.u_sdram32 : at time 16897.0 ns WRITE: Bank = 3 Row = 128, Col = 244, Data = 3cf11979
|
# tb_core.u_sdram32 : at time 16737.0 ns ERROR: tRRD violation during Activate bank = 0
|
|
# tb_core.u_sdram32 : at time 16767.0 ns WRITE: Bank = 3 Row = 128, Col = 244, Data = 3cf11979
|
|
# Status: Burst-No: 0 Write Address: 00080fd0 WriteData: 3cf11979
|
# Status: Burst-No: 0 Write Address: 00080fd0 WriteData: 3cf11979
|
# tb_core.u_sdram32 : at time 16777.0 ns WRITE: Bank = 3 Row = 128, Col = 245, Data = 2231ff44
|
# tb_core.u_sdram32 : at time 16907.0 ns WRITE: Bank = 3 Row = 128, Col = 245, Data = 2231ff44
|
# Status: Burst-No: 1 Write Address: 00080fd0 WriteData: 2231ff44
|
# Status: Burst-No: 1 Write Address: 00080fd0 WriteData: 2231ff44
|
# tb_core.u_sdram32 : at time 16787.0 ns WRITE: Bank = 3 Row = 128, Col = 246, Data = e8740cd0
|
# tb_core.u_sdram32 : at time 16917.0 ns WRITE: Bank = 3 Row = 128, Col = 246, Data = e8740cd0
|
# Status: Burst-No: 2 Write Address: 00080fd0 WriteData: e8740cd0
|
# Status: Burst-No: 2 Write Address: 00080fd0 WriteData: e8740cd0
|
# tb_core.u_sdram32 : at time 16797.0 ns WRITE: Bank = 3 Row = 128, Col = 247, Data = 15090b2a
|
# tb_core.u_sdram32 : at time 16927.0 ns WRITE: Bank = 3 Row = 128, Col = 247, Data = 15090b2a
|
# Status: Burst-No: 3 Write Address: 00080fd0 WriteData: 15090b2a
|
# Status: Burst-No: 3 Write Address: 00080fd0 WriteData: 15090b2a
|
# tb_core.u_sdram32 : at time 16807.0 ns WRITE: Bank = 3 Row = 128, Col = 248, Data = 55f6adab
|
# tb_core.u_sdram32 : at time 16937.0 ns WRITE: Bank = 3 Row = 128, Col = 248, Data = 55f6adab
|
# Status: Burst-No: 4 Write Address: 00080fd0 WriteData: 55f6adab
|
# Status: Burst-No: 4 Write Address: 00080fd0 WriteData: 55f6adab
|
# tb_core.u_sdram32 : at time 16817.0 ns WRITE: Bank = 3 Row = 128, Col = 249, Data = 076fcf0e
|
# tb_core.u_sdram32 : at time 16947.0 ns ACT : Bank = 0 Row = 129
|
|
# tb_core.u_sdram32 : at time 16947.0 ns WRITE: Bank = 3 Row = 128, Col = 249, Data = 076fcf0e
|
# Status: Burst-No: 5 Write Address: 00080fd0 WriteData: 076fcf0e
|
# Status: Burst-No: 5 Write Address: 00080fd0 WriteData: 076fcf0e
|
# tb_core.u_sdram32 : at time 16827.0 ns WRITE: Bank = 3 Row = 128, Col = 250, Data = 6e5daddc
|
# tb_core.u_sdram32 : at time 16957.0 ns WRITE: Bank = 3 Row = 128, Col = 250, Data = 6e5daddc
|
# Status: Burst-No: 6 Write Address: 00080fd0 WriteData: 6e5daddc
|
# Status: Burst-No: 6 Write Address: 00080fd0 WriteData: 6e5daddc
|
# tb_core.u_sdram32 : at time 16837.0 ns WRITE: Bank = 3 Row = 128, Col = 251, Data = cd5ebc9a
|
# tb_core.u_sdram32 : at time 16967.0 ns WRITE: Bank = 3 Row = 128, Col = 251, Data = cd5ebc9a
|
# Status: Burst-No: 7 Write Address: 00080fd0 WriteData: cd5ebc9a
|
# Status: Burst-No: 7 Write Address: 00080fd0 WriteData: cd5ebc9a
|
# tb_core.u_sdram32 : at time 16847.0 ns WRITE: Bank = 3 Row = 128, Col = 252, Data = fedf72fd
|
# tb_core.u_sdram32 : at time 16977.0 ns WRITE: Bank = 3 Row = 128, Col = 252, Data = fedf72fd
|
# Status: Burst-No: 8 Write Address: 00080fd0 WriteData: fedf72fd
|
# Status: Burst-No: 8 Write Address: 00080fd0 WriteData: fedf72fd
|
# tb_core.u_sdram32 : at time 16857.0 ns WRITE: Bank = 3 Row = 128, Col = 253, Data = e1f102c3
|
# tb_core.u_sdram32 : at time 16987.0 ns WRITE: Bank = 3 Row = 128, Col = 253, Data = e1f102c3
|
# Status: Burst-No: 9 Write Address: 00080fd0 WriteData: e1f102c3
|
# Status: Burst-No: 9 Write Address: 00080fd0 WriteData: e1f102c3
|
# tb_core.u_sdram32 : at time 16867.0 ns WRITE: Bank = 3 Row = 128, Col = 254, Data = 2b0eed56
|
# tb_core.u_sdram32 : at time 16997.0 ns WRITE: Bank = 3 Row = 128, Col = 254, Data = 2b0eed56
|
# Status: Burst-No: 10 Write Address: 00080fd0 WriteData: 2b0eed56
|
# Status: Burst-No: 10 Write Address: 00080fd0 WriteData: 2b0eed56
|
# tb_core.u_sdram32 : at time 16877.0 ns WRITE: Bank = 3 Row = 128, Col = 255, Data = 2779e94e
|
# tb_core.u_sdram32 : at time 17007.0 ns WRITE: Bank = 3 Row = 128, Col = 255, Data = 2779e94e
|
# Status: Burst-No: 11 Write Address: 00080fd0 WriteData: 2779e94e
|
# Status: Burst-No: 11 Write Address: 00080fd0 WriteData: 2779e94e
|
# tb_core.u_sdram32 : at time 16887.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 17017.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 16897.0 ns WRITE: Bank = 0 Row = 129, Col = 0, Data = b3d97667
|
# tb_core.u_sdram32 : at time 17027.0 ns WRITE: Bank = 0 Row = 129, Col = 0, Data = b3d97667
|
# Status: Burst-No: 12 Write Address: 00080fd0 WriteData: b3d97667
|
# Status: Burst-No: 12 Write Address: 00080fd0 WriteData: b3d97667
|
# tb_core.u_sdram32 : at time 16907.0 ns WRITE: Bank = 0 Row = 129, Col = 1, Data = 8531340a
|
# tb_core.u_sdram32 : at time 17037.0 ns WRITE: Bank = 0 Row = 129, Col = 1, Data = 8531340a
|
# Status: Burst-No: 13 Write Address: 00080fd0 WriteData: 8531340a
|
# Status: Burst-No: 13 Write Address: 00080fd0 WriteData: 8531340a
|
# tb_core.u_sdram32 : at time 16917.0 ns WRITE: Bank = 0 Row = 129, Col = 2, Data = 5b6fb9b6
|
# tb_core.u_sdram32 : at time 17047.0 ns WRITE: Bank = 0 Row = 129, Col = 2, Data = 5b6fb9b6
|
# Status: Burst-No: 14 Write Address: 00080fd0 WriteData: 5b6fb9b6
|
# Status: Burst-No: 14 Write Address: 00080fd0 WriteData: 5b6fb9b6
|
# tb_core.u_sdram32 : at time 16927.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 17057.0 ns BST : Burst Terminate
|
# Write Address: 00090fd4, Burst Size: 15
|
# Write Address: 00090fd4, Burst Size: 15
|
# tb_core.u_sdram32 : at time 16997.0 ns ACT : Bank = 3 Row = 144
|
# tb_core.u_sdram32 : at time 17127.0 ns ACT : Bank = 3 Row = 144
|
# tb_core.u_sdram32 : at time 17007.0 ns ACT : Bank = 0 Row = 145
|
# tb_core.u_sdram32 : at time 17167.0 ns WRITE: Bank = 3 Row = 144, Col = 245, Data = 9c0e8a38
|
# tb_core.u_sdram32 : at time 17007.0 ns ERROR: tRRD violation during Activate bank = 0
|
|
# tb_core.u_sdram32 : at time 17037.0 ns WRITE: Bank = 3 Row = 144, Col = 245, Data = 9c0e8a38
|
|
# Status: Burst-No: 0 Write Address: 00090fd4 WriteData: 9c0e8a38
|
# Status: Burst-No: 0 Write Address: 00090fd4 WriteData: 9c0e8a38
|
# tb_core.u_sdram32 : at time 17047.0 ns WRITE: Bank = 3 Row = 144, Col = 246, Data = 3cd18779
|
# tb_core.u_sdram32 : at time 17177.0 ns WRITE: Bank = 3 Row = 144, Col = 246, Data = 3cd18779
|
# Status: Burst-No: 1 Write Address: 00090fd4 WriteData: 3cd18779
|
# Status: Burst-No: 1 Write Address: 00090fd4 WriteData: 3cd18779
|
# tb_core.u_sdram32 : at time 17057.0 ns WRITE: Bank = 3 Row = 144, Col = 247, Data = dc2bc4b8
|
# tb_core.u_sdram32 : at time 17187.0 ns WRITE: Bank = 3 Row = 144, Col = 247, Data = dc2bc4b8
|
# Status: Burst-No: 2 Write Address: 00090fd4 WriteData: dc2bc4b8
|
# Status: Burst-No: 2 Write Address: 00090fd4 WriteData: dc2bc4b8
|
# tb_core.u_sdram32 : at time 17067.0 ns WRITE: Bank = 3 Row = 144, Col = 248, Data = 4a74bf94
|
# tb_core.u_sdram32 : at time 17197.0 ns WRITE: Bank = 3 Row = 144, Col = 248, Data = 4a74bf94
|
# Status: Burst-No: 3 Write Address: 00090fd4 WriteData: 4a74bf94
|
# Status: Burst-No: 3 Write Address: 00090fd4 WriteData: 4a74bf94
|
# tb_core.u_sdram32 : at time 17077.0 ns WRITE: Bank = 3 Row = 144, Col = 249, Data = 49c65d93
|
# tb_core.u_sdram32 : at time 17207.0 ns WRITE: Bank = 3 Row = 144, Col = 249, Data = 49c65d93
|
# Status: Burst-No: 4 Write Address: 00090fd4 WriteData: 49c65d93
|
# Status: Burst-No: 4 Write Address: 00090fd4 WriteData: 49c65d93
|
# tb_core.u_sdram32 : at time 17087.0 ns WRITE: Bank = 3 Row = 144, Col = 250, Data = 823f2c04
|
# tb_core.u_sdram32 : at time 17217.0 ns ACT : Bank = 0 Row = 145
|
|
# tb_core.u_sdram32 : at time 17217.0 ns WRITE: Bank = 3 Row = 144, Col = 250, Data = 823f2c04
|
# Status: Burst-No: 5 Write Address: 00090fd4 WriteData: 823f2c04
|
# Status: Burst-No: 5 Write Address: 00090fd4 WriteData: 823f2c04
|
# tb_core.u_sdram32 : at time 17097.0 ns WRITE: Bank = 3 Row = 144, Col = 251, Data = acb7ca59
|
# tb_core.u_sdram32 : at time 17227.0 ns WRITE: Bank = 3 Row = 144, Col = 251, Data = acb7ca59
|
# Status: Burst-No: 6 Write Address: 00090fd4 WriteData: acb7ca59
|
# Status: Burst-No: 6 Write Address: 00090fd4 WriteData: acb7ca59
|
# tb_core.u_sdram32 : at time 17107.0 ns WRITE: Bank = 3 Row = 144, Col = 252, Data = 6dcb69db
|
# tb_core.u_sdram32 : at time 17237.0 ns WRITE: Bank = 3 Row = 144, Col = 252, Data = 6dcb69db
|
# Status: Burst-No: 7 Write Address: 00090fd4 WriteData: 6dcb69db
|
# Status: Burst-No: 7 Write Address: 00090fd4 WriteData: 6dcb69db
|
# tb_core.u_sdram32 : at time 17117.0 ns WRITE: Bank = 3 Row = 144, Col = 253, Data = a6fcde4d
|
# tb_core.u_sdram32 : at time 17247.0 ns WRITE: Bank = 3 Row = 144, Col = 253, Data = a6fcde4d
|
# Status: Burst-No: 8 Write Address: 00090fd4 WriteData: a6fcde4d
|
# Status: Burst-No: 8 Write Address: 00090fd4 WriteData: a6fcde4d
|
# tb_core.u_sdram32 : at time 17127.0 ns WRITE: Bank = 3 Row = 144, Col = 254, Data = 6cb0b7d9
|
# tb_core.u_sdram32 : at time 17257.0 ns WRITE: Bank = 3 Row = 144, Col = 254, Data = 6cb0b7d9
|
# Status: Burst-No: 9 Write Address: 00090fd4 WriteData: 6cb0b7d9
|
# Status: Burst-No: 9 Write Address: 00090fd4 WriteData: 6cb0b7d9
|
# tb_core.u_sdram32 : at time 17137.0 ns WRITE: Bank = 3 Row = 144, Col = 255, Data = b6a4266d
|
# tb_core.u_sdram32 : at time 17267.0 ns WRITE: Bank = 3 Row = 144, Col = 255, Data = b6a4266d
|
# Status: Burst-No: 10 Write Address: 00090fd4 WriteData: b6a4266d
|
# Status: Burst-No: 10 Write Address: 00090fd4 WriteData: b6a4266d
|
# tb_core.u_sdram32 : at time 17147.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 17277.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 17157.0 ns WRITE: Bank = 0 Row = 145, Col = 0, Data = bb45e276
|
# tb_core.u_sdram32 : at time 17287.0 ns WRITE: Bank = 0 Row = 145, Col = 0, Data = bb45e276
|
# Status: Burst-No: 11 Write Address: 00090fd4 WriteData: bb45e276
|
# Status: Burst-No: 11 Write Address: 00090fd4 WriteData: bb45e276
|
# tb_core.u_sdram32 : at time 17167.0 ns WRITE: Bank = 0 Row = 145, Col = 1, Data = 653b49ca
|
# tb_core.u_sdram32 : at time 17297.0 ns WRITE: Bank = 0 Row = 145, Col = 1, Data = 653b49ca
|
# Status: Burst-No: 12 Write Address: 00090fd4 WriteData: 653b49ca
|
# Status: Burst-No: 12 Write Address: 00090fd4 WriteData: 653b49ca
|
# tb_core.u_sdram32 : at time 17177.0 ns WRITE: Bank = 0 Row = 145, Col = 2, Data = 5b172db6
|
# tb_core.u_sdram32 : at time 17307.0 ns WRITE: Bank = 0 Row = 145, Col = 2, Data = 5b172db6
|
# Status: Burst-No: 13 Write Address: 00090fd4 WriteData: 5b172db6
|
# Status: Burst-No: 13 Write Address: 00090fd4 WriteData: 5b172db6
|
# tb_core.u_sdram32 : at time 17187.0 ns WRITE: Bank = 0 Row = 145, Col = 3, Data = 4a937195
|
# tb_core.u_sdram32 : at time 17317.0 ns WRITE: Bank = 0 Row = 145, Col = 3, Data = 4a937195
|
# Status: Burst-No: 14 Write Address: 00090fd4 WriteData: 4a937195
|
# Status: Burst-No: 14 Write Address: 00090fd4 WriteData: 4a937195
|
# tb_core.u_sdram32 : at time 17197.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 17327.0 ns BST : Burst Terminate
|
# Write Address: 000a0fd8, Burst Size: 15
|
# Write Address: 000a0fd8, Burst Size: 15
|
# tb_core.u_sdram32 : at time 17267.0 ns ACT : Bank = 3 Row = 160
|
# tb_core.u_sdram32 : at time 17397.0 ns ACT : Bank = 3 Row = 160
|
# tb_core.u_sdram32 : at time 17277.0 ns ACT : Bank = 0 Row = 161
|
# tb_core.u_sdram32 : at time 17437.0 ns WRITE: Bank = 3 Row = 160, Col = 246, Data = a3071a46
|
# tb_core.u_sdram32 : at time 17277.0 ns ERROR: tRRD violation during Activate bank = 0
|
|
# tb_core.u_sdram32 : at time 17307.0 ns WRITE: Bank = 3 Row = 160, Col = 246, Data = a3071a46
|
|
# Status: Burst-No: 0 Write Address: 000a0fd8 WriteData: a3071a46
|
# Status: Burst-No: 0 Write Address: 000a0fd8 WriteData: a3071a46
|
# tb_core.u_sdram32 : at time 17317.0 ns WRITE: Bank = 3 Row = 160, Col = 247, Data = 02749b04
|
# tb_core.u_sdram32 : at time 17447.0 ns WRITE: Bank = 3 Row = 160, Col = 247, Data = 02749b04
|
# Status: Burst-No: 1 Write Address: 000a0fd8 WriteData: 02749b04
|
# Status: Burst-No: 1 Write Address: 000a0fd8 WriteData: 02749b04
|
# tb_core.u_sdram32 : at time 17327.0 ns WRITE: Bank = 3 Row = 160, Col = 248, Data = 7bd261f7
|
# tb_core.u_sdram32 : at time 17457.0 ns WRITE: Bank = 3 Row = 160, Col = 248, Data = 7bd261f7
|
# Status: Burst-No: 2 Write Address: 000a0fd8 WriteData: 7bd261f7
|
# Status: Burst-No: 2 Write Address: 000a0fd8 WriteData: 7bd261f7
|
# tb_core.u_sdram32 : at time 17337.0 ns WRITE: Bank = 3 Row = 160, Col = 249, Data = 34980769
|
# tb_core.u_sdram32 : at time 17467.0 ns WRITE: Bank = 3 Row = 160, Col = 249, Data = 34980769
|
# Status: Burst-No: 3 Write Address: 000a0fd8 WriteData: 34980769
|
# Status: Burst-No: 3 Write Address: 000a0fd8 WriteData: 34980769
|
# tb_core.u_sdram32 : at time 17347.0 ns WRITE: Bank = 3 Row = 160, Col = 250, Data = da6ebab4
|
# tb_core.u_sdram32 : at time 17477.0 ns WRITE: Bank = 3 Row = 160, Col = 250, Data = da6ebab4
|
# Status: Burst-No: 4 Write Address: 000a0fd8 WriteData: da6ebab4
|
# Status: Burst-No: 4 Write Address: 000a0fd8 WriteData: da6ebab4
|
# tb_core.u_sdram32 : at time 17357.0 ns WRITE: Bank = 3 Row = 160, Col = 251, Data = 44018d88
|
# tb_core.u_sdram32 : at time 17487.0 ns ACT : Bank = 0 Row = 161
|
|
# tb_core.u_sdram32 : at time 17487.0 ns WRITE: Bank = 3 Row = 160, Col = 251, Data = 44018d88
|
# Status: Burst-No: 5 Write Address: 000a0fd8 WriteData: 44018d88
|
# Status: Burst-No: 5 Write Address: 000a0fd8 WriteData: 44018d88
|
# tb_core.u_sdram32 : at time 17367.0 ns WRITE: Bank = 3 Row = 160, Col = 252, Data = 147cd928
|
# tb_core.u_sdram32 : at time 17497.0 ns WRITE: Bank = 3 Row = 160, Col = 252, Data = 147cd928
|
# Status: Burst-No: 6 Write Address: 000a0fd8 WriteData: 147cd928
|
# Status: Burst-No: 6 Write Address: 000a0fd8 WriteData: 147cd928
|
# tb_core.u_sdram32 : at time 17377.0 ns WRITE: Bank = 3 Row = 160, Col = 253, Data = 9690042d
|
# tb_core.u_sdram32 : at time 17507.0 ns WRITE: Bank = 3 Row = 160, Col = 253, Data = 9690042d
|
# Status: Burst-No: 7 Write Address: 000a0fd8 WriteData: 9690042d
|
# Status: Burst-No: 7 Write Address: 000a0fd8 WriteData: 9690042d
|
# tb_core.u_sdram32 : at time 17387.0 ns WRITE: Bank = 3 Row = 160, Col = 254, Data = e3c530c7
|
# tb_core.u_sdram32 : at time 17517.0 ns WRITE: Bank = 3 Row = 160, Col = 254, Data = e3c530c7
|
# Status: Burst-No: 8 Write Address: 000a0fd8 WriteData: e3c530c7
|
# Status: Burst-No: 8 Write Address: 000a0fd8 WriteData: e3c530c7
|
# tb_core.u_sdram32 : at time 17397.0 ns WRITE: Bank = 3 Row = 160, Col = 255, Data = 975c9c2e
|
# tb_core.u_sdram32 : at time 17527.0 ns WRITE: Bank = 3 Row = 160, Col = 255, Data = 975c9c2e
|
# Status: Burst-No: 9 Write Address: 000a0fd8 WriteData: 975c9c2e
|
# Status: Burst-No: 9 Write Address: 000a0fd8 WriteData: 975c9c2e
|
# tb_core.u_sdram32 : at time 17407.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 17537.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 17417.0 ns WRITE: Bank = 0 Row = 161, Col = 0, Data = 8477e408
|
# tb_core.u_sdram32 : at time 17547.0 ns WRITE: Bank = 0 Row = 161, Col = 0, Data = 8477e408
|
# Status: Burst-No: 10 Write Address: 000a0fd8 WriteData: 8477e408
|
# Status: Burst-No: 10 Write Address: 000a0fd8 WriteData: 8477e408
|
# tb_core.u_sdram32 : at time 17427.0 ns WRITE: Bank = 0 Row = 161, Col = 1, Data = 0e41451c
|
# tb_core.u_sdram32 : at time 17557.0 ns WRITE: Bank = 0 Row = 161, Col = 1, Data = 0e41451c
|
# Status: Burst-No: 11 Write Address: 000a0fd8 WriteData: 0e41451c
|
# Status: Burst-No: 11 Write Address: 000a0fd8 WriteData: 0e41451c
|
# tb_core.u_sdram32 : at time 17437.0 ns WRITE: Bank = 0 Row = 161, Col = 2, Data = fea7a6fd
|
# tb_core.u_sdram32 : at time 17567.0 ns WRITE: Bank = 0 Row = 161, Col = 2, Data = fea7a6fd
|
# Status: Burst-No: 12 Write Address: 000a0fd8 WriteData: fea7a6fd
|
# Status: Burst-No: 12 Write Address: 000a0fd8 WriteData: fea7a6fd
|
# tb_core.u_sdram32 : at time 17447.0 ns WRITE: Bank = 0 Row = 161, Col = 3, Data = 149e0729
|
# tb_core.u_sdram32 : at time 17577.0 ns WRITE: Bank = 0 Row = 161, Col = 3, Data = 149e0729
|
# Status: Burst-No: 13 Write Address: 000a0fd8 WriteData: 149e0729
|
# Status: Burst-No: 13 Write Address: 000a0fd8 WriteData: 149e0729
|
# tb_core.u_sdram32 : at time 17457.0 ns WRITE: Bank = 0 Row = 161, Col = 4, Data = 8e37901c
|
# tb_core.u_sdram32 : at time 17587.0 ns WRITE: Bank = 0 Row = 161, Col = 4, Data = 8e37901c
|
# Status: Burst-No: 14 Write Address: 000a0fd8 WriteData: 8e37901c
|
# Status: Burst-No: 14 Write Address: 000a0fd8 WriteData: 8e37901c
|
# tb_core.u_sdram32 : at time 17467.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 17597.0 ns BST : Burst Terminate
|
# Write Address: 000b0fdc, Burst Size: 15
|
# Write Address: 000b0fdc, Burst Size: 15
|
# tb_core.u_sdram32 : at time 17537.0 ns ACT : Bank = 3 Row = 176
|
# tb_core.u_sdram32 : at time 17667.0 ns ACT : Bank = 3 Row = 176
|
# tb_core.u_sdram32 : at time 17547.0 ns ACT : Bank = 0 Row = 177
|
# tb_core.u_sdram32 : at time 17707.0 ns WRITE: Bank = 3 Row = 176, Col = 247, Data = 43356786
|
# tb_core.u_sdram32 : at time 17547.0 ns ERROR: tRRD violation during Activate bank = 0
|
|
# tb_core.u_sdram32 : at time 17577.0 ns WRITE: Bank = 3 Row = 176, Col = 247, Data = 43356786
|
|
# Status: Burst-No: 0 Write Address: 000b0fdc WriteData: 43356786
|
# Status: Burst-No: 0 Write Address: 000b0fdc WriteData: 43356786
|
# tb_core.u_sdram32 : at time 17587.0 ns WRITE: Bank = 3 Row = 176, Col = 248, Data = ed3408da
|
# tb_core.u_sdram32 : at time 17717.0 ns WRITE: Bank = 3 Row = 176, Col = 248, Data = ed3408da
|
# Status: Burst-No: 1 Write Address: 000b0fdc WriteData: ed3408da
|
# Status: Burst-No: 1 Write Address: 000b0fdc WriteData: ed3408da
|
# tb_core.u_sdram32 : at time 17597.0 ns WRITE: Bank = 3 Row = 176, Col = 249, Data = 9eb7c63d
|
# tb_core.u_sdram32 : at time 17727.0 ns WRITE: Bank = 3 Row = 176, Col = 249, Data = 9eb7c63d
|
# Status: Burst-No: 2 Write Address: 000b0fdc WriteData: 9eb7c63d
|
# Status: Burst-No: 2 Write Address: 000b0fdc WriteData: 9eb7c63d
|
# tb_core.u_sdram32 : at time 17607.0 ns WRITE: Bank = 3 Row = 176, Col = 250, Data = 334ea766
|
# tb_core.u_sdram32 : at time 17737.0 ns WRITE: Bank = 3 Row = 176, Col = 250, Data = 334ea766
|
# Status: Burst-No: 3 Write Address: 000b0fdc WriteData: 334ea766
|
# Status: Burst-No: 3 Write Address: 000b0fdc WriteData: 334ea766
|
# tb_core.u_sdram32 : at time 17617.0 ns WRITE: Bank = 3 Row = 176, Col = 251, Data = b855c470
|
# tb_core.u_sdram32 : at time 17747.0 ns WRITE: Bank = 3 Row = 176, Col = 251, Data = b855c470
|
# Status: Burst-No: 4 Write Address: 000b0fdc WriteData: b855c470
|
# Status: Burst-No: 4 Write Address: 000b0fdc WriteData: b855c470
|
# tb_core.u_sdram32 : at time 17627.0 ns WRITE: Bank = 3 Row = 176, Col = 252, Data = b9f50473
|
# tb_core.u_sdram32 : at time 17757.0 ns WRITE: Bank = 3 Row = 176, Col = 252, Data = b9f50473
|
# Status: Burst-No: 5 Write Address: 000b0fdc WriteData: b9f50473
|
# Status: Burst-No: 5 Write Address: 000b0fdc WriteData: b9f50473
|
# tb_core.u_sdram32 : at time 17637.0 ns WRITE: Bank = 3 Row = 176, Col = 253, Data = 5d7199ba
|
# tb_core.u_sdram32 : at time 17767.0 ns WRITE: Bank = 3 Row = 176, Col = 253, Data = 5d7199ba
|
# Status: Burst-No: 6 Write Address: 000b0fdc WriteData: 5d7199ba
|
# Status: Burst-No: 6 Write Address: 000b0fdc WriteData: 5d7199ba
|
# tb_core.u_sdram32 : at time 17647.0 ns WRITE: Bank = 3 Row = 176, Col = 254, Data = 2f3ab35e
|
# tb_core.u_sdram32 : at time 17777.0 ns WRITE: Bank = 3 Row = 176, Col = 254, Data = 2f3ab35e
|
# Status: Burst-No: 7 Write Address: 000b0fdc WriteData: 2f3ab35e
|
# Status: Burst-No: 7 Write Address: 000b0fdc WriteData: 2f3ab35e
|
# tb_core.u_sdram32 : at time 17657.0 ns WRITE: Bank = 3 Row = 176, Col = 255, Data = 7d4779fa
|
# tb_core.u_sdram32 : at time 17787.0 ns WRITE: Bank = 3 Row = 176, Col = 255, Data = 7d4779fa
|
# Status: Burst-No: 8 Write Address: 000b0fdc WriteData: 7d4779fa
|
# Status: Burst-No: 8 Write Address: 000b0fdc WriteData: 7d4779fa
|
# tb_core.u_sdram32 : at time 17667.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 17797.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 17677.0 ns WRITE: Bank = 0 Row = 177, Col = 0, Data = 6a8e05d5
|
# tb_core.u_sdram32 : at time 17857.0 ns ACT : Bank = 0 Row = 177
|
|
# tb_core.u_sdram32 : at time 17897.0 ns WRITE: Bank = 0 Row = 177, Col = 0, Data = 6a8e05d5
|
# Status: Burst-No: 9 Write Address: 000b0fdc WriteData: 6a8e05d5
|
# Status: Burst-No: 9 Write Address: 000b0fdc WriteData: 6a8e05d5
|
# tb_core.u_sdram32 : at time 17687.0 ns WRITE: Bank = 0 Row = 177, Col = 1, Data = 8d24f61a
|
# tb_core.u_sdram32 : at time 17907.0 ns WRITE: Bank = 0 Row = 177, Col = 1, Data = 8d24f61a
|
# Status: Burst-No: 10 Write Address: 000b0fdc WriteData: 8d24f61a
|
# Status: Burst-No: 10 Write Address: 000b0fdc WriteData: 8d24f61a
|
# tb_core.u_sdram32 : at time 17697.0 ns WRITE: Bank = 0 Row = 177, Col = 2, Data = dcf000b9
|
# tb_core.u_sdram32 : at time 17917.0 ns WRITE: Bank = 0 Row = 177, Col = 2, Data = dcf000b9
|
# Status: Burst-No: 11 Write Address: 000b0fdc WriteData: dcf000b9
|
# Status: Burst-No: 11 Write Address: 000b0fdc WriteData: dcf000b9
|
# tb_core.u_sdram32 : at time 17707.0 ns WRITE: Bank = 0 Row = 177, Col = 3, Data = 1b876137
|
# tb_core.u_sdram32 : at time 17927.0 ns WRITE: Bank = 0 Row = 177, Col = 3, Data = 1b876137
|
# Status: Burst-No: 12 Write Address: 000b0fdc WriteData: 1b876137
|
# Status: Burst-No: 12 Write Address: 000b0fdc WriteData: 1b876137
|
# tb_core.u_sdram32 : at time 17717.0 ns WRITE: Bank = 0 Row = 177, Col = 4, Data = 4b273796
|
# tb_core.u_sdram32 : at time 17937.0 ns WRITE: Bank = 0 Row = 177, Col = 4, Data = 4b273796
|
# Status: Burst-No: 13 Write Address: 000b0fdc WriteData: 4b273796
|
# Status: Burst-No: 13 Write Address: 000b0fdc WriteData: 4b273796
|
# tb_core.u_sdram32 : at time 17727.0 ns WRITE: Bank = 0 Row = 177, Col = 5, Data = 603921c0
|
# tb_core.u_sdram32 : at time 17947.0 ns WRITE: Bank = 0 Row = 177, Col = 5, Data = 603921c0
|
# Status: Burst-No: 14 Write Address: 000b0fdc WriteData: 603921c0
|
# Status: Burst-No: 14 Write Address: 000b0fdc WriteData: 603921c0
|
# tb_core.u_sdram32 : at time 17737.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 17957.0 ns BST : Burst Terminate
|
# Write Address: 000c0fc0, Burst Size: 15
|
# Write Address: 000c0fc0, Burst Size: 15
|
# tb_core.u_sdram32 : at time 17807.0 ns ACT : Bank = 3 Row = 192
|
# tb_core.u_sdram32 : at time 18027.0 ns ACT : Bank = 3 Row = 192
|
# tb_core.u_sdram32 : at time 17847.0 ns WRITE: Bank = 3 Row = 192, Col = 240, Data = 13259f26
|
# tb_core.u_sdram32 : at time 18067.0 ns WRITE: Bank = 3 Row = 192, Col = 240, Data = 13259f26
|
# Status: Burst-No: 0 Write Address: 000c0fc0 WriteData: 13259f26
|
# Status: Burst-No: 0 Write Address: 000c0fc0 WriteData: 13259f26
|
# tb_core.u_sdram32 : at time 17857.0 ns WRITE: Bank = 3 Row = 192, Col = 241, Data = db461ab6
|
# tb_core.u_sdram32 : at time 18077.0 ns WRITE: Bank = 3 Row = 192, Col = 241, Data = db461ab6
|
# Status: Burst-No: 1 Write Address: 000c0fc0 WriteData: db461ab6
|
# Status: Burst-No: 1 Write Address: 000c0fc0 WriteData: db461ab6
|
# tb_core.u_sdram32 : at time 17867.0 ns WRITE: Bank = 3 Row = 192, Col = 242, Data = 3e99837d
|
# tb_core.u_sdram32 : at time 18087.0 ns WRITE: Bank = 3 Row = 192, Col = 242, Data = 3e99837d
|
# Status: Burst-No: 2 Write Address: 000c0fc0 WriteData: 3e99837d
|
# Status: Burst-No: 2 Write Address: 000c0fc0 WriteData: 3e99837d
|
# tb_core.u_sdram32 : at time 17877.0 ns WRITE: Bank = 3 Row = 192, Col = 243, Data = 6e5f0fdc
|
# tb_core.u_sdram32 : at time 18097.0 ns WRITE: Bank = 3 Row = 192, Col = 243, Data = 6e5f0fdc
|
# Status: Burst-No: 3 Write Address: 000c0fc0 WriteData: 6e5f0fdc
|
# Status: Burst-No: 3 Write Address: 000c0fc0 WriteData: 6e5f0fdc
|
# tb_core.u_sdram32 : at time 17887.0 ns WRITE: Bank = 3 Row = 192, Col = 244, Data = 43615786
|
# tb_core.u_sdram32 : at time 18107.0 ns WRITE: Bank = 3 Row = 192, Col = 244, Data = 43615786
|
# Status: Burst-No: 4 Write Address: 000c0fc0 WriteData: 43615786
|
# Status: Burst-No: 4 Write Address: 000c0fc0 WriteData: 43615786
|
# tb_core.u_sdram32 : at time 17897.0 ns WRITE: Bank = 3 Row = 192, Col = 245, Data = 3c03ff78
|
# tb_core.u_sdram32 : at time 18117.0 ns WRITE: Bank = 3 Row = 192, Col = 245, Data = 3c03ff78
|
# Status: Burst-No: 5 Write Address: 000c0fc0 WriteData: 3c03ff78
|
# Status: Burst-No: 5 Write Address: 000c0fc0 WriteData: 3c03ff78
|
# tb_core.u_sdram32 : at time 17907.0 ns WRITE: Bank = 3 Row = 192, Col = 246, Data = 3f5a9b7e
|
# tb_core.u_sdram32 : at time 18127.0 ns WRITE: Bank = 3 Row = 192, Col = 246, Data = 3f5a9b7e
|
# Status: Burst-No: 6 Write Address: 000c0fc0 WriteData: 3f5a9b7e
|
# Status: Burst-No: 6 Write Address: 000c0fc0 WriteData: 3f5a9b7e
|
# tb_core.u_sdram32 : at time 17917.0 ns WRITE: Bank = 3 Row = 192, Col = 247, Data = ed8d80db
|
# tb_core.u_sdram32 : at time 18137.0 ns WRITE: Bank = 3 Row = 192, Col = 247, Data = ed8d80db
|
# Status: Burst-No: 7 Write Address: 000c0fc0 WriteData: ed8d80db
|
# Status: Burst-No: 7 Write Address: 000c0fc0 WriteData: ed8d80db
|
# tb_core.u_sdram32 : at time 17927.0 ns WRITE: Bank = 3 Row = 192, Col = 248, Data = e7c3b6cf
|
# tb_core.u_sdram32 : at time 18147.0 ns WRITE: Bank = 3 Row = 192, Col = 248, Data = e7c3b6cf
|
# Status: Burst-No: 8 Write Address: 000c0fc0 WriteData: e7c3b6cf
|
# Status: Burst-No: 8 Write Address: 000c0fc0 WriteData: e7c3b6cf
|
# tb_core.u_sdram32 : at time 17937.0 ns WRITE: Bank = 3 Row = 192, Col = 249, Data = 3ced2b79
|
# tb_core.u_sdram32 : at time 18157.0 ns WRITE: Bank = 3 Row = 192, Col = 249, Data = 3ced2b79
|
# Status: Burst-No: 9 Write Address: 000c0fc0 WriteData: 3ced2b79
|
# Status: Burst-No: 9 Write Address: 000c0fc0 WriteData: 3ced2b79
|
# tb_core.u_sdram32 : at time 17947.0 ns WRITE: Bank = 3 Row = 192, Col = 250, Data = fd28e4fa
|
# tb_core.u_sdram32 : at time 18167.0 ns WRITE: Bank = 3 Row = 192, Col = 250, Data = fd28e4fa
|
# Status: Burst-No: 10 Write Address: 000c0fc0 WriteData: fd28e4fa
|
# Status: Burst-No: 10 Write Address: 000c0fc0 WriteData: fd28e4fa
|
# tb_core.u_sdram32 : at time 17957.0 ns WRITE: Bank = 3 Row = 192, Col = 251, Data = b0bcee61
|
# tb_core.u_sdram32 : at time 18177.0 ns WRITE: Bank = 3 Row = 192, Col = 251, Data = b0bcee61
|
# Status: Burst-No: 11 Write Address: 000c0fc0 WriteData: b0bcee61
|
# Status: Burst-No: 11 Write Address: 000c0fc0 WriteData: b0bcee61
|
# tb_core.u_sdram32 : at time 17967.0 ns WRITE: Bank = 3 Row = 192, Col = 252, Data = 0b940917
|
# tb_core.u_sdram32 : at time 18187.0 ns WRITE: Bank = 3 Row = 192, Col = 252, Data = 0b940917
|
# Status: Burst-No: 12 Write Address: 000c0fc0 WriteData: 0b940917
|
# Status: Burst-No: 12 Write Address: 000c0fc0 WriteData: 0b940917
|
# tb_core.u_sdram32 : at time 17977.0 ns WRITE: Bank = 3 Row = 192, Col = 253, Data = d0f578a1
|
# tb_core.u_sdram32 : at time 18197.0 ns WRITE: Bank = 3 Row = 192, Col = 253, Data = d0f578a1
|
# Status: Burst-No: 13 Write Address: 000c0fc0 WriteData: d0f578a1
|
# Status: Burst-No: 13 Write Address: 000c0fc0 WriteData: d0f578a1
|
# tb_core.u_sdram32 : at time 17987.0 ns WRITE: Bank = 3 Row = 192, Col = 254, Data = 43779186
|
# tb_core.u_sdram32 : at time 18207.0 ns WRITE: Bank = 3 Row = 192, Col = 254, Data = 43779186
|
# Status: Burst-No: 14 Write Address: 000c0fc0 WriteData: 43779186
|
# Status: Burst-No: 14 Write Address: 000c0fc0 WriteData: 43779186
|
# tb_core.u_sdram32 : at time 17997.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 18217.0 ns BST : Burst Terminate
|
# Write Address: 000d0fc4, Burst Size: 15
|
# Write Address: 000d0fc4, Burst Size: 15
|
# tb_core.u_sdram32 : at time 18067.0 ns ACT : Bank = 3 Row = 208
|
# tb_core.u_sdram32 : at time 18287.0 ns ACT : Bank = 3 Row = 208
|
# tb_core.u_sdram32 : at time 18107.0 ns WRITE: Bank = 3 Row = 208, Col = 241, Data = a8639650
|
# tb_core.u_sdram32 : at time 18327.0 ns WRITE: Bank = 3 Row = 208, Col = 241, Data = a8639650
|
# Status: Burst-No: 0 Write Address: 000d0fc4 WriteData: a8639650
|
# Status: Burst-No: 0 Write Address: 000d0fc4 WriteData: a8639650
|
# tb_core.u_sdram32 : at time 18117.0 ns WRITE: Bank = 3 Row = 208, Col = 242, Data = 7a8c59f5
|
# tb_core.u_sdram32 : at time 18337.0 ns WRITE: Bank = 3 Row = 208, Col = 242, Data = 7a8c59f5
|
# Status: Burst-No: 1 Write Address: 000d0fc4 WriteData: 7a8c59f5
|
# Status: Burst-No: 1 Write Address: 000d0fc4 WriteData: 7a8c59f5
|
# tb_core.u_sdram32 : at time 18127.0 ns WRITE: Bank = 3 Row = 208, Col = 243, Data = 9ab48835
|
# tb_core.u_sdram32 : at time 18347.0 ns WRITE: Bank = 3 Row = 208, Col = 243, Data = 9ab48835
|
# Status: Burst-No: 2 Write Address: 000d0fc4 WriteData: 9ab48835
|
# Status: Burst-No: 2 Write Address: 000d0fc4 WriteData: 9ab48835
|
# tb_core.u_sdram32 : at time 18137.0 ns WRITE: Bank = 3 Row = 208, Col = 244, Data = 949a8a29
|
# tb_core.u_sdram32 : at time 18357.0 ns WRITE: Bank = 3 Row = 208, Col = 244, Data = 949a8a29
|
# Status: Burst-No: 3 Write Address: 000d0fc4 WriteData: 949a8a29
|
# Status: Burst-No: 3 Write Address: 000d0fc4 WriteData: 949a8a29
|
# tb_core.u_sdram32 : at time 18147.0 ns WRITE: Bank = 3 Row = 208, Col = 245, Data = 60b175c1
|
# tb_core.u_sdram32 : at time 18367.0 ns WRITE: Bank = 3 Row = 208, Col = 245, Data = 60b175c1
|
# Status: Burst-No: 4 Write Address: 000d0fc4 WriteData: 60b175c1
|
# Status: Burst-No: 4 Write Address: 000d0fc4 WriteData: 60b175c1
|
# tb_core.u_sdram32 : at time 18157.0 ns WRITE: Bank = 3 Row = 208, Col = 246, Data = e2e574c5
|
# tb_core.u_sdram32 : at time 18377.0 ns WRITE: Bank = 3 Row = 208, Col = 246, Data = e2e574c5
|
# Status: Burst-No: 5 Write Address: 000d0fc4 WriteData: e2e574c5
|
# Status: Burst-No: 5 Write Address: 000d0fc4 WriteData: e2e574c5
|
# tb_core.u_sdram32 : at time 18167.0 ns WRITE: Bank = 3 Row = 208, Col = 247, Data = cc01b498
|
# tb_core.u_sdram32 : at time 18387.0 ns WRITE: Bank = 3 Row = 208, Col = 247, Data = cc01b498
|
# Status: Burst-No: 6 Write Address: 000d0fc4 WriteData: cc01b498
|
# Status: Burst-No: 6 Write Address: 000d0fc4 WriteData: cc01b498
|
# tb_core.u_sdram32 : at time 18177.0 ns WRITE: Bank = 3 Row = 208, Col = 248, Data = 25b27b4b
|
# tb_core.u_sdram32 : at time 18397.0 ns WRITE: Bank = 3 Row = 208, Col = 248, Data = 25b27b4b
|
# Status: Burst-No: 7 Write Address: 000d0fc4 WriteData: 25b27b4b
|
# Status: Burst-No: 7 Write Address: 000d0fc4 WriteData: 25b27b4b
|
# tb_core.u_sdram32 : at time 18187.0 ns WRITE: Bank = 3 Row = 208, Col = 249, Data = b98c4273
|
# tb_core.u_sdram32 : at time 18407.0 ns WRITE: Bank = 3 Row = 208, Col = 249, Data = b98c4273
|
# Status: Burst-No: 8 Write Address: 000d0fc4 WriteData: b98c4273
|
# Status: Burst-No: 8 Write Address: 000d0fc4 WriteData: b98c4273
|
# tb_core.u_sdram32 : at time 18197.0 ns WRITE: Bank = 3 Row = 208, Col = 250, Data = f622e6ec
|
# tb_core.u_sdram32 : at time 18417.0 ns WRITE: Bank = 3 Row = 208, Col = 250, Data = f622e6ec
|
# Status: Burst-No: 9 Write Address: 000d0fc4 WriteData: f622e6ec
|
# Status: Burst-No: 9 Write Address: 000d0fc4 WriteData: f622e6ec
|
# tb_core.u_sdram32 : at time 18207.0 ns WRITE: Bank = 3 Row = 208, Col = 251, Data = c550168a
|
# tb_core.u_sdram32 : at time 18427.0 ns WRITE: Bank = 3 Row = 208, Col = 251, Data = c550168a
|
# Status: Burst-No: 10 Write Address: 000d0fc4 WriteData: c550168a
|
# Status: Burst-No: 10 Write Address: 000d0fc4 WriteData: c550168a
|
# tb_core.u_sdram32 : at time 18217.0 ns WRITE: Bank = 3 Row = 208, Col = 252, Data = 2758d14e
|
# tb_core.u_sdram32 : at time 18437.0 ns WRITE: Bank = 3 Row = 208, Col = 252, Data = 2758d14e
|
# Status: Burst-No: 11 Write Address: 000d0fc4 WriteData: 2758d14e
|
# Status: Burst-No: 11 Write Address: 000d0fc4 WriteData: 2758d14e
|
# tb_core.u_sdram32 : at time 18227.0 ns WRITE: Bank = 3 Row = 208, Col = 253, Data = d44b80a8
|
# tb_core.u_sdram32 : at time 18447.0 ns WRITE: Bank = 3 Row = 208, Col = 253, Data = d44b80a8
|
# Status: Burst-No: 12 Write Address: 000d0fc4 WriteData: d44b80a8
|
# Status: Burst-No: 12 Write Address: 000d0fc4 WriteData: d44b80a8
|
# tb_core.u_sdram32 : at time 18237.0 ns WRITE: Bank = 3 Row = 208, Col = 254, Data = 549efda9
|
# tb_core.u_sdram32 : at time 18457.0 ns WRITE: Bank = 3 Row = 208, Col = 254, Data = 549efda9
|
# Status: Burst-No: 13 Write Address: 000d0fc4 WriteData: 549efda9
|
# Status: Burst-No: 13 Write Address: 000d0fc4 WriteData: 549efda9
|
# tb_core.u_sdram32 : at time 18247.0 ns WRITE: Bank = 3 Row = 208, Col = 255, Data = d0ca8ca1
|
# tb_core.u_sdram32 : at time 18467.0 ns WRITE: Bank = 3 Row = 208, Col = 255, Data = d0ca8ca1
|
# Status: Burst-No: 14 Write Address: 000d0fc4 WriteData: d0ca8ca1
|
# Status: Burst-No: 14 Write Address: 000d0fc4 WriteData: d0ca8ca1
|
# tb_core.u_sdram32 : at time 18257.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 18477.0 ns BST : Burst Terminate
|
# Write Address: 000e0fc8, Burst Size: 15
|
# Write Address: 000e0fc8, Burst Size: 15
|
# tb_core.u_sdram32 : at time 18327.0 ns ACT : Bank = 3 Row = 224
|
# tb_core.u_sdram32 : at time 18547.0 ns ACT : Bank = 3 Row = 224
|
# tb_core.u_sdram32 : at time 18337.0 ns ACT : Bank = 0 Row = 225
|
# tb_core.u_sdram32 : at time 18587.0 ns WRITE: Bank = 3 Row = 224, Col = 242, Data = 070bb90e
|
# tb_core.u_sdram32 : at time 18337.0 ns ERROR: tRRD violation during Activate bank = 0
|
|
# tb_core.u_sdram32 : at time 18367.0 ns WRITE: Bank = 3 Row = 224, Col = 242, Data = 070bb90e
|
|
# Status: Burst-No: 0 Write Address: 000e0fc8 WriteData: 070bb90e
|
# Status: Burst-No: 0 Write Address: 000e0fc8 WriteData: 070bb90e
|
# tb_core.u_sdram32 : at time 18377.0 ns WRITE: Bank = 3 Row = 224, Col = 243, Data = f33466e6
|
# tb_core.u_sdram32 : at time 18597.0 ns WRITE: Bank = 3 Row = 224, Col = 243, Data = f33466e6
|
# Status: Burst-No: 1 Write Address: 000e0fc8 WriteData: f33466e6
|
# Status: Burst-No: 1 Write Address: 000e0fc8 WriteData: f33466e6
|
# tb_core.u_sdram32 : at time 18387.0 ns WRITE: Bank = 3 Row = 224, Col = 244, Data = cfd6c09f
|
# tb_core.u_sdram32 : at time 18607.0 ns WRITE: Bank = 3 Row = 224, Col = 244, Data = cfd6c09f
|
# Status: Burst-No: 2 Write Address: 000e0fc8 WriteData: cfd6c09f
|
# Status: Burst-No: 2 Write Address: 000e0fc8 WriteData: cfd6c09f
|
# tb_core.u_sdram32 : at time 18397.0 ns WRITE: Bank = 3 Row = 224, Col = 245, Data = 152fb52a
|
# tb_core.u_sdram32 : at time 18617.0 ns WRITE: Bank = 3 Row = 224, Col = 245, Data = 152fb52a
|
# Status: Burst-No: 3 Write Address: 000e0fc8 WriteData: 152fb52a
|
# Status: Burst-No: 3 Write Address: 000e0fc8 WriteData: 152fb52a
|
# tb_core.u_sdram32 : at time 18407.0 ns WRITE: Bank = 3 Row = 224, Col = 246, Data = 155a1d2a
|
# tb_core.u_sdram32 : at time 18627.0 ns WRITE: Bank = 3 Row = 224, Col = 246, Data = 155a1d2a
|
# Status: Burst-No: 4 Write Address: 000e0fc8 WriteData: 155a1d2a
|
# Status: Burst-No: 4 Write Address: 000e0fc8 WriteData: 155a1d2a
|
# tb_core.u_sdram32 : at time 18417.0 ns WRITE: Bank = 3 Row = 224, Col = 247, Data = c6b5f48d
|
# tb_core.u_sdram32 : at time 18637.0 ns ACT : Bank = 0 Row = 225
|
|
# tb_core.u_sdram32 : at time 18637.0 ns WRITE: Bank = 3 Row = 224, Col = 247, Data = c6b5f48d
|
# Status: Burst-No: 5 Write Address: 000e0fc8 WriteData: c6b5f48d
|
# Status: Burst-No: 5 Write Address: 000e0fc8 WriteData: c6b5f48d
|
# tb_core.u_sdram32 : at time 18427.0 ns WRITE: Bank = 3 Row = 224, Col = 248, Data = 4f75ff9e
|
# tb_core.u_sdram32 : at time 18647.0 ns WRITE: Bank = 3 Row = 224, Col = 248, Data = 4f75ff9e
|
# Status: Burst-No: 6 Write Address: 000e0fc8 WriteData: 4f75ff9e
|
# Status: Burst-No: 6 Write Address: 000e0fc8 WriteData: 4f75ff9e
|
# tb_core.u_sdram32 : at time 18437.0 ns WRITE: Bank = 3 Row = 224, Col = 249, Data = 9c6de638
|
# tb_core.u_sdram32 : at time 18657.0 ns WRITE: Bank = 3 Row = 224, Col = 249, Data = 9c6de638
|
# Status: Burst-No: 7 Write Address: 000e0fc8 WriteData: 9c6de638
|
# Status: Burst-No: 7 Write Address: 000e0fc8 WriteData: 9c6de638
|
# tb_core.u_sdram32 : at time 18447.0 ns WRITE: Bank = 3 Row = 224, Col = 250, Data = bccfa879
|
# tb_core.u_sdram32 : at time 18667.0 ns WRITE: Bank = 3 Row = 224, Col = 250, Data = bccfa879
|
# Status: Burst-No: 8 Write Address: 000e0fc8 WriteData: bccfa879
|
# Status: Burst-No: 8 Write Address: 000e0fc8 WriteData: bccfa879
|
# tb_core.u_sdram32 : at time 18457.0 ns WRITE: Bank = 3 Row = 224, Col = 251, Data = 6464e3c8
|
# tb_core.u_sdram32 : at time 18677.0 ns WRITE: Bank = 3 Row = 224, Col = 251, Data = 6464e3c8
|
# Status: Burst-No: 9 Write Address: 000e0fc8 WriteData: 6464e3c8
|
# Status: Burst-No: 9 Write Address: 000e0fc8 WriteData: 6464e3c8
|
# tb_core.u_sdram32 : at time 18467.0 ns WRITE: Bank = 3 Row = 224, Col = 252, Data = 652345ca
|
# tb_core.u_sdram32 : at time 18687.0 ns WRITE: Bank = 3 Row = 224, Col = 252, Data = 652345ca
|
# Status: Burst-No: 10 Write Address: 000e0fc8 WriteData: 652345ca
|
# Status: Burst-No: 10 Write Address: 000e0fc8 WriteData: 652345ca
|
# tb_core.u_sdram32 : at time 18477.0 ns WRITE: Bank = 3 Row = 224, Col = 253, Data = 09ff4113
|
# tb_core.u_sdram32 : at time 18697.0 ns WRITE: Bank = 3 Row = 224, Col = 253, Data = 09ff4113
|
# Status: Burst-No: 11 Write Address: 000e0fc8 WriteData: 09ff4113
|
# Status: Burst-No: 11 Write Address: 000e0fc8 WriteData: 09ff4113
|
# tb_core.u_sdram32 : at time 18487.0 ns WRITE: Bank = 3 Row = 224, Col = 254, Data = 35a0c96b
|
# tb_core.u_sdram32 : at time 18707.0 ns WRITE: Bank = 3 Row = 224, Col = 254, Data = 35a0c96b
|
# Status: Burst-No: 12 Write Address: 000e0fc8 WriteData: 35a0c96b
|
# Status: Burst-No: 12 Write Address: 000e0fc8 WriteData: 35a0c96b
|
# tb_core.u_sdram32 : at time 18497.0 ns WRITE: Bank = 3 Row = 224, Col = 255, Data = e3b7aec7
|
# tb_core.u_sdram32 : at time 18717.0 ns WRITE: Bank = 3 Row = 224, Col = 255, Data = e3b7aec7
|
# Status: Burst-No: 13 Write Address: 000e0fc8 WriteData: e3b7aec7
|
# Status: Burst-No: 13 Write Address: 000e0fc8 WriteData: e3b7aec7
|
# tb_core.u_sdram32 : at time 18507.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 18727.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 18517.0 ns WRITE: Bank = 0 Row = 225, Col = 0, Data = 5b0bddb6
|
# tb_core.u_sdram32 : at time 18737.0 ns WRITE: Bank = 0 Row = 225, Col = 0, Data = 5b0bddb6
|
# Status: Burst-No: 14 Write Address: 000e0fc8 WriteData: 5b0bddb6
|
# Status: Burst-No: 14 Write Address: 000e0fc8 WriteData: 5b0bddb6
|
# tb_core.u_sdram32 : at time 18527.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 18747.0 ns BST : Burst Terminate
|
# Write Address: 000f0fcc, Burst Size: 15
|
# Write Address: 000f0fcc, Burst Size: 15
|
# tb_core.u_sdram32 : at time 18597.0 ns ACT : Bank = 3 Row = 240
|
# tb_core.u_sdram32 : at time 18817.0 ns ACT : Bank = 3 Row = 240
|
# tb_core.u_sdram32 : at time 18607.0 ns ACT : Bank = 0 Row = 241
|
# tb_core.u_sdram32 : at time 18857.0 ns WRITE: Bank = 3 Row = 240, Col = 243, Data = 5d059dba
|
# tb_core.u_sdram32 : at time 18607.0 ns ERROR: tRRD violation during Activate bank = 0
|
|
# tb_core.u_sdram32 : at time 18637.0 ns WRITE: Bank = 3 Row = 240, Col = 243, Data = 5d059dba
|
|
# Status: Burst-No: 0 Write Address: 000f0fcc WriteData: 5d059dba
|
# Status: Burst-No: 0 Write Address: 000f0fcc WriteData: 5d059dba
|
# tb_core.u_sdram32 : at time 18647.0 ns WRITE: Bank = 3 Row = 240, Col = 244, Data = 6216abc4
|
# tb_core.u_sdram32 : at time 18867.0 ns WRITE: Bank = 3 Row = 240, Col = 244, Data = 6216abc4
|
# Status: Burst-No: 1 Write Address: 000f0fcc WriteData: 6216abc4
|
# Status: Burst-No: 1 Write Address: 000f0fcc WriteData: 6216abc4
|
# tb_core.u_sdram32 : at time 18657.0 ns WRITE: Bank = 3 Row = 240, Col = 245, Data = 5c8295b9
|
# tb_core.u_sdram32 : at time 18877.0 ns WRITE: Bank = 3 Row = 240, Col = 245, Data = 5c8295b9
|
# Status: Burst-No: 2 Write Address: 000f0fcc WriteData: 5c8295b9
|
# Status: Burst-No: 2 Write Address: 000f0fcc WriteData: 5c8295b9
|
# tb_core.u_sdram32 : at time 18667.0 ns WRITE: Bank = 3 Row = 240, Col = 246, Data = 492fd392
|
# tb_core.u_sdram32 : at time 18887.0 ns WRITE: Bank = 3 Row = 240, Col = 246, Data = 492fd392
|
# Status: Burst-No: 3 Write Address: 000f0fcc WriteData: 492fd392
|
# Status: Burst-No: 3 Write Address: 000f0fcc WriteData: 492fd392
|
# tb_core.u_sdram32 : at time 18677.0 ns WRITE: Bank = 3 Row = 240, Col = 247, Data = da269ab4
|
# tb_core.u_sdram32 : at time 18897.0 ns WRITE: Bank = 3 Row = 240, Col = 247, Data = da269ab4
|
# Status: Burst-No: 4 Write Address: 000f0fcc WriteData: da269ab4
|
# Status: Burst-No: 4 Write Address: 000f0fcc WriteData: da269ab4
|
# tb_core.u_sdram32 : at time 18687.0 ns WRITE: Bank = 3 Row = 240, Col = 248, Data = 3fbb3b7f
|
# tb_core.u_sdram32 : at time 18907.0 ns WRITE: Bank = 3 Row = 240, Col = 248, Data = 3fbb3b7f
|
# Status: Burst-No: 5 Write Address: 000f0fcc WriteData: 3fbb3b7f
|
# Status: Burst-No: 5 Write Address: 000f0fcc WriteData: 3fbb3b7f
|
# tb_core.u_sdram32 : at time 18697.0 ns WRITE: Bank = 3 Row = 240, Col = 249, Data = c3339086
|
# tb_core.u_sdram32 : at time 18917.0 ns WRITE: Bank = 3 Row = 240, Col = 249, Data = c3339086
|
# Status: Burst-No: 6 Write Address: 000f0fcc WriteData: c3339086
|
# Status: Burst-No: 6 Write Address: 000f0fcc WriteData: c3339086
|
# tb_core.u_sdram32 : at time 18707.0 ns WRITE: Bank = 3 Row = 240, Col = 250, Data = 7d6df5fa
|
# tb_core.u_sdram32 : at time 18927.0 ns WRITE: Bank = 3 Row = 240, Col = 250, Data = 7d6df5fa
|
# Status: Burst-No: 7 Write Address: 000f0fcc WriteData: 7d6df5fa
|
# Status: Burst-No: 7 Write Address: 000f0fcc WriteData: 7d6df5fa
|
# tb_core.u_sdram32 : at time 18717.0 ns WRITE: Bank = 3 Row = 240, Col = 251, Data = f92794f2
|
# tb_core.u_sdram32 : at time 18937.0 ns WRITE: Bank = 3 Row = 240, Col = 251, Data = f92794f2
|
# Status: Burst-No: 8 Write Address: 000f0fcc WriteData: f92794f2
|
# Status: Burst-No: 8 Write Address: 000f0fcc WriteData: f92794f2
|
# tb_core.u_sdram32 : at time 18727.0 ns WRITE: Bank = 3 Row = 240, Col = 252, Data = 19452132
|
# tb_core.u_sdram32 : at time 18947.0 ns WRITE: Bank = 3 Row = 240, Col = 252, Data = 19452132
|
# Status: Burst-No: 9 Write Address: 000f0fcc WriteData: 19452132
|
# Status: Burst-No: 9 Write Address: 000f0fcc WriteData: 19452132
|
# tb_core.u_sdram32 : at time 18737.0 ns WRITE: Bank = 3 Row = 240, Col = 253, Data = dece5ebd
|
# tb_core.u_sdram32 : at time 18957.0 ns WRITE: Bank = 3 Row = 240, Col = 253, Data = dece5ebd
|
# Status: Burst-No: 10 Write Address: 000f0fcc WriteData: dece5ebd
|
# Status: Burst-No: 10 Write Address: 000f0fcc WriteData: dece5ebd
|
# tb_core.u_sdram32 : at time 18747.0 ns WRITE: Bank = 3 Row = 240, Col = 254, Data = 424fcd84
|
# tb_core.u_sdram32 : at time 18967.0 ns WRITE: Bank = 3 Row = 240, Col = 254, Data = 424fcd84
|
# Status: Burst-No: 11 Write Address: 000f0fcc WriteData: 424fcd84
|
# Status: Burst-No: 11 Write Address: 000f0fcc WriteData: 424fcd84
|
# tb_core.u_sdram32 : at time 18757.0 ns WRITE: Bank = 3 Row = 240, Col = 255, Data = f249a4e4
|
# tb_core.u_sdram32 : at time 18977.0 ns WRITE: Bank = 3 Row = 240, Col = 255, Data = f249a4e4
|
# Status: Burst-No: 12 Write Address: 000f0fcc WriteData: f249a4e4
|
# Status: Burst-No: 12 Write Address: 000f0fcc WriteData: f249a4e4
|
# tb_core.u_sdram32 : at time 18767.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 18987.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 18777.0 ns WRITE: Bank = 0 Row = 241, Col = 0, Data = 6543cfca
|
# tb_core.u_sdram32 : at time 19047.0 ns ACT : Bank = 0 Row = 241
|
|
# tb_core.u_sdram32 : at time 19087.0 ns WRITE: Bank = 0 Row = 241, Col = 0, Data = 6543cfca
|
# Status: Burst-No: 13 Write Address: 000f0fcc WriteData: 6543cfca
|
# Status: Burst-No: 13 Write Address: 000f0fcc WriteData: 6543cfca
|
# tb_core.u_sdram32 : at time 18787.0 ns WRITE: Bank = 0 Row = 241, Col = 1, Data = 54a879a9
|
# tb_core.u_sdram32 : at time 19097.0 ns WRITE: Bank = 0 Row = 241, Col = 1, Data = 54a879a9
|
# Status: Burst-No: 14 Write Address: 000f0fcc WriteData: 54a879a9
|
# Status: Burst-No: 14 Write Address: 000f0fcc WriteData: 54a879a9
|
# tb_core.u_sdram32 : at time 18797.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 19107.0 ns BST : Burst Terminate
|
# Write Address: 00100fb0, Burst Size: 15
|
# Write Address: 00100fb0, Burst Size: 15
|
# tb_core.u_sdram32 : at time 18867.0 ns ACT : Bank = 3 Row = 256
|
# tb_core.u_sdram32 : at time 19177.0 ns ACT : Bank = 3 Row = 256
|
# tb_core.u_sdram32 : at time 18907.0 ns WRITE: Bank = 3 Row = 256, Col = 236, Data = d095a8a1
|
# tb_core.u_sdram32 : at time 19217.0 ns WRITE: Bank = 3 Row = 256, Col = 236, Data = d095a8a1
|
# Status: Burst-No: 0 Write Address: 00100fb0 WriteData: d095a8a1
|
# Status: Burst-No: 0 Write Address: 00100fb0 WriteData: d095a8a1
|
# tb_core.u_sdram32 : at time 18917.0 ns WRITE: Bank = 3 Row = 256, Col = 237, Data = 4765a98e
|
# tb_core.u_sdram32 : at time 19227.0 ns WRITE: Bank = 3 Row = 256, Col = 237, Data = 4765a98e
|
# Status: Burst-No: 1 Write Address: 00100fb0 WriteData: 4765a98e
|
# Status: Burst-No: 1 Write Address: 00100fb0 WriteData: 4765a98e
|
# tb_core.u_sdram32 : at time 18927.0 ns WRITE: Bank = 3 Row = 256, Col = 238, Data = fd8b6afb
|
# tb_core.u_sdram32 : at time 19237.0 ns WRITE: Bank = 3 Row = 256, Col = 238, Data = fd8b6afb
|
# Status: Burst-No: 2 Write Address: 00100fb0 WriteData: fd8b6afb
|
# Status: Burst-No: 2 Write Address: 00100fb0 WriteData: fd8b6afb
|
# tb_core.u_sdram32 : at time 18937.0 ns WRITE: Bank = 3 Row = 256, Col = 239, Data = 85e51e0b
|
# tb_core.u_sdram32 : at time 19247.0 ns WRITE: Bank = 3 Row = 256, Col = 239, Data = 85e51e0b
|
# Status: Burst-No: 3 Write Address: 00100fb0 WriteData: 85e51e0b
|
# Status: Burst-No: 3 Write Address: 00100fb0 WriteData: 85e51e0b
|
# tb_core.u_sdram32 : at time 18947.0 ns WRITE: Bank = 3 Row = 256, Col = 240, Data = f78290ef
|
# tb_core.u_sdram32 : at time 19257.0 ns WRITE: Bank = 3 Row = 256, Col = 240, Data = f78290ef
|
# Status: Burst-No: 4 Write Address: 00100fb0 WriteData: f78290ef
|
# Status: Burst-No: 4 Write Address: 00100fb0 WriteData: f78290ef
|
# tb_core.u_sdram32 : at time 18957.0 ns WRITE: Bank = 3 Row = 256, Col = 241, Data = 64c83dc9
|
# tb_core.u_sdram32 : at time 19267.0 ns WRITE: Bank = 3 Row = 256, Col = 241, Data = 64c83dc9
|
# Status: Burst-No: 5 Write Address: 00100fb0 WriteData: 64c83dc9
|
# Status: Burst-No: 5 Write Address: 00100fb0 WriteData: 64c83dc9
|
# tb_core.u_sdram32 : at time 18967.0 ns WRITE: Bank = 3 Row = 256, Col = 242, Data = 1b60e536
|
# tb_core.u_sdram32 : at time 19277.0 ns WRITE: Bank = 3 Row = 256, Col = 242, Data = 1b60e536
|
# Status: Burst-No: 6 Write Address: 00100fb0 WriteData: 1b60e536
|
# Status: Burst-No: 6 Write Address: 00100fb0 WriteData: 1b60e536
|
# tb_core.u_sdram32 : at time 18977.0 ns WRITE: Bank = 3 Row = 256, Col = 243, Data = bab14875
|
# tb_core.u_sdram32 : at time 19287.0 ns WRITE: Bank = 3 Row = 256, Col = 243, Data = bab14875
|
# Status: Burst-No: 7 Write Address: 00100fb0 WriteData: bab14875
|
# Status: Burst-No: 7 Write Address: 00100fb0 WriteData: bab14875
|
# tb_core.u_sdram32 : at time 18987.0 ns WRITE: Bank = 3 Row = 256, Col = 244, Data = c7e8568f
|
# tb_core.u_sdram32 : at time 19297.0 ns WRITE: Bank = 3 Row = 256, Col = 244, Data = c7e8568f
|
# Status: Burst-No: 8 Write Address: 00100fb0 WriteData: c7e8568f
|
# Status: Burst-No: 8 Write Address: 00100fb0 WriteData: c7e8568f
|
# tb_core.u_sdram32 : at time 18997.0 ns WRITE: Bank = 3 Row = 256, Col = 245, Data = 35cdbf6b
|
# tb_core.u_sdram32 : at time 19307.0 ns WRITE: Bank = 3 Row = 256, Col = 245, Data = 35cdbf6b
|
# Status: Burst-No: 9 Write Address: 00100fb0 WriteData: 35cdbf6b
|
# Status: Burst-No: 9 Write Address: 00100fb0 WriteData: 35cdbf6b
|
# tb_core.u_sdram32 : at time 19007.0 ns WRITE: Bank = 3 Row = 256, Col = 246, Data = 4465e788
|
# tb_core.u_sdram32 : at time 19317.0 ns WRITE: Bank = 3 Row = 256, Col = 246, Data = 4465e788
|
# Status: Burst-No: 10 Write Address: 00100fb0 WriteData: 4465e788
|
# Status: Burst-No: 10 Write Address: 00100fb0 WriteData: 4465e788
|
# tb_core.u_sdram32 : at time 19017.0 ns WRITE: Bank = 3 Row = 256, Col = 247, Data = d73fb4ae
|
# tb_core.u_sdram32 : at time 19327.0 ns WRITE: Bank = 3 Row = 256, Col = 247, Data = d73fb4ae
|
# Status: Burst-No: 11 Write Address: 00100fb0 WriteData: d73fb4ae
|
# Status: Burst-No: 11 Write Address: 00100fb0 WriteData: d73fb4ae
|
# tb_core.u_sdram32 : at time 19027.0 ns WRITE: Bank = 3 Row = 256, Col = 248, Data = 4df3819b
|
# tb_core.u_sdram32 : at time 19337.0 ns WRITE: Bank = 3 Row = 256, Col = 248, Data = 4df3819b
|
# Status: Burst-No: 12 Write Address: 00100fb0 WriteData: 4df3819b
|
# Status: Burst-No: 12 Write Address: 00100fb0 WriteData: 4df3819b
|
# tb_core.u_sdram32 : at time 19037.0 ns WRITE: Bank = 3 Row = 256, Col = 249, Data = 493e4592
|
# tb_core.u_sdram32 : at time 19347.0 ns WRITE: Bank = 3 Row = 256, Col = 249, Data = 493e4592
|
# Status: Burst-No: 13 Write Address: 00100fb0 WriteData: 493e4592
|
# Status: Burst-No: 13 Write Address: 00100fb0 WriteData: 493e4592
|
# tb_core.u_sdram32 : at time 19047.0 ns WRITE: Bank = 3 Row = 256, Col = 250, Data = 1444df28
|
# tb_core.u_sdram32 : at time 19357.0 ns WRITE: Bank = 3 Row = 256, Col = 250, Data = 1444df28
|
# Status: Burst-No: 14 Write Address: 00100fb0 WriteData: 1444df28
|
# Status: Burst-No: 14 Write Address: 00100fb0 WriteData: 1444df28
|
# tb_core.u_sdram32 : at time 19057.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 19367.0 ns BST : Burst Terminate
|
# Write Address: 00110fb4, Burst Size: 15
|
# Write Address: 00110fb4, Burst Size: 15
|
# tb_core.u_sdram32 : at time 19127.0 ns ACT : Bank = 3 Row = 272
|
# tb_core.u_sdram32 : at time 19437.0 ns ACT : Bank = 3 Row = 272
|
# tb_core.u_sdram32 : at time 19167.0 ns WRITE: Bank = 3 Row = 272, Col = 237, Data = 9684e02d
|
# tb_core.u_sdram32 : at time 19477.0 ns WRITE: Bank = 3 Row = 272, Col = 237, Data = 9684e02d
|
# Status: Burst-No: 0 Write Address: 00110fb4 WriteData: 9684e02d
|
# Status: Burst-No: 0 Write Address: 00110fb4 WriteData: 9684e02d
|
# tb_core.u_sdram32 : at time 19177.0 ns WRITE: Bank = 3 Row = 272, Col = 238, Data = 25b75f4b
|
# tb_core.u_sdram32 : at time 19487.0 ns WRITE: Bank = 3 Row = 272, Col = 238, Data = 25b75f4b
|
# Status: Burst-No: 1 Write Address: 00110fb4 WriteData: 25b75f4b
|
# Status: Burst-No: 1 Write Address: 00110fb4 WriteData: 25b75f4b
|
# tb_core.u_sdram32 : at time 19187.0 ns WRITE: Bank = 3 Row = 272, Col = 239, Data = e169b0c2
|
# tb_core.u_sdram32 : at time 19497.0 ns WRITE: Bank = 3 Row = 272, Col = 239, Data = e169b0c2
|
# Status: Burst-No: 2 Write Address: 00110fb4 WriteData: e169b0c2
|
# Status: Burst-No: 2 Write Address: 00110fb4 WriteData: e169b0c2
|
# tb_core.u_sdram32 : at time 19197.0 ns WRITE: Bank = 3 Row = 272, Col = 240, Data = 8f1cf61e
|
# tb_core.u_sdram32 : at time 19507.0 ns WRITE: Bank = 3 Row = 272, Col = 240, Data = 8f1cf61e
|
# Status: Burst-No: 3 Write Address: 00110fb4 WriteData: 8f1cf61e
|
# Status: Burst-No: 3 Write Address: 00110fb4 WriteData: 8f1cf61e
|
# tb_core.u_sdram32 : at time 19207.0 ns WRITE: Bank = 3 Row = 272, Col = 241, Data = 06b3050d
|
# tb_core.u_sdram32 : at time 19517.0 ns WRITE: Bank = 3 Row = 272, Col = 241, Data = 06b3050d
|
# Status: Burst-No: 4 Write Address: 00110fb4 WriteData: 06b3050d
|
# Status: Burst-No: 4 Write Address: 00110fb4 WriteData: 06b3050d
|
# tb_core.u_sdram32 : at time 19217.0 ns WRITE: Bank = 3 Row = 272, Col = 242, Data = 7679fdec
|
# tb_core.u_sdram32 : at time 19527.0 ns WRITE: Bank = 3 Row = 272, Col = 242, Data = 7679fdec
|
# Status: Burst-No: 5 Write Address: 00110fb4 WriteData: 7679fdec
|
# Status: Burst-No: 5 Write Address: 00110fb4 WriteData: 7679fdec
|
# tb_core.u_sdram32 : at time 19227.0 ns WRITE: Bank = 3 Row = 272, Col = 243, Data = 0c039d18
|
# tb_core.u_sdram32 : at time 19537.0 ns WRITE: Bank = 3 Row = 272, Col = 243, Data = 0c039d18
|
# Status: Burst-No: 6 Write Address: 00110fb4 WriteData: 0c039d18
|
# Status: Burst-No: 6 Write Address: 00110fb4 WriteData: 0c039d18
|
# tb_core.u_sdram32 : at time 19237.0 ns WRITE: Bank = 3 Row = 272, Col = 244, Data = 68ae1bd1
|
# tb_core.u_sdram32 : at time 19547.0 ns WRITE: Bank = 3 Row = 272, Col = 244, Data = 68ae1bd1
|
# Status: Burst-No: 7 Write Address: 00110fb4 WriteData: 68ae1bd1
|
# Status: Burst-No: 7 Write Address: 00110fb4 WriteData: 68ae1bd1
|
# tb_core.u_sdram32 : at time 19247.0 ns WRITE: Bank = 3 Row = 272, Col = 245, Data = c3761c86
|
# tb_core.u_sdram32 : at time 19557.0 ns WRITE: Bank = 3 Row = 272, Col = 245, Data = c3761c86
|
# Status: Burst-No: 8 Write Address: 00110fb4 WriteData: c3761c86
|
# Status: Burst-No: 8 Write Address: 00110fb4 WriteData: c3761c86
|
# tb_core.u_sdram32 : at time 19257.0 ns WRITE: Bank = 3 Row = 272, Col = 246, Data = a0c02441
|
# tb_core.u_sdram32 : at time 19567.0 ns WRITE: Bank = 3 Row = 272, Col = 246, Data = a0c02441
|
# Status: Burst-No: 9 Write Address: 00110fb4 WriteData: a0c02441
|
# Status: Burst-No: 9 Write Address: 00110fb4 WriteData: a0c02441
|
# tb_core.u_sdram32 : at time 19267.0 ns WRITE: Bank = 3 Row = 272, Col = 247, Data = 9dbf643b
|
# tb_core.u_sdram32 : at time 19577.0 ns WRITE: Bank = 3 Row = 272, Col = 247, Data = 9dbf643b
|
# Status: Burst-No: 10 Write Address: 00110fb4 WriteData: 9dbf643b
|
# Status: Burst-No: 10 Write Address: 00110fb4 WriteData: 9dbf643b
|
# tb_core.u_sdram32 : at time 19277.0 ns WRITE: Bank = 3 Row = 272, Col = 248, Data = 6c44f9d8
|
# tb_core.u_sdram32 : at time 19587.0 ns WRITE: Bank = 3 Row = 272, Col = 248, Data = 6c44f9d8
|
# Status: Burst-No: 11 Write Address: 00110fb4 WriteData: 6c44f9d8
|
# Status: Burst-No: 11 Write Address: 00110fb4 WriteData: 6c44f9d8
|
# tb_core.u_sdram32 : at time 19287.0 ns WRITE: Bank = 3 Row = 272, Col = 249, Data = 29efe953
|
# tb_core.u_sdram32 : at time 19597.0 ns WRITE: Bank = 3 Row = 272, Col = 249, Data = 29efe953
|
# Status: Burst-No: 12 Write Address: 00110fb4 WriteData: 29efe953
|
# Status: Burst-No: 12 Write Address: 00110fb4 WriteData: 29efe953
|
# tb_core.u_sdram32 : at time 19297.0 ns WRITE: Bank = 3 Row = 272, Col = 250, Data = ab196256
|
# tb_core.u_sdram32 : at time 19607.0 ns WRITE: Bank = 3 Row = 272, Col = 250, Data = ab196256
|
# Status: Burst-No: 13 Write Address: 00110fb4 WriteData: ab196256
|
# Status: Burst-No: 13 Write Address: 00110fb4 WriteData: ab196256
|
# tb_core.u_sdram32 : at time 19307.0 ns WRITE: Bank = 3 Row = 272, Col = 251, Data = adac225b
|
# tb_core.u_sdram32 : at time 19617.0 ns WRITE: Bank = 3 Row = 272, Col = 251, Data = adac225b
|
# Status: Burst-No: 14 Write Address: 00110fb4 WriteData: adac225b
|
# Status: Burst-No: 14 Write Address: 00110fb4 WriteData: adac225b
|
# tb_core.u_sdram32 : at time 19317.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 19627.0 ns BST : Burst Terminate
|
# Write Address: 00120fb8, Burst Size: 15
|
# Write Address: 00120fb8, Burst Size: 15
|
# tb_core.u_sdram32 : at time 19387.0 ns ACT : Bank = 3 Row = 288
|
# tb_core.u_sdram32 : at time 19697.0 ns ACT : Bank = 3 Row = 288
|
# tb_core.u_sdram32 : at time 19427.0 ns WRITE: Bank = 3 Row = 288, Col = 238, Data = f166fae2
|
# tb_core.u_sdram32 : at time 19737.0 ns WRITE: Bank = 3 Row = 288, Col = 238, Data = f166fae2
|
# Status: Burst-No: 0 Write Address: 00120fb8 WriteData: f166fae2
|
# Status: Burst-No: 0 Write Address: 00120fb8 WriteData: f166fae2
|
# tb_core.u_sdram32 : at time 19437.0 ns WRITE: Bank = 3 Row = 288, Col = 239, Data = 8273e204
|
# tb_core.u_sdram32 : at time 19747.0 ns WRITE: Bank = 3 Row = 288, Col = 239, Data = 8273e204
|
# Status: Burst-No: 1 Write Address: 00120fb8 WriteData: 8273e204
|
# Status: Burst-No: 1 Write Address: 00120fb8 WriteData: 8273e204
|
# tb_core.u_sdram32 : at time 19447.0 ns WRITE: Bank = 3 Row = 288, Col = 240, Data = 39ac0373
|
# tb_core.u_sdram32 : at time 19757.0 ns WRITE: Bank = 3 Row = 288, Col = 240, Data = 39ac0373
|
# Status: Burst-No: 2 Write Address: 00120fb8 WriteData: 39ac0373
|
# Status: Burst-No: 2 Write Address: 00120fb8 WriteData: 39ac0373
|
# tb_core.u_sdram32 : at time 19457.0 ns WRITE: Bank = 3 Row = 288, Col = 241, Data = ec50b4d8
|
# tb_core.u_sdram32 : at time 19767.0 ns WRITE: Bank = 3 Row = 288, Col = 241, Data = ec50b4d8
|
# Status: Burst-No: 3 Write Address: 00120fb8 WriteData: ec50b4d8
|
# Status: Burst-No: 3 Write Address: 00120fb8 WriteData: ec50b4d8
|
# tb_core.u_sdram32 : at time 19467.0 ns WRITE: Bank = 3 Row = 288, Col = 242, Data = 093e4d12
|
# tb_core.u_sdram32 : at time 19777.0 ns WRITE: Bank = 3 Row = 288, Col = 242, Data = 093e4d12
|
# Status: Burst-No: 4 Write Address: 00120fb8 WriteData: 093e4d12
|
# Status: Burst-No: 4 Write Address: 00120fb8 WriteData: 093e4d12
|
# tb_core.u_sdram32 : at time 19477.0 ns WRITE: Bank = 3 Row = 288, Col = 243, Data = dc0344b8
|
# tb_core.u_sdram32 : at time 19787.0 ns WRITE: Bank = 3 Row = 288, Col = 243, Data = dc0344b8
|
# Status: Burst-No: 5 Write Address: 00120fb8 WriteData: dc0344b8
|
# Status: Burst-No: 5 Write Address: 00120fb8 WriteData: dc0344b8
|
# tb_core.u_sdram32 : at time 19487.0 ns WRITE: Bank = 3 Row = 288, Col = 244, Data = 9c811239
|
# tb_core.u_sdram32 : at time 19797.0 ns WRITE: Bank = 3 Row = 288, Col = 244, Data = 9c811239
|
# Status: Burst-No: 6 Write Address: 00120fb8 WriteData: 9c811239
|
# Status: Burst-No: 6 Write Address: 00120fb8 WriteData: 9c811239
|
# tb_core.u_sdram32 : at time 19497.0 ns WRITE: Bank = 3 Row = 288, Col = 245, Data = f287b6e5
|
# tb_core.u_sdram32 : at time 19807.0 ns WRITE: Bank = 3 Row = 288, Col = 245, Data = f287b6e5
|
# Status: Burst-No: 7 Write Address: 00120fb8 WriteData: f287b6e5
|
# Status: Burst-No: 7 Write Address: 00120fb8 WriteData: f287b6e5
|
# tb_core.u_sdram32 : at time 19507.0 ns WRITE: Bank = 3 Row = 288, Col = 246, Data = d0c5dca1
|
# tb_core.u_sdram32 : at time 19817.0 ns WRITE: Bank = 3 Row = 288, Col = 246, Data = d0c5dca1
|
# Status: Burst-No: 8 Write Address: 00120fb8 WriteData: d0c5dca1
|
# Status: Burst-No: 8 Write Address: 00120fb8 WriteData: d0c5dca1
|
# tb_core.u_sdram32 : at time 19517.0 ns WRITE: Bank = 3 Row = 288, Col = 247, Data = 15890f2b
|
# tb_core.u_sdram32 : at time 19827.0 ns WRITE: Bank = 3 Row = 288, Col = 247, Data = 15890f2b
|
# Status: Burst-No: 9 Write Address: 00120fb8 WriteData: 15890f2b
|
# Status: Burst-No: 9 Write Address: 00120fb8 WriteData: 15890f2b
|
# tb_core.u_sdram32 : at time 19527.0 ns WRITE: Bank = 3 Row = 288, Col = 248, Data = 40905d81
|
# tb_core.u_sdram32 : at time 19837.0 ns WRITE: Bank = 3 Row = 288, Col = 248, Data = 40905d81
|
# Status: Burst-No: 10 Write Address: 00120fb8 WriteData: 40905d81
|
# Status: Burst-No: 10 Write Address: 00120fb8 WriteData: 40905d81
|
# tb_core.u_sdram32 : at time 19537.0 ns WRITE: Bank = 3 Row = 288, Col = 249, Data = 641b85c8
|
# tb_core.u_sdram32 : at time 19847.0 ns WRITE: Bank = 3 Row = 288, Col = 249, Data = 641b85c8
|
# Status: Burst-No: 11 Write Address: 00120fb8 WriteData: 641b85c8
|
# Status: Burst-No: 11 Write Address: 00120fb8 WriteData: 641b85c8
|
# tb_core.u_sdram32 : at time 19547.0 ns WRITE: Bank = 3 Row = 288, Col = 250, Data = 13b55527
|
# tb_core.u_sdram32 : at time 19857.0 ns WRITE: Bank = 3 Row = 288, Col = 250, Data = 13b55527
|
# Status: Burst-No: 12 Write Address: 00120fb8 WriteData: 13b55527
|
# Status: Burst-No: 12 Write Address: 00120fb8 WriteData: 13b55527
|
# tb_core.u_sdram32 : at time 19557.0 ns WRITE: Bank = 3 Row = 288, Col = 251, Data = 50d5f9a1
|
# tb_core.u_sdram32 : at time 19867.0 ns WRITE: Bank = 3 Row = 288, Col = 251, Data = 50d5f9a1
|
# Status: Burst-No: 13 Write Address: 00120fb8 WriteData: 50d5f9a1
|
# Status: Burst-No: 13 Write Address: 00120fb8 WriteData: 50d5f9a1
|
# tb_core.u_sdram32 : at time 19567.0 ns WRITE: Bank = 3 Row = 288, Col = 252, Data = 8f8c6e1f
|
# tb_core.u_sdram32 : at time 19877.0 ns WRITE: Bank = 3 Row = 288, Col = 252, Data = 8f8c6e1f
|
# Status: Burst-No: 14 Write Address: 00120fb8 WriteData: 8f8c6e1f
|
# Status: Burst-No: 14 Write Address: 00120fb8 WriteData: 8f8c6e1f
|
# tb_core.u_sdram32 : at time 19577.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 19887.0 ns BST : Burst Terminate
|
# Write Address: 00130fbc, Burst Size: 15
|
# Write Address: 00130fbc, Burst Size: 15
|
# tb_core.u_sdram32 : at time 19647.0 ns ACT : Bank = 3 Row = 304
|
# tb_core.u_sdram32 : at time 19957.0 ns ACT : Bank = 3 Row = 304
|
# tb_core.u_sdram32 : at time 19687.0 ns WRITE: Bank = 3 Row = 304, Col = 239, Data = 82223a04
|
# tb_core.u_sdram32 : at time 19997.0 ns WRITE: Bank = 3 Row = 304, Col = 239, Data = 82223a04
|
# Status: Burst-No: 0 Write Address: 00130fbc WriteData: 82223a04
|
# Status: Burst-No: 0 Write Address: 00130fbc WriteData: 82223a04
|
# tb_core.u_sdram32 : at time 19697.0 ns WRITE: Bank = 3 Row = 304, Col = 240, Data = 2c2d2358
|
# tb_core.u_sdram32 : at time 20007.0 ns WRITE: Bank = 3 Row = 304, Col = 240, Data = 2c2d2358
|
# Status: Burst-No: 1 Write Address: 00130fbc WriteData: 2c2d2358
|
# Status: Burst-No: 1 Write Address: 00130fbc WriteData: 2c2d2358
|
# tb_core.u_sdram32 : at time 19707.0 ns WRITE: Bank = 3 Row = 304, Col = 241, Data = cb5c8096
|
# tb_core.u_sdram32 : at time 20017.0 ns WRITE: Bank = 3 Row = 304, Col = 241, Data = cb5c8096
|
# Status: Burst-No: 2 Write Address: 00130fbc WriteData: cb5c8096
|
# Status: Burst-No: 2 Write Address: 00130fbc WriteData: cb5c8096
|
# tb_core.u_sdram32 : at time 19717.0 ns WRITE: Bank = 3 Row = 304, Col = 242, Data = 0a6e9314
|
# tb_core.u_sdram32 : at time 20027.0 ns WRITE: Bank = 3 Row = 304, Col = 242, Data = 0a6e9314
|
# Status: Burst-No: 3 Write Address: 00130fbc WriteData: 0a6e9314
|
# Status: Burst-No: 3 Write Address: 00130fbc WriteData: 0a6e9314
|
# tb_core.u_sdram32 : at time 19727.0 ns WRITE: Bank = 3 Row = 304, Col = 243, Data = 8919b412
|
# tb_core.u_sdram32 : at time 20037.0 ns WRITE: Bank = 3 Row = 304, Col = 243, Data = 8919b412
|
# Status: Burst-No: 4 Write Address: 00130fbc WriteData: 8919b412
|
# Status: Burst-No: 4 Write Address: 00130fbc WriteData: 8919b412
|
# tb_core.u_sdram32 : at time 19737.0 ns WRITE: Bank = 3 Row = 304, Col = 244, Data = cb227096
|
# tb_core.u_sdram32 : at time 20047.0 ns WRITE: Bank = 3 Row = 304, Col = 244, Data = cb227096
|
# Status: Burst-No: 5 Write Address: 00130fbc WriteData: cb227096
|
# Status: Burst-No: 5 Write Address: 00130fbc WriteData: cb227096
|
# tb_core.u_sdram32 : at time 19747.0 ns WRITE: Bank = 3 Row = 304, Col = 245, Data = d8ace2b1
|
# tb_core.u_sdram32 : at time 20057.0 ns WRITE: Bank = 3 Row = 304, Col = 245, Data = d8ace2b1
|
# Status: Burst-No: 6 Write Address: 00130fbc WriteData: d8ace2b1
|
# Status: Burst-No: 6 Write Address: 00130fbc WriteData: d8ace2b1
|
# tb_core.u_sdram32 : at time 19757.0 ns WRITE: Bank = 3 Row = 304, Col = 246, Data = 2ac2d555
|
# tb_core.u_sdram32 : at time 20067.0 ns WRITE: Bank = 3 Row = 304, Col = 246, Data = 2ac2d555
|
# Status: Burst-No: 7 Write Address: 00130fbc WriteData: 2ac2d555
|
# Status: Burst-No: 7 Write Address: 00130fbc WriteData: 2ac2d555
|
# tb_core.u_sdram32 : at time 19767.0 ns WRITE: Bank = 3 Row = 304, Col = 247, Data = f6c38eed
|
# tb_core.u_sdram32 : at time 20077.0 ns WRITE: Bank = 3 Row = 304, Col = 247, Data = f6c38eed
|
# Status: Burst-No: 8 Write Address: 00130fbc WriteData: f6c38eed
|
# Status: Burst-No: 8 Write Address: 00130fbc WriteData: f6c38eed
|
# tb_core.u_sdram32 : at time 19777.0 ns WRITE: Bank = 3 Row = 304, Col = 248, Data = 158b2b2b
|
# tb_core.u_sdram32 : at time 20087.0 ns WRITE: Bank = 3 Row = 304, Col = 248, Data = 158b2b2b
|
# Status: Burst-No: 9 Write Address: 00130fbc WriteData: 158b2b2b
|
# Status: Burst-No: 9 Write Address: 00130fbc WriteData: 158b2b2b
|
# tb_core.u_sdram32 : at time 19787.0 ns WRITE: Bank = 3 Row = 304, Col = 249, Data = 7ab11bf5
|
# tb_core.u_sdram32 : at time 20097.0 ns WRITE: Bank = 3 Row = 304, Col = 249, Data = 7ab11bf5
|
# Status: Burst-No: 10 Write Address: 00130fbc WriteData: 7ab11bf5
|
# Status: Burst-No: 10 Write Address: 00130fbc WriteData: 7ab11bf5
|
# tb_core.u_sdram32 : at time 19797.0 ns WRITE: Bank = 3 Row = 304, Col = 250, Data = 56b403ad
|
# tb_core.u_sdram32 : at time 20107.0 ns WRITE: Bank = 3 Row = 304, Col = 250, Data = 56b403ad
|
# Status: Burst-No: 11 Write Address: 00130fbc WriteData: 56b403ad
|
# Status: Burst-No: 11 Write Address: 00130fbc WriteData: 56b403ad
|
# tb_core.u_sdram32 : at time 19807.0 ns WRITE: Bank = 3 Row = 304, Col = 251, Data = 93c12227
|
# tb_core.u_sdram32 : at time 20117.0 ns WRITE: Bank = 3 Row = 304, Col = 251, Data = 93c12227
|
# Status: Burst-No: 12 Write Address: 00130fbc WriteData: 93c12227
|
# Status: Burst-No: 12 Write Address: 00130fbc WriteData: 93c12227
|
# tb_core.u_sdram32 : at time 19817.0 ns WRITE: Bank = 3 Row = 304, Col = 252, Data = 4249ff84
|
# tb_core.u_sdram32 : at time 20127.0 ns WRITE: Bank = 3 Row = 304, Col = 252, Data = 4249ff84
|
# Status: Burst-No: 13 Write Address: 00130fbc WriteData: 4249ff84
|
# Status: Burst-No: 13 Write Address: 00130fbc WriteData: 4249ff84
|
# tb_core.u_sdram32 : at time 19827.0 ns WRITE: Bank = 3 Row = 304, Col = 253, Data = d3a8e4a7
|
# tb_core.u_sdram32 : at time 20137.0 ns WRITE: Bank = 3 Row = 304, Col = 253, Data = d3a8e4a7
|
# Status: Burst-No: 14 Write Address: 00130fbc WriteData: d3a8e4a7
|
# Status: Burst-No: 14 Write Address: 00130fbc WriteData: d3a8e4a7
|
# tb_core.u_sdram32 : at time 19837.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 20147.0 ns BST : Burst Terminate
|
# Write Address: 00140fa0, Burst Size: 15
|
# Write Address: 00140fa0, Burst Size: 15
|
# tb_core.u_sdram32 : at time 19907.0 ns ACT : Bank = 3 Row = 320
|
# tb_core.u_sdram32 : at time 20217.0 ns ACT : Bank = 3 Row = 320
|
# tb_core.u_sdram32 : at time 19947.0 ns WRITE: Bank = 3 Row = 320, Col = 232, Data = f3d7a6e7
|
# tb_core.u_sdram32 : at time 20257.0 ns WRITE: Bank = 3 Row = 320, Col = 232, Data = f3d7a6e7
|
# Status: Burst-No: 0 Write Address: 00140fa0 WriteData: f3d7a6e7
|
# Status: Burst-No: 0 Write Address: 00140fa0 WriteData: f3d7a6e7
|
# tb_core.u_sdram32 : at time 19957.0 ns WRITE: Bank = 3 Row = 320, Col = 233, Data = dcef90b9
|
# tb_core.u_sdram32 : at time 20267.0 ns WRITE: Bank = 3 Row = 320, Col = 233, Data = dcef90b9
|
# Status: Burst-No: 1 Write Address: 00140fa0 WriteData: dcef90b9
|
# Status: Burst-No: 1 Write Address: 00140fa0 WriteData: dcef90b9
|
# tb_core.u_sdram32 : at time 19967.0 ns WRITE: Bank = 3 Row = 320, Col = 234, Data = a4da5649
|
# tb_core.u_sdram32 : at time 20277.0 ns WRITE: Bank = 3 Row = 320, Col = 234, Data = a4da5649
|
# Status: Burst-No: 2 Write Address: 00140fa0 WriteData: a4da5649
|
# Status: Burst-No: 2 Write Address: 00140fa0 WriteData: a4da5649
|
# tb_core.u_sdram32 : at time 19977.0 ns WRITE: Bank = 3 Row = 320, Col = 235, Data = 6de5bbdb
|
# tb_core.u_sdram32 : at time 20287.0 ns WRITE: Bank = 3 Row = 320, Col = 235, Data = 6de5bbdb
|
# Status: Burst-No: 3 Write Address: 00140fa0 WriteData: 6de5bbdb
|
# Status: Burst-No: 3 Write Address: 00140fa0 WriteData: 6de5bbdb
|
# tb_core.u_sdram32 : at time 19987.0 ns WRITE: Bank = 3 Row = 320, Col = 236, Data = 64ba0fc9
|
# tb_core.u_sdram32 : at time 20297.0 ns WRITE: Bank = 3 Row = 320, Col = 236, Data = 64ba0fc9
|
# Status: Burst-No: 4 Write Address: 00140fa0 WriteData: 64ba0fc9
|
# Status: Burst-No: 4 Write Address: 00140fa0 WriteData: 64ba0fc9
|
# tb_core.u_sdram32 : at time 19997.0 ns WRITE: Bank = 3 Row = 320, Col = 237, Data = 2883b151
|
# tb_core.u_sdram32 : at time 20307.0 ns WRITE: Bank = 3 Row = 320, Col = 237, Data = 2883b151
|
# Status: Burst-No: 5 Write Address: 00140fa0 WriteData: 2883b151
|
# Status: Burst-No: 5 Write Address: 00140fa0 WriteData: 2883b151
|
# tb_core.u_sdram32 : at time 20007.0 ns WRITE: Bank = 3 Row = 320, Col = 238, Data = d0bc5ea1
|
# tb_core.u_sdram32 : at time 20317.0 ns WRITE: Bank = 3 Row = 320, Col = 238, Data = d0bc5ea1
|
# Status: Burst-No: 6 Write Address: 00140fa0 WriteData: d0bc5ea1
|
# Status: Burst-No: 6 Write Address: 00140fa0 WriteData: d0bc5ea1
|
# tb_core.u_sdram32 : at time 20017.0 ns WRITE: Bank = 3 Row = 320, Col = 239, Data = 1546dd2a
|
# tb_core.u_sdram32 : at time 20327.0 ns WRITE: Bank = 3 Row = 320, Col = 239, Data = 1546dd2a
|
# Status: Burst-No: 7 Write Address: 00140fa0 WriteData: 1546dd2a
|
# Status: Burst-No: 7 Write Address: 00140fa0 WriteData: 1546dd2a
|
# tb_core.u_sdram32 : at time 20027.0 ns WRITE: Bank = 3 Row = 320, Col = 240, Data = 7d2a45fa
|
# tb_core.u_sdram32 : at time 20337.0 ns WRITE: Bank = 3 Row = 320, Col = 240, Data = 7d2a45fa
|
# Status: Burst-No: 8 Write Address: 00140fa0 WriteData: 7d2a45fa
|
# Status: Burst-No: 8 Write Address: 00140fa0 WriteData: 7d2a45fa
|
# tb_core.u_sdram32 : at time 20037.0 ns WRITE: Bank = 3 Row = 320, Col = 241, Data = a2e62045
|
# tb_core.u_sdram32 : at time 20347.0 ns WRITE: Bank = 3 Row = 320, Col = 241, Data = a2e62045
|
# Status: Burst-No: 9 Write Address: 00140fa0 WriteData: a2e62045
|
# Status: Burst-No: 9 Write Address: 00140fa0 WriteData: a2e62045
|
# tb_core.u_sdram32 : at time 20047.0 ns WRITE: Bank = 3 Row = 320, Col = 242, Data = 41a10583
|
# tb_core.u_sdram32 : at time 20357.0 ns WRITE: Bank = 3 Row = 320, Col = 242, Data = 41a10583
|
# Status: Burst-No: 10 Write Address: 00140fa0 WriteData: 41a10583
|
# Status: Burst-No: 10 Write Address: 00140fa0 WriteData: 41a10583
|
# tb_core.u_sdram32 : at time 20057.0 ns WRITE: Bank = 3 Row = 320, Col = 243, Data = be75427c
|
# tb_core.u_sdram32 : at time 20367.0 ns WRITE: Bank = 3 Row = 320, Col = 243, Data = be75427c
|
# Status: Burst-No: 11 Write Address: 00140fa0 WriteData: be75427c
|
# Status: Burst-No: 11 Write Address: 00140fa0 WriteData: be75427c
|
# tb_core.u_sdram32 : at time 20067.0 ns WRITE: Bank = 3 Row = 320, Col = 244, Data = b9461472
|
# tb_core.u_sdram32 : at time 20377.0 ns WRITE: Bank = 3 Row = 320, Col = 244, Data = b9461472
|
# Status: Burst-No: 12 Write Address: 00140fa0 WriteData: b9461472
|
# Status: Burst-No: 12 Write Address: 00140fa0 WriteData: b9461472
|
# tb_core.u_sdram32 : at time 20077.0 ns WRITE: Bank = 3 Row = 320, Col = 245, Data = ff4f3cfe
|
# tb_core.u_sdram32 : at time 20387.0 ns WRITE: Bank = 3 Row = 320, Col = 245, Data = ff4f3cfe
|
# Status: Burst-No: 13 Write Address: 00140fa0 WriteData: ff4f3cfe
|
# Status: Burst-No: 13 Write Address: 00140fa0 WriteData: ff4f3cfe
|
# tb_core.u_sdram32 : at time 20087.0 ns WRITE: Bank = 3 Row = 320, Col = 246, Data = b455f268
|
# tb_core.u_sdram32 : at time 20397.0 ns WRITE: Bank = 3 Row = 320, Col = 246, Data = b455f268
|
# Status: Burst-No: 14 Write Address: 00140fa0 WriteData: b455f268
|
# Status: Burst-No: 14 Write Address: 00140fa0 WriteData: b455f268
|
# tb_core.u_sdram32 : at time 20097.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 20407.0 ns BST : Burst Terminate
|
# Write Address: 00150fa4, Burst Size: 15
|
# Write Address: 00150fa4, Burst Size: 15
|
# tb_core.u_sdram32 : at time 20167.0 ns ACT : Bank = 3 Row = 336
|
# tb_core.u_sdram32 : at time 20477.0 ns ACT : Bank = 3 Row = 336
|
# tb_core.u_sdram32 : at time 20207.0 ns WRITE: Bank = 3 Row = 336, Col = 233, Data = b7dfaa6f
|
# tb_core.u_sdram32 : at time 20517.0 ns WRITE: Bank = 3 Row = 336, Col = 233, Data = b7dfaa6f
|
# Status: Burst-No: 0 Write Address: 00150fa4 WriteData: b7dfaa6f
|
# Status: Burst-No: 0 Write Address: 00150fa4 WriteData: b7dfaa6f
|
# tb_core.u_sdram32 : at time 20217.0 ns WRITE: Bank = 3 Row = 336, Col = 234, Data = 43460d86
|
# tb_core.u_sdram32 : at time 20527.0 ns WRITE: Bank = 3 Row = 336, Col = 234, Data = 43460d86
|
# Status: Burst-No: 1 Write Address: 00150fa4 WriteData: 43460d86
|
# Status: Burst-No: 1 Write Address: 00150fa4 WriteData: 43460d86
|
# tb_core.u_sdram32 : at time 20227.0 ns WRITE: Bank = 3 Row = 336, Col = 235, Data = 782321f0
|
# tb_core.u_sdram32 : at time 20537.0 ns WRITE: Bank = 3 Row = 336, Col = 235, Data = 782321f0
|
# Status: Burst-No: 2 Write Address: 00150fa4 WriteData: 782321f0
|
# Status: Burst-No: 2 Write Address: 00150fa4 WriteData: 782321f0
|
# tb_core.u_sdram32 : at time 20237.0 ns WRITE: Bank = 3 Row = 336, Col = 236, Data = 1c719738
|
# tb_core.u_sdram32 : at time 20547.0 ns WRITE: Bank = 3 Row = 336, Col = 236, Data = 1c719738
|
# Status: Burst-No: 3 Write Address: 00150fa4 WriteData: 1c719738
|
# Status: Burst-No: 3 Write Address: 00150fa4 WriteData: 1c719738
|
# tb_core.u_sdram32 : at time 20247.0 ns WRITE: Bank = 3 Row = 336, Col = 237, Data = 20769140
|
# tb_core.u_sdram32 : at time 20557.0 ns WRITE: Bank = 3 Row = 336, Col = 237, Data = 20769140
|
# Status: Burst-No: 4 Write Address: 00150fa4 WriteData: 20769140
|
# Status: Burst-No: 4 Write Address: 00150fa4 WriteData: 20769140
|
# tb_core.u_sdram32 : at time 20257.0 ns WRITE: Bank = 3 Row = 336, Col = 238, Data = 94097628
|
# tb_core.u_sdram32 : at time 20567.0 ns WRITE: Bank = 3 Row = 336, Col = 238, Data = 94097628
|
# Status: Burst-No: 5 Write Address: 00150fa4 WriteData: 94097628
|
# Status: Burst-No: 5 Write Address: 00150fa4 WriteData: 94097628
|
# tb_core.u_sdram32 : at time 20267.0 ns WRITE: Bank = 3 Row = 336, Col = 239, Data = 7b0da9f6
|
# tb_core.u_sdram32 : at time 20577.0 ns WRITE: Bank = 3 Row = 336, Col = 239, Data = 7b0da9f6
|
# Status: Burst-No: 6 Write Address: 00150fa4 WriteData: 7b0da9f6
|
# Status: Burst-No: 6 Write Address: 00150fa4 WriteData: 7b0da9f6
|
# tb_core.u_sdram32 : at time 20277.0 ns WRITE: Bank = 3 Row = 336, Col = 240, Data = e2bf1ac5
|
# tb_core.u_sdram32 : at time 20587.0 ns WRITE: Bank = 3 Row = 336, Col = 240, Data = e2bf1ac5
|
# Status: Burst-No: 7 Write Address: 00150fa4 WriteData: e2bf1ac5
|
# Status: Burst-No: 7 Write Address: 00150fa4 WriteData: e2bf1ac5
|
# tb_core.u_sdram32 : at time 20287.0 ns WRITE: Bank = 3 Row = 336, Col = 241, Data = 602831c0
|
# tb_core.u_sdram32 : at time 20597.0 ns WRITE: Bank = 3 Row = 336, Col = 241, Data = 602831c0
|
# Status: Burst-No: 8 Write Address: 00150fa4 WriteData: 602831c0
|
# Status: Burst-No: 8 Write Address: 00150fa4 WriteData: 602831c0
|
# tb_core.u_sdram32 : at time 20297.0 ns WRITE: Bank = 3 Row = 336, Col = 242, Data = 3a625f74
|
# tb_core.u_sdram32 : at time 20607.0 ns WRITE: Bank = 3 Row = 336, Col = 242, Data = 3a625f74
|
# Status: Burst-No: 9 Write Address: 00150fa4 WriteData: 3a625f74
|
# Status: Burst-No: 9 Write Address: 00150fa4 WriteData: 3a625f74
|
# tb_core.u_sdram32 : at time 20307.0 ns WRITE: Bank = 3 Row = 336, Col = 243, Data = 1cde7139
|
# tb_core.u_sdram32 : at time 20617.0 ns WRITE: Bank = 3 Row = 336, Col = 243, Data = 1cde7139
|
# Status: Burst-No: 10 Write Address: 00150fa4 WriteData: 1cde7139
|
# Status: Burst-No: 10 Write Address: 00150fa4 WriteData: 1cde7139
|
# tb_core.u_sdram32 : at time 20317.0 ns WRITE: Bank = 3 Row = 336, Col = 244, Data = d86a6ab0
|
# tb_core.u_sdram32 : at time 20627.0 ns WRITE: Bank = 3 Row = 336, Col = 244, Data = d86a6ab0
|
# Status: Burst-No: 11 Write Address: 00150fa4 WriteData: d86a6ab0
|
# Status: Burst-No: 11 Write Address: 00150fa4 WriteData: d86a6ab0
|
# tb_core.u_sdram32 : at time 20327.0 ns WRITE: Bank = 3 Row = 336, Col = 245, Data = 1e1c873c
|
# tb_core.u_sdram32 : at time 20637.0 ns WRITE: Bank = 3 Row = 336, Col = 245, Data = 1e1c873c
|
# Status: Burst-No: 12 Write Address: 00150fa4 WriteData: 1e1c873c
|
# Status: Burst-No: 12 Write Address: 00150fa4 WriteData: 1e1c873c
|
# tb_core.u_sdram32 : at time 20337.0 ns WRITE: Bank = 3 Row = 336, Col = 246, Data = 1521932a
|
# tb_core.u_sdram32 : at time 20647.0 ns WRITE: Bank = 3 Row = 336, Col = 246, Data = 1521932a
|
# Status: Burst-No: 13 Write Address: 00150fa4 WriteData: 1521932a
|
# Status: Burst-No: 13 Write Address: 00150fa4 WriteData: 1521932a
|
# tb_core.u_sdram32 : at time 20347.0 ns WRITE: Bank = 3 Row = 336, Col = 247, Data = 3124d362
|
# tb_core.u_sdram32 : at time 20657.0 ns WRITE: Bank = 3 Row = 336, Col = 247, Data = 3124d362
|
# Status: Burst-No: 14 Write Address: 00150fa4 WriteData: 3124d362
|
# Status: Burst-No: 14 Write Address: 00150fa4 WriteData: 3124d362
|
# tb_core.u_sdram32 : at time 20357.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 20667.0 ns BST : Burst Terminate
|
# Write Address: 00160fa8, Burst Size: 15
|
# Write Address: 00160fa8, Burst Size: 15
|
# tb_core.u_sdram32 : at time 20427.0 ns ACT : Bank = 3 Row = 352
|
# tb_core.u_sdram32 : at time 20737.0 ns ACT : Bank = 3 Row = 352
|
# tb_core.u_sdram32 : at time 20467.0 ns WRITE: Bank = 3 Row = 352, Col = 234, Data = 0aec3515
|
# tb_core.u_sdram32 : at time 20777.0 ns WRITE: Bank = 3 Row = 352, Col = 234, Data = 0aec3515
|
# Status: Burst-No: 0 Write Address: 00160fa8 WriteData: 0aec3515
|
# Status: Burst-No: 0 Write Address: 00160fa8 WriteData: 0aec3515
|
# tb_core.u_sdram32 : at time 20477.0 ns WRITE: Bank = 3 Row = 352, Col = 235, Data = f0b14ee1
|
# tb_core.u_sdram32 : at time 20787.0 ns WRITE: Bank = 3 Row = 352, Col = 235, Data = f0b14ee1
|
# Status: Burst-No: 1 Write Address: 00160fa8 WriteData: f0b14ee1
|
# Status: Burst-No: 1 Write Address: 00160fa8 WriteData: f0b14ee1
|
# tb_core.u_sdram32 : at time 20487.0 ns WRITE: Bank = 3 Row = 352, Col = 236, Data = 0be29d17
|
# tb_core.u_sdram32 : at time 20797.0 ns WRITE: Bank = 3 Row = 352, Col = 236, Data = 0be29d17
|
# Status: Burst-No: 2 Write Address: 00160fa8 WriteData: 0be29d17
|
# Status: Burst-No: 2 Write Address: 00160fa8 WriteData: 0be29d17
|
# tb_core.u_sdram32 : at time 20497.0 ns WRITE: Bank = 3 Row = 352, Col = 237, Data = a18bee43
|
# tb_core.u_sdram32 : at time 20807.0 ns WRITE: Bank = 3 Row = 352, Col = 237, Data = a18bee43
|
# Status: Burst-No: 3 Write Address: 00160fa8 WriteData: a18bee43
|
# Status: Burst-No: 3 Write Address: 00160fa8 WriteData: a18bee43
|
# tb_core.u_sdram32 : at time 20507.0 ns WRITE: Bank = 3 Row = 352, Col = 238, Data = 64b5e3c9
|
# tb_core.u_sdram32 : at time 20817.0 ns WRITE: Bank = 3 Row = 352, Col = 238, Data = 64b5e3c9
|
# Status: Burst-No: 4 Write Address: 00160fa8 WriteData: 64b5e3c9
|
# Status: Burst-No: 4 Write Address: 00160fa8 WriteData: 64b5e3c9
|
# tb_core.u_sdram32 : at time 20517.0 ns WRITE: Bank = 3 Row = 352, Col = 239, Data = c3360486
|
# tb_core.u_sdram32 : at time 20827.0 ns WRITE: Bank = 3 Row = 352, Col = 239, Data = c3360486
|
# Status: Burst-No: 5 Write Address: 00160fa8 WriteData: c3360486
|
# Status: Burst-No: 5 Write Address: 00160fa8 WriteData: c3360486
|
# tb_core.u_sdram32 : at time 20527.0 ns WRITE: Bank = 3 Row = 352, Col = 240, Data = 1297cb25
|
# tb_core.u_sdram32 : at time 20837.0 ns WRITE: Bank = 3 Row = 352, Col = 240, Data = 1297cb25
|
# Status: Burst-No: 6 Write Address: 00160fa8 WriteData: 1297cb25
|
# Status: Burst-No: 6 Write Address: 00160fa8 WriteData: 1297cb25
|
# tb_core.u_sdram32 : at time 20537.0 ns WRITE: Bank = 3 Row = 352, Col = 241, Data = 60f69dc1
|
# tb_core.u_sdram32 : at time 20847.0 ns WRITE: Bank = 3 Row = 352, Col = 241, Data = 60f69dc1
|
# Status: Burst-No: 7 Write Address: 00160fa8 WriteData: 60f69dc1
|
# Status: Burst-No: 7 Write Address: 00160fa8 WriteData: 60f69dc1
|
# tb_core.u_sdram32 : at time 20547.0 ns WRITE: Bank = 3 Row = 352, Col = 242, Data = c69da28d
|
# tb_core.u_sdram32 : at time 20857.0 ns WRITE: Bank = 3 Row = 352, Col = 242, Data = c69da28d
|
# Status: Burst-No: 8 Write Address: 00160fa8 WriteData: c69da28d
|
# Status: Burst-No: 8 Write Address: 00160fa8 WriteData: c69da28d
|
# tb_core.u_sdram32 : at time 20557.0 ns WRITE: Bank = 3 Row = 352, Col = 243, Data = ad67e25a
|
# tb_core.u_sdram32 : at time 20867.0 ns WRITE: Bank = 3 Row = 352, Col = 243, Data = ad67e25a
|
# Status: Burst-No: 9 Write Address: 00160fa8 WriteData: ad67e25a
|
# Status: Burst-No: 9 Write Address: 00160fa8 WriteData: ad67e25a
|
# tb_core.u_sdram32 : at time 20567.0 ns WRITE: Bank = 3 Row = 352, Col = 244, Data = 03d62707
|
# tb_core.u_sdram32 : at time 20877.0 ns WRITE: Bank = 3 Row = 352, Col = 244, Data = 03d62707
|
# Status: Burst-No: 10 Write Address: 00160fa8 WriteData: 03d62707
|
# Status: Burst-No: 10 Write Address: 00160fa8 WriteData: 03d62707
|
# tb_core.u_sdram32 : at time 20577.0 ns WRITE: Bank = 3 Row = 352, Col = 245, Data = 165b7b2c
|
# tb_core.u_sdram32 : at time 20887.0 ns WRITE: Bank = 3 Row = 352, Col = 245, Data = 165b7b2c
|
# Status: Burst-No: 11 Write Address: 00160fa8 WriteData: 165b7b2c
|
# Status: Burst-No: 11 Write Address: 00160fa8 WriteData: 165b7b2c
|
# tb_core.u_sdram32 : at time 20587.0 ns WRITE: Bank = 3 Row = 352, Col = 246, Data = 060a5d0c
|
# tb_core.u_sdram32 : at time 20897.0 ns WRITE: Bank = 3 Row = 352, Col = 246, Data = 060a5d0c
|
# Status: Burst-No: 12 Write Address: 00160fa8 WriteData: 060a5d0c
|
# Status: Burst-No: 12 Write Address: 00160fa8 WriteData: 060a5d0c
|
# tb_core.u_sdram32 : at time 20597.0 ns WRITE: Bank = 3 Row = 352, Col = 247, Data = b8ade671
|
# tb_core.u_sdram32 : at time 20907.0 ns WRITE: Bank = 3 Row = 352, Col = 247, Data = b8ade671
|
# Status: Burst-No: 13 Write Address: 00160fa8 WriteData: b8ade671
|
# Status: Burst-No: 13 Write Address: 00160fa8 WriteData: b8ade671
|
# tb_core.u_sdram32 : at time 20607.0 ns WRITE: Bank = 3 Row = 352, Col = 248, Data = 9de17c3b
|
# tb_core.u_sdram32 : at time 20917.0 ns WRITE: Bank = 3 Row = 352, Col = 248, Data = 9de17c3b
|
# Status: Burst-No: 14 Write Address: 00160fa8 WriteData: 9de17c3b
|
# Status: Burst-No: 14 Write Address: 00160fa8 WriteData: 9de17c3b
|
# tb_core.u_sdram32 : at time 20617.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 20927.0 ns BST : Burst Terminate
|
# Write Address: 00170fac, Burst Size: 15
|
# Write Address: 00170fac, Burst Size: 15
|
# tb_core.u_sdram32 : at time 20687.0 ns ACT : Bank = 3 Row = 368
|
# tb_core.u_sdram32 : at time 20997.0 ns ACT : Bank = 3 Row = 368
|
# tb_core.u_sdram32 : at time 20727.0 ns WRITE: Bank = 3 Row = 368, Col = 235, Data = 5b60e5b6
|
# tb_core.u_sdram32 : at time 21037.0 ns WRITE: Bank = 3 Row = 368, Col = 235, Data = 5b60e5b6
|
# Status: Burst-No: 0 Write Address: 00170fac WriteData: 5b60e5b6
|
# Status: Burst-No: 0 Write Address: 00170fac WriteData: 5b60e5b6
|
# tb_core.u_sdram32 : at time 20737.0 ns WRITE: Bank = 3 Row = 368, Col = 236, Data = fbdfc2f7
|
# tb_core.u_sdram32 : at time 21047.0 ns WRITE: Bank = 3 Row = 368, Col = 236, Data = fbdfc2f7
|
# Status: Burst-No: 1 Write Address: 00170fac WriteData: fbdfc2f7
|
# Status: Burst-No: 1 Write Address: 00170fac WriteData: fbdfc2f7
|
# tb_core.u_sdram32 : at time 20747.0 ns WRITE: Bank = 3 Row = 368, Col = 237, Data = cf14ce9e
|
# tb_core.u_sdram32 : at time 21057.0 ns WRITE: Bank = 3 Row = 368, Col = 237, Data = cf14ce9e
|
# Status: Burst-No: 2 Write Address: 00170fac WriteData: cf14ce9e
|
# Status: Burst-No: 2 Write Address: 00170fac WriteData: cf14ce9e
|
# tb_core.u_sdram32 : at time 20757.0 ns WRITE: Bank = 3 Row = 368, Col = 238, Data = ae78585c
|
# tb_core.u_sdram32 : at time 21067.0 ns WRITE: Bank = 3 Row = 368, Col = 238, Data = ae78585c
|
# Status: Burst-No: 3 Write Address: 00170fac WriteData: ae78585c
|
# Status: Burst-No: 3 Write Address: 00170fac WriteData: ae78585c
|
# tb_core.u_sdram32 : at time 20767.0 ns WRITE: Bank = 3 Row = 368, Col = 239, Data = 2ab8f755
|
# tb_core.u_sdram32 : at time 21077.0 ns WRITE: Bank = 3 Row = 368, Col = 239, Data = 2ab8f755
|
# Status: Burst-No: 4 Write Address: 00170fac WriteData: 2ab8f755
|
# Status: Burst-No: 4 Write Address: 00170fac WriteData: 2ab8f755
|
# tb_core.u_sdram32 : at time 20777.0 ns WRITE: Bank = 3 Row = 368, Col = 240, Data = 902a3a20
|
# tb_core.u_sdram32 : at time 21087.0 ns WRITE: Bank = 3 Row = 368, Col = 240, Data = 902a3a20
|
# Status: Burst-No: 5 Write Address: 00170fac WriteData: 902a3a20
|
# Status: Burst-No: 5 Write Address: 00170fac WriteData: 902a3a20
|
# tb_core.u_sdram32 : at time 20787.0 ns WRITE: Bank = 3 Row = 368, Col = 241, Data = d00b12a0
|
# tb_core.u_sdram32 : at time 21097.0 ns WRITE: Bank = 3 Row = 368, Col = 241, Data = d00b12a0
|
# Status: Burst-No: 6 Write Address: 00170fac WriteData: d00b12a0
|
# Status: Burst-No: 6 Write Address: 00170fac WriteData: d00b12a0
|
# tb_core.u_sdram32 : at time 20797.0 ns WRITE: Bank = 3 Row = 368, Col = 242, Data = 39600972
|
# tb_core.u_sdram32 : at time 21107.0 ns WRITE: Bank = 3 Row = 368, Col = 242, Data = 39600972
|
# Status: Burst-No: 7 Write Address: 00170fac WriteData: 39600972
|
# Status: Burst-No: 7 Write Address: 00170fac WriteData: 39600972
|
# tb_core.u_sdram32 : at time 20807.0 ns WRITE: Bank = 3 Row = 368, Col = 243, Data = da3d8cb4
|
# tb_core.u_sdram32 : at time 21117.0 ns WRITE: Bank = 3 Row = 368, Col = 243, Data = da3d8cb4
|
# Status: Burst-No: 8 Write Address: 00170fac WriteData: da3d8cb4
|
# Status: Burst-No: 8 Write Address: 00170fac WriteData: da3d8cb4
|
# tb_core.u_sdram32 : at time 20817.0 ns WRITE: Bank = 3 Row = 368, Col = 244, Data = 6e8af5dd
|
# tb_core.u_sdram32 : at time 21127.0 ns WRITE: Bank = 3 Row = 368, Col = 244, Data = 6e8af5dd
|
# Status: Burst-No: 9 Write Address: 00170fac WriteData: 6e8af5dd
|
# Status: Burst-No: 9 Write Address: 00170fac WriteData: 6e8af5dd
|
# tb_core.u_sdram32 : at time 20827.0 ns WRITE: Bank = 3 Row = 368, Col = 245, Data = 86dcf00d
|
# tb_core.u_sdram32 : at time 21137.0 ns WRITE: Bank = 3 Row = 368, Col = 245, Data = 86dcf00d
|
# Status: Burst-No: 10 Write Address: 00170fac WriteData: 86dcf00d
|
# Status: Burst-No: 10 Write Address: 00170fac WriteData: 86dcf00d
|
# tb_core.u_sdram32 : at time 20837.0 ns WRITE: Bank = 3 Row = 368, Col = 246, Data = 25b0994b
|
# tb_core.u_sdram32 : at time 21147.0 ns WRITE: Bank = 3 Row = 368, Col = 246, Data = 25b0994b
|
# Status: Burst-No: 11 Write Address: 00170fac WriteData: 25b0994b
|
# Status: Burst-No: 11 Write Address: 00170fac WriteData: 25b0994b
|
# tb_core.u_sdram32 : at time 20847.0 ns WRITE: Bank = 3 Row = 368, Col = 247, Data = bccc4279
|
# tb_core.u_sdram32 : at time 21157.0 ns WRITE: Bank = 3 Row = 368, Col = 247, Data = bccc4279
|
# Status: Burst-No: 12 Write Address: 00170fac WriteData: bccc4279
|
# Status: Burst-No: 12 Write Address: 00170fac WriteData: bccc4279
|
# tb_core.u_sdram32 : at time 20857.0 ns WRITE: Bank = 3 Row = 368, Col = 248, Data = cf63da9e
|
# tb_core.u_sdram32 : at time 21167.0 ns WRITE: Bank = 3 Row = 368, Col = 248, Data = cf63da9e
|
# Status: Burst-No: 13 Write Address: 00170fac WriteData: cf63da9e
|
# Status: Burst-No: 13 Write Address: 00170fac WriteData: cf63da9e
|
# tb_core.u_sdram32 : at time 20867.0 ns WRITE: Bank = 3 Row = 368, Col = 249, Data = fef064fd
|
# tb_core.u_sdram32 : at time 21177.0 ns WRITE: Bank = 3 Row = 368, Col = 249, Data = fef064fd
|
# Status: Burst-No: 14 Write Address: 00170fac WriteData: fef064fd
|
# Status: Burst-No: 14 Write Address: 00170fac WriteData: fef064fd
|
# tb_core.u_sdram32 : at time 20877.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 21187.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 20937.0 ns ACT : Bank = 3 Row = 0
|
# tb_core.u_sdram32 : at time 21257.0 ns ACT : Bank = 3 Row = 0
|
# tb_core.u_sdram32 : at time 20947.0 ns ACT : Bank = 0 Row = 1
|
# tb_core.u_sdram32 : at time 21323.0 ns READ : Bank = 3 Row = 0, Col = 252, Data = 462df78c
|
# tb_core.u_sdram32 : at time 20947.0 ns ERROR: tRRD violation during Activate bank = 0
|
# tb_core.u_sdram32 : at time 21333.0 ns READ : Bank = 3 Row = 0, Col = 253, Data = 7cfde9f9
|
# tb_core.u_sdram32 : at time 21003.0 ns READ : Bank = 3 Row = 0, Col = 252, Data = 462df78c
|
|
# tb_core.u_sdram32 : at time 21013.0 ns READ : Bank = 3 Row = 0, Col = 253, Data = 7cfde9f9
|
|
# READ STATUS: Burst-No: 0 Addr: 00000ff0 Rxd: 462df78c
|
# READ STATUS: Burst-No: 0 Addr: 00000ff0 Rxd: 462df78c
|
# tb_core.u_sdram32 : at time 21017.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 21337.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 21023.0 ns READ : Bank = 3 Row = 0, Col = 254, Data = e33724c6
|
# tb_core.u_sdram32 : at time 21343.0 ns READ : Bank = 3 Row = 0, Col = 254, Data = e33724c6
|
|
# tb_core.u_sdram32 : at time 21347.0 ns ACT : Bank = 0 Row = 1
|
# READ STATUS: Burst-No: 1 Addr: 00000ff2 Rxd: 7cfde9f9
|
# READ STATUS: Burst-No: 1 Addr: 00000ff2 Rxd: 7cfde9f9
|
# tb_core.u_sdram32 : at time 21033.0 ns READ : Bank = 3 Row = 0, Col = 255, Data = e2f784c5
|
# tb_core.u_sdram32 : at time 21353.0 ns READ : Bank = 3 Row = 0, Col = 255, Data = e2f784c5
|
# READ STATUS: Burst-No: 2 Addr: 00000ff4 Rxd: e33724c6
|
# READ STATUS: Burst-No: 2 Addr: 00000ff4 Rxd: e33724c6
|
# READ STATUS: Burst-No: 3 Addr: 00000ff6 Rxd: e2f784c5
|
# READ STATUS: Burst-No: 3 Addr: 00000ff6 Rxd: e2f784c5
|
# tb_core.u_sdram32 : at time 21053.0 ns READ : Bank = 0 Row = 1, Col = 0, Data = d513d2aa
|
# tb_core.u_sdram32 : at time 21413.0 ns READ : Bank = 0 Row = 1, Col = 0, Data = d513d2aa
|
# tb_core.u_sdram32 : at time 21063.0 ns READ : Bank = 0 Row = 1, Col = 1, Data = 72aff7e5
|
# tb_core.u_sdram32 : at time 21423.0 ns READ : Bank = 0 Row = 1, Col = 1, Data = 72aff7e5
|
# READ STATUS: Burst-No: 4 Addr: 00000ff8 Rxd: d513d2aa
|
# READ STATUS: Burst-No: 4 Addr: 00000ff8 Rxd: d513d2aa
|
# tb_core.u_sdram32 : at time 21067.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 21427.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 21073.0 ns READ : Bank = 0 Row = 1, Col = 2, Data = bbd27277
|
# tb_core.u_sdram32 : at time 21433.0 ns READ : Bank = 0 Row = 1, Col = 2, Data = bbd27277
|
# READ STATUS: Burst-No: 5 Addr: 00000ffa Rxd: 72aff7e5
|
# READ STATUS: Burst-No: 5 Addr: 00000ffa Rxd: 72aff7e5
|
# tb_core.u_sdram32 : at time 21083.0 ns READ : Bank = 0 Row = 1, Col = 3, Data = 8932d612
|
# tb_core.u_sdram32 : at time 21443.0 ns READ : Bank = 0 Row = 1, Col = 3, Data = 8932d612
|
# READ STATUS: Burst-No: 6 Addr: 00000ffc Rxd: bbd27277
|
# READ STATUS: Burst-No: 6 Addr: 00000ffc Rxd: bbd27277
|
# READ STATUS: Burst-No: 7 Addr: 00000ffe Rxd: 8932d612
|
# READ STATUS: Burst-No: 7 Addr: 00000ffe Rxd: 8932d612
|
# tb_core.u_sdram32 : at time 21177.0 ns ACT : Bank = 3 Row = 16
|
# tb_core.u_sdram32 : at time 21547.0 ns ACT : Bank = 3 Row = 16
|
# tb_core.u_sdram32 : at time 21187.0 ns ACT : Bank = 0 Row = 17
|
# tb_core.u_sdram32 : at time 21613.0 ns READ : Bank = 3 Row = 16, Col = 253, Data = 47ecdb8f
|
# tb_core.u_sdram32 : at time 21187.0 ns ERROR: tRRD violation during Activate bank = 0
|
# tb_core.u_sdram32 : at time 21617.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 21243.0 ns READ : Bank = 3 Row = 16, Col = 253, Data = 47ecdb8f
|
# tb_core.u_sdram32 : at time 21623.0 ns READ : Bank = 3 Row = 16, Col = 254, Data = 793069f2
|
# tb_core.u_sdram32 : at time 21247.0 ns BST : Burst Terminate
|
|
# tb_core.u_sdram32 : at time 21253.0 ns READ : Bank = 3 Row = 16, Col = 254, Data = 793069f2
|
|
# READ STATUS: Burst-No: 0 Addr: 00010ff4 Rxd: 47ecdb8f
|
# READ STATUS: Burst-No: 0 Addr: 00010ff4 Rxd: 47ecdb8f
|
# tb_core.u_sdram32 : at time 21263.0 ns READ : Bank = 3 Row = 16, Col = 255, Data = e77696ce
|
# tb_core.u_sdram32 : at time 21633.0 ns READ : Bank = 3 Row = 16, Col = 255, Data = e77696ce
|
|
# tb_core.u_sdram32 : at time 21637.0 ns ACT : Bank = 0 Row = 17
|
# READ STATUS: Burst-No: 1 Addr: 00010ff6 Rxd: 793069f2
|
# READ STATUS: Burst-No: 1 Addr: 00010ff6 Rxd: 793069f2
|
# READ STATUS: Burst-No: 2 Addr: 00010ff8 Rxd: e77696ce
|
# READ STATUS: Burst-No: 2 Addr: 00010ff8 Rxd: e77696ce
|
# tb_core.u_sdram32 : at time 21283.0 ns READ : Bank = 0 Row = 17, Col = 0, Data = f4007ae8
|
# tb_core.u_sdram32 : at time 21703.0 ns READ : Bank = 0 Row = 17, Col = 0, Data = f4007ae8
|
# tb_core.u_sdram32 : at time 21287.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 21713.0 ns READ : Bank = 0 Row = 17, Col = 1, Data = e2ca4ec5
|
# tb_core.u_sdram32 : at time 21293.0 ns READ : Bank = 0 Row = 17, Col = 1, Data = e2ca4ec5
|
|
# READ STATUS: Burst-No: 3 Addr: 00010ffa Rxd: f4007ae8
|
# READ STATUS: Burst-No: 3 Addr: 00010ffa Rxd: f4007ae8
|
# tb_core.u_sdram32 : at time 21303.0 ns READ : Bank = 0 Row = 17, Col = 2, Data = 2e58495c
|
# tb_core.u_sdram32 : at time 21723.0 ns READ : Bank = 0 Row = 17, Col = 2, Data = 2e58495c
|
# READ STATUS: Burst-No: 4 Addr: 00010ffc Rxd: e2ca4ec5
|
# READ STATUS: Burst-No: 4 Addr: 00010ffc Rxd: e2ca4ec5
|
|
# tb_core.u_sdram32 : at time 21733.0 ns READ : Bank = 0 Row = 17, Col = 3, Data = de8e28bd
|
# READ STATUS: Burst-No: 5 Addr: 00010ffe Rxd: 2e58495c
|
# READ STATUS: Burst-No: 5 Addr: 00010ffe Rxd: 2e58495c
|
# tb_core.u_sdram32 : at time 21323.0 ns READ : Bank = 0 Row = 17, Col = 3, Data = de8e28bd
|
# tb_core.u_sdram32 : at time 21743.0 ns READ : Bank = 0 Row = 17, Col = 4, Data = 96ab582d
|
# tb_core.u_sdram32 : at time 21327.0 ns BST : Burst Terminate
|
|
# tb_core.u_sdram32 : at time 21333.0 ns READ : Bank = 0 Row = 17, Col = 4, Data = 96ab582d
|
|
# READ STATUS: Burst-No: 6 Addr: 00011000 Rxd: de8e28bd
|
# READ STATUS: Burst-No: 6 Addr: 00011000 Rxd: de8e28bd
|
# tb_core.u_sdram32 : at time 21343.0 ns READ : Bank = 0 Row = 17, Col = 5, Data = b2a72665
|
# tb_core.u_sdram32 : at time 21753.0 ns READ : Bank = 0 Row = 17, Col = 5, Data = b2a72665
|
# READ STATUS: Burst-No: 7 Addr: 00011002 Rxd: 96ab582d
|
# READ STATUS: Burst-No: 7 Addr: 00011002 Rxd: 96ab582d
|
|
# tb_core.u_sdram32 : at time 21763.0 ns READ : Bank = 0 Row = 17, Col = 6, Data = b1ef6263
|
# READ STATUS: Burst-No: 8 Addr: 00011004 Rxd: b2a72665
|
# READ STATUS: Burst-No: 8 Addr: 00011004 Rxd: b2a72665
|
# tb_core.u_sdram32 : at time 21363.0 ns READ : Bank = 0 Row = 17, Col = 6, Data = b1ef6263
|
# tb_core.u_sdram32 : at time 21773.0 ns READ : Bank = 0 Row = 17, Col = 7, Data = 0573870a
|
# tb_core.u_sdram32 : at time 21367.0 ns BST : Burst Terminate
|
|
# tb_core.u_sdram32 : at time 21373.0 ns READ : Bank = 0 Row = 17, Col = 7, Data = 0573870a
|
|
# READ STATUS: Burst-No: 9 Addr: 00011006 Rxd: b1ef6263
|
# READ STATUS: Burst-No: 9 Addr: 00011006 Rxd: b1ef6263
|
# tb_core.u_sdram32 : at time 21383.0 ns READ : Bank = 0 Row = 17, Col = 8, Data = c03b2280
|
# tb_core.u_sdram32 : at time 21783.0 ns READ : Bank = 0 Row = 17, Col = 8, Data = c03b2280
|
# READ STATUS: Burst-No: 10 Addr: 00011008 Rxd: 0573870a
|
# READ STATUS: Burst-No: 10 Addr: 00011008 Rxd: 0573870a
|
|
# tb_core.u_sdram32 : at time 21793.0 ns READ : Bank = 0 Row = 17, Col = 9, Data = 10642120
|
|
# tb_core.u_sdram32 : at time 21797.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 11 Addr: 0001100a Rxd: c03b2280
|
# READ STATUS: Burst-No: 11 Addr: 0001100a Rxd: c03b2280
|
# tb_core.u_sdram32 : at time 21403.0 ns READ : Bank = 0 Row = 17, Col = 9, Data = 10642120
|
# tb_core.u_sdram32 : at time 21803.0 ns READ : Bank = 0 Row = 17, Col = 10, Data = 557845aa
|
# tb_core.u_sdram32 : at time 21407.0 ns BST : Burst Terminate
|
|
# tb_core.u_sdram32 : at time 21413.0 ns READ : Bank = 0 Row = 17, Col = 10, Data = 557845aa
|
|
# READ STATUS: Burst-No: 12 Addr: 0001100c Rxd: 10642120
|
# READ STATUS: Burst-No: 12 Addr: 0001100c Rxd: 10642120
|
# tb_core.u_sdram32 : at time 21423.0 ns READ : Bank = 0 Row = 17, Col = 11, Data = cecccc9d
|
# tb_core.u_sdram32 : at time 21813.0 ns READ : Bank = 0 Row = 17, Col = 11, Data = cecccc9d
|
# READ STATUS: Burst-No: 13 Addr: 0001100e Rxd: 557845aa
|
# READ STATUS: Burst-No: 13 Addr: 0001100e Rxd: 557845aa
|
# READ STATUS: Burst-No: 14 Addr: 00011010 Rxd: cecccc9d
|
# READ STATUS: Burst-No: 14 Addr: 00011010 Rxd: cecccc9d
|
# tb_core.u_sdram32 : at time 21517.0 ns ACT : Bank = 3 Row = 32
|
# tb_core.u_sdram32 : at time 21917.0 ns ACT : Bank = 3 Row = 32
|
# tb_core.u_sdram32 : at time 21527.0 ns ACT : Bank = 0 Row = 33
|
# tb_core.u_sdram32 : at time 21977.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 21527.0 ns ERROR: tRRD violation during Activate bank = 0
|
# tb_core.u_sdram32 : at time 21983.0 ns READ : Bank = 3 Row = 32, Col = 254, Data = cb203e96
|
# tb_core.u_sdram32 : at time 21577.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 21993.0 ns READ : Bank = 3 Row = 32, Col = 255, Data = 8983b813
|
# tb_core.u_sdram32 : at time 21583.0 ns READ : Bank = 3 Row = 32, Col = 254, Data = cb203e96
|
|
# tb_core.u_sdram32 : at time 21593.0 ns READ : Bank = 3 Row = 32, Col = 255, Data = 8983b813
|
|
# READ STATUS: Burst-No: 0 Addr: 00020ff8 Rxd: cb203e96
|
# READ STATUS: Burst-No: 0 Addr: 00020ff8 Rxd: cb203e96
|
# tb_core.u_sdram32 : at time 21607.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 22007.0 ns ACT : Bank = 0 Row = 33
|
# READ STATUS: Burst-No: 1 Addr: 00020ffa Rxd: 8983b813
|
# READ STATUS: Burst-No: 1 Addr: 00020ffa Rxd: 8983b813
|
# tb_core.u_sdram32 : at time 21613.0 ns READ : Bank = 0 Row = 33, Col = 0, Data = 86bc380d
|
# tb_core.u_sdram32 : at time 22073.0 ns READ : Bank = 0 Row = 33, Col = 0, Data = 86bc380d
|
# tb_core.u_sdram32 : at time 21623.0 ns READ : Bank = 0 Row = 33, Col = 1, Data = a9a7d653
|
# tb_core.u_sdram32 : at time 22083.0 ns READ : Bank = 0 Row = 33, Col = 1, Data = a9a7d653
|
# READ STATUS: Burst-No: 2 Addr: 00020ffc Rxd: 86bc380d
|
# READ STATUS: Burst-No: 2 Addr: 00020ffc Rxd: 86bc380d
|
# tb_core.u_sdram32 : at time 21637.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 22093.0 ns READ : Bank = 0 Row = 33, Col = 2, Data = 359fdd6b
|
# READ STATUS: Burst-No: 3 Addr: 00020ffe Rxd: a9a7d653
|
# READ STATUS: Burst-No: 3 Addr: 00020ffe Rxd: a9a7d653
|
# tb_core.u_sdram32 : at time 21643.0 ns READ : Bank = 0 Row = 33, Col = 2, Data = 359fdd6b
|
# tb_core.u_sdram32 : at time 22103.0 ns READ : Bank = 0 Row = 33, Col = 3, Data = eaa62ad5
|
# tb_core.u_sdram32 : at time 21653.0 ns READ : Bank = 0 Row = 33, Col = 3, Data = eaa62ad5
|
|
# READ STATUS: Burst-No: 4 Addr: 00021000 Rxd: 359fdd6b
|
# READ STATUS: Burst-No: 4 Addr: 00021000 Rxd: 359fdd6b
|
# tb_core.u_sdram32 : at time 21667.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 22113.0 ns READ : Bank = 0 Row = 33, Col = 4, Data = 81174a02
|
# READ STATUS: Burst-No: 5 Addr: 00021002 Rxd: eaa62ad5
|
# READ STATUS: Burst-No: 5 Addr: 00021002 Rxd: eaa62ad5
|
# tb_core.u_sdram32 : at time 21673.0 ns READ : Bank = 0 Row = 33, Col = 4, Data = 81174a02
|
# tb_core.u_sdram32 : at time 22123.0 ns READ : Bank = 0 Row = 33, Col = 5, Data = d7563eae
|
# tb_core.u_sdram32 : at time 21683.0 ns READ : Bank = 0 Row = 33, Col = 5, Data = d7563eae
|
|
# READ STATUS: Burst-No: 6 Addr: 00021004 Rxd: 81174a02
|
# READ STATUS: Burst-No: 6 Addr: 00021004 Rxd: 81174a02
|
# tb_core.u_sdram32 : at time 21697.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 22133.0 ns READ : Bank = 0 Row = 33, Col = 6, Data = 0effe91d
|
# READ STATUS: Burst-No: 7 Addr: 00021006 Rxd: d7563eae
|
# READ STATUS: Burst-No: 7 Addr: 00021006 Rxd: d7563eae
|
# tb_core.u_sdram32 : at time 21703.0 ns READ : Bank = 0 Row = 33, Col = 6, Data = 0effe91d
|
# tb_core.u_sdram32 : at time 22143.0 ns READ : Bank = 0 Row = 33, Col = 7, Data = e7c572cf
|
# tb_core.u_sdram32 : at time 21713.0 ns READ : Bank = 0 Row = 33, Col = 7, Data = e7c572cf
|
|
# READ STATUS: Burst-No: 8 Addr: 00021008 Rxd: 0effe91d
|
# READ STATUS: Burst-No: 8 Addr: 00021008 Rxd: 0effe91d
|
# tb_core.u_sdram32 : at time 21727.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 22153.0 ns READ : Bank = 0 Row = 33, Col = 8, Data = 11844923
|
# READ STATUS: Burst-No: 9 Addr: 0002100a Rxd: e7c572cf
|
# READ STATUS: Burst-No: 9 Addr: 0002100a Rxd: e7c572cf
|
# tb_core.u_sdram32 : at time 21733.0 ns READ : Bank = 0 Row = 33, Col = 8, Data = 11844923
|
# tb_core.u_sdram32 : at time 22163.0 ns READ : Bank = 0 Row = 33, Col = 9, Data = 0509650a
|
# tb_core.u_sdram32 : at time 21743.0 ns READ : Bank = 0 Row = 33, Col = 9, Data = 0509650a
|
|
# READ STATUS: Burst-No: 10 Addr: 0002100c Rxd: 11844923
|
# READ STATUS: Burst-No: 10 Addr: 0002100c Rxd: 11844923
|
# tb_core.u_sdram32 : at time 21757.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 22173.0 ns READ : Bank = 0 Row = 33, Col = 10, Data = e5730aca
|
|
# tb_core.u_sdram32 : at time 22177.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 11 Addr: 0002100e Rxd: 0509650a
|
# READ STATUS: Burst-No: 11 Addr: 0002100e Rxd: 0509650a
|
# tb_core.u_sdram32 : at time 21763.0 ns READ : Bank = 0 Row = 33, Col = 10, Data = e5730aca
|
# tb_core.u_sdram32 : at time 22183.0 ns READ : Bank = 0 Row = 33, Col = 11, Data = 9e314c3c
|
# tb_core.u_sdram32 : at time 21773.0 ns READ : Bank = 0 Row = 33, Col = 11, Data = 9e314c3c
|
|
# READ STATUS: Burst-No: 12 Addr: 00021010 Rxd: e5730aca
|
# READ STATUS: Burst-No: 12 Addr: 00021010 Rxd: e5730aca
|
# tb_core.u_sdram32 : at time 21777.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 22193.0 ns READ : Bank = 0 Row = 33, Col = 12, Data = 7968bdf2
|
# READ STATUS: Burst-No: 13 Addr: 00021012 Rxd: 9e314c3c
|
# READ STATUS: Burst-No: 13 Addr: 00021012 Rxd: 9e314c3c
|
# tb_core.u_sdram32 : at time 21793.0 ns READ : Bank = 0 Row = 33, Col = 12, Data = 7968bdf2
|
|
# READ STATUS: Burst-No: 14 Addr: 00021014 Rxd: 7968bdf2
|
# READ STATUS: Burst-No: 14 Addr: 00021014 Rxd: 7968bdf2
|
# tb_core.u_sdram32 : at time 21887.0 ns ACT : Bank = 3 Row = 48
|
# tb_core.u_sdram32 : at time 22297.0 ns ACT : Bank = 3 Row = 48
|
# tb_core.u_sdram32 : at time 21897.0 ns ACT : Bank = 0 Row = 49
|
# tb_core.u_sdram32 : at time 22347.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 21897.0 ns ERROR: tRRD violation during Activate bank = 0
|
# tb_core.u_sdram32 : at time 22363.0 ns READ : Bank = 3 Row = 48, Col = 255, Data = 452e618a
|
# tb_core.u_sdram32 : at time 21937.0 ns BST : Burst Terminate
|
|
# tb_core.u_sdram32 : at time 21953.0 ns READ : Bank = 3 Row = 48, Col = 255, Data = 452e618a
|
|
# tb_core.u_sdram32 : at time 21957.0 ns BST : Burst Terminate
|
|
# READ STATUS: Burst-No: 0 Addr: 00030ffc Rxd: 452e618a
|
# READ STATUS: Burst-No: 0 Addr: 00030ffc Rxd: 452e618a
|
# tb_core.u_sdram32 : at time 21973.0 ns READ : Bank = 0 Row = 49, Col = 0, Data = 20c4b341
|
# tb_core.u_sdram32 : at time 22407.0 ns ACT : Bank = 0 Row = 49
|
# tb_core.u_sdram32 : at time 21977.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 22473.0 ns READ : Bank = 0 Row = 49, Col = 0, Data = 20c4b341
|
|
# tb_core.u_sdram32 : at time 22483.0 ns READ : Bank = 0 Row = 49, Col = 1, Data = ec4b34d8
|
# READ STATUS: Burst-No: 1 Addr: 00030ffe Rxd: 20c4b341
|
# READ STATUS: Burst-No: 1 Addr: 00030ffe Rxd: 20c4b341
|
# tb_core.u_sdram32 : at time 21993.0 ns READ : Bank = 0 Row = 49, Col = 1, Data = ec4b34d8
|
# tb_core.u_sdram32 : at time 22493.0 ns READ : Bank = 0 Row = 49, Col = 2, Data = 3c20f378
|
# tb_core.u_sdram32 : at time 21997.0 ns BST : Burst Terminate
|
|
# READ STATUS: Burst-No: 2 Addr: 00031000 Rxd: ec4b34d8
|
# READ STATUS: Burst-No: 2 Addr: 00031000 Rxd: ec4b34d8
|
# tb_core.u_sdram32 : at time 22013.0 ns READ : Bank = 0 Row = 49, Col = 2, Data = 3c20f378
|
# tb_core.u_sdram32 : at time 22503.0 ns READ : Bank = 0 Row = 49, Col = 3, Data = c48a1289
|
# tb_core.u_sdram32 : at time 22017.0 ns BST : Burst Terminate
|
|
# READ STATUS: Burst-No: 3 Addr: 00031002 Rxd: 3c20f378
|
# READ STATUS: Burst-No: 3 Addr: 00031002 Rxd: 3c20f378
|
# tb_core.u_sdram32 : at time 22033.0 ns READ : Bank = 0 Row = 49, Col = 3, Data = c48a1289
|
# tb_core.u_sdram32 : at time 22513.0 ns READ : Bank = 0 Row = 49, Col = 4, Data = 75c50deb
|
# tb_core.u_sdram32 : at time 22037.0 ns BST : Burst Terminate
|
|
# READ STATUS: Burst-No: 4 Addr: 00031004 Rxd: c48a1289
|
# READ STATUS: Burst-No: 4 Addr: 00031004 Rxd: c48a1289
|
# tb_core.u_sdram32 : at time 22053.0 ns READ : Bank = 0 Row = 49, Col = 4, Data = 75c50deb
|
# tb_core.u_sdram32 : at time 22523.0 ns READ : Bank = 0 Row = 49, Col = 5, Data = 5b0265b6
|
# tb_core.u_sdram32 : at time 22057.0 ns BST : Burst Terminate
|
|
# READ STATUS: Burst-No: 5 Addr: 00031006 Rxd: 75c50deb
|
# READ STATUS: Burst-No: 5 Addr: 00031006 Rxd: 75c50deb
|
# tb_core.u_sdram32 : at time 22073.0 ns READ : Bank = 0 Row = 49, Col = 5, Data = 5b0265b6
|
# tb_core.u_sdram32 : at time 22533.0 ns READ : Bank = 0 Row = 49, Col = 6, Data = 634bf9c6
|
# tb_core.u_sdram32 : at time 22077.0 ns BST : Burst Terminate
|
|
# READ STATUS: Burst-No: 6 Addr: 00031008 Rxd: 5b0265b6
|
# READ STATUS: Burst-No: 6 Addr: 00031008 Rxd: 5b0265b6
|
# tb_core.u_sdram32 : at time 22093.0 ns READ : Bank = 0 Row = 49, Col = 6, Data = 634bf9c6
|
# tb_core.u_sdram32 : at time 22543.0 ns READ : Bank = 0 Row = 49, Col = 7, Data = 571513ae
|
# tb_core.u_sdram32 : at time 22097.0 ns BST : Burst Terminate
|
|
# READ STATUS: Burst-No: 7 Addr: 0003100a Rxd: 634bf9c6
|
# READ STATUS: Burst-No: 7 Addr: 0003100a Rxd: 634bf9c6
|
# tb_core.u_sdram32 : at time 22113.0 ns READ : Bank = 0 Row = 49, Col = 7, Data = 571513ae
|
# tb_core.u_sdram32 : at time 22553.0 ns READ : Bank = 0 Row = 49, Col = 8, Data = de7502bc
|
# tb_core.u_sdram32 : at time 22117.0 ns BST : Burst Terminate
|
|
# READ STATUS: Burst-No: 8 Addr: 0003100c Rxd: 571513ae
|
# READ STATUS: Burst-No: 8 Addr: 0003100c Rxd: 571513ae
|
# tb_core.u_sdram32 : at time 22133.0 ns READ : Bank = 0 Row = 49, Col = 8, Data = de7502bc
|
# tb_core.u_sdram32 : at time 22563.0 ns READ : Bank = 0 Row = 49, Col = 9, Data = 150fdd2a
|
# tb_core.u_sdram32 : at time 22137.0 ns BST : Burst Terminate
|
|
# READ STATUS: Burst-No: 9 Addr: 0003100e Rxd: de7502bc
|
# READ STATUS: Burst-No: 9 Addr: 0003100e Rxd: de7502bc
|
# tb_core.u_sdram32 : at time 22153.0 ns READ : Bank = 0 Row = 49, Col = 9, Data = 150fdd2a
|
# tb_core.u_sdram32 : at time 22573.0 ns READ : Bank = 0 Row = 49, Col = 10, Data = 85d79a0b
|
# tb_core.u_sdram32 : at time 22157.0 ns BST : Burst Terminate
|
|
# READ STATUS: Burst-No: 10 Addr: 00031010 Rxd: 150fdd2a
|
# READ STATUS: Burst-No: 10 Addr: 00031010 Rxd: 150fdd2a
|
# tb_core.u_sdram32 : at time 22173.0 ns READ : Bank = 0 Row = 49, Col = 10, Data = 85d79a0b
|
# tb_core.u_sdram32 : at time 22583.0 ns READ : Bank = 0 Row = 49, Col = 11, Data = b897be71
|
# tb_core.u_sdram32 : at time 22177.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 22587.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 11 Addr: 00031012 Rxd: 85d79a0b
|
# READ STATUS: Burst-No: 11 Addr: 00031012 Rxd: 85d79a0b
|
# tb_core.u_sdram32 : at time 22193.0 ns READ : Bank = 0 Row = 49, Col = 11, Data = b897be71
|
# tb_core.u_sdram32 : at time 22593.0 ns READ : Bank = 0 Row = 49, Col = 12, Data = 42f24185
|
# tb_core.u_sdram32 : at time 22197.0 ns BST : Burst Terminate
|
|
# READ STATUS: Burst-No: 12 Addr: 00031014 Rxd: b897be71
|
# READ STATUS: Burst-No: 12 Addr: 00031014 Rxd: b897be71
|
# tb_core.u_sdram32 : at time 22213.0 ns READ : Bank = 0 Row = 49, Col = 12, Data = 42f24185
|
# tb_core.u_sdram32 : at time 22603.0 ns READ : Bank = 0 Row = 49, Col = 13, Data = 27f2554f
|
# tb_core.u_sdram32 : at time 22217.0 ns BST : Burst Terminate
|
|
# READ STATUS: Burst-No: 13 Addr: 00031016 Rxd: 42f24185
|
# READ STATUS: Burst-No: 13 Addr: 00031016 Rxd: 42f24185
|
# tb_core.u_sdram32 : at time 22233.0 ns READ : Bank = 0 Row = 49, Col = 13, Data = 27f2554f
|
|
# READ STATUS: Burst-No: 14 Addr: 00031018 Rxd: 27f2554f
|
# READ STATUS: Burst-No: 14 Addr: 00031018 Rxd: 27f2554f
|
# tb_core.u_sdram32 : at time 22327.0 ns ACT : Bank = 3 Row = 64
|
# tb_core.u_sdram32 : at time 22707.0 ns ACT : Bank = 3 Row = 64
|
# tb_core.u_sdram32 : at time 22337.0 ns ACT : Bank = 0 Row = 65
|
# tb_core.u_sdram32 : at time 22773.0 ns READ : Bank = 3 Row = 64, Col = 248, Data = 9dcc603b
|
# tb_core.u_sdram32 : at time 22337.0 ns ERROR: tRRD violation during Activate bank = 0
|
# tb_core.u_sdram32 : at time 22783.0 ns READ : Bank = 3 Row = 64, Col = 249, Data = 1d06333a
|
# tb_core.u_sdram32 : at time 22393.0 ns READ : Bank = 3 Row = 64, Col = 248, Data = 9dcc603b
|
|
# tb_core.u_sdram32 : at time 22403.0 ns READ : Bank = 3 Row = 64, Col = 249, Data = 1d06333a
|
|
# READ STATUS: Burst-No: 0 Addr: 00040fe0 Rxd: 9dcc603b
|
# READ STATUS: Burst-No: 0 Addr: 00040fe0 Rxd: 9dcc603b
|
# tb_core.u_sdram32 : at time 22413.0 ns READ : Bank = 3 Row = 64, Col = 250, Data = bf23327e
|
# tb_core.u_sdram32 : at time 22793.0 ns READ : Bank = 3 Row = 64, Col = 250, Data = bf23327e
|
|
# tb_core.u_sdram32 : at time 22797.0 ns ACT : Bank = 0 Row = 65
|
# READ STATUS: Burst-No: 1 Addr: 00040fe2 Rxd: 1d06333a
|
# READ STATUS: Burst-No: 1 Addr: 00040fe2 Rxd: 1d06333a
|
# tb_core.u_sdram32 : at time 22423.0 ns READ : Bank = 3 Row = 64, Col = 251, Data = 0aaa4b15
|
# tb_core.u_sdram32 : at time 22803.0 ns READ : Bank = 3 Row = 64, Col = 251, Data = 0aaa4b15
|
# READ STATUS: Burst-No: 2 Addr: 00040fe4 Rxd: bf23327e
|
# READ STATUS: Burst-No: 2 Addr: 00040fe4 Rxd: bf23327e
|
# tb_core.u_sdram32 : at time 22433.0 ns READ : Bank = 3 Row = 64, Col = 252, Data = 78d99bf1
|
# tb_core.u_sdram32 : at time 22813.0 ns READ : Bank = 3 Row = 64, Col = 252, Data = 78d99bf1
|
# READ STATUS: Burst-No: 3 Addr: 00040fe6 Rxd: 0aaa4b15
|
# READ STATUS: Burst-No: 3 Addr: 00040fe6 Rxd: 0aaa4b15
|
# tb_core.u_sdram32 : at time 22443.0 ns READ : Bank = 3 Row = 64, Col = 253, Data = 6c9c4bd9
|
# tb_core.u_sdram32 : at time 22823.0 ns READ : Bank = 3 Row = 64, Col = 253, Data = 6c9c4bd9
|
# tb_core.u_sdram32 : at time 22447.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 22827.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 4 Addr: 00040fe8 Rxd: 78d99bf1
|
# READ STATUS: Burst-No: 4 Addr: 00040fe8 Rxd: 78d99bf1
|
# tb_core.u_sdram32 : at time 22453.0 ns READ : Bank = 3 Row = 64, Col = 254, Data = 31230762
|
# tb_core.u_sdram32 : at time 22833.0 ns READ : Bank = 3 Row = 64, Col = 254, Data = 31230762
|
# READ STATUS: Burst-No: 5 Addr: 00040fea Rxd: 6c9c4bd9
|
# READ STATUS: Burst-No: 5 Addr: 00040fea Rxd: 6c9c4bd9
|
# tb_core.u_sdram32 : at time 22463.0 ns READ : Bank = 3 Row = 64, Col = 255, Data = 2635fb4c
|
# tb_core.u_sdram32 : at time 22843.0 ns READ : Bank = 3 Row = 64, Col = 255, Data = 2635fb4c
|
# READ STATUS: Burst-No: 6 Addr: 00040fec Rxd: 31230762
|
# READ STATUS: Burst-No: 6 Addr: 00040fec Rxd: 31230762
|
# READ STATUS: Burst-No: 7 Addr: 00040fee Rxd: 2635fb4c
|
# READ STATUS: Burst-No: 7 Addr: 00040fee Rxd: 2635fb4c
|
# tb_core.u_sdram32 : at time 22483.0 ns READ : Bank = 0 Row = 65, Col = 0, Data = 4fa1559f
|
# tb_core.u_sdram32 : at time 22863.0 ns READ : Bank = 0 Row = 65, Col = 0, Data = 4fa1559f
|
# tb_core.u_sdram32 : at time 22493.0 ns READ : Bank = 0 Row = 65, Col = 1, Data = 47b9a18f
|
# tb_core.u_sdram32 : at time 22873.0 ns READ : Bank = 0 Row = 65, Col = 1, Data = 47b9a18f
|
# READ STATUS: Burst-No: 8 Addr: 00040ff0 Rxd: 4fa1559f
|
# READ STATUS: Burst-No: 8 Addr: 00040ff0 Rxd: 4fa1559f
|
# tb_core.u_sdram32 : at time 22503.0 ns READ : Bank = 0 Row = 65, Col = 2, Data = 7c6da9f8
|
# tb_core.u_sdram32 : at time 22883.0 ns READ : Bank = 0 Row = 65, Col = 2, Data = 7c6da9f8
|
# READ STATUS: Burst-No: 9 Addr: 00040ff2 Rxd: 47b9a18f
|
# READ STATUS: Burst-No: 9 Addr: 00040ff2 Rxd: 47b9a18f
|
# tb_core.u_sdram32 : at time 22513.0 ns READ : Bank = 0 Row = 65, Col = 3, Data = dbcd60b7
|
# tb_core.u_sdram32 : at time 22893.0 ns READ : Bank = 0 Row = 65, Col = 3, Data = dbcd60b7
|
# READ STATUS: Burst-No: 10 Addr: 00040ff4 Rxd: 7c6da9f8
|
# READ STATUS: Burst-No: 10 Addr: 00040ff4 Rxd: 7c6da9f8
|
# tb_core.u_sdram32 : at time 22523.0 ns READ : Bank = 0 Row = 65, Col = 4, Data = cfc4569f
|
# tb_core.u_sdram32 : at time 22903.0 ns READ : Bank = 0 Row = 65, Col = 4, Data = cfc4569f
|
# tb_core.u_sdram32 : at time 22527.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 22907.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 11 Addr: 00040ff6 Rxd: dbcd60b7
|
# READ STATUS: Burst-No: 11 Addr: 00040ff6 Rxd: dbcd60b7
|
# tb_core.u_sdram32 : at time 22533.0 ns READ : Bank = 0 Row = 65, Col = 5, Data = ae7d945c
|
# tb_core.u_sdram32 : at time 22913.0 ns READ : Bank = 0 Row = 65, Col = 5, Data = ae7d945c
|
# READ STATUS: Burst-No: 12 Addr: 00040ff8 Rxd: cfc4569f
|
# READ STATUS: Burst-No: 12 Addr: 00040ff8 Rxd: cfc4569f
|
# tb_core.u_sdram32 : at time 22543.0 ns READ : Bank = 0 Row = 65, Col = 6, Data = adcbc05b
|
# tb_core.u_sdram32 : at time 22923.0 ns READ : Bank = 0 Row = 65, Col = 6, Data = adcbc05b
|
# READ STATUS: Burst-No: 13 Addr: 00040ffa Rxd: ae7d945c
|
# READ STATUS: Burst-No: 13 Addr: 00040ffa Rxd: ae7d945c
|
# READ STATUS: Burst-No: 14 Addr: 00040ffc Rxd: adcbc05b
|
# READ STATUS: Burst-No: 14 Addr: 00040ffc Rxd: adcbc05b
|
# tb_core.u_sdram32 : at time 22637.0 ns ACT : Bank = 3 Row = 80
|
# tb_core.u_sdram32 : at time 23027.0 ns ACT : Bank = 3 Row = 80
|
# tb_core.u_sdram32 : at time 22647.0 ns ACT : Bank = 0 Row = 81
|
# tb_core.u_sdram32 : at time 23093.0 ns READ : Bank = 3 Row = 80, Col = 249, Data = 44de3789
|
# tb_core.u_sdram32 : at time 22647.0 ns ERROR: tRRD violation during Activate bank = 0
|
# tb_core.u_sdram32 : at time 23103.0 ns READ : Bank = 3 Row = 80, Col = 250, Data = a4ae3249
|
# tb_core.u_sdram32 : at time 22703.0 ns READ : Bank = 3 Row = 80, Col = 249, Data = 44de3789
|
|
# tb_core.u_sdram32 : at time 22713.0 ns READ : Bank = 3 Row = 80, Col = 250, Data = a4ae3249
|
|
# READ STATUS: Burst-No: 0 Addr: 00050fe4 Rxd: 44de3789
|
# READ STATUS: Burst-No: 0 Addr: 00050fe4 Rxd: 44de3789
|
# tb_core.u_sdram32 : at time 22723.0 ns READ : Bank = 3 Row = 80, Col = 251, Data = e8233ed0
|
# tb_core.u_sdram32 : at time 23113.0 ns READ : Bank = 3 Row = 80, Col = 251, Data = e8233ed0
|
|
# tb_core.u_sdram32 : at time 23117.0 ns ACT : Bank = 0 Row = 81
|
# READ STATUS: Burst-No: 1 Addr: 00050fe6 Rxd: a4ae3249
|
# READ STATUS: Burst-No: 1 Addr: 00050fe6 Rxd: a4ae3249
|
# tb_core.u_sdram32 : at time 22733.0 ns READ : Bank = 3 Row = 80, Col = 252, Data = ebfec0d7
|
# tb_core.u_sdram32 : at time 23123.0 ns READ : Bank = 3 Row = 80, Col = 252, Data = ebfec0d7
|
# READ STATUS: Burst-No: 2 Addr: 00050fe8 Rxd: e8233ed0
|
# READ STATUS: Burst-No: 2 Addr: 00050fe8 Rxd: e8233ed0
|
# tb_core.u_sdram32 : at time 22743.0 ns READ : Bank = 3 Row = 80, Col = 253, Data = a8c7fc51
|
# tb_core.u_sdram32 : at time 23133.0 ns READ : Bank = 3 Row = 80, Col = 253, Data = a8c7fc51
|
# tb_core.u_sdram32 : at time 22747.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 23137.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 3 Addr: 00050fea Rxd: ebfec0d7
|
# READ STATUS: Burst-No: 3 Addr: 00050fea Rxd: ebfec0d7
|
# tb_core.u_sdram32 : at time 22753.0 ns READ : Bank = 3 Row = 80, Col = 254, Data = 4b212f96
|
# tb_core.u_sdram32 : at time 23143.0 ns READ : Bank = 3 Row = 80, Col = 254, Data = 4b212f96
|
# READ STATUS: Burst-No: 4 Addr: 00050fec Rxd: a8c7fc51
|
# READ STATUS: Burst-No: 4 Addr: 00050fec Rxd: a8c7fc51
|
# tb_core.u_sdram32 : at time 22763.0 ns READ : Bank = 3 Row = 80, Col = 255, Data = 061d7f0c
|
# tb_core.u_sdram32 : at time 23153.0 ns READ : Bank = 3 Row = 80, Col = 255, Data = 061d7f0c
|
# READ STATUS: Burst-No: 5 Addr: 00050fee Rxd: 4b212f96
|
# READ STATUS: Burst-No: 5 Addr: 00050fee Rxd: 4b212f96
|
# READ STATUS: Burst-No: 6 Addr: 00050ff0 Rxd: 061d7f0c
|
# READ STATUS: Burst-No: 6 Addr: 00050ff0 Rxd: 061d7f0c
|
# tb_core.u_sdram32 : at time 22783.0 ns READ : Bank = 0 Row = 81, Col = 0, Data = e12ccec2
|
# tb_core.u_sdram32 : at time 23183.0 ns READ : Bank = 0 Row = 81, Col = 0, Data = e12ccec2
|
# tb_core.u_sdram32 : at time 22793.0 ns READ : Bank = 0 Row = 81, Col = 1, Data = 6457edc8
|
# tb_core.u_sdram32 : at time 23193.0 ns READ : Bank = 0 Row = 81, Col = 1, Data = 6457edc8
|
# READ STATUS: Burst-No: 7 Addr: 00050ff2 Rxd: e12ccec2
|
# READ STATUS: Burst-No: 7 Addr: 00050ff2 Rxd: e12ccec2
|
# tb_core.u_sdram32 : at time 22803.0 ns READ : Bank = 0 Row = 81, Col = 2, Data = bb825a77
|
# tb_core.u_sdram32 : at time 23203.0 ns READ : Bank = 0 Row = 81, Col = 2, Data = bb825a77
|
# READ STATUS: Burst-No: 8 Addr: 00050ff4 Rxd: 6457edc8
|
# READ STATUS: Burst-No: 8 Addr: 00050ff4 Rxd: 6457edc8
|
# tb_core.u_sdram32 : at time 22813.0 ns READ : Bank = 0 Row = 81, Col = 3, Data = 1ef2ed3d
|
# tb_core.u_sdram32 : at time 23213.0 ns READ : Bank = 0 Row = 81, Col = 3, Data = 1ef2ed3d
|
# READ STATUS: Burst-No: 9 Addr: 00050ff6 Rxd: bb825a77
|
# READ STATUS: Burst-No: 9 Addr: 00050ff6 Rxd: bb825a77
|
# tb_core.u_sdram32 : at time 22823.0 ns READ : Bank = 0 Row = 81, Col = 4, Data = 090cdb12
|
# tb_core.u_sdram32 : at time 23223.0 ns READ : Bank = 0 Row = 81, Col = 4, Data = 090cdb12
|
# tb_core.u_sdram32 : at time 22827.0 ns BST : Burst Terminate
|
|
# READ STATUS: Burst-No: 10 Addr: 00050ff8 Rxd: 1ef2ed3d
|
# READ STATUS: Burst-No: 10 Addr: 00050ff8 Rxd: 1ef2ed3d
|
# tb_core.u_sdram32 : at time 22833.0 ns READ : Bank = 0 Row = 81, Col = 5, Data = bf05007e
|
# tb_core.u_sdram32 : at time 23233.0 ns READ : Bank = 0 Row = 81, Col = 5, Data = bf05007e
|
|
# tb_core.u_sdram32 : at time 23237.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 11 Addr: 00050ffa Rxd: 090cdb12
|
# READ STATUS: Burst-No: 11 Addr: 00050ffa Rxd: 090cdb12
|
# tb_core.u_sdram32 : at time 22843.0 ns READ : Bank = 0 Row = 81, Col = 6, Data = 36e5816d
|
# tb_core.u_sdram32 : at time 23243.0 ns READ : Bank = 0 Row = 81, Col = 6, Data = 36e5816d
|
# tb_core.u_sdram32 : at time 22847.0 ns BST : Burst Terminate
|
|
# READ STATUS: Burst-No: 12 Addr: 00050ffc Rxd: bf05007e
|
# READ STATUS: Burst-No: 12 Addr: 00050ffc Rxd: bf05007e
|
|
# tb_core.u_sdram32 : at time 23253.0 ns READ : Bank = 0 Row = 81, Col = 7, Data = 1cd9e739
|
# READ STATUS: Burst-No: 13 Addr: 00050ffe Rxd: 36e5816d
|
# READ STATUS: Burst-No: 13 Addr: 00050ffe Rxd: 36e5816d
|
# tb_core.u_sdram32 : at time 22863.0 ns READ : Bank = 0 Row = 81, Col = 7, Data = 1cd9e739
|
|
# READ STATUS: Burst-No: 14 Addr: 00051000 Rxd: 1cd9e739
|
# READ STATUS: Burst-No: 14 Addr: 00051000 Rxd: 1cd9e739
|
# tb_core.u_sdram32 : at time 22957.0 ns ACT : Bank = 3 Row = 96
|
# tb_core.u_sdram32 : at time 23357.0 ns ACT : Bank = 3 Row = 96
|
# tb_core.u_sdram32 : at time 22967.0 ns ACT : Bank = 0 Row = 97
|
# tb_core.u_sdram32 : at time 23423.0 ns READ : Bank = 3 Row = 96, Col = 250, Data = 0fd28f1f
|
# tb_core.u_sdram32 : at time 22967.0 ns ERROR: tRRD violation during Activate bank = 0
|
# tb_core.u_sdram32 : at time 23433.0 ns READ : Bank = 3 Row = 96, Col = 251, Data = e9ebf6d3
|
# tb_core.u_sdram32 : at time 23023.0 ns READ : Bank = 3 Row = 96, Col = 250, Data = 0fd28f1f
|
|
# tb_core.u_sdram32 : at time 23033.0 ns READ : Bank = 3 Row = 96, Col = 251, Data = e9ebf6d3
|
|
# READ STATUS: Burst-No: 0 Addr: 00060fe8 Rxd: 0fd28f1f
|
# READ STATUS: Burst-No: 0 Addr: 00060fe8 Rxd: 0fd28f1f
|
# tb_core.u_sdram32 : at time 23043.0 ns READ : Bank = 3 Row = 96, Col = 252, Data = 42d92f85
|
# tb_core.u_sdram32 : at time 23443.0 ns READ : Bank = 3 Row = 96, Col = 252, Data = 42d92f85
|
|
# tb_core.u_sdram32 : at time 23447.0 ns ACT : Bank = 0 Row = 97
|
# READ STATUS: Burst-No: 1 Addr: 00060fea Rxd: e9ebf6d3
|
# READ STATUS: Burst-No: 1 Addr: 00060fea Rxd: e9ebf6d3
|
# tb_core.u_sdram32 : at time 23053.0 ns READ : Bank = 3 Row = 96, Col = 253, Data = bc148878
|
# tb_core.u_sdram32 : at time 23453.0 ns READ : Bank = 3 Row = 96, Col = 253, Data = bc148878
|
# tb_core.u_sdram32 : at time 23057.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 23457.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 2 Addr: 00060fec Rxd: 42d92f85
|
# READ STATUS: Burst-No: 2 Addr: 00060fec Rxd: 42d92f85
|
# tb_core.u_sdram32 : at time 23063.0 ns READ : Bank = 3 Row = 96, Col = 254, Data = 2dda595b
|
# tb_core.u_sdram32 : at time 23463.0 ns READ : Bank = 3 Row = 96, Col = 254, Data = 2dda595b
|
# READ STATUS: Burst-No: 3 Addr: 00060fee Rxd: bc148878
|
# READ STATUS: Burst-No: 3 Addr: 00060fee Rxd: bc148878
|
# tb_core.u_sdram32 : at time 23073.0 ns READ : Bank = 3 Row = 96, Col = 255, Data = 248b4b49
|
# tb_core.u_sdram32 : at time 23473.0 ns READ : Bank = 3 Row = 96, Col = 255, Data = 248b4b49
|
# READ STATUS: Burst-No: 4 Addr: 00060ff0 Rxd: 2dda595b
|
# READ STATUS: Burst-No: 4 Addr: 00060ff0 Rxd: 2dda595b
|
# READ STATUS: Burst-No: 5 Addr: 00060ff2 Rxd: 248b4b49
|
# READ STATUS: Burst-No: 5 Addr: 00060ff2 Rxd: 248b4b49
|
# tb_core.u_sdram32 : at time 23093.0 ns READ : Bank = 0 Row = 97, Col = 0, Data = 9ff2ae3f
|
# tb_core.u_sdram32 : at time 23513.0 ns READ : Bank = 0 Row = 97, Col = 0, Data = 9ff2ae3f
|
# tb_core.u_sdram32 : at time 23103.0 ns READ : Bank = 0 Row = 97, Col = 1, Data = 150caf2a
|
# tb_core.u_sdram32 : at time 23523.0 ns READ : Bank = 0 Row = 97, Col = 1, Data = 150caf2a
|
# READ STATUS: Burst-No: 6 Addr: 00060ff4 Rxd: 9ff2ae3f
|
# READ STATUS: Burst-No: 6 Addr: 00060ff4 Rxd: 9ff2ae3f
|
# tb_core.u_sdram32 : at time 23113.0 ns READ : Bank = 0 Row = 97, Col = 2, Data = 2c156358
|
# tb_core.u_sdram32 : at time 23533.0 ns READ : Bank = 0 Row = 97, Col = 2, Data = 2c156358
|
# READ STATUS: Burst-No: 7 Addr: 00060ff6 Rxd: 150caf2a
|
# READ STATUS: Burst-No: 7 Addr: 00060ff6 Rxd: 150caf2a
|
# tb_core.u_sdram32 : at time 23123.0 ns READ : Bank = 0 Row = 97, Col = 3, Data = c33f3886
|
# tb_core.u_sdram32 : at time 23543.0 ns READ : Bank = 0 Row = 97, Col = 3, Data = c33f3886
|
# tb_core.u_sdram32 : at time 23127.0 ns BST : Burst Terminate
|
|
# READ STATUS: Burst-No: 8 Addr: 00060ff8 Rxd: 2c156358
|
# READ STATUS: Burst-No: 8 Addr: 00060ff8 Rxd: 2c156358
|
# tb_core.u_sdram32 : at time 23133.0 ns READ : Bank = 0 Row = 97, Col = 4, Data = c71a0c8e
|
# tb_core.u_sdram32 : at time 23553.0 ns READ : Bank = 0 Row = 97, Col = 4, Data = c71a0c8e
|
# READ STATUS: Burst-No: 9 Addr: 00060ffa Rxd: c33f3886
|
# READ STATUS: Burst-No: 9 Addr: 00060ffa Rxd: c33f3886
|
# tb_core.u_sdram32 : at time 23143.0 ns READ : Bank = 0 Row = 97, Col = 5, Data = ce2ff29c
|
# tb_core.u_sdram32 : at time 23563.0 ns READ : Bank = 0 Row = 97, Col = 5, Data = ce2ff29c
|
# READ STATUS: Burst-No: 10 Addr: 00060ffc Rxd: c71a0c8e
|
# READ STATUS: Burst-No: 10 Addr: 00060ffc Rxd: c71a0c8e
|
|
# tb_core.u_sdram32 : at time 23573.0 ns READ : Bank = 0 Row = 97, Col = 6, Data = 7d3599fa
|
|
# tb_core.u_sdram32 : at time 23577.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 11 Addr: 00060ffe Rxd: ce2ff29c
|
# READ STATUS: Burst-No: 11 Addr: 00060ffe Rxd: ce2ff29c
|
# tb_core.u_sdram32 : at time 23163.0 ns READ : Bank = 0 Row = 97, Col = 6, Data = 7d3599fa
|
# tb_core.u_sdram32 : at time 23583.0 ns READ : Bank = 0 Row = 97, Col = 7, Data = 937dbc26
|
# tb_core.u_sdram32 : at time 23167.0 ns BST : Burst Terminate
|
|
# tb_core.u_sdram32 : at time 23173.0 ns READ : Bank = 0 Row = 97, Col = 7, Data = 937dbc26
|
|
# READ STATUS: Burst-No: 12 Addr: 00061000 Rxd: 7d3599fa
|
# READ STATUS: Burst-No: 12 Addr: 00061000 Rxd: 7d3599fa
|
# tb_core.u_sdram32 : at time 23183.0 ns READ : Bank = 0 Row = 97, Col = 8, Data = 39961773
|
# tb_core.u_sdram32 : at time 23593.0 ns READ : Bank = 0 Row = 97, Col = 8, Data = 39961773
|
# READ STATUS: Burst-No: 13 Addr: 00061002 Rxd: 937dbc26
|
# READ STATUS: Burst-No: 13 Addr: 00061002 Rxd: 937dbc26
|
# READ STATUS: Burst-No: 14 Addr: 00061004 Rxd: 39961773
|
# READ STATUS: Burst-No: 14 Addr: 00061004 Rxd: 39961773
|
# tb_core.u_sdram32 : at time 23277.0 ns ACT : Bank = 3 Row = 112
|
# tb_core.u_sdram32 : at time 23697.0 ns ACT : Bank = 3 Row = 112
|
# tb_core.u_sdram32 : at time 23287.0 ns ACT : Bank = 0 Row = 113
|
# tb_core.u_sdram32 : at time 23763.0 ns READ : Bank = 3 Row = 112, Col = 251, Data = d18bb4a3
|
# tb_core.u_sdram32 : at time 23287.0 ns ERROR: tRRD violation during Activate bank = 0
|
# tb_core.u_sdram32 : at time 23773.0 ns READ : Bank = 3 Row = 112, Col = 252, Data = 9799a82f
|
# tb_core.u_sdram32 : at time 23343.0 ns READ : Bank = 3 Row = 112, Col = 251, Data = d18bb4a3
|
|
# tb_core.u_sdram32 : at time 23353.0 ns READ : Bank = 3 Row = 112, Col = 252, Data = 9799a82f
|
|
# READ STATUS: Burst-No: 0 Addr: 00070fec Rxd: d18bb4a3
|
# READ STATUS: Burst-No: 0 Addr: 00070fec Rxd: d18bb4a3
|
# tb_core.u_sdram32 : at time 23363.0 ns READ : Bank = 3 Row = 112, Col = 253, Data = d9d292b3
|
# tb_core.u_sdram32 : at time 23783.0 ns READ : Bank = 3 Row = 112, Col = 253, Data = d9d292b3
|
# tb_core.u_sdram32 : at time 23367.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 23787.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 1 Addr: 00070fee Rxd: 9799a82f
|
# READ STATUS: Burst-No: 1 Addr: 00070fee Rxd: 9799a82f
|
# tb_core.u_sdram32 : at time 23373.0 ns READ : Bank = 3 Row = 112, Col = 254, Data = afd8565f
|
# tb_core.u_sdram32 : at time 23793.0 ns READ : Bank = 3 Row = 112, Col = 254, Data = afd8565f
|
# READ STATUS: Burst-No: 2 Addr: 00070ff0 Rxd: d9d292b3
|
# READ STATUS: Burst-No: 2 Addr: 00070ff0 Rxd: d9d292b3
|
# tb_core.u_sdram32 : at time 23383.0 ns READ : Bank = 3 Row = 112, Col = 255, Data = 22290d44
|
# tb_core.u_sdram32 : at time 23803.0 ns READ : Bank = 3 Row = 112, Col = 255, Data = 22290d44
|
# READ STATUS: Burst-No: 3 Addr: 00070ff2 Rxd: afd8565f
|
# READ STATUS: Burst-No: 3 Addr: 00070ff2 Rxd: afd8565f
|
# READ STATUS: Burst-No: 4 Addr: 00070ff4 Rxd: 22290d44
|
# READ STATUS: Burst-No: 4 Addr: 00070ff4 Rxd: 22290d44
|
# tb_core.u_sdram32 : at time 23403.0 ns READ : Bank = 0 Row = 113, Col = 0, Data = 7bf8fdf7
|
# tb_core.u_sdram32 : at time 23847.0 ns ACT : Bank = 0 Row = 113
|
# tb_core.u_sdram32 : at time 23413.0 ns READ : Bank = 0 Row = 113, Col = 1, Data = e59b36cb
|
# tb_core.u_sdram32 : at time 23913.0 ns READ : Bank = 0 Row = 113, Col = 0, Data = 7bf8fdf7
|
|
# tb_core.u_sdram32 : at time 23923.0 ns READ : Bank = 0 Row = 113, Col = 1, Data = e59b36cb
|
# READ STATUS: Burst-No: 5 Addr: 00070ff6 Rxd: 7bf8fdf7
|
# READ STATUS: Burst-No: 5 Addr: 00070ff6 Rxd: 7bf8fdf7
|
# tb_core.u_sdram32 : at time 23423.0 ns READ : Bank = 0 Row = 113, Col = 2, Data = f3091ae6
|
# tb_core.u_sdram32 : at time 23933.0 ns READ : Bank = 0 Row = 113, Col = 2, Data = f3091ae6
|
# tb_core.u_sdram32 : at time 23427.0 ns BST : Burst Terminate
|
|
# READ STATUS: Burst-No: 6 Addr: 00070ff8 Rxd: e59b36cb
|
# READ STATUS: Burst-No: 6 Addr: 00070ff8 Rxd: e59b36cb
|
# tb_core.u_sdram32 : at time 23433.0 ns READ : Bank = 0 Row = 113, Col = 3, Data = 2d28db5a
|
# tb_core.u_sdram32 : at time 23943.0 ns READ : Bank = 0 Row = 113, Col = 3, Data = 2d28db5a
|
# READ STATUS: Burst-No: 7 Addr: 00070ffa Rxd: f3091ae6
|
# READ STATUS: Burst-No: 7 Addr: 00070ffa Rxd: f3091ae6
|
# tb_core.u_sdram32 : at time 23443.0 ns READ : Bank = 0 Row = 113, Col = 4, Data = 14cfc129
|
# tb_core.u_sdram32 : at time 23953.0 ns READ : Bank = 0 Row = 113, Col = 4, Data = 14cfc129
|
# READ STATUS: Burst-No: 8 Addr: 00070ffc Rxd: 2d28db5a
|
# READ STATUS: Burst-No: 8 Addr: 00070ffc Rxd: 2d28db5a
|
|
# tb_core.u_sdram32 : at time 23963.0 ns READ : Bank = 0 Row = 113, Col = 5, Data = f682e2ed
|
# READ STATUS: Burst-No: 9 Addr: 00070ffe Rxd: 14cfc129
|
# READ STATUS: Burst-No: 9 Addr: 00070ffe Rxd: 14cfc129
|
# tb_core.u_sdram32 : at time 23463.0 ns READ : Bank = 0 Row = 113, Col = 5, Data = f682e2ed
|
# tb_core.u_sdram32 : at time 23973.0 ns READ : Bank = 0 Row = 113, Col = 6, Data = ed536cda
|
# tb_core.u_sdram32 : at time 23473.0 ns READ : Bank = 0 Row = 113, Col = 6, Data = ed536cda
|
|
# READ STATUS: Burst-No: 10 Addr: 00071000 Rxd: f682e2ed
|
# READ STATUS: Burst-No: 10 Addr: 00071000 Rxd: f682e2ed
|
# tb_core.u_sdram32 : at time 23483.0 ns READ : Bank = 0 Row = 113, Col = 7, Data = b29fb665
|
# tb_core.u_sdram32 : at time 23983.0 ns READ : Bank = 0 Row = 113, Col = 7, Data = b29fb665
|
# tb_core.u_sdram32 : at time 23487.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 23987.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 11 Addr: 00071002 Rxd: ed536cda
|
# READ STATUS: Burst-No: 11 Addr: 00071002 Rxd: ed536cda
|
# tb_core.u_sdram32 : at time 23493.0 ns READ : Bank = 0 Row = 113, Col = 8, Data = da8ae2b5
|
# tb_core.u_sdram32 : at time 23993.0 ns READ : Bank = 0 Row = 113, Col = 8, Data = da8ae2b5
|
# READ STATUS: Burst-No: 12 Addr: 00071004 Rxd: b29fb665
|
# READ STATUS: Burst-No: 12 Addr: 00071004 Rxd: b29fb665
|
# tb_core.u_sdram32 : at time 23503.0 ns READ : Bank = 0 Row = 113, Col = 9, Data = efbe94df
|
# tb_core.u_sdram32 : at time 24003.0 ns READ : Bank = 0 Row = 113, Col = 9, Data = efbe94df
|
# READ STATUS: Burst-No: 13 Addr: 00071006 Rxd: da8ae2b5
|
# READ STATUS: Burst-No: 13 Addr: 00071006 Rxd: da8ae2b5
|
# READ STATUS: Burst-No: 14 Addr: 00071008 Rxd: efbe94df
|
# READ STATUS: Burst-No: 14 Addr: 00071008 Rxd: efbe94df
|
# tb_core.u_sdram32 : at time 23597.0 ns ACT : Bank = 3 Row = 128
|
# tb_core.u_sdram32 : at time 24107.0 ns ACT : Bank = 3 Row = 128
|
# tb_core.u_sdram32 : at time 23607.0 ns ACT : Bank = 0 Row = 129
|
# tb_core.u_sdram32 : at time 24173.0 ns READ : Bank = 3 Row = 128, Col = 244, Data = 3cf11979
|
# tb_core.u_sdram32 : at time 23607.0 ns ERROR: tRRD violation during Activate bank = 0
|
# tb_core.u_sdram32 : at time 24183.0 ns READ : Bank = 3 Row = 128, Col = 245, Data = 2231ff44
|
# tb_core.u_sdram32 : at time 23663.0 ns READ : Bank = 3 Row = 128, Col = 244, Data = 3cf11979
|
|
# tb_core.u_sdram32 : at time 23673.0 ns READ : Bank = 3 Row = 128, Col = 245, Data = 2231ff44
|
|
# READ STATUS: Burst-No: 0 Addr: 00080fd0 Rxd: 3cf11979
|
# READ STATUS: Burst-No: 0 Addr: 00080fd0 Rxd: 3cf11979
|
# tb_core.u_sdram32 : at time 23683.0 ns READ : Bank = 3 Row = 128, Col = 246, Data = e8740cd0
|
# tb_core.u_sdram32 : at time 24193.0 ns READ : Bank = 3 Row = 128, Col = 246, Data = e8740cd0
|
|
# tb_core.u_sdram32 : at time 24197.0 ns ACT : Bank = 0 Row = 129
|
# READ STATUS: Burst-No: 1 Addr: 00080fd2 Rxd: 2231ff44
|
# READ STATUS: Burst-No: 1 Addr: 00080fd2 Rxd: 2231ff44
|
# tb_core.u_sdram32 : at time 23693.0 ns READ : Bank = 3 Row = 128, Col = 247, Data = 15090b2a
|
# tb_core.u_sdram32 : at time 24203.0 ns READ : Bank = 3 Row = 128, Col = 247, Data = 15090b2a
|
# READ STATUS: Burst-No: 2 Addr: 00080fd4 Rxd: e8740cd0
|
# READ STATUS: Burst-No: 2 Addr: 00080fd4 Rxd: e8740cd0
|
# tb_core.u_sdram32 : at time 23703.0 ns READ : Bank = 3 Row = 128, Col = 248, Data = 55f6adab
|
# tb_core.u_sdram32 : at time 24213.0 ns READ : Bank = 3 Row = 128, Col = 248, Data = 55f6adab
|
# READ STATUS: Burst-No: 3 Addr: 00080fd6 Rxd: 15090b2a
|
# READ STATUS: Burst-No: 3 Addr: 00080fd6 Rxd: 15090b2a
|
# tb_core.u_sdram32 : at time 23713.0 ns READ : Bank = 3 Row = 128, Col = 249, Data = 076fcf0e
|
# tb_core.u_sdram32 : at time 24223.0 ns READ : Bank = 3 Row = 128, Col = 249, Data = 076fcf0e
|
# READ STATUS: Burst-No: 4 Addr: 00080fd8 Rxd: 55f6adab
|
# READ STATUS: Burst-No: 4 Addr: 00080fd8 Rxd: 55f6adab
|
# tb_core.u_sdram32 : at time 23723.0 ns READ : Bank = 3 Row = 128, Col = 250, Data = 6e5daddc
|
# tb_core.u_sdram32 : at time 24233.0 ns READ : Bank = 3 Row = 128, Col = 250, Data = 6e5daddc
|
# READ STATUS: Burst-No: 5 Addr: 00080fda Rxd: 076fcf0e
|
# READ STATUS: Burst-No: 5 Addr: 00080fda Rxd: 076fcf0e
|
# tb_core.u_sdram32 : at time 23733.0 ns READ : Bank = 3 Row = 128, Col = 251, Data = cd5ebc9a
|
# tb_core.u_sdram32 : at time 24243.0 ns READ : Bank = 3 Row = 128, Col = 251, Data = cd5ebc9a
|
# READ STATUS: Burst-No: 6 Addr: 00080fdc Rxd: 6e5daddc
|
# READ STATUS: Burst-No: 6 Addr: 00080fdc Rxd: 6e5daddc
|
# tb_core.u_sdram32 : at time 23743.0 ns READ : Bank = 3 Row = 128, Col = 252, Data = fedf72fd
|
# tb_core.u_sdram32 : at time 24253.0 ns READ : Bank = 3 Row = 128, Col = 252, Data = fedf72fd
|
# READ STATUS: Burst-No: 7 Addr: 00080fde Rxd: cd5ebc9a
|
# READ STATUS: Burst-No: 7 Addr: 00080fde Rxd: cd5ebc9a
|
# tb_core.u_sdram32 : at time 23753.0 ns READ : Bank = 3 Row = 128, Col = 253, Data = e1f102c3
|
# tb_core.u_sdram32 : at time 24263.0 ns READ : Bank = 3 Row = 128, Col = 253, Data = e1f102c3
|
# tb_core.u_sdram32 : at time 23757.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 24267.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 8 Addr: 00080fe0 Rxd: fedf72fd
|
# READ STATUS: Burst-No: 8 Addr: 00080fe0 Rxd: fedf72fd
|
# tb_core.u_sdram32 : at time 23763.0 ns READ : Bank = 3 Row = 128, Col = 254, Data = 2b0eed56
|
# tb_core.u_sdram32 : at time 24273.0 ns READ : Bank = 3 Row = 128, Col = 254, Data = 2b0eed56
|
# READ STATUS: Burst-No: 9 Addr: 00080fe2 Rxd: e1f102c3
|
# READ STATUS: Burst-No: 9 Addr: 00080fe2 Rxd: e1f102c3
|
# tb_core.u_sdram32 : at time 23773.0 ns READ : Bank = 3 Row = 128, Col = 255, Data = 2779e94e
|
# tb_core.u_sdram32 : at time 24283.0 ns READ : Bank = 3 Row = 128, Col = 255, Data = 2779e94e
|
# READ STATUS: Burst-No: 10 Addr: 00080fe4 Rxd: 2b0eed56
|
# READ STATUS: Burst-No: 10 Addr: 00080fe4 Rxd: 2b0eed56
|
# READ STATUS: Burst-No: 11 Addr: 00080fe6 Rxd: 2779e94e
|
# READ STATUS: Burst-No: 11 Addr: 00080fe6 Rxd: 2779e94e
|
# tb_core.u_sdram32 : at time 23793.0 ns READ : Bank = 0 Row = 129, Col = 0, Data = b3d97667
|
# tb_core.u_sdram32 : at time 24303.0 ns READ : Bank = 0 Row = 129, Col = 0, Data = b3d97667
|
# tb_core.u_sdram32 : at time 23797.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 24307.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 23803.0 ns READ : Bank = 0 Row = 129, Col = 1, Data = 8531340a
|
# tb_core.u_sdram32 : at time 24313.0 ns READ : Bank = 0 Row = 129, Col = 1, Data = 8531340a
|
# READ STATUS: Burst-No: 12 Addr: 00080fe8 Rxd: b3d97667
|
# READ STATUS: Burst-No: 12 Addr: 00080fe8 Rxd: b3d97667
|
# tb_core.u_sdram32 : at time 23813.0 ns READ : Bank = 0 Row = 129, Col = 2, Data = 5b6fb9b6
|
# tb_core.u_sdram32 : at time 24323.0 ns READ : Bank = 0 Row = 129, Col = 2, Data = 5b6fb9b6
|
# READ STATUS: Burst-No: 13 Addr: 00080fea Rxd: 8531340a
|
# READ STATUS: Burst-No: 13 Addr: 00080fea Rxd: 8531340a
|
# READ STATUS: Burst-No: 14 Addr: 00080fec Rxd: 5b6fb9b6
|
# READ STATUS: Burst-No: 14 Addr: 00080fec Rxd: 5b6fb9b6
|
# tb_core.u_sdram32 : at time 23907.0 ns ACT : Bank = 3 Row = 144
|
# tb_core.u_sdram32 : at time 24427.0 ns ACT : Bank = 3 Row = 144
|
# tb_core.u_sdram32 : at time 23917.0 ns ACT : Bank = 0 Row = 145
|
# tb_core.u_sdram32 : at time 24493.0 ns READ : Bank = 3 Row = 144, Col = 245, Data = 9c0e8a38
|
# tb_core.u_sdram32 : at time 23917.0 ns ERROR: tRRD violation during Activate bank = 0
|
# tb_core.u_sdram32 : at time 24503.0 ns READ : Bank = 3 Row = 144, Col = 246, Data = 3cd18779
|
# tb_core.u_sdram32 : at time 23973.0 ns READ : Bank = 3 Row = 144, Col = 245, Data = 9c0e8a38
|
|
# tb_core.u_sdram32 : at time 23983.0 ns READ : Bank = 3 Row = 144, Col = 246, Data = 3cd18779
|
|
# READ STATUS: Burst-No: 0 Addr: 00090fd4 Rxd: 9c0e8a38
|
# READ STATUS: Burst-No: 0 Addr: 00090fd4 Rxd: 9c0e8a38
|
# tb_core.u_sdram32 : at time 23993.0 ns READ : Bank = 3 Row = 144, Col = 247, Data = dc2bc4b8
|
# tb_core.u_sdram32 : at time 24513.0 ns READ : Bank = 3 Row = 144, Col = 247, Data = dc2bc4b8
|
|
# tb_core.u_sdram32 : at time 24517.0 ns ACT : Bank = 0 Row = 145
|
# READ STATUS: Burst-No: 1 Addr: 00090fd6 Rxd: 3cd18779
|
# READ STATUS: Burst-No: 1 Addr: 00090fd6 Rxd: 3cd18779
|
# tb_core.u_sdram32 : at time 24003.0 ns READ : Bank = 3 Row = 144, Col = 248, Data = 4a74bf94
|
# tb_core.u_sdram32 : at time 24523.0 ns READ : Bank = 3 Row = 144, Col = 248, Data = 4a74bf94
|
# READ STATUS: Burst-No: 2 Addr: 00090fd8 Rxd: dc2bc4b8
|
# READ STATUS: Burst-No: 2 Addr: 00090fd8 Rxd: dc2bc4b8
|
# tb_core.u_sdram32 : at time 24013.0 ns READ : Bank = 3 Row = 144, Col = 249, Data = 49c65d93
|
# tb_core.u_sdram32 : at time 24533.0 ns READ : Bank = 3 Row = 144, Col = 249, Data = 49c65d93
|
# READ STATUS: Burst-No: 3 Addr: 00090fda Rxd: 4a74bf94
|
# READ STATUS: Burst-No: 3 Addr: 00090fda Rxd: 4a74bf94
|
# tb_core.u_sdram32 : at time 24023.0 ns READ : Bank = 3 Row = 144, Col = 250, Data = 823f2c04
|
# tb_core.u_sdram32 : at time 24543.0 ns READ : Bank = 3 Row = 144, Col = 250, Data = 823f2c04
|
# READ STATUS: Burst-No: 4 Addr: 00090fdc Rxd: 49c65d93
|
# READ STATUS: Burst-No: 4 Addr: 00090fdc Rxd: 49c65d93
|
# tb_core.u_sdram32 : at time 24033.0 ns READ : Bank = 3 Row = 144, Col = 251, Data = acb7ca59
|
# tb_core.u_sdram32 : at time 24553.0 ns READ : Bank = 3 Row = 144, Col = 251, Data = acb7ca59
|
# READ STATUS: Burst-No: 5 Addr: 00090fde Rxd: 823f2c04
|
# READ STATUS: Burst-No: 5 Addr: 00090fde Rxd: 823f2c04
|
# tb_core.u_sdram32 : at time 24043.0 ns READ : Bank = 3 Row = 144, Col = 252, Data = 6dcb69db
|
# tb_core.u_sdram32 : at time 24563.0 ns READ : Bank = 3 Row = 144, Col = 252, Data = 6dcb69db
|
# READ STATUS: Burst-No: 6 Addr: 00090fe0 Rxd: acb7ca59
|
# READ STATUS: Burst-No: 6 Addr: 00090fe0 Rxd: acb7ca59
|
# tb_core.u_sdram32 : at time 24053.0 ns READ : Bank = 3 Row = 144, Col = 253, Data = a6fcde4d
|
# tb_core.u_sdram32 : at time 24573.0 ns READ : Bank = 3 Row = 144, Col = 253, Data = a6fcde4d
|
# tb_core.u_sdram32 : at time 24057.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 24577.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 7 Addr: 00090fe2 Rxd: 6dcb69db
|
# READ STATUS: Burst-No: 7 Addr: 00090fe2 Rxd: 6dcb69db
|
# tb_core.u_sdram32 : at time 24063.0 ns READ : Bank = 3 Row = 144, Col = 254, Data = 6cb0b7d9
|
# tb_core.u_sdram32 : at time 24583.0 ns READ : Bank = 3 Row = 144, Col = 254, Data = 6cb0b7d9
|
# READ STATUS: Burst-No: 8 Addr: 00090fe4 Rxd: a6fcde4d
|
# READ STATUS: Burst-No: 8 Addr: 00090fe4 Rxd: a6fcde4d
|
# tb_core.u_sdram32 : at time 24073.0 ns READ : Bank = 3 Row = 144, Col = 255, Data = b6a4266d
|
# tb_core.u_sdram32 : at time 24593.0 ns READ : Bank = 3 Row = 144, Col = 255, Data = b6a4266d
|
# READ STATUS: Burst-No: 9 Addr: 00090fe6 Rxd: 6cb0b7d9
|
# READ STATUS: Burst-No: 9 Addr: 00090fe6 Rxd: 6cb0b7d9
|
# READ STATUS: Burst-No: 10 Addr: 00090fe8 Rxd: b6a4266d
|
# READ STATUS: Burst-No: 10 Addr: 00090fe8 Rxd: b6a4266d
|
# tb_core.u_sdram32 : at time 24093.0 ns READ : Bank = 0 Row = 145, Col = 0, Data = bb45e276
|
# tb_core.u_sdram32 : at time 24613.0 ns READ : Bank = 0 Row = 145, Col = 0, Data = bb45e276
|
# tb_core.u_sdram32 : at time 24103.0 ns READ : Bank = 0 Row = 145, Col = 1, Data = 653b49ca
|
# tb_core.u_sdram32 : at time 24623.0 ns READ : Bank = 0 Row = 145, Col = 1, Data = 653b49ca
|
# READ STATUS: Burst-No: 11 Addr: 00090fea Rxd: bb45e276
|
# READ STATUS: Burst-No: 11 Addr: 00090fea Rxd: bb45e276
|
# tb_core.u_sdram32 : at time 24107.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 24627.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 24113.0 ns READ : Bank = 0 Row = 145, Col = 2, Data = 5b172db6
|
# tb_core.u_sdram32 : at time 24633.0 ns READ : Bank = 0 Row = 145, Col = 2, Data = 5b172db6
|
# READ STATUS: Burst-No: 12 Addr: 00090fec Rxd: 653b49ca
|
# READ STATUS: Burst-No: 12 Addr: 00090fec Rxd: 653b49ca
|
# tb_core.u_sdram32 : at time 24123.0 ns READ : Bank = 0 Row = 145, Col = 3, Data = 4a937195
|
# tb_core.u_sdram32 : at time 24643.0 ns READ : Bank = 0 Row = 145, Col = 3, Data = 4a937195
|
# READ STATUS: Burst-No: 13 Addr: 00090fee Rxd: 5b172db6
|
# READ STATUS: Burst-No: 13 Addr: 00090fee Rxd: 5b172db6
|
# READ STATUS: Burst-No: 14 Addr: 00090ff0 Rxd: 4a937195
|
# READ STATUS: Burst-No: 14 Addr: 00090ff0 Rxd: 4a937195
|
# tb_core.u_sdram32 : at time 24217.0 ns ACT : Bank = 3 Row = 160
|
# tb_core.u_sdram32 : at time 24747.0 ns ACT : Bank = 3 Row = 160
|
# tb_core.u_sdram32 : at time 24227.0 ns ACT : Bank = 0 Row = 161
|
# tb_core.u_sdram32 : at time 24813.0 ns READ : Bank = 3 Row = 160, Col = 246, Data = a3071a46
|
# tb_core.u_sdram32 : at time 24227.0 ns ERROR: tRRD violation during Activate bank = 0
|
# tb_core.u_sdram32 : at time 24823.0 ns READ : Bank = 3 Row = 160, Col = 247, Data = 02749b04
|
# tb_core.u_sdram32 : at time 24283.0 ns READ : Bank = 3 Row = 160, Col = 246, Data = a3071a46
|
|
# tb_core.u_sdram32 : at time 24293.0 ns READ : Bank = 3 Row = 160, Col = 247, Data = 02749b04
|
|
# READ STATUS: Burst-No: 0 Addr: 000a0fd8 Rxd: a3071a46
|
# READ STATUS: Burst-No: 0 Addr: 000a0fd8 Rxd: a3071a46
|
# tb_core.u_sdram32 : at time 24303.0 ns READ : Bank = 3 Row = 160, Col = 248, Data = 7bd261f7
|
# tb_core.u_sdram32 : at time 24833.0 ns READ : Bank = 3 Row = 160, Col = 248, Data = 7bd261f7
|
|
# tb_core.u_sdram32 : at time 24837.0 ns ACT : Bank = 0 Row = 161
|
# READ STATUS: Burst-No: 1 Addr: 000a0fda Rxd: 02749b04
|
# READ STATUS: Burst-No: 1 Addr: 000a0fda Rxd: 02749b04
|
# tb_core.u_sdram32 : at time 24313.0 ns READ : Bank = 3 Row = 160, Col = 249, Data = 34980769
|
# tb_core.u_sdram32 : at time 24843.0 ns READ : Bank = 3 Row = 160, Col = 249, Data = 34980769
|
# READ STATUS: Burst-No: 2 Addr: 000a0fdc Rxd: 7bd261f7
|
# READ STATUS: Burst-No: 2 Addr: 000a0fdc Rxd: 7bd261f7
|
# tb_core.u_sdram32 : at time 24323.0 ns READ : Bank = 3 Row = 160, Col = 250, Data = da6ebab4
|
# tb_core.u_sdram32 : at time 24853.0 ns READ : Bank = 3 Row = 160, Col = 250, Data = da6ebab4
|
# READ STATUS: Burst-No: 3 Addr: 000a0fde Rxd: 34980769
|
# READ STATUS: Burst-No: 3 Addr: 000a0fde Rxd: 34980769
|
# tb_core.u_sdram32 : at time 24333.0 ns READ : Bank = 3 Row = 160, Col = 251, Data = 44018d88
|
# tb_core.u_sdram32 : at time 24863.0 ns READ : Bank = 3 Row = 160, Col = 251, Data = 44018d88
|
# READ STATUS: Burst-No: 4 Addr: 000a0fe0 Rxd: da6ebab4
|
# READ STATUS: Burst-No: 4 Addr: 000a0fe0 Rxd: da6ebab4
|
# tb_core.u_sdram32 : at time 24343.0 ns READ : Bank = 3 Row = 160, Col = 252, Data = 147cd928
|
# tb_core.u_sdram32 : at time 24873.0 ns READ : Bank = 3 Row = 160, Col = 252, Data = 147cd928
|
# READ STATUS: Burst-No: 5 Addr: 000a0fe2 Rxd: 44018d88
|
# READ STATUS: Burst-No: 5 Addr: 000a0fe2 Rxd: 44018d88
|
# tb_core.u_sdram32 : at time 24353.0 ns READ : Bank = 3 Row = 160, Col = 253, Data = 9690042d
|
# tb_core.u_sdram32 : at time 24883.0 ns READ : Bank = 3 Row = 160, Col = 253, Data = 9690042d
|
# tb_core.u_sdram32 : at time 24357.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 24887.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 6 Addr: 000a0fe4 Rxd: 147cd928
|
# READ STATUS: Burst-No: 6 Addr: 000a0fe4 Rxd: 147cd928
|
# tb_core.u_sdram32 : at time 24363.0 ns READ : Bank = 3 Row = 160, Col = 254, Data = e3c530c7
|
# tb_core.u_sdram32 : at time 24893.0 ns READ : Bank = 3 Row = 160, Col = 254, Data = e3c530c7
|
# READ STATUS: Burst-No: 7 Addr: 000a0fe6 Rxd: 9690042d
|
# READ STATUS: Burst-No: 7 Addr: 000a0fe6 Rxd: 9690042d
|
# tb_core.u_sdram32 : at time 24373.0 ns READ : Bank = 3 Row = 160, Col = 255, Data = 975c9c2e
|
# tb_core.u_sdram32 : at time 24903.0 ns READ : Bank = 3 Row = 160, Col = 255, Data = 975c9c2e
|
# READ STATUS: Burst-No: 8 Addr: 000a0fe8 Rxd: e3c530c7
|
# READ STATUS: Burst-No: 8 Addr: 000a0fe8 Rxd: e3c530c7
|
# READ STATUS: Burst-No: 9 Addr: 000a0fea Rxd: 975c9c2e
|
# READ STATUS: Burst-No: 9 Addr: 000a0fea Rxd: 975c9c2e
|
# tb_core.u_sdram32 : at time 24393.0 ns READ : Bank = 0 Row = 161, Col = 0, Data = 8477e408
|
# tb_core.u_sdram32 : at time 24923.0 ns READ : Bank = 0 Row = 161, Col = 0, Data = 8477e408
|
# tb_core.u_sdram32 : at time 24403.0 ns READ : Bank = 0 Row = 161, Col = 1, Data = 0e41451c
|
# tb_core.u_sdram32 : at time 24933.0 ns READ : Bank = 0 Row = 161, Col = 1, Data = 0e41451c
|
# READ STATUS: Burst-No: 10 Addr: 000a0fec Rxd: 8477e408
|
# READ STATUS: Burst-No: 10 Addr: 000a0fec Rxd: 8477e408
|
# tb_core.u_sdram32 : at time 24413.0 ns READ : Bank = 0 Row = 161, Col = 2, Data = fea7a6fd
|
# tb_core.u_sdram32 : at time 24943.0 ns READ : Bank = 0 Row = 161, Col = 2, Data = fea7a6fd
|
# tb_core.u_sdram32 : at time 24417.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 24947.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 11 Addr: 000a0fee Rxd: 0e41451c
|
# READ STATUS: Burst-No: 11 Addr: 000a0fee Rxd: 0e41451c
|
# tb_core.u_sdram32 : at time 24423.0 ns READ : Bank = 0 Row = 161, Col = 3, Data = 149e0729
|
# tb_core.u_sdram32 : at time 24953.0 ns READ : Bank = 0 Row = 161, Col = 3, Data = 149e0729
|
# READ STATUS: Burst-No: 12 Addr: 000a0ff0 Rxd: fea7a6fd
|
# READ STATUS: Burst-No: 12 Addr: 000a0ff0 Rxd: fea7a6fd
|
# tb_core.u_sdram32 : at time 24433.0 ns READ : Bank = 0 Row = 161, Col = 4, Data = 8e37901c
|
# tb_core.u_sdram32 : at time 24963.0 ns READ : Bank = 0 Row = 161, Col = 4, Data = 8e37901c
|
# READ STATUS: Burst-No: 13 Addr: 000a0ff2 Rxd: 149e0729
|
# READ STATUS: Burst-No: 13 Addr: 000a0ff2 Rxd: 149e0729
|
# READ STATUS: Burst-No: 14 Addr: 000a0ff4 Rxd: 8e37901c
|
# READ STATUS: Burst-No: 14 Addr: 000a0ff4 Rxd: 8e37901c
|
# tb_core.u_sdram32 : at time 24527.0 ns ACT : Bank = 3 Row = 176
|
# tb_core.u_sdram32 : at time 25067.0 ns ACT : Bank = 3 Row = 176
|
# tb_core.u_sdram32 : at time 24537.0 ns ACT : Bank = 0 Row = 177
|
# tb_core.u_sdram32 : at time 25133.0 ns READ : Bank = 3 Row = 176, Col = 247, Data = 43356786
|
# tb_core.u_sdram32 : at time 24537.0 ns ERROR: tRRD violation during Activate bank = 0
|
# tb_core.u_sdram32 : at time 25143.0 ns READ : Bank = 3 Row = 176, Col = 248, Data = ed3408da
|
# tb_core.u_sdram32 : at time 24593.0 ns READ : Bank = 3 Row = 176, Col = 247, Data = 43356786
|
|
# tb_core.u_sdram32 : at time 24603.0 ns READ : Bank = 3 Row = 176, Col = 248, Data = ed3408da
|
|
# READ STATUS: Burst-No: 0 Addr: 000b0fdc Rxd: 43356786
|
# READ STATUS: Burst-No: 0 Addr: 000b0fdc Rxd: 43356786
|
# tb_core.u_sdram32 : at time 24613.0 ns READ : Bank = 3 Row = 176, Col = 249, Data = 9eb7c63d
|
# tb_core.u_sdram32 : at time 25153.0 ns READ : Bank = 3 Row = 176, Col = 249, Data = 9eb7c63d
|
# READ STATUS: Burst-No: 1 Addr: 000b0fde Rxd: ed3408da
|
# READ STATUS: Burst-No: 1 Addr: 000b0fde Rxd: ed3408da
|
# tb_core.u_sdram32 : at time 24623.0 ns READ : Bank = 3 Row = 176, Col = 250, Data = 334ea766
|
# tb_core.u_sdram32 : at time 25163.0 ns READ : Bank = 3 Row = 176, Col = 250, Data = 334ea766
|
# READ STATUS: Burst-No: 2 Addr: 000b0fe0 Rxd: 9eb7c63d
|
# READ STATUS: Burst-No: 2 Addr: 000b0fe0 Rxd: 9eb7c63d
|
# tb_core.u_sdram32 : at time 24633.0 ns READ : Bank = 3 Row = 176, Col = 251, Data = b855c470
|
# tb_core.u_sdram32 : at time 25173.0 ns READ : Bank = 3 Row = 176, Col = 251, Data = b855c470
|
# READ STATUS: Burst-No: 3 Addr: 000b0fe2 Rxd: 334ea766
|
# READ STATUS: Burst-No: 3 Addr: 000b0fe2 Rxd: 334ea766
|
# tb_core.u_sdram32 : at time 24643.0 ns READ : Bank = 3 Row = 176, Col = 252, Data = b9f50473
|
# tb_core.u_sdram32 : at time 25183.0 ns READ : Bank = 3 Row = 176, Col = 252, Data = b9f50473
|
# READ STATUS: Burst-No: 4 Addr: 000b0fe4 Rxd: b855c470
|
# READ STATUS: Burst-No: 4 Addr: 000b0fe4 Rxd: b855c470
|
# tb_core.u_sdram32 : at time 24653.0 ns READ : Bank = 3 Row = 176, Col = 253, Data = 5d7199ba
|
# tb_core.u_sdram32 : at time 25193.0 ns READ : Bank = 3 Row = 176, Col = 253, Data = 5d7199ba
|
# tb_core.u_sdram32 : at time 24657.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 25197.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 5 Addr: 000b0fe6 Rxd: b9f50473
|
# READ STATUS: Burst-No: 5 Addr: 000b0fe6 Rxd: b9f50473
|
# tb_core.u_sdram32 : at time 24663.0 ns READ : Bank = 3 Row = 176, Col = 254, Data = 2f3ab35e
|
# tb_core.u_sdram32 : at time 25203.0 ns READ : Bank = 3 Row = 176, Col = 254, Data = 2f3ab35e
|
# READ STATUS: Burst-No: 6 Addr: 000b0fe8 Rxd: 5d7199ba
|
# READ STATUS: Burst-No: 6 Addr: 000b0fe8 Rxd: 5d7199ba
|
# tb_core.u_sdram32 : at time 24673.0 ns READ : Bank = 3 Row = 176, Col = 255, Data = 7d4779fa
|
# tb_core.u_sdram32 : at time 25213.0 ns READ : Bank = 3 Row = 176, Col = 255, Data = 7d4779fa
|
# READ STATUS: Burst-No: 7 Addr: 000b0fea Rxd: 2f3ab35e
|
# READ STATUS: Burst-No: 7 Addr: 000b0fea Rxd: 2f3ab35e
|
# READ STATUS: Burst-No: 8 Addr: 000b0fec Rxd: 7d4779fa
|
# READ STATUS: Burst-No: 8 Addr: 000b0fec Rxd: 7d4779fa
|
# tb_core.u_sdram32 : at time 24693.0 ns READ : Bank = 0 Row = 177, Col = 0, Data = 6a8e05d5
|
# tb_core.u_sdram32 : at time 25257.0 ns ACT : Bank = 0 Row = 177
|
# tb_core.u_sdram32 : at time 24703.0 ns READ : Bank = 0 Row = 177, Col = 1, Data = 8d24f61a
|
# tb_core.u_sdram32 : at time 25323.0 ns READ : Bank = 0 Row = 177, Col = 0, Data = 6a8e05d5
|
|
# tb_core.u_sdram32 : at time 25333.0 ns READ : Bank = 0 Row = 177, Col = 1, Data = 8d24f61a
|
# READ STATUS: Burst-No: 9 Addr: 000b0fee Rxd: 6a8e05d5
|
# READ STATUS: Burst-No: 9 Addr: 000b0fee Rxd: 6a8e05d5
|
# tb_core.u_sdram32 : at time 24713.0 ns READ : Bank = 0 Row = 177, Col = 2, Data = dcf000b9
|
# tb_core.u_sdram32 : at time 25343.0 ns READ : Bank = 0 Row = 177, Col = 2, Data = dcf000b9
|
# READ STATUS: Burst-No: 10 Addr: 000b0ff0 Rxd: 8d24f61a
|
# READ STATUS: Burst-No: 10 Addr: 000b0ff0 Rxd: 8d24f61a
|
# tb_core.u_sdram32 : at time 24723.0 ns READ : Bank = 0 Row = 177, Col = 3, Data = 1b876137
|
# tb_core.u_sdram32 : at time 25353.0 ns READ : Bank = 0 Row = 177, Col = 3, Data = 1b876137
|
# tb_core.u_sdram32 : at time 24727.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 25357.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 11 Addr: 000b0ff2 Rxd: dcf000b9
|
# READ STATUS: Burst-No: 11 Addr: 000b0ff2 Rxd: dcf000b9
|
# tb_core.u_sdram32 : at time 24733.0 ns READ : Bank = 0 Row = 177, Col = 4, Data = 4b273796
|
# tb_core.u_sdram32 : at time 25363.0 ns READ : Bank = 0 Row = 177, Col = 4, Data = 4b273796
|
# READ STATUS: Burst-No: 12 Addr: 000b0ff4 Rxd: 1b876137
|
# READ STATUS: Burst-No: 12 Addr: 000b0ff4 Rxd: 1b876137
|
# tb_core.u_sdram32 : at time 24743.0 ns READ : Bank = 0 Row = 177, Col = 5, Data = 603921c0
|
# tb_core.u_sdram32 : at time 25373.0 ns READ : Bank = 0 Row = 177, Col = 5, Data = 603921c0
|
# READ STATUS: Burst-No: 13 Addr: 000b0ff6 Rxd: 4b273796
|
# READ STATUS: Burst-No: 13 Addr: 000b0ff6 Rxd: 4b273796
|
# READ STATUS: Burst-No: 14 Addr: 000b0ff8 Rxd: 603921c0
|
# READ STATUS: Burst-No: 14 Addr: 000b0ff8 Rxd: 603921c0
|
# tb_core.u_sdram32 : at time 24837.0 ns ACT : Bank = 3 Row = 192
|
# tb_core.u_sdram32 : at time 25477.0 ns ACT : Bank = 3 Row = 192
|
# tb_core.u_sdram32 : at time 24903.0 ns READ : Bank = 3 Row = 192, Col = 240, Data = 13259f26
|
# tb_core.u_sdram32 : at time 25543.0 ns READ : Bank = 3 Row = 192, Col = 240, Data = 13259f26
|
# tb_core.u_sdram32 : at time 24913.0 ns READ : Bank = 3 Row = 192, Col = 241, Data = db461ab6
|
# tb_core.u_sdram32 : at time 25553.0 ns READ : Bank = 3 Row = 192, Col = 241, Data = db461ab6
|
# READ STATUS: Burst-No: 0 Addr: 000c0fc0 Rxd: 13259f26
|
# READ STATUS: Burst-No: 0 Addr: 000c0fc0 Rxd: 13259f26
|
# tb_core.u_sdram32 : at time 24923.0 ns READ : Bank = 3 Row = 192, Col = 242, Data = 3e99837d
|
# tb_core.u_sdram32 : at time 25563.0 ns READ : Bank = 3 Row = 192, Col = 242, Data = 3e99837d
|
# READ STATUS: Burst-No: 1 Addr: 000c0fc2 Rxd: db461ab6
|
# READ STATUS: Burst-No: 1 Addr: 000c0fc2 Rxd: db461ab6
|
# tb_core.u_sdram32 : at time 24933.0 ns READ : Bank = 3 Row = 192, Col = 243, Data = 6e5f0fdc
|
# tb_core.u_sdram32 : at time 25573.0 ns READ : Bank = 3 Row = 192, Col = 243, Data = 6e5f0fdc
|
# READ STATUS: Burst-No: 2 Addr: 000c0fc4 Rxd: 3e99837d
|
# READ STATUS: Burst-No: 2 Addr: 000c0fc4 Rxd: 3e99837d
|
# tb_core.u_sdram32 : at time 24943.0 ns READ : Bank = 3 Row = 192, Col = 244, Data = 43615786
|
# tb_core.u_sdram32 : at time 25583.0 ns READ : Bank = 3 Row = 192, Col = 244, Data = 43615786
|
# READ STATUS: Burst-No: 3 Addr: 000c0fc6 Rxd: 6e5f0fdc
|
# READ STATUS: Burst-No: 3 Addr: 000c0fc6 Rxd: 6e5f0fdc
|
# tb_core.u_sdram32 : at time 24953.0 ns READ : Bank = 3 Row = 192, Col = 245, Data = 3c03ff78
|
# tb_core.u_sdram32 : at time 25593.0 ns READ : Bank = 3 Row = 192, Col = 245, Data = 3c03ff78
|
# READ STATUS: Burst-No: 4 Addr: 000c0fc8 Rxd: 43615786
|
# READ STATUS: Burst-No: 4 Addr: 000c0fc8 Rxd: 43615786
|
# tb_core.u_sdram32 : at time 24963.0 ns READ : Bank = 3 Row = 192, Col = 246, Data = 3f5a9b7e
|
# tb_core.u_sdram32 : at time 25603.0 ns READ : Bank = 3 Row = 192, Col = 246, Data = 3f5a9b7e
|
# READ STATUS: Burst-No: 5 Addr: 000c0fca Rxd: 3c03ff78
|
# READ STATUS: Burst-No: 5 Addr: 000c0fca Rxd: 3c03ff78
|
# tb_core.u_sdram32 : at time 24973.0 ns READ : Bank = 3 Row = 192, Col = 247, Data = ed8d80db
|
# tb_core.u_sdram32 : at time 25613.0 ns READ : Bank = 3 Row = 192, Col = 247, Data = ed8d80db
|
# READ STATUS: Burst-No: 6 Addr: 000c0fcc Rxd: 3f5a9b7e
|
# READ STATUS: Burst-No: 6 Addr: 000c0fcc Rxd: 3f5a9b7e
|
# tb_core.u_sdram32 : at time 24983.0 ns READ : Bank = 3 Row = 192, Col = 248, Data = e7c3b6cf
|
# tb_core.u_sdram32 : at time 25623.0 ns READ : Bank = 3 Row = 192, Col = 248, Data = e7c3b6cf
|
# READ STATUS: Burst-No: 7 Addr: 000c0fce Rxd: ed8d80db
|
# READ STATUS: Burst-No: 7 Addr: 000c0fce Rxd: ed8d80db
|
# tb_core.u_sdram32 : at time 24993.0 ns READ : Bank = 3 Row = 192, Col = 249, Data = 3ced2b79
|
# tb_core.u_sdram32 : at time 25633.0 ns READ : Bank = 3 Row = 192, Col = 249, Data = 3ced2b79
|
# READ STATUS: Burst-No: 8 Addr: 000c0fd0 Rxd: e7c3b6cf
|
# READ STATUS: Burst-No: 8 Addr: 000c0fd0 Rxd: e7c3b6cf
|
# tb_core.u_sdram32 : at time 25003.0 ns READ : Bank = 3 Row = 192, Col = 250, Data = fd28e4fa
|
# tb_core.u_sdram32 : at time 25643.0 ns READ : Bank = 3 Row = 192, Col = 250, Data = fd28e4fa
|
# READ STATUS: Burst-No: 9 Addr: 000c0fd2 Rxd: 3ced2b79
|
# READ STATUS: Burst-No: 9 Addr: 000c0fd2 Rxd: 3ced2b79
|
# tb_core.u_sdram32 : at time 25013.0 ns READ : Bank = 3 Row = 192, Col = 251, Data = b0bcee61
|
# tb_core.u_sdram32 : at time 25653.0 ns READ : Bank = 3 Row = 192, Col = 251, Data = b0bcee61
|
# READ STATUS: Burst-No: 10 Addr: 000c0fd4 Rxd: fd28e4fa
|
# READ STATUS: Burst-No: 10 Addr: 000c0fd4 Rxd: fd28e4fa
|
# tb_core.u_sdram32 : at time 25023.0 ns READ : Bank = 3 Row = 192, Col = 252, Data = 0b940917
|
# tb_core.u_sdram32 : at time 25663.0 ns READ : Bank = 3 Row = 192, Col = 252, Data = 0b940917
|
# tb_core.u_sdram32 : at time 25027.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 25667.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 11 Addr: 000c0fd6 Rxd: b0bcee61
|
# READ STATUS: Burst-No: 11 Addr: 000c0fd6 Rxd: b0bcee61
|
# tb_core.u_sdram32 : at time 25033.0 ns READ : Bank = 3 Row = 192, Col = 253, Data = d0f578a1
|
# tb_core.u_sdram32 : at time 25673.0 ns READ : Bank = 3 Row = 192, Col = 253, Data = d0f578a1
|
# READ STATUS: Burst-No: 12 Addr: 000c0fd8 Rxd: 0b940917
|
# READ STATUS: Burst-No: 12 Addr: 000c0fd8 Rxd: 0b940917
|
# tb_core.u_sdram32 : at time 25043.0 ns READ : Bank = 3 Row = 192, Col = 254, Data = 43779186
|
# tb_core.u_sdram32 : at time 25683.0 ns READ : Bank = 3 Row = 192, Col = 254, Data = 43779186
|
# READ STATUS: Burst-No: 13 Addr: 000c0fda Rxd: d0f578a1
|
# READ STATUS: Burst-No: 13 Addr: 000c0fda Rxd: d0f578a1
|
# READ STATUS: Burst-No: 14 Addr: 000c0fdc Rxd: 43779186
|
# READ STATUS: Burst-No: 14 Addr: 000c0fdc Rxd: 43779186
|
# tb_core.u_sdram32 : at time 25137.0 ns ACT : Bank = 3 Row = 208
|
# tb_core.u_sdram32 : at time 25717.0 ns AREF : Auto Refresh
|
# tb_core.u_sdram32 : at time 25203.0 ns READ : Bank = 3 Row = 208, Col = 241, Data = a8639650
|
# tb_core.u_sdram32 : at time 25807.0 ns AREF : Auto Refresh
|
# tb_core.u_sdram32 : at time 25213.0 ns READ : Bank = 3 Row = 208, Col = 242, Data = 7a8c59f5
|
# tb_core.u_sdram32 : at time 25897.0 ns AREF : Auto Refresh
|
|
# tb_core.u_sdram32 : at time 25987.0 ns AREF : Auto Refresh
|
|
# tb_core.u_sdram32 : at time 26077.0 ns AREF : Auto Refresh
|
|
# tb_core.u_sdram32 : at time 26167.0 ns AREF : Auto Refresh
|
|
# tb_core.u_sdram32 : at time 26297.0 ns ACT : Bank = 3 Row = 208
|
|
# tb_core.u_sdram32 : at time 26363.0 ns READ : Bank = 3 Row = 208, Col = 241, Data = a8639650
|
|
# tb_core.u_sdram32 : at time 26373.0 ns READ : Bank = 3 Row = 208, Col = 242, Data = 7a8c59f5
|
# READ STATUS: Burst-No: 0 Addr: 000d0fc4 Rxd: a8639650
|
# READ STATUS: Burst-No: 0 Addr: 000d0fc4 Rxd: a8639650
|
# tb_core.u_sdram32 : at time 25223.0 ns READ : Bank = 3 Row = 208, Col = 243, Data = 9ab48835
|
# tb_core.u_sdram32 : at time 26383.0 ns READ : Bank = 3 Row = 208, Col = 243, Data = 9ab48835
|
# READ STATUS: Burst-No: 1 Addr: 000d0fc6 Rxd: 7a8c59f5
|
# READ STATUS: Burst-No: 1 Addr: 000d0fc6 Rxd: 7a8c59f5
|
# tb_core.u_sdram32 : at time 25233.0 ns READ : Bank = 3 Row = 208, Col = 244, Data = 949a8a29
|
# tb_core.u_sdram32 : at time 26393.0 ns READ : Bank = 3 Row = 208, Col = 244, Data = 949a8a29
|
# READ STATUS: Burst-No: 2 Addr: 000d0fc8 Rxd: 9ab48835
|
# READ STATUS: Burst-No: 2 Addr: 000d0fc8 Rxd: 9ab48835
|
# tb_core.u_sdram32 : at time 25243.0 ns READ : Bank = 3 Row = 208, Col = 245, Data = 60b175c1
|
# tb_core.u_sdram32 : at time 26403.0 ns READ : Bank = 3 Row = 208, Col = 245, Data = 60b175c1
|
# READ STATUS: Burst-No: 3 Addr: 000d0fca Rxd: 949a8a29
|
# READ STATUS: Burst-No: 3 Addr: 000d0fca Rxd: 949a8a29
|
# tb_core.u_sdram32 : at time 25253.0 ns READ : Bank = 3 Row = 208, Col = 246, Data = e2e574c5
|
# tb_core.u_sdram32 : at time 26413.0 ns READ : Bank = 3 Row = 208, Col = 246, Data = e2e574c5
|
# READ STATUS: Burst-No: 4 Addr: 000d0fcc Rxd: 60b175c1
|
# READ STATUS: Burst-No: 4 Addr: 000d0fcc Rxd: 60b175c1
|
# tb_core.u_sdram32 : at time 25263.0 ns READ : Bank = 3 Row = 208, Col = 247, Data = cc01b498
|
# tb_core.u_sdram32 : at time 26423.0 ns READ : Bank = 3 Row = 208, Col = 247, Data = cc01b498
|
# READ STATUS: Burst-No: 5 Addr: 000d0fce Rxd: e2e574c5
|
# READ STATUS: Burst-No: 5 Addr: 000d0fce Rxd: e2e574c5
|
# tb_core.u_sdram32 : at time 25273.0 ns READ : Bank = 3 Row = 208, Col = 248, Data = 25b27b4b
|
# tb_core.u_sdram32 : at time 26433.0 ns READ : Bank = 3 Row = 208, Col = 248, Data = 25b27b4b
|
# READ STATUS: Burst-No: 6 Addr: 000d0fd0 Rxd: cc01b498
|
# READ STATUS: Burst-No: 6 Addr: 000d0fd0 Rxd: cc01b498
|
# tb_core.u_sdram32 : at time 25283.0 ns READ : Bank = 3 Row = 208, Col = 249, Data = b98c4273
|
# tb_core.u_sdram32 : at time 26443.0 ns READ : Bank = 3 Row = 208, Col = 249, Data = b98c4273
|
# READ STATUS: Burst-No: 7 Addr: 000d0fd2 Rxd: 25b27b4b
|
# READ STATUS: Burst-No: 7 Addr: 000d0fd2 Rxd: 25b27b4b
|
# tb_core.u_sdram32 : at time 25293.0 ns READ : Bank = 3 Row = 208, Col = 250, Data = f622e6ec
|
# tb_core.u_sdram32 : at time 26453.0 ns READ : Bank = 3 Row = 208, Col = 250, Data = f622e6ec
|
# READ STATUS: Burst-No: 8 Addr: 000d0fd4 Rxd: b98c4273
|
# READ STATUS: Burst-No: 8 Addr: 000d0fd4 Rxd: b98c4273
|
# tb_core.u_sdram32 : at time 25303.0 ns READ : Bank = 3 Row = 208, Col = 251, Data = c550168a
|
# tb_core.u_sdram32 : at time 26463.0 ns READ : Bank = 3 Row = 208, Col = 251, Data = c550168a
|
# READ STATUS: Burst-No: 9 Addr: 000d0fd6 Rxd: f622e6ec
|
# READ STATUS: Burst-No: 9 Addr: 000d0fd6 Rxd: f622e6ec
|
# tb_core.u_sdram32 : at time 25313.0 ns READ : Bank = 3 Row = 208, Col = 252, Data = 2758d14e
|
# tb_core.u_sdram32 : at time 26473.0 ns READ : Bank = 3 Row = 208, Col = 252, Data = 2758d14e
|
# READ STATUS: Burst-No: 10 Addr: 000d0fd8 Rxd: c550168a
|
# READ STATUS: Burst-No: 10 Addr: 000d0fd8 Rxd: c550168a
|
# tb_core.u_sdram32 : at time 25323.0 ns READ : Bank = 3 Row = 208, Col = 253, Data = d44b80a8
|
# tb_core.u_sdram32 : at time 26483.0 ns READ : Bank = 3 Row = 208, Col = 253, Data = d44b80a8
|
# tb_core.u_sdram32 : at time 25327.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 26487.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 11 Addr: 000d0fda Rxd: 2758d14e
|
# READ STATUS: Burst-No: 11 Addr: 000d0fda Rxd: 2758d14e
|
# tb_core.u_sdram32 : at time 25333.0 ns READ : Bank = 3 Row = 208, Col = 254, Data = 549efda9
|
# tb_core.u_sdram32 : at time 26493.0 ns READ : Bank = 3 Row = 208, Col = 254, Data = 549efda9
|
# READ STATUS: Burst-No: 12 Addr: 000d0fdc Rxd: d44b80a8
|
# READ STATUS: Burst-No: 12 Addr: 000d0fdc Rxd: d44b80a8
|
# tb_core.u_sdram32 : at time 25343.0 ns READ : Bank = 3 Row = 208, Col = 255, Data = d0ca8ca1
|
# tb_core.u_sdram32 : at time 26503.0 ns READ : Bank = 3 Row = 208, Col = 255, Data = d0ca8ca1
|
# READ STATUS: Burst-No: 13 Addr: 000d0fde Rxd: 549efda9
|
# READ STATUS: Burst-No: 13 Addr: 000d0fde Rxd: 549efda9
|
# READ STATUS: Burst-No: 14 Addr: 000d0fe0 Rxd: d0ca8ca1
|
# READ STATUS: Burst-No: 14 Addr: 000d0fe0 Rxd: d0ca8ca1
|
# tb_core.u_sdram32 : at time 25437.0 ns ACT : Bank = 3 Row = 224
|
# tb_core.u_sdram32 : at time 26607.0 ns ACT : Bank = 3 Row = 224
|
# tb_core.u_sdram32 : at time 25447.0 ns ACT : Bank = 0 Row = 225
|
# tb_core.u_sdram32 : at time 26673.0 ns READ : Bank = 3 Row = 224, Col = 242, Data = 070bb90e
|
# tb_core.u_sdram32 : at time 25447.0 ns ERROR: tRRD violation during Activate bank = 0
|
# tb_core.u_sdram32 : at time 26683.0 ns READ : Bank = 3 Row = 224, Col = 243, Data = f33466e6
|
# tb_core.u_sdram32 : at time 25503.0 ns READ : Bank = 3 Row = 224, Col = 242, Data = 070bb90e
|
|
# tb_core.u_sdram32 : at time 25513.0 ns READ : Bank = 3 Row = 224, Col = 243, Data = f33466e6
|
|
# READ STATUS: Burst-No: 0 Addr: 000e0fc8 Rxd: 070bb90e
|
# READ STATUS: Burst-No: 0 Addr: 000e0fc8 Rxd: 070bb90e
|
# tb_core.u_sdram32 : at time 25523.0 ns READ : Bank = 3 Row = 224, Col = 244, Data = cfd6c09f
|
# tb_core.u_sdram32 : at time 26693.0 ns READ : Bank = 3 Row = 224, Col = 244, Data = cfd6c09f
|
|
# tb_core.u_sdram32 : at time 26697.0 ns ACT : Bank = 0 Row = 225
|
# READ STATUS: Burst-No: 1 Addr: 000e0fca Rxd: f33466e6
|
# READ STATUS: Burst-No: 1 Addr: 000e0fca Rxd: f33466e6
|
# tb_core.u_sdram32 : at time 25533.0 ns READ : Bank = 3 Row = 224, Col = 245, Data = 152fb52a
|
# tb_core.u_sdram32 : at time 26703.0 ns READ : Bank = 3 Row = 224, Col = 245, Data = 152fb52a
|
# READ STATUS: Burst-No: 2 Addr: 000e0fcc Rxd: cfd6c09f
|
# READ STATUS: Burst-No: 2 Addr: 000e0fcc Rxd: cfd6c09f
|
# tb_core.u_sdram32 : at time 25543.0 ns READ : Bank = 3 Row = 224, Col = 246, Data = 155a1d2a
|
# tb_core.u_sdram32 : at time 26713.0 ns READ : Bank = 3 Row = 224, Col = 246, Data = 155a1d2a
|
# READ STATUS: Burst-No: 3 Addr: 000e0fce Rxd: 152fb52a
|
# READ STATUS: Burst-No: 3 Addr: 000e0fce Rxd: 152fb52a
|
# tb_core.u_sdram32 : at time 25553.0 ns READ : Bank = 3 Row = 224, Col = 247, Data = c6b5f48d
|
# tb_core.u_sdram32 : at time 26723.0 ns READ : Bank = 3 Row = 224, Col = 247, Data = c6b5f48d
|
# READ STATUS: Burst-No: 4 Addr: 000e0fd0 Rxd: 155a1d2a
|
# READ STATUS: Burst-No: 4 Addr: 000e0fd0 Rxd: 155a1d2a
|
# tb_core.u_sdram32 : at time 25563.0 ns READ : Bank = 3 Row = 224, Col = 248, Data = 4f75ff9e
|
# tb_core.u_sdram32 : at time 26733.0 ns READ : Bank = 3 Row = 224, Col = 248, Data = 4f75ff9e
|
# READ STATUS: Burst-No: 5 Addr: 000e0fd2 Rxd: c6b5f48d
|
# READ STATUS: Burst-No: 5 Addr: 000e0fd2 Rxd: c6b5f48d
|
# tb_core.u_sdram32 : at time 25573.0 ns READ : Bank = 3 Row = 224, Col = 249, Data = 9c6de638
|
# tb_core.u_sdram32 : at time 26743.0 ns READ : Bank = 3 Row = 224, Col = 249, Data = 9c6de638
|
# READ STATUS: Burst-No: 6 Addr: 000e0fd4 Rxd: 4f75ff9e
|
# READ STATUS: Burst-No: 6 Addr: 000e0fd4 Rxd: 4f75ff9e
|
# tb_core.u_sdram32 : at time 25583.0 ns READ : Bank = 3 Row = 224, Col = 250, Data = bccfa879
|
# tb_core.u_sdram32 : at time 26753.0 ns READ : Bank = 3 Row = 224, Col = 250, Data = bccfa879
|
# READ STATUS: Burst-No: 7 Addr: 000e0fd6 Rxd: 9c6de638
|
# READ STATUS: Burst-No: 7 Addr: 000e0fd6 Rxd: 9c6de638
|
# tb_core.u_sdram32 : at time 25593.0 ns READ : Bank = 3 Row = 224, Col = 251, Data = 6464e3c8
|
# tb_core.u_sdram32 : at time 26763.0 ns READ : Bank = 3 Row = 224, Col = 251, Data = 6464e3c8
|
# READ STATUS: Burst-No: 8 Addr: 000e0fd8 Rxd: bccfa879
|
# READ STATUS: Burst-No: 8 Addr: 000e0fd8 Rxd: bccfa879
|
# tb_core.u_sdram32 : at time 25603.0 ns READ : Bank = 3 Row = 224, Col = 252, Data = 652345ca
|
# tb_core.u_sdram32 : at time 26773.0 ns READ : Bank = 3 Row = 224, Col = 252, Data = 652345ca
|
# READ STATUS: Burst-No: 9 Addr: 000e0fda Rxd: 6464e3c8
|
# READ STATUS: Burst-No: 9 Addr: 000e0fda Rxd: 6464e3c8
|
# tb_core.u_sdram32 : at time 25613.0 ns READ : Bank = 3 Row = 224, Col = 253, Data = 09ff4113
|
# tb_core.u_sdram32 : at time 26783.0 ns READ : Bank = 3 Row = 224, Col = 253, Data = 09ff4113
|
# tb_core.u_sdram32 : at time 25617.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 26787.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 10 Addr: 000e0fdc Rxd: 652345ca
|
# READ STATUS: Burst-No: 10 Addr: 000e0fdc Rxd: 652345ca
|
# tb_core.u_sdram32 : at time 25623.0 ns READ : Bank = 3 Row = 224, Col = 254, Data = 35a0c96b
|
# tb_core.u_sdram32 : at time 26793.0 ns READ : Bank = 3 Row = 224, Col = 254, Data = 35a0c96b
|
# READ STATUS: Burst-No: 11 Addr: 000e0fde Rxd: 09ff4113
|
# READ STATUS: Burst-No: 11 Addr: 000e0fde Rxd: 09ff4113
|
# tb_core.u_sdram32 : at time 25633.0 ns READ : Bank = 3 Row = 224, Col = 255, Data = e3b7aec7
|
# tb_core.u_sdram32 : at time 26803.0 ns READ : Bank = 3 Row = 224, Col = 255, Data = e3b7aec7
|
|
# tb_core.u_sdram32 : at time 26807.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 12 Addr: 000e0fe0 Rxd: 35a0c96b
|
# READ STATUS: Burst-No: 12 Addr: 000e0fe0 Rxd: 35a0c96b
|
# READ STATUS: Burst-No: 13 Addr: 000e0fe2 Rxd: e3b7aec7
|
# READ STATUS: Burst-No: 13 Addr: 000e0fe2 Rxd: e3b7aec7
|
# tb_core.u_sdram32 : at time 25667.0 ns AREF : Auto Refresh
|
# tb_core.u_sdram32 : at time 26823.0 ns READ : Bank = 0 Row = 225, Col = 0, Data = 5b0bddb6
|
# tb_core.u_sdram32 : at time 25757.0 ns AREF : Auto Refresh
|
|
# tb_core.u_sdram32 : at time 25847.0 ns AREF : Auto Refresh
|
|
# tb_core.u_sdram32 : at time 25937.0 ns AREF : Auto Refresh
|
|
# tb_core.u_sdram32 : at time 26027.0 ns AREF : Auto Refresh
|
|
# tb_core.u_sdram32 : at time 26117.0 ns AREF : Auto Refresh
|
|
# tb_core.u_sdram32 : at time 26207.0 ns ACT : Bank = 0 Row = 225
|
|
# tb_core.u_sdram32 : at time 26257.0 ns BST : Burst Terminate
|
|
# tb_core.u_sdram32 : at time 26273.0 ns READ : Bank = 0 Row = 225, Col = 0, Data = 5b0bddb6
|
|
# READ STATUS: Burst-No: 14 Addr: 000e0fe4 Rxd: 5b0bddb6
|
# READ STATUS: Burst-No: 14 Addr: 000e0fe4 Rxd: 5b0bddb6
|
# tb_core.u_sdram32 : at time 26367.0 ns ACT : Bank = 3 Row = 240
|
# tb_core.u_sdram32 : at time 26927.0 ns ACT : Bank = 3 Row = 240
|
# tb_core.u_sdram32 : at time 26377.0 ns ACT : Bank = 0 Row = 241
|
# tb_core.u_sdram32 : at time 26993.0 ns READ : Bank = 3 Row = 240, Col = 243, Data = 5d059dba
|
# tb_core.u_sdram32 : at time 26377.0 ns ERROR: tRRD violation during Activate bank = 0
|
# tb_core.u_sdram32 : at time 27003.0 ns READ : Bank = 3 Row = 240, Col = 244, Data = 6216abc4
|
# tb_core.u_sdram32 : at time 26433.0 ns READ : Bank = 3 Row = 240, Col = 243, Data = 5d059dba
|
|
# tb_core.u_sdram32 : at time 26443.0 ns READ : Bank = 3 Row = 240, Col = 244, Data = 6216abc4
|
|
# READ STATUS: Burst-No: 0 Addr: 000f0fcc Rxd: 5d059dba
|
# READ STATUS: Burst-No: 0 Addr: 000f0fcc Rxd: 5d059dba
|
# tb_core.u_sdram32 : at time 26453.0 ns READ : Bank = 3 Row = 240, Col = 245, Data = 5c8295b9
|
# tb_core.u_sdram32 : at time 27013.0 ns READ : Bank = 3 Row = 240, Col = 245, Data = 5c8295b9
|
# READ STATUS: Burst-No: 1 Addr: 000f0fce Rxd: 6216abc4
|
# READ STATUS: Burst-No: 1 Addr: 000f0fce Rxd: 6216abc4
|
# tb_core.u_sdram32 : at time 26463.0 ns READ : Bank = 3 Row = 240, Col = 246, Data = 492fd392
|
# tb_core.u_sdram32 : at time 27023.0 ns READ : Bank = 3 Row = 240, Col = 246, Data = 492fd392
|
# READ STATUS: Burst-No: 2 Addr: 000f0fd0 Rxd: 5c8295b9
|
# READ STATUS: Burst-No: 2 Addr: 000f0fd0 Rxd: 5c8295b9
|
# tb_core.u_sdram32 : at time 26473.0 ns READ : Bank = 3 Row = 240, Col = 247, Data = da269ab4
|
# tb_core.u_sdram32 : at time 27033.0 ns READ : Bank = 3 Row = 240, Col = 247, Data = da269ab4
|
# READ STATUS: Burst-No: 3 Addr: 000f0fd2 Rxd: 492fd392
|
# READ STATUS: Burst-No: 3 Addr: 000f0fd2 Rxd: 492fd392
|
# tb_core.u_sdram32 : at time 26483.0 ns READ : Bank = 3 Row = 240, Col = 248, Data = 3fbb3b7f
|
# tb_core.u_sdram32 : at time 27043.0 ns READ : Bank = 3 Row = 240, Col = 248, Data = 3fbb3b7f
|
# READ STATUS: Burst-No: 4 Addr: 000f0fd4 Rxd: da269ab4
|
# READ STATUS: Burst-No: 4 Addr: 000f0fd4 Rxd: da269ab4
|
# tb_core.u_sdram32 : at time 26493.0 ns READ : Bank = 3 Row = 240, Col = 249, Data = c3339086
|
# tb_core.u_sdram32 : at time 27053.0 ns READ : Bank = 3 Row = 240, Col = 249, Data = c3339086
|
# READ STATUS: Burst-No: 5 Addr: 000f0fd6 Rxd: 3fbb3b7f
|
# READ STATUS: Burst-No: 5 Addr: 000f0fd6 Rxd: 3fbb3b7f
|
# tb_core.u_sdram32 : at time 26503.0 ns READ : Bank = 3 Row = 240, Col = 250, Data = 7d6df5fa
|
# tb_core.u_sdram32 : at time 27063.0 ns READ : Bank = 3 Row = 240, Col = 250, Data = 7d6df5fa
|
# READ STATUS: Burst-No: 6 Addr: 000f0fd8 Rxd: c3339086
|
# READ STATUS: Burst-No: 6 Addr: 000f0fd8 Rxd: c3339086
|
# tb_core.u_sdram32 : at time 26513.0 ns READ : Bank = 3 Row = 240, Col = 251, Data = f92794f2
|
# tb_core.u_sdram32 : at time 27073.0 ns READ : Bank = 3 Row = 240, Col = 251, Data = f92794f2
|
# READ STATUS: Burst-No: 7 Addr: 000f0fda Rxd: 7d6df5fa
|
# READ STATUS: Burst-No: 7 Addr: 000f0fda Rxd: 7d6df5fa
|
# tb_core.u_sdram32 : at time 26523.0 ns READ : Bank = 3 Row = 240, Col = 252, Data = 19452132
|
# tb_core.u_sdram32 : at time 27083.0 ns READ : Bank = 3 Row = 240, Col = 252, Data = 19452132
|
# READ STATUS: Burst-No: 8 Addr: 000f0fdc Rxd: f92794f2
|
# READ STATUS: Burst-No: 8 Addr: 000f0fdc Rxd: f92794f2
|
# tb_core.u_sdram32 : at time 26533.0 ns READ : Bank = 3 Row = 240, Col = 253, Data = dece5ebd
|
# tb_core.u_sdram32 : at time 27093.0 ns READ : Bank = 3 Row = 240, Col = 253, Data = dece5ebd
|
# tb_core.u_sdram32 : at time 26537.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 27097.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 9 Addr: 000f0fde Rxd: 19452132
|
# READ STATUS: Burst-No: 9 Addr: 000f0fde Rxd: 19452132
|
# tb_core.u_sdram32 : at time 26543.0 ns READ : Bank = 3 Row = 240, Col = 254, Data = 424fcd84
|
# tb_core.u_sdram32 : at time 27103.0 ns READ : Bank = 3 Row = 240, Col = 254, Data = 424fcd84
|
# READ STATUS: Burst-No: 10 Addr: 000f0fe0 Rxd: dece5ebd
|
# READ STATUS: Burst-No: 10 Addr: 000f0fe0 Rxd: dece5ebd
|
# tb_core.u_sdram32 : at time 26553.0 ns READ : Bank = 3 Row = 240, Col = 255, Data = f249a4e4
|
# tb_core.u_sdram32 : at time 27113.0 ns READ : Bank = 3 Row = 240, Col = 255, Data = f249a4e4
|
# READ STATUS: Burst-No: 11 Addr: 000f0fe2 Rxd: 424fcd84
|
# READ STATUS: Burst-No: 11 Addr: 000f0fe2 Rxd: 424fcd84
|
# tb_core.u_sdram32 : at time 26567.0 ns BST : Burst Terminate
|
|
# READ STATUS: Burst-No: 12 Addr: 000f0fe4 Rxd: f249a4e4
|
# READ STATUS: Burst-No: 12 Addr: 000f0fe4 Rxd: f249a4e4
|
# tb_core.u_sdram32 : at time 26573.0 ns READ : Bank = 0 Row = 241, Col = 0, Data = 6543cfca
|
# tb_core.u_sdram32 : at time 27157.0 ns ACT : Bank = 0 Row = 241
|
# tb_core.u_sdram32 : at time 26583.0 ns READ : Bank = 0 Row = 241, Col = 1, Data = 54a879a9
|
# tb_core.u_sdram32 : at time 27217.0 ns BST : Burst Terminate
|
|
# tb_core.u_sdram32 : at time 27223.0 ns READ : Bank = 0 Row = 241, Col = 0, Data = 6543cfca
|
|
# tb_core.u_sdram32 : at time 27233.0 ns READ : Bank = 0 Row = 241, Col = 1, Data = 54a879a9
|
# READ STATUS: Burst-No: 13 Addr: 000f0fe6 Rxd: 6543cfca
|
# READ STATUS: Burst-No: 13 Addr: 000f0fe6 Rxd: 6543cfca
|
# READ STATUS: Burst-No: 14 Addr: 000f0fe8 Rxd: 54a879a9
|
# READ STATUS: Burst-No: 14 Addr: 000f0fe8 Rxd: 54a879a9
|
# tb_core.u_sdram32 : at time 26677.0 ns ACT : Bank = 3 Row = 256
|
# tb_core.u_sdram32 : at time 27337.0 ns ACT : Bank = 3 Row = 256
|
# tb_core.u_sdram32 : at time 26743.0 ns READ : Bank = 3 Row = 256, Col = 236, Data = d095a8a1
|
# tb_core.u_sdram32 : at time 27403.0 ns READ : Bank = 3 Row = 256, Col = 236, Data = d095a8a1
|
# tb_core.u_sdram32 : at time 26753.0 ns READ : Bank = 3 Row = 256, Col = 237, Data = 4765a98e
|
# tb_core.u_sdram32 : at time 27413.0 ns READ : Bank = 3 Row = 256, Col = 237, Data = 4765a98e
|
# READ STATUS: Burst-No: 0 Addr: 00100fb0 Rxd: d095a8a1
|
# READ STATUS: Burst-No: 0 Addr: 00100fb0 Rxd: d095a8a1
|
# tb_core.u_sdram32 : at time 26763.0 ns READ : Bank = 3 Row = 256, Col = 238, Data = fd8b6afb
|
# tb_core.u_sdram32 : at time 27423.0 ns READ : Bank = 3 Row = 256, Col = 238, Data = fd8b6afb
|
# READ STATUS: Burst-No: 1 Addr: 00100fb2 Rxd: 4765a98e
|
# READ STATUS: Burst-No: 1 Addr: 00100fb2 Rxd: 4765a98e
|
# tb_core.u_sdram32 : at time 26773.0 ns READ : Bank = 3 Row = 256, Col = 239, Data = 85e51e0b
|
# tb_core.u_sdram32 : at time 27433.0 ns READ : Bank = 3 Row = 256, Col = 239, Data = 85e51e0b
|
# READ STATUS: Burst-No: 2 Addr: 00100fb4 Rxd: fd8b6afb
|
# READ STATUS: Burst-No: 2 Addr: 00100fb4 Rxd: fd8b6afb
|
# tb_core.u_sdram32 : at time 26783.0 ns READ : Bank = 3 Row = 256, Col = 240, Data = f78290ef
|
# tb_core.u_sdram32 : at time 27443.0 ns READ : Bank = 3 Row = 256, Col = 240, Data = f78290ef
|
# READ STATUS: Burst-No: 3 Addr: 00100fb6 Rxd: 85e51e0b
|
# READ STATUS: Burst-No: 3 Addr: 00100fb6 Rxd: 85e51e0b
|
# tb_core.u_sdram32 : at time 26793.0 ns READ : Bank = 3 Row = 256, Col = 241, Data = 64c83dc9
|
# tb_core.u_sdram32 : at time 27453.0 ns READ : Bank = 3 Row = 256, Col = 241, Data = 64c83dc9
|
# READ STATUS: Burst-No: 4 Addr: 00100fb8 Rxd: f78290ef
|
# READ STATUS: Burst-No: 4 Addr: 00100fb8 Rxd: f78290ef
|
# tb_core.u_sdram32 : at time 26803.0 ns READ : Bank = 3 Row = 256, Col = 242, Data = 1b60e536
|
# tb_core.u_sdram32 : at time 27463.0 ns READ : Bank = 3 Row = 256, Col = 242, Data = 1b60e536
|
# READ STATUS: Burst-No: 5 Addr: 00100fba Rxd: 64c83dc9
|
# READ STATUS: Burst-No: 5 Addr: 00100fba Rxd: 64c83dc9
|
# tb_core.u_sdram32 : at time 26813.0 ns READ : Bank = 3 Row = 256, Col = 243, Data = bab14875
|
# tb_core.u_sdram32 : at time 27473.0 ns READ : Bank = 3 Row = 256, Col = 243, Data = bab14875
|
# READ STATUS: Burst-No: 6 Addr: 00100fbc Rxd: 1b60e536
|
# READ STATUS: Burst-No: 6 Addr: 00100fbc Rxd: 1b60e536
|
# tb_core.u_sdram32 : at time 26823.0 ns READ : Bank = 3 Row = 256, Col = 244, Data = c7e8568f
|
# tb_core.u_sdram32 : at time 27483.0 ns READ : Bank = 3 Row = 256, Col = 244, Data = c7e8568f
|
# READ STATUS: Burst-No: 7 Addr: 00100fbe Rxd: bab14875
|
# READ STATUS: Burst-No: 7 Addr: 00100fbe Rxd: bab14875
|
# tb_core.u_sdram32 : at time 26833.0 ns READ : Bank = 3 Row = 256, Col = 245, Data = 35cdbf6b
|
# tb_core.u_sdram32 : at time 27493.0 ns READ : Bank = 3 Row = 256, Col = 245, Data = 35cdbf6b
|
# READ STATUS: Burst-No: 8 Addr: 00100fc0 Rxd: c7e8568f
|
# READ STATUS: Burst-No: 8 Addr: 00100fc0 Rxd: c7e8568f
|
# tb_core.u_sdram32 : at time 26843.0 ns READ : Bank = 3 Row = 256, Col = 246, Data = 4465e788
|
# tb_core.u_sdram32 : at time 27503.0 ns READ : Bank = 3 Row = 256, Col = 246, Data = 4465e788
|
# READ STATUS: Burst-No: 9 Addr: 00100fc2 Rxd: 35cdbf6b
|
# READ STATUS: Burst-No: 9 Addr: 00100fc2 Rxd: 35cdbf6b
|
# tb_core.u_sdram32 : at time 26853.0 ns READ : Bank = 3 Row = 256, Col = 247, Data = d73fb4ae
|
# tb_core.u_sdram32 : at time 27513.0 ns READ : Bank = 3 Row = 256, Col = 247, Data = d73fb4ae
|
# READ STATUS: Burst-No: 10 Addr: 00100fc4 Rxd: 4465e788
|
# READ STATUS: Burst-No: 10 Addr: 00100fc4 Rxd: 4465e788
|
# tb_core.u_sdram32 : at time 26863.0 ns READ : Bank = 3 Row = 256, Col = 248, Data = 4df3819b
|
# tb_core.u_sdram32 : at time 27523.0 ns READ : Bank = 3 Row = 256, Col = 248, Data = 4df3819b
|
# tb_core.u_sdram32 : at time 26867.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 27527.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 11 Addr: 00100fc6 Rxd: d73fb4ae
|
# READ STATUS: Burst-No: 11 Addr: 00100fc6 Rxd: d73fb4ae
|
# tb_core.u_sdram32 : at time 26873.0 ns READ : Bank = 3 Row = 256, Col = 249, Data = 493e4592
|
# tb_core.u_sdram32 : at time 27533.0 ns READ : Bank = 3 Row = 256, Col = 249, Data = 493e4592
|
# READ STATUS: Burst-No: 12 Addr: 00100fc8 Rxd: 4df3819b
|
# READ STATUS: Burst-No: 12 Addr: 00100fc8 Rxd: 4df3819b
|
# tb_core.u_sdram32 : at time 26883.0 ns READ : Bank = 3 Row = 256, Col = 250, Data = 1444df28
|
# tb_core.u_sdram32 : at time 27543.0 ns READ : Bank = 3 Row = 256, Col = 250, Data = 1444df28
|
# READ STATUS: Burst-No: 13 Addr: 00100fca Rxd: 493e4592
|
# READ STATUS: Burst-No: 13 Addr: 00100fca Rxd: 493e4592
|
# READ STATUS: Burst-No: 14 Addr: 00100fcc Rxd: 1444df28
|
# READ STATUS: Burst-No: 14 Addr: 00100fcc Rxd: 1444df28
|
# tb_core.u_sdram32 : at time 26977.0 ns ACT : Bank = 3 Row = 272
|
# tb_core.u_sdram32 : at time 27647.0 ns ACT : Bank = 3 Row = 272
|
# tb_core.u_sdram32 : at time 27043.0 ns READ : Bank = 3 Row = 272, Col = 237, Data = 9684e02d
|
# tb_core.u_sdram32 : at time 27713.0 ns READ : Bank = 3 Row = 272, Col = 237, Data = 9684e02d
|
# tb_core.u_sdram32 : at time 27053.0 ns READ : Bank = 3 Row = 272, Col = 238, Data = 25b75f4b
|
# tb_core.u_sdram32 : at time 27723.0 ns READ : Bank = 3 Row = 272, Col = 238, Data = 25b75f4b
|
# READ STATUS: Burst-No: 0 Addr: 00110fb4 Rxd: 9684e02d
|
# READ STATUS: Burst-No: 0 Addr: 00110fb4 Rxd: 9684e02d
|
# tb_core.u_sdram32 : at time 27063.0 ns READ : Bank = 3 Row = 272, Col = 239, Data = e169b0c2
|
# tb_core.u_sdram32 : at time 27733.0 ns READ : Bank = 3 Row = 272, Col = 239, Data = e169b0c2
|
# READ STATUS: Burst-No: 1 Addr: 00110fb6 Rxd: 25b75f4b
|
# READ STATUS: Burst-No: 1 Addr: 00110fb6 Rxd: 25b75f4b
|
# tb_core.u_sdram32 : at time 27073.0 ns READ : Bank = 3 Row = 272, Col = 240, Data = 8f1cf61e
|
# tb_core.u_sdram32 : at time 27743.0 ns READ : Bank = 3 Row = 272, Col = 240, Data = 8f1cf61e
|
# READ STATUS: Burst-No: 2 Addr: 00110fb8 Rxd: e169b0c2
|
# READ STATUS: Burst-No: 2 Addr: 00110fb8 Rxd: e169b0c2
|
# tb_core.u_sdram32 : at time 27083.0 ns READ : Bank = 3 Row = 272, Col = 241, Data = 06b3050d
|
# tb_core.u_sdram32 : at time 27753.0 ns READ : Bank = 3 Row = 272, Col = 241, Data = 06b3050d
|
# READ STATUS: Burst-No: 3 Addr: 00110fba Rxd: 8f1cf61e
|
# READ STATUS: Burst-No: 3 Addr: 00110fba Rxd: 8f1cf61e
|
# tb_core.u_sdram32 : at time 27093.0 ns READ : Bank = 3 Row = 272, Col = 242, Data = 7679fdec
|
# tb_core.u_sdram32 : at time 27763.0 ns READ : Bank = 3 Row = 272, Col = 242, Data = 7679fdec
|
# READ STATUS: Burst-No: 4 Addr: 00110fbc Rxd: 06b3050d
|
# READ STATUS: Burst-No: 4 Addr: 00110fbc Rxd: 06b3050d
|
# tb_core.u_sdram32 : at time 27103.0 ns READ : Bank = 3 Row = 272, Col = 243, Data = 0c039d18
|
# tb_core.u_sdram32 : at time 27773.0 ns READ : Bank = 3 Row = 272, Col = 243, Data = 0c039d18
|
# READ STATUS: Burst-No: 5 Addr: 00110fbe Rxd: 7679fdec
|
# READ STATUS: Burst-No: 5 Addr: 00110fbe Rxd: 7679fdec
|
# tb_core.u_sdram32 : at time 27113.0 ns READ : Bank = 3 Row = 272, Col = 244, Data = 68ae1bd1
|
# tb_core.u_sdram32 : at time 27783.0 ns READ : Bank = 3 Row = 272, Col = 244, Data = 68ae1bd1
|
# READ STATUS: Burst-No: 6 Addr: 00110fc0 Rxd: 0c039d18
|
# READ STATUS: Burst-No: 6 Addr: 00110fc0 Rxd: 0c039d18
|
# tb_core.u_sdram32 : at time 27123.0 ns READ : Bank = 3 Row = 272, Col = 245, Data = c3761c86
|
# tb_core.u_sdram32 : at time 27793.0 ns READ : Bank = 3 Row = 272, Col = 245, Data = c3761c86
|
# READ STATUS: Burst-No: 7 Addr: 00110fc2 Rxd: 68ae1bd1
|
# READ STATUS: Burst-No: 7 Addr: 00110fc2 Rxd: 68ae1bd1
|
# tb_core.u_sdram32 : at time 27133.0 ns READ : Bank = 3 Row = 272, Col = 246, Data = a0c02441
|
# tb_core.u_sdram32 : at time 27803.0 ns READ : Bank = 3 Row = 272, Col = 246, Data = a0c02441
|
# READ STATUS: Burst-No: 8 Addr: 00110fc4 Rxd: c3761c86
|
# READ STATUS: Burst-No: 8 Addr: 00110fc4 Rxd: c3761c86
|
# tb_core.u_sdram32 : at time 27143.0 ns READ : Bank = 3 Row = 272, Col = 247, Data = 9dbf643b
|
# tb_core.u_sdram32 : at time 27813.0 ns READ : Bank = 3 Row = 272, Col = 247, Data = 9dbf643b
|
# READ STATUS: Burst-No: 9 Addr: 00110fc6 Rxd: a0c02441
|
# READ STATUS: Burst-No: 9 Addr: 00110fc6 Rxd: a0c02441
|
# tb_core.u_sdram32 : at time 27153.0 ns READ : Bank = 3 Row = 272, Col = 248, Data = 6c44f9d8
|
# tb_core.u_sdram32 : at time 27823.0 ns READ : Bank = 3 Row = 272, Col = 248, Data = 6c44f9d8
|
# READ STATUS: Burst-No: 10 Addr: 00110fc8 Rxd: 9dbf643b
|
# READ STATUS: Burst-No: 10 Addr: 00110fc8 Rxd: 9dbf643b
|
# tb_core.u_sdram32 : at time 27163.0 ns READ : Bank = 3 Row = 272, Col = 249, Data = 29efe953
|
# tb_core.u_sdram32 : at time 27833.0 ns READ : Bank = 3 Row = 272, Col = 249, Data = 29efe953
|
# tb_core.u_sdram32 : at time 27167.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 27837.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 11 Addr: 00110fca Rxd: 6c44f9d8
|
# READ STATUS: Burst-No: 11 Addr: 00110fca Rxd: 6c44f9d8
|
# tb_core.u_sdram32 : at time 27173.0 ns READ : Bank = 3 Row = 272, Col = 250, Data = ab196256
|
# tb_core.u_sdram32 : at time 27843.0 ns READ : Bank = 3 Row = 272, Col = 250, Data = ab196256
|
# READ STATUS: Burst-No: 12 Addr: 00110fcc Rxd: 29efe953
|
# READ STATUS: Burst-No: 12 Addr: 00110fcc Rxd: 29efe953
|
# tb_core.u_sdram32 : at time 27183.0 ns READ : Bank = 3 Row = 272, Col = 251, Data = adac225b
|
# tb_core.u_sdram32 : at time 27853.0 ns READ : Bank = 3 Row = 272, Col = 251, Data = adac225b
|
# READ STATUS: Burst-No: 13 Addr: 00110fce Rxd: ab196256
|
# READ STATUS: Burst-No: 13 Addr: 00110fce Rxd: ab196256
|
# READ STATUS: Burst-No: 14 Addr: 00110fd0 Rxd: adac225b
|
# READ STATUS: Burst-No: 14 Addr: 00110fd0 Rxd: adac225b
|
# tb_core.u_sdram32 : at time 27277.0 ns ACT : Bank = 3 Row = 288
|
# tb_core.u_sdram32 : at time 27957.0 ns ACT : Bank = 3 Row = 288
|
# tb_core.u_sdram32 : at time 27343.0 ns READ : Bank = 3 Row = 288, Col = 238, Data = f166fae2
|
# tb_core.u_sdram32 : at time 28023.0 ns READ : Bank = 3 Row = 288, Col = 238, Data = f166fae2
|
# tb_core.u_sdram32 : at time 27353.0 ns READ : Bank = 3 Row = 288, Col = 239, Data = 8273e204
|
# tb_core.u_sdram32 : at time 28033.0 ns READ : Bank = 3 Row = 288, Col = 239, Data = 8273e204
|
# READ STATUS: Burst-No: 0 Addr: 00120fb8 Rxd: f166fae2
|
# READ STATUS: Burst-No: 0 Addr: 00120fb8 Rxd: f166fae2
|
# tb_core.u_sdram32 : at time 27363.0 ns READ : Bank = 3 Row = 288, Col = 240, Data = 39ac0373
|
# tb_core.u_sdram32 : at time 28043.0 ns READ : Bank = 3 Row = 288, Col = 240, Data = 39ac0373
|
# READ STATUS: Burst-No: 1 Addr: 00120fba Rxd: 8273e204
|
# READ STATUS: Burst-No: 1 Addr: 00120fba Rxd: 8273e204
|
# tb_core.u_sdram32 : at time 27373.0 ns READ : Bank = 3 Row = 288, Col = 241, Data = ec50b4d8
|
# tb_core.u_sdram32 : at time 28053.0 ns READ : Bank = 3 Row = 288, Col = 241, Data = ec50b4d8
|
# READ STATUS: Burst-No: 2 Addr: 00120fbc Rxd: 39ac0373
|
# READ STATUS: Burst-No: 2 Addr: 00120fbc Rxd: 39ac0373
|
# tb_core.u_sdram32 : at time 27383.0 ns READ : Bank = 3 Row = 288, Col = 242, Data = 093e4d12
|
# tb_core.u_sdram32 : at time 28063.0 ns READ : Bank = 3 Row = 288, Col = 242, Data = 093e4d12
|
# READ STATUS: Burst-No: 3 Addr: 00120fbe Rxd: ec50b4d8
|
# READ STATUS: Burst-No: 3 Addr: 00120fbe Rxd: ec50b4d8
|
# tb_core.u_sdram32 : at time 27393.0 ns READ : Bank = 3 Row = 288, Col = 243, Data = dc0344b8
|
# tb_core.u_sdram32 : at time 28073.0 ns READ : Bank = 3 Row = 288, Col = 243, Data = dc0344b8
|
# READ STATUS: Burst-No: 4 Addr: 00120fc0 Rxd: 093e4d12
|
# READ STATUS: Burst-No: 4 Addr: 00120fc0 Rxd: 093e4d12
|
# tb_core.u_sdram32 : at time 27403.0 ns READ : Bank = 3 Row = 288, Col = 244, Data = 9c811239
|
# tb_core.u_sdram32 : at time 28083.0 ns READ : Bank = 3 Row = 288, Col = 244, Data = 9c811239
|
# READ STATUS: Burst-No: 5 Addr: 00120fc2 Rxd: dc0344b8
|
# READ STATUS: Burst-No: 5 Addr: 00120fc2 Rxd: dc0344b8
|
# tb_core.u_sdram32 : at time 27413.0 ns READ : Bank = 3 Row = 288, Col = 245, Data = f287b6e5
|
# tb_core.u_sdram32 : at time 28093.0 ns READ : Bank = 3 Row = 288, Col = 245, Data = f287b6e5
|
# READ STATUS: Burst-No: 6 Addr: 00120fc4 Rxd: 9c811239
|
# READ STATUS: Burst-No: 6 Addr: 00120fc4 Rxd: 9c811239
|
# tb_core.u_sdram32 : at time 27423.0 ns READ : Bank = 3 Row = 288, Col = 246, Data = d0c5dca1
|
# tb_core.u_sdram32 : at time 28103.0 ns READ : Bank = 3 Row = 288, Col = 246, Data = d0c5dca1
|
# READ STATUS: Burst-No: 7 Addr: 00120fc6 Rxd: f287b6e5
|
# READ STATUS: Burst-No: 7 Addr: 00120fc6 Rxd: f287b6e5
|
# tb_core.u_sdram32 : at time 27433.0 ns READ : Bank = 3 Row = 288, Col = 247, Data = 15890f2b
|
# tb_core.u_sdram32 : at time 28113.0 ns READ : Bank = 3 Row = 288, Col = 247, Data = 15890f2b
|
# READ STATUS: Burst-No: 8 Addr: 00120fc8 Rxd: d0c5dca1
|
# READ STATUS: Burst-No: 8 Addr: 00120fc8 Rxd: d0c5dca1
|
# tb_core.u_sdram32 : at time 27443.0 ns READ : Bank = 3 Row = 288, Col = 248, Data = 40905d81
|
# tb_core.u_sdram32 : at time 28123.0 ns READ : Bank = 3 Row = 288, Col = 248, Data = 40905d81
|
# READ STATUS: Burst-No: 9 Addr: 00120fca Rxd: 15890f2b
|
# READ STATUS: Burst-No: 9 Addr: 00120fca Rxd: 15890f2b
|
# tb_core.u_sdram32 : at time 27453.0 ns READ : Bank = 3 Row = 288, Col = 249, Data = 641b85c8
|
# tb_core.u_sdram32 : at time 28133.0 ns READ : Bank = 3 Row = 288, Col = 249, Data = 641b85c8
|
# READ STATUS: Burst-No: 10 Addr: 00120fcc Rxd: 40905d81
|
# READ STATUS: Burst-No: 10 Addr: 00120fcc Rxd: 40905d81
|
# tb_core.u_sdram32 : at time 27463.0 ns READ : Bank = 3 Row = 288, Col = 250, Data = 13b55527
|
# tb_core.u_sdram32 : at time 28143.0 ns READ : Bank = 3 Row = 288, Col = 250, Data = 13b55527
|
# tb_core.u_sdram32 : at time 27467.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 28147.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 11 Addr: 00120fce Rxd: 641b85c8
|
# READ STATUS: Burst-No: 11 Addr: 00120fce Rxd: 641b85c8
|
# tb_core.u_sdram32 : at time 27473.0 ns READ : Bank = 3 Row = 288, Col = 251, Data = 50d5f9a1
|
# tb_core.u_sdram32 : at time 28153.0 ns READ : Bank = 3 Row = 288, Col = 251, Data = 50d5f9a1
|
# READ STATUS: Burst-No: 12 Addr: 00120fd0 Rxd: 13b55527
|
# READ STATUS: Burst-No: 12 Addr: 00120fd0 Rxd: 13b55527
|
# tb_core.u_sdram32 : at time 27483.0 ns READ : Bank = 3 Row = 288, Col = 252, Data = 8f8c6e1f
|
# tb_core.u_sdram32 : at time 28163.0 ns READ : Bank = 3 Row = 288, Col = 252, Data = 8f8c6e1f
|
# READ STATUS: Burst-No: 13 Addr: 00120fd2 Rxd: 50d5f9a1
|
# READ STATUS: Burst-No: 13 Addr: 00120fd2 Rxd: 50d5f9a1
|
# READ STATUS: Burst-No: 14 Addr: 00120fd4 Rxd: 8f8c6e1f
|
# READ STATUS: Burst-No: 14 Addr: 00120fd4 Rxd: 8f8c6e1f
|
# tb_core.u_sdram32 : at time 27577.0 ns ACT : Bank = 3 Row = 304
|
# tb_core.u_sdram32 : at time 28267.0 ns ACT : Bank = 3 Row = 304
|
# tb_core.u_sdram32 : at time 27643.0 ns READ : Bank = 3 Row = 304, Col = 239, Data = 82223a04
|
# tb_core.u_sdram32 : at time 28333.0 ns READ : Bank = 3 Row = 304, Col = 239, Data = 82223a04
|
# tb_core.u_sdram32 : at time 27653.0 ns READ : Bank = 3 Row = 304, Col = 240, Data = 2c2d2358
|
# tb_core.u_sdram32 : at time 28343.0 ns READ : Bank = 3 Row = 304, Col = 240, Data = 2c2d2358
|
# READ STATUS: Burst-No: 0 Addr: 00130fbc Rxd: 82223a04
|
# READ STATUS: Burst-No: 0 Addr: 00130fbc Rxd: 82223a04
|
# tb_core.u_sdram32 : at time 27663.0 ns READ : Bank = 3 Row = 304, Col = 241, Data = cb5c8096
|
# tb_core.u_sdram32 : at time 28353.0 ns READ : Bank = 3 Row = 304, Col = 241, Data = cb5c8096
|
# READ STATUS: Burst-No: 1 Addr: 00130fbe Rxd: 2c2d2358
|
# READ STATUS: Burst-No: 1 Addr: 00130fbe Rxd: 2c2d2358
|
# tb_core.u_sdram32 : at time 27673.0 ns READ : Bank = 3 Row = 304, Col = 242, Data = 0a6e9314
|
# tb_core.u_sdram32 : at time 28363.0 ns READ : Bank = 3 Row = 304, Col = 242, Data = 0a6e9314
|
# READ STATUS: Burst-No: 2 Addr: 00130fc0 Rxd: cb5c8096
|
# READ STATUS: Burst-No: 2 Addr: 00130fc0 Rxd: cb5c8096
|
# tb_core.u_sdram32 : at time 27683.0 ns READ : Bank = 3 Row = 304, Col = 243, Data = 8919b412
|
# tb_core.u_sdram32 : at time 28373.0 ns READ : Bank = 3 Row = 304, Col = 243, Data = 8919b412
|
# READ STATUS: Burst-No: 3 Addr: 00130fc2 Rxd: 0a6e9314
|
# READ STATUS: Burst-No: 3 Addr: 00130fc2 Rxd: 0a6e9314
|
# tb_core.u_sdram32 : at time 27693.0 ns READ : Bank = 3 Row = 304, Col = 244, Data = cb227096
|
# tb_core.u_sdram32 : at time 28383.0 ns READ : Bank = 3 Row = 304, Col = 244, Data = cb227096
|
# READ STATUS: Burst-No: 4 Addr: 00130fc4 Rxd: 8919b412
|
# READ STATUS: Burst-No: 4 Addr: 00130fc4 Rxd: 8919b412
|
# tb_core.u_sdram32 : at time 27703.0 ns READ : Bank = 3 Row = 304, Col = 245, Data = d8ace2b1
|
# tb_core.u_sdram32 : at time 28393.0 ns READ : Bank = 3 Row = 304, Col = 245, Data = d8ace2b1
|
# READ STATUS: Burst-No: 5 Addr: 00130fc6 Rxd: cb227096
|
# READ STATUS: Burst-No: 5 Addr: 00130fc6 Rxd: cb227096
|
# tb_core.u_sdram32 : at time 27713.0 ns READ : Bank = 3 Row = 304, Col = 246, Data = 2ac2d555
|
# tb_core.u_sdram32 : at time 28403.0 ns READ : Bank = 3 Row = 304, Col = 246, Data = 2ac2d555
|
# READ STATUS: Burst-No: 6 Addr: 00130fc8 Rxd: d8ace2b1
|
# READ STATUS: Burst-No: 6 Addr: 00130fc8 Rxd: d8ace2b1
|
# tb_core.u_sdram32 : at time 27723.0 ns READ : Bank = 3 Row = 304, Col = 247, Data = f6c38eed
|
# tb_core.u_sdram32 : at time 28413.0 ns READ : Bank = 3 Row = 304, Col = 247, Data = f6c38eed
|
# READ STATUS: Burst-No: 7 Addr: 00130fca Rxd: 2ac2d555
|
# READ STATUS: Burst-No: 7 Addr: 00130fca Rxd: 2ac2d555
|
# tb_core.u_sdram32 : at time 27733.0 ns READ : Bank = 3 Row = 304, Col = 248, Data = 158b2b2b
|
# tb_core.u_sdram32 : at time 28423.0 ns READ : Bank = 3 Row = 304, Col = 248, Data = 158b2b2b
|
# READ STATUS: Burst-No: 8 Addr: 00130fcc Rxd: f6c38eed
|
# READ STATUS: Burst-No: 8 Addr: 00130fcc Rxd: f6c38eed
|
# tb_core.u_sdram32 : at time 27743.0 ns READ : Bank = 3 Row = 304, Col = 249, Data = 7ab11bf5
|
# tb_core.u_sdram32 : at time 28433.0 ns READ : Bank = 3 Row = 304, Col = 249, Data = 7ab11bf5
|
# READ STATUS: Burst-No: 9 Addr: 00130fce Rxd: 158b2b2b
|
# READ STATUS: Burst-No: 9 Addr: 00130fce Rxd: 158b2b2b
|
# tb_core.u_sdram32 : at time 27753.0 ns READ : Bank = 3 Row = 304, Col = 250, Data = 56b403ad
|
# tb_core.u_sdram32 : at time 28443.0 ns READ : Bank = 3 Row = 304, Col = 250, Data = 56b403ad
|
# READ STATUS: Burst-No: 10 Addr: 00130fd0 Rxd: 7ab11bf5
|
# READ STATUS: Burst-No: 10 Addr: 00130fd0 Rxd: 7ab11bf5
|
# tb_core.u_sdram32 : at time 27763.0 ns READ : Bank = 3 Row = 304, Col = 251, Data = 93c12227
|
# tb_core.u_sdram32 : at time 28453.0 ns READ : Bank = 3 Row = 304, Col = 251, Data = 93c12227
|
# tb_core.u_sdram32 : at time 27767.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 28457.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 11 Addr: 00130fd2 Rxd: 56b403ad
|
# READ STATUS: Burst-No: 11 Addr: 00130fd2 Rxd: 56b403ad
|
# tb_core.u_sdram32 : at time 27773.0 ns READ : Bank = 3 Row = 304, Col = 252, Data = 4249ff84
|
# tb_core.u_sdram32 : at time 28463.0 ns READ : Bank = 3 Row = 304, Col = 252, Data = 4249ff84
|
# READ STATUS: Burst-No: 12 Addr: 00130fd4 Rxd: 93c12227
|
# READ STATUS: Burst-No: 12 Addr: 00130fd4 Rxd: 93c12227
|
# tb_core.u_sdram32 : at time 27783.0 ns READ : Bank = 3 Row = 304, Col = 253, Data = d3a8e4a7
|
# tb_core.u_sdram32 : at time 28473.0 ns READ : Bank = 3 Row = 304, Col = 253, Data = d3a8e4a7
|
# READ STATUS: Burst-No: 13 Addr: 00130fd6 Rxd: 4249ff84
|
# READ STATUS: Burst-No: 13 Addr: 00130fd6 Rxd: 4249ff84
|
# READ STATUS: Burst-No: 14 Addr: 00130fd8 Rxd: d3a8e4a7
|
# READ STATUS: Burst-No: 14 Addr: 00130fd8 Rxd: d3a8e4a7
|
# tb_core.u_sdram32 : at time 27877.0 ns ACT : Bank = 3 Row = 320
|
# tb_core.u_sdram32 : at time 28577.0 ns ACT : Bank = 3 Row = 320
|
# tb_core.u_sdram32 : at time 27943.0 ns READ : Bank = 3 Row = 320, Col = 232, Data = f3d7a6e7
|
# tb_core.u_sdram32 : at time 28643.0 ns READ : Bank = 3 Row = 320, Col = 232, Data = f3d7a6e7
|
# tb_core.u_sdram32 : at time 27953.0 ns READ : Bank = 3 Row = 320, Col = 233, Data = dcef90b9
|
# tb_core.u_sdram32 : at time 28653.0 ns READ : Bank = 3 Row = 320, Col = 233, Data = dcef90b9
|
# READ STATUS: Burst-No: 0 Addr: 00140fa0 Rxd: f3d7a6e7
|
# READ STATUS: Burst-No: 0 Addr: 00140fa0 Rxd: f3d7a6e7
|
# tb_core.u_sdram32 : at time 27963.0 ns READ : Bank = 3 Row = 320, Col = 234, Data = a4da5649
|
# tb_core.u_sdram32 : at time 28663.0 ns READ : Bank = 3 Row = 320, Col = 234, Data = a4da5649
|
# READ STATUS: Burst-No: 1 Addr: 00140fa2 Rxd: dcef90b9
|
# READ STATUS: Burst-No: 1 Addr: 00140fa2 Rxd: dcef90b9
|
# tb_core.u_sdram32 : at time 27973.0 ns READ : Bank = 3 Row = 320, Col = 235, Data = 6de5bbdb
|
# tb_core.u_sdram32 : at time 28673.0 ns READ : Bank = 3 Row = 320, Col = 235, Data = 6de5bbdb
|
# READ STATUS: Burst-No: 2 Addr: 00140fa4 Rxd: a4da5649
|
# READ STATUS: Burst-No: 2 Addr: 00140fa4 Rxd: a4da5649
|
# tb_core.u_sdram32 : at time 27983.0 ns READ : Bank = 3 Row = 320, Col = 236, Data = 64ba0fc9
|
# tb_core.u_sdram32 : at time 28683.0 ns READ : Bank = 3 Row = 320, Col = 236, Data = 64ba0fc9
|
# READ STATUS: Burst-No: 3 Addr: 00140fa6 Rxd: 6de5bbdb
|
# READ STATUS: Burst-No: 3 Addr: 00140fa6 Rxd: 6de5bbdb
|
# tb_core.u_sdram32 : at time 27993.0 ns READ : Bank = 3 Row = 320, Col = 237, Data = 2883b151
|
# tb_core.u_sdram32 : at time 28693.0 ns READ : Bank = 3 Row = 320, Col = 237, Data = 2883b151
|
# READ STATUS: Burst-No: 4 Addr: 00140fa8 Rxd: 64ba0fc9
|
# READ STATUS: Burst-No: 4 Addr: 00140fa8 Rxd: 64ba0fc9
|
# tb_core.u_sdram32 : at time 28003.0 ns READ : Bank = 3 Row = 320, Col = 238, Data = d0bc5ea1
|
# tb_core.u_sdram32 : at time 28703.0 ns READ : Bank = 3 Row = 320, Col = 238, Data = d0bc5ea1
|
# READ STATUS: Burst-No: 5 Addr: 00140faa Rxd: 2883b151
|
# READ STATUS: Burst-No: 5 Addr: 00140faa Rxd: 2883b151
|
# tb_core.u_sdram32 : at time 28013.0 ns READ : Bank = 3 Row = 320, Col = 239, Data = 1546dd2a
|
# tb_core.u_sdram32 : at time 28713.0 ns READ : Bank = 3 Row = 320, Col = 239, Data = 1546dd2a
|
# READ STATUS: Burst-No: 6 Addr: 00140fac Rxd: d0bc5ea1
|
# READ STATUS: Burst-No: 6 Addr: 00140fac Rxd: d0bc5ea1
|
# tb_core.u_sdram32 : at time 28023.0 ns READ : Bank = 3 Row = 320, Col = 240, Data = 7d2a45fa
|
# tb_core.u_sdram32 : at time 28723.0 ns READ : Bank = 3 Row = 320, Col = 240, Data = 7d2a45fa
|
# READ STATUS: Burst-No: 7 Addr: 00140fae Rxd: 1546dd2a
|
# READ STATUS: Burst-No: 7 Addr: 00140fae Rxd: 1546dd2a
|
# tb_core.u_sdram32 : at time 28033.0 ns READ : Bank = 3 Row = 320, Col = 241, Data = a2e62045
|
# tb_core.u_sdram32 : at time 28733.0 ns READ : Bank = 3 Row = 320, Col = 241, Data = a2e62045
|
# READ STATUS: Burst-No: 8 Addr: 00140fb0 Rxd: 7d2a45fa
|
# READ STATUS: Burst-No: 8 Addr: 00140fb0 Rxd: 7d2a45fa
|
# tb_core.u_sdram32 : at time 28043.0 ns READ : Bank = 3 Row = 320, Col = 242, Data = 41a10583
|
# tb_core.u_sdram32 : at time 28743.0 ns READ : Bank = 3 Row = 320, Col = 242, Data = 41a10583
|
# READ STATUS: Burst-No: 9 Addr: 00140fb2 Rxd: a2e62045
|
# READ STATUS: Burst-No: 9 Addr: 00140fb2 Rxd: a2e62045
|
# tb_core.u_sdram32 : at time 28053.0 ns READ : Bank = 3 Row = 320, Col = 243, Data = be75427c
|
# tb_core.u_sdram32 : at time 28753.0 ns READ : Bank = 3 Row = 320, Col = 243, Data = be75427c
|
# READ STATUS: Burst-No: 10 Addr: 00140fb4 Rxd: 41a10583
|
# READ STATUS: Burst-No: 10 Addr: 00140fb4 Rxd: 41a10583
|
# tb_core.u_sdram32 : at time 28063.0 ns READ : Bank = 3 Row = 320, Col = 244, Data = b9461472
|
# tb_core.u_sdram32 : at time 28763.0 ns READ : Bank = 3 Row = 320, Col = 244, Data = b9461472
|
# tb_core.u_sdram32 : at time 28067.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 28767.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 11 Addr: 00140fb6 Rxd: be75427c
|
# READ STATUS: Burst-No: 11 Addr: 00140fb6 Rxd: be75427c
|
# tb_core.u_sdram32 : at time 28073.0 ns READ : Bank = 3 Row = 320, Col = 245, Data = ff4f3cfe
|
# tb_core.u_sdram32 : at time 28773.0 ns READ : Bank = 3 Row = 320, Col = 245, Data = ff4f3cfe
|
# READ STATUS: Burst-No: 12 Addr: 00140fb8 Rxd: b9461472
|
# READ STATUS: Burst-No: 12 Addr: 00140fb8 Rxd: b9461472
|
# tb_core.u_sdram32 : at time 28083.0 ns READ : Bank = 3 Row = 320, Col = 246, Data = b455f268
|
# tb_core.u_sdram32 : at time 28783.0 ns READ : Bank = 3 Row = 320, Col = 246, Data = b455f268
|
# READ STATUS: Burst-No: 13 Addr: 00140fba Rxd: ff4f3cfe
|
# READ STATUS: Burst-No: 13 Addr: 00140fba Rxd: ff4f3cfe
|
# READ STATUS: Burst-No: 14 Addr: 00140fbc Rxd: b455f268
|
# READ STATUS: Burst-No: 14 Addr: 00140fbc Rxd: b455f268
|
# tb_core.u_sdram32 : at time 28177.0 ns ACT : Bank = 3 Row = 336
|
# tb_core.u_sdram32 : at time 28887.0 ns ACT : Bank = 3 Row = 336
|
# tb_core.u_sdram32 : at time 28243.0 ns READ : Bank = 3 Row = 336, Col = 233, Data = b7dfaa6f
|
# tb_core.u_sdram32 : at time 28953.0 ns READ : Bank = 3 Row = 336, Col = 233, Data = b7dfaa6f
|
# tb_core.u_sdram32 : at time 28253.0 ns READ : Bank = 3 Row = 336, Col = 234, Data = 43460d86
|
# tb_core.u_sdram32 : at time 28963.0 ns READ : Bank = 3 Row = 336, Col = 234, Data = 43460d86
|
# READ STATUS: Burst-No: 0 Addr: 00150fa4 Rxd: b7dfaa6f
|
# READ STATUS: Burst-No: 0 Addr: 00150fa4 Rxd: b7dfaa6f
|
# tb_core.u_sdram32 : at time 28263.0 ns READ : Bank = 3 Row = 336, Col = 235, Data = 782321f0
|
# tb_core.u_sdram32 : at time 28973.0 ns READ : Bank = 3 Row = 336, Col = 235, Data = 782321f0
|
# READ STATUS: Burst-No: 1 Addr: 00150fa6 Rxd: 43460d86
|
# READ STATUS: Burst-No: 1 Addr: 00150fa6 Rxd: 43460d86
|
# tb_core.u_sdram32 : at time 28273.0 ns READ : Bank = 3 Row = 336, Col = 236, Data = 1c719738
|
# tb_core.u_sdram32 : at time 28983.0 ns READ : Bank = 3 Row = 336, Col = 236, Data = 1c719738
|
# READ STATUS: Burst-No: 2 Addr: 00150fa8 Rxd: 782321f0
|
# READ STATUS: Burst-No: 2 Addr: 00150fa8 Rxd: 782321f0
|
# tb_core.u_sdram32 : at time 28283.0 ns READ : Bank = 3 Row = 336, Col = 237, Data = 20769140
|
# tb_core.u_sdram32 : at time 28993.0 ns READ : Bank = 3 Row = 336, Col = 237, Data = 20769140
|
# READ STATUS: Burst-No: 3 Addr: 00150faa Rxd: 1c719738
|
# READ STATUS: Burst-No: 3 Addr: 00150faa Rxd: 1c719738
|
# tb_core.u_sdram32 : at time 28293.0 ns READ : Bank = 3 Row = 336, Col = 238, Data = 94097628
|
# tb_core.u_sdram32 : at time 29003.0 ns READ : Bank = 3 Row = 336, Col = 238, Data = 94097628
|
# READ STATUS: Burst-No: 4 Addr: 00150fac Rxd: 20769140
|
# READ STATUS: Burst-No: 4 Addr: 00150fac Rxd: 20769140
|
# tb_core.u_sdram32 : at time 28303.0 ns READ : Bank = 3 Row = 336, Col = 239, Data = 7b0da9f6
|
# tb_core.u_sdram32 : at time 29013.0 ns READ : Bank = 3 Row = 336, Col = 239, Data = 7b0da9f6
|
# READ STATUS: Burst-No: 5 Addr: 00150fae Rxd: 94097628
|
# READ STATUS: Burst-No: 5 Addr: 00150fae Rxd: 94097628
|
# tb_core.u_sdram32 : at time 28313.0 ns READ : Bank = 3 Row = 336, Col = 240, Data = e2bf1ac5
|
# tb_core.u_sdram32 : at time 29023.0 ns READ : Bank = 3 Row = 336, Col = 240, Data = e2bf1ac5
|
# READ STATUS: Burst-No: 6 Addr: 00150fb0 Rxd: 7b0da9f6
|
# READ STATUS: Burst-No: 6 Addr: 00150fb0 Rxd: 7b0da9f6
|
# tb_core.u_sdram32 : at time 28323.0 ns READ : Bank = 3 Row = 336, Col = 241, Data = 602831c0
|
# tb_core.u_sdram32 : at time 29033.0 ns READ : Bank = 3 Row = 336, Col = 241, Data = 602831c0
|
# READ STATUS: Burst-No: 7 Addr: 00150fb2 Rxd: e2bf1ac5
|
# READ STATUS: Burst-No: 7 Addr: 00150fb2 Rxd: e2bf1ac5
|
# tb_core.u_sdram32 : at time 28333.0 ns READ : Bank = 3 Row = 336, Col = 242, Data = 3a625f74
|
# tb_core.u_sdram32 : at time 29043.0 ns READ : Bank = 3 Row = 336, Col = 242, Data = 3a625f74
|
# READ STATUS: Burst-No: 8 Addr: 00150fb4 Rxd: 602831c0
|
# READ STATUS: Burst-No: 8 Addr: 00150fb4 Rxd: 602831c0
|
# tb_core.u_sdram32 : at time 28343.0 ns READ : Bank = 3 Row = 336, Col = 243, Data = 1cde7139
|
# tb_core.u_sdram32 : at time 29053.0 ns READ : Bank = 3 Row = 336, Col = 243, Data = 1cde7139
|
# READ STATUS: Burst-No: 9 Addr: 00150fb6 Rxd: 3a625f74
|
# READ STATUS: Burst-No: 9 Addr: 00150fb6 Rxd: 3a625f74
|
# tb_core.u_sdram32 : at time 28353.0 ns READ : Bank = 3 Row = 336, Col = 244, Data = d86a6ab0
|
# tb_core.u_sdram32 : at time 29063.0 ns READ : Bank = 3 Row = 336, Col = 244, Data = d86a6ab0
|
# READ STATUS: Burst-No: 10 Addr: 00150fb8 Rxd: 1cde7139
|
# READ STATUS: Burst-No: 10 Addr: 00150fb8 Rxd: 1cde7139
|
# tb_core.u_sdram32 : at time 28363.0 ns READ : Bank = 3 Row = 336, Col = 245, Data = 1e1c873c
|
# tb_core.u_sdram32 : at time 29073.0 ns READ : Bank = 3 Row = 336, Col = 245, Data = 1e1c873c
|
# tb_core.u_sdram32 : at time 28367.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 29077.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 11 Addr: 00150fba Rxd: d86a6ab0
|
# READ STATUS: Burst-No: 11 Addr: 00150fba Rxd: d86a6ab0
|
# tb_core.u_sdram32 : at time 28373.0 ns READ : Bank = 3 Row = 336, Col = 246, Data = 1521932a
|
# tb_core.u_sdram32 : at time 29083.0 ns READ : Bank = 3 Row = 336, Col = 246, Data = 1521932a
|
# READ STATUS: Burst-No: 12 Addr: 00150fbc Rxd: 1e1c873c
|
# READ STATUS: Burst-No: 12 Addr: 00150fbc Rxd: 1e1c873c
|
# tb_core.u_sdram32 : at time 28383.0 ns READ : Bank = 3 Row = 336, Col = 247, Data = 3124d362
|
# tb_core.u_sdram32 : at time 29093.0 ns READ : Bank = 3 Row = 336, Col = 247, Data = 3124d362
|
# READ STATUS: Burst-No: 13 Addr: 00150fbe Rxd: 1521932a
|
# READ STATUS: Burst-No: 13 Addr: 00150fbe Rxd: 1521932a
|
# READ STATUS: Burst-No: 14 Addr: 00150fc0 Rxd: 3124d362
|
# READ STATUS: Burst-No: 14 Addr: 00150fc0 Rxd: 3124d362
|
# tb_core.u_sdram32 : at time 28477.0 ns ACT : Bank = 3 Row = 352
|
# tb_core.u_sdram32 : at time 29197.0 ns ACT : Bank = 3 Row = 352
|
# tb_core.u_sdram32 : at time 28543.0 ns READ : Bank = 3 Row = 352, Col = 234, Data = 0aec3515
|
# tb_core.u_sdram32 : at time 29263.0 ns READ : Bank = 3 Row = 352, Col = 234, Data = 0aec3515
|
# tb_core.u_sdram32 : at time 28553.0 ns READ : Bank = 3 Row = 352, Col = 235, Data = f0b14ee1
|
# tb_core.u_sdram32 : at time 29273.0 ns READ : Bank = 3 Row = 352, Col = 235, Data = f0b14ee1
|
# READ STATUS: Burst-No: 0 Addr: 00160fa8 Rxd: 0aec3515
|
# READ STATUS: Burst-No: 0 Addr: 00160fa8 Rxd: 0aec3515
|
# tb_core.u_sdram32 : at time 28563.0 ns READ : Bank = 3 Row = 352, Col = 236, Data = 0be29d17
|
# tb_core.u_sdram32 : at time 29283.0 ns READ : Bank = 3 Row = 352, Col = 236, Data = 0be29d17
|
# READ STATUS: Burst-No: 1 Addr: 00160faa Rxd: f0b14ee1
|
# READ STATUS: Burst-No: 1 Addr: 00160faa Rxd: f0b14ee1
|
# tb_core.u_sdram32 : at time 28573.0 ns READ : Bank = 3 Row = 352, Col = 237, Data = a18bee43
|
# tb_core.u_sdram32 : at time 29293.0 ns READ : Bank = 3 Row = 352, Col = 237, Data = a18bee43
|
# READ STATUS: Burst-No: 2 Addr: 00160fac Rxd: 0be29d17
|
# READ STATUS: Burst-No: 2 Addr: 00160fac Rxd: 0be29d17
|
# tb_core.u_sdram32 : at time 28583.0 ns READ : Bank = 3 Row = 352, Col = 238, Data = 64b5e3c9
|
# tb_core.u_sdram32 : at time 29303.0 ns READ : Bank = 3 Row = 352, Col = 238, Data = 64b5e3c9
|
# READ STATUS: Burst-No: 3 Addr: 00160fae Rxd: a18bee43
|
# READ STATUS: Burst-No: 3 Addr: 00160fae Rxd: a18bee43
|
# tb_core.u_sdram32 : at time 28593.0 ns READ : Bank = 3 Row = 352, Col = 239, Data = c3360486
|
# tb_core.u_sdram32 : at time 29313.0 ns READ : Bank = 3 Row = 352, Col = 239, Data = c3360486
|
# READ STATUS: Burst-No: 4 Addr: 00160fb0 Rxd: 64b5e3c9
|
# READ STATUS: Burst-No: 4 Addr: 00160fb0 Rxd: 64b5e3c9
|
# tb_core.u_sdram32 : at time 28603.0 ns READ : Bank = 3 Row = 352, Col = 240, Data = 1297cb25
|
# tb_core.u_sdram32 : at time 29323.0 ns READ : Bank = 3 Row = 352, Col = 240, Data = 1297cb25
|
# READ STATUS: Burst-No: 5 Addr: 00160fb2 Rxd: c3360486
|
# READ STATUS: Burst-No: 5 Addr: 00160fb2 Rxd: c3360486
|
# tb_core.u_sdram32 : at time 28613.0 ns READ : Bank = 3 Row = 352, Col = 241, Data = 60f69dc1
|
# tb_core.u_sdram32 : at time 29333.0 ns READ : Bank = 3 Row = 352, Col = 241, Data = 60f69dc1
|
# READ STATUS: Burst-No: 6 Addr: 00160fb4 Rxd: 1297cb25
|
# READ STATUS: Burst-No: 6 Addr: 00160fb4 Rxd: 1297cb25
|
# tb_core.u_sdram32 : at time 28623.0 ns READ : Bank = 3 Row = 352, Col = 242, Data = c69da28d
|
# tb_core.u_sdram32 : at time 29343.0 ns READ : Bank = 3 Row = 352, Col = 242, Data = c69da28d
|
# READ STATUS: Burst-No: 7 Addr: 00160fb6 Rxd: 60f69dc1
|
# READ STATUS: Burst-No: 7 Addr: 00160fb6 Rxd: 60f69dc1
|
# tb_core.u_sdram32 : at time 28633.0 ns READ : Bank = 3 Row = 352, Col = 243, Data = ad67e25a
|
# tb_core.u_sdram32 : at time 29353.0 ns READ : Bank = 3 Row = 352, Col = 243, Data = ad67e25a
|
# READ STATUS: Burst-No: 8 Addr: 00160fb8 Rxd: c69da28d
|
# READ STATUS: Burst-No: 8 Addr: 00160fb8 Rxd: c69da28d
|
# tb_core.u_sdram32 : at time 28643.0 ns READ : Bank = 3 Row = 352, Col = 244, Data = 03d62707
|
# tb_core.u_sdram32 : at time 29363.0 ns READ : Bank = 3 Row = 352, Col = 244, Data = 03d62707
|
# READ STATUS: Burst-No: 9 Addr: 00160fba Rxd: ad67e25a
|
# READ STATUS: Burst-No: 9 Addr: 00160fba Rxd: ad67e25a
|
# tb_core.u_sdram32 : at time 28653.0 ns READ : Bank = 3 Row = 352, Col = 245, Data = 165b7b2c
|
# tb_core.u_sdram32 : at time 29373.0 ns READ : Bank = 3 Row = 352, Col = 245, Data = 165b7b2c
|
# READ STATUS: Burst-No: 10 Addr: 00160fbc Rxd: 03d62707
|
# READ STATUS: Burst-No: 10 Addr: 00160fbc Rxd: 03d62707
|
# tb_core.u_sdram32 : at time 28663.0 ns READ : Bank = 3 Row = 352, Col = 246, Data = 060a5d0c
|
# tb_core.u_sdram32 : at time 29383.0 ns READ : Bank = 3 Row = 352, Col = 246, Data = 060a5d0c
|
# tb_core.u_sdram32 : at time 28667.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 29387.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 11 Addr: 00160fbe Rxd: 165b7b2c
|
# READ STATUS: Burst-No: 11 Addr: 00160fbe Rxd: 165b7b2c
|
# tb_core.u_sdram32 : at time 28673.0 ns READ : Bank = 3 Row = 352, Col = 247, Data = b8ade671
|
# tb_core.u_sdram32 : at time 29393.0 ns READ : Bank = 3 Row = 352, Col = 247, Data = b8ade671
|
# READ STATUS: Burst-No: 12 Addr: 00160fc0 Rxd: 060a5d0c
|
# READ STATUS: Burst-No: 12 Addr: 00160fc0 Rxd: 060a5d0c
|
# tb_core.u_sdram32 : at time 28683.0 ns READ : Bank = 3 Row = 352, Col = 248, Data = 9de17c3b
|
# tb_core.u_sdram32 : at time 29403.0 ns READ : Bank = 3 Row = 352, Col = 248, Data = 9de17c3b
|
# READ STATUS: Burst-No: 13 Addr: 00160fc2 Rxd: b8ade671
|
# READ STATUS: Burst-No: 13 Addr: 00160fc2 Rxd: b8ade671
|
# READ STATUS: Burst-No: 14 Addr: 00160fc4 Rxd: 9de17c3b
|
# READ STATUS: Burst-No: 14 Addr: 00160fc4 Rxd: 9de17c3b
|
# tb_core.u_sdram32 : at time 28777.0 ns ACT : Bank = 3 Row = 368
|
# tb_core.u_sdram32 : at time 29507.0 ns ACT : Bank = 3 Row = 368
|
# tb_core.u_sdram32 : at time 28843.0 ns READ : Bank = 3 Row = 368, Col = 235, Data = 5b60e5b6
|
# tb_core.u_sdram32 : at time 29573.0 ns READ : Bank = 3 Row = 368, Col = 235, Data = 5b60e5b6
|
# tb_core.u_sdram32 : at time 28853.0 ns READ : Bank = 3 Row = 368, Col = 236, Data = fbdfc2f7
|
# tb_core.u_sdram32 : at time 29583.0 ns READ : Bank = 3 Row = 368, Col = 236, Data = fbdfc2f7
|
# READ STATUS: Burst-No: 0 Addr: 00170fac Rxd: 5b60e5b6
|
# READ STATUS: Burst-No: 0 Addr: 00170fac Rxd: 5b60e5b6
|
# tb_core.u_sdram32 : at time 28863.0 ns READ : Bank = 3 Row = 368, Col = 237, Data = cf14ce9e
|
# tb_core.u_sdram32 : at time 29593.0 ns READ : Bank = 3 Row = 368, Col = 237, Data = cf14ce9e
|
# READ STATUS: Burst-No: 1 Addr: 00170fae Rxd: fbdfc2f7
|
# READ STATUS: Burst-No: 1 Addr: 00170fae Rxd: fbdfc2f7
|
# tb_core.u_sdram32 : at time 28873.0 ns READ : Bank = 3 Row = 368, Col = 238, Data = ae78585c
|
# tb_core.u_sdram32 : at time 29603.0 ns READ : Bank = 3 Row = 368, Col = 238, Data = ae78585c
|
# READ STATUS: Burst-No: 2 Addr: 00170fb0 Rxd: cf14ce9e
|
# READ STATUS: Burst-No: 2 Addr: 00170fb0 Rxd: cf14ce9e
|
# tb_core.u_sdram32 : at time 28883.0 ns READ : Bank = 3 Row = 368, Col = 239, Data = 2ab8f755
|
# tb_core.u_sdram32 : at time 29613.0 ns READ : Bank = 3 Row = 368, Col = 239, Data = 2ab8f755
|
# READ STATUS: Burst-No: 3 Addr: 00170fb2 Rxd: ae78585c
|
# READ STATUS: Burst-No: 3 Addr: 00170fb2 Rxd: ae78585c
|
# tb_core.u_sdram32 : at time 28893.0 ns READ : Bank = 3 Row = 368, Col = 240, Data = 902a3a20
|
# tb_core.u_sdram32 : at time 29623.0 ns READ : Bank = 3 Row = 368, Col = 240, Data = 902a3a20
|
# READ STATUS: Burst-No: 4 Addr: 00170fb4 Rxd: 2ab8f755
|
# READ STATUS: Burst-No: 4 Addr: 00170fb4 Rxd: 2ab8f755
|
# tb_core.u_sdram32 : at time 28903.0 ns READ : Bank = 3 Row = 368, Col = 241, Data = d00b12a0
|
# tb_core.u_sdram32 : at time 29633.0 ns READ : Bank = 3 Row = 368, Col = 241, Data = d00b12a0
|
# READ STATUS: Burst-No: 5 Addr: 00170fb6 Rxd: 902a3a20
|
# READ STATUS: Burst-No: 5 Addr: 00170fb6 Rxd: 902a3a20
|
# tb_core.u_sdram32 : at time 28913.0 ns READ : Bank = 3 Row = 368, Col = 242, Data = 39600972
|
# tb_core.u_sdram32 : at time 29643.0 ns READ : Bank = 3 Row = 368, Col = 242, Data = 39600972
|
# READ STATUS: Burst-No: 6 Addr: 00170fb8 Rxd: d00b12a0
|
# READ STATUS: Burst-No: 6 Addr: 00170fb8 Rxd: d00b12a0
|
# tb_core.u_sdram32 : at time 28923.0 ns READ : Bank = 3 Row = 368, Col = 243, Data = da3d8cb4
|
# tb_core.u_sdram32 : at time 29653.0 ns READ : Bank = 3 Row = 368, Col = 243, Data = da3d8cb4
|
# READ STATUS: Burst-No: 7 Addr: 00170fba Rxd: 39600972
|
# READ STATUS: Burst-No: 7 Addr: 00170fba Rxd: 39600972
|
# tb_core.u_sdram32 : at time 28933.0 ns READ : Bank = 3 Row = 368, Col = 244, Data = 6e8af5dd
|
# tb_core.u_sdram32 : at time 29663.0 ns READ : Bank = 3 Row = 368, Col = 244, Data = 6e8af5dd
|
# READ STATUS: Burst-No: 8 Addr: 00170fbc Rxd: da3d8cb4
|
# READ STATUS: Burst-No: 8 Addr: 00170fbc Rxd: da3d8cb4
|
# tb_core.u_sdram32 : at time 28943.0 ns READ : Bank = 3 Row = 368, Col = 245, Data = 86dcf00d
|
# tb_core.u_sdram32 : at time 29673.0 ns READ : Bank = 3 Row = 368, Col = 245, Data = 86dcf00d
|
# READ STATUS: Burst-No: 9 Addr: 00170fbe Rxd: 6e8af5dd
|
# READ STATUS: Burst-No: 9 Addr: 00170fbe Rxd: 6e8af5dd
|
# tb_core.u_sdram32 : at time 28953.0 ns READ : Bank = 3 Row = 368, Col = 246, Data = 25b0994b
|
# tb_core.u_sdram32 : at time 29683.0 ns READ : Bank = 3 Row = 368, Col = 246, Data = 25b0994b
|
# READ STATUS: Burst-No: 10 Addr: 00170fc0 Rxd: 86dcf00d
|
# READ STATUS: Burst-No: 10 Addr: 00170fc0 Rxd: 86dcf00d
|
# tb_core.u_sdram32 : at time 28963.0 ns READ : Bank = 3 Row = 368, Col = 247, Data = bccc4279
|
# tb_core.u_sdram32 : at time 29693.0 ns READ : Bank = 3 Row = 368, Col = 247, Data = bccc4279
|
# tb_core.u_sdram32 : at time 28967.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 29697.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 11 Addr: 00170fc2 Rxd: 25b0994b
|
# READ STATUS: Burst-No: 11 Addr: 00170fc2 Rxd: 25b0994b
|
# tb_core.u_sdram32 : at time 28973.0 ns READ : Bank = 3 Row = 368, Col = 248, Data = cf63da9e
|
# tb_core.u_sdram32 : at time 29703.0 ns READ : Bank = 3 Row = 368, Col = 248, Data = cf63da9e
|
# READ STATUS: Burst-No: 12 Addr: 00170fc4 Rxd: bccc4279
|
# READ STATUS: Burst-No: 12 Addr: 00170fc4 Rxd: bccc4279
|
# tb_core.u_sdram32 : at time 28983.0 ns READ : Bank = 3 Row = 368, Col = 249, Data = fef064fd
|
# tb_core.u_sdram32 : at time 29713.0 ns READ : Bank = 3 Row = 368, Col = 249, Data = fef064fd
|
# READ STATUS: Burst-No: 13 Addr: 00170fc6 Rxd: cf63da9e
|
# READ STATUS: Burst-No: 13 Addr: 00170fc6 Rxd: cf63da9e
|
# READ STATUS: Burst-No: 14 Addr: 00170fc8 Rxd: fef064fd
|
# READ STATUS: Burst-No: 14 Addr: 00170fc8 Rxd: fef064fd
|
# ----------------------------------------
|
# ----------------------------------------
|
# Case:4 4 Write & 4 Read
|
# Case:4 4 Write & 4 Read
|
# ----------------------------------------
|
# ----------------------------------------
|
# Write Address: 00040000, Burst Size: 4
|
# Write Address: 00040000, Burst Size: 4
|
# tb_core.u_sdram32 : at time 29087.0 ns ACT : Bank = 0 Row = 64
|
# tb_core.u_sdram32 : at time 29817.0 ns ACT : Bank = 0 Row = 64
|
# tb_core.u_sdram32 : at time 29127.0 ns WRITE: Bank = 0 Row = 64, Col = 0, Data = bde0d27b
|
# tb_core.u_sdram32 : at time 29857.0 ns WRITE: Bank = 0 Row = 64, Col = 0, Data = bde0d27b
|
# Status: Burst-No: 0 Write Address: 00040000 WriteData: bde0d27b
|
# Status: Burst-No: 0 Write Address: 00040000 WriteData: bde0d27b
|
# tb_core.u_sdram32 : at time 29137.0 ns WRITE: Bank = 0 Row = 64, Col = 1, Data = 47e2738f
|
# tb_core.u_sdram32 : at time 29867.0 ns WRITE: Bank = 0 Row = 64, Col = 1, Data = 47e2738f
|
# Status: Burst-No: 1 Write Address: 00040000 WriteData: 47e2738f
|
# Status: Burst-No: 1 Write Address: 00040000 WriteData: 47e2738f
|
# tb_core.u_sdram32 : at time 29147.0 ns WRITE: Bank = 0 Row = 64, Col = 2, Data = 81c39a03
|
# tb_core.u_sdram32 : at time 29877.0 ns WRITE: Bank = 0 Row = 64, Col = 2, Data = 81c39a03
|
# Status: Burst-No: 2 Write Address: 00040000 WriteData: 81c39a03
|
# Status: Burst-No: 2 Write Address: 00040000 WriteData: 81c39a03
|
# tb_core.u_sdram32 : at time 29157.0 ns WRITE: Bank = 0 Row = 64, Col = 3, Data = 71c129e3
|
# tb_core.u_sdram32 : at time 29887.0 ns WRITE: Bank = 0 Row = 64, Col = 3, Data = 71c129e3
|
# Status: Burst-No: 3 Write Address: 00040000 WriteData: 71c129e3
|
# Status: Burst-No: 3 Write Address: 00040000 WriteData: 71c129e3
|
# tb_core.u_sdram32 : at time 29167.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 29897.0 ns BST : Burst Terminate
|
# Write Address: 00050000, Burst Size: 5
|
# Write Address: 00050000, Burst Size: 5
|
# tb_core.u_sdram32 : at time 29237.0 ns ACT : Bank = 0 Row = 80
|
# tb_core.u_sdram32 : at time 29967.0 ns ACT : Bank = 0 Row = 80
|
# tb_core.u_sdram32 : at time 29277.0 ns WRITE: Bank = 0 Row = 80, Col = 0, Data = 0e92431d
|
# tb_core.u_sdram32 : at time 30007.0 ns WRITE: Bank = 0 Row = 80, Col = 0, Data = 0e92431d
|
# Status: Burst-No: 0 Write Address: 00050000 WriteData: 0e92431d
|
# Status: Burst-No: 0 Write Address: 00050000 WriteData: 0e92431d
|
# tb_core.u_sdram32 : at time 29287.0 ns WRITE: Bank = 0 Row = 80, Col = 1, Data = 58f93db1
|
# tb_core.u_sdram32 : at time 30017.0 ns WRITE: Bank = 0 Row = 80, Col = 1, Data = 58f93db1
|
# Status: Burst-No: 1 Write Address: 00050000 WriteData: 58f93db1
|
# Status: Burst-No: 1 Write Address: 00050000 WriteData: 58f93db1
|
# tb_core.u_sdram32 : at time 29297.0 ns WRITE: Bank = 0 Row = 80, Col = 2, Data = 22119f44
|
# tb_core.u_sdram32 : at time 30027.0 ns WRITE: Bank = 0 Row = 80, Col = 2, Data = 22119f44
|
# Status: Burst-No: 2 Write Address: 00050000 WriteData: 22119f44
|
# Status: Burst-No: 2 Write Address: 00050000 WriteData: 22119f44
|
# tb_core.u_sdram32 : at time 29307.0 ns WRITE: Bank = 0 Row = 80, Col = 3, Data = ca9cbc95
|
# tb_core.u_sdram32 : at time 30037.0 ns WRITE: Bank = 0 Row = 80, Col = 3, Data = ca9cbc95
|
# Status: Burst-No: 3 Write Address: 00050000 WriteData: ca9cbc95
|
# Status: Burst-No: 3 Write Address: 00050000 WriteData: ca9cbc95
|
# tb_core.u_sdram32 : at time 29317.0 ns WRITE: Bank = 0 Row = 80, Col = 4, Data = f01d34e0
|
# tb_core.u_sdram32 : at time 30047.0 ns WRITE: Bank = 0 Row = 80, Col = 4, Data = f01d34e0
|
# Status: Burst-No: 4 Write Address: 00050000 WriteData: f01d34e0
|
# Status: Burst-No: 4 Write Address: 00050000 WriteData: f01d34e0
|
# tb_core.u_sdram32 : at time 29327.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 30057.0 ns BST : Burst Terminate
|
# Write Address: 00060000, Burst Size: 6
|
# Write Address: 00060000, Burst Size: 6
|
# tb_core.u_sdram32 : at time 29397.0 ns ACT : Bank = 0 Row = 96
|
# tb_core.u_sdram32 : at time 30127.0 ns ACT : Bank = 0 Row = 96
|
# tb_core.u_sdram32 : at time 29437.0 ns WRITE: Bank = 0 Row = 96, Col = 0, Data = f6a178ed
|
# tb_core.u_sdram32 : at time 30167.0 ns WRITE: Bank = 0 Row = 96, Col = 0, Data = f6a178ed
|
# Status: Burst-No: 0 Write Address: 00060000 WriteData: f6a178ed
|
# Status: Burst-No: 0 Write Address: 00060000 WriteData: f6a178ed
|
# tb_core.u_sdram32 : at time 29447.0 ns WRITE: Bank = 0 Row = 96, Col = 1, Data = 297a1552
|
# tb_core.u_sdram32 : at time 30177.0 ns WRITE: Bank = 0 Row = 96, Col = 1, Data = 297a1552
|
# Status: Burst-No: 1 Write Address: 00060000 WriteData: 297a1552
|
# Status: Burst-No: 1 Write Address: 00060000 WriteData: 297a1552
|
# tb_core.u_sdram32 : at time 29457.0 ns WRITE: Bank = 0 Row = 96, Col = 2, Data = 7c1e5bf8
|
# tb_core.u_sdram32 : at time 30187.0 ns WRITE: Bank = 0 Row = 96, Col = 2, Data = 7c1e5bf8
|
# Status: Burst-No: 2 Write Address: 00060000 WriteData: 7c1e5bf8
|
# Status: Burst-No: 2 Write Address: 00060000 WriteData: 7c1e5bf8
|
# tb_core.u_sdram32 : at time 29467.0 ns WRITE: Bank = 0 Row = 96, Col = 3, Data = 46dcb78d
|
# tb_core.u_sdram32 : at time 30197.0 ns WRITE: Bank = 0 Row = 96, Col = 3, Data = 46dcb78d
|
# Status: Burst-No: 3 Write Address: 00060000 WriteData: 46dcb78d
|
# Status: Burst-No: 3 Write Address: 00060000 WriteData: 46dcb78d
|
# tb_core.u_sdram32 : at time 29477.0 ns WRITE: Bank = 0 Row = 96, Col = 4, Data = a95fc452
|
# tb_core.u_sdram32 : at time 30207.0 ns WRITE: Bank = 0 Row = 96, Col = 4, Data = a95fc452
|
# Status: Burst-No: 4 Write Address: 00060000 WriteData: a95fc452
|
# Status: Burst-No: 4 Write Address: 00060000 WriteData: a95fc452
|
# tb_core.u_sdram32 : at time 29487.0 ns WRITE: Bank = 0 Row = 96, Col = 5, Data = 4219e784
|
# tb_core.u_sdram32 : at time 30217.0 ns WRITE: Bank = 0 Row = 96, Col = 5, Data = 4219e784
|
# Status: Burst-No: 5 Write Address: 00060000 WriteData: 4219e784
|
# Status: Burst-No: 5 Write Address: 00060000 WriteData: 4219e784
|
# tb_core.u_sdram32 : at time 29497.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 30227.0 ns BST : Burst Terminate
|
# Write Address: 00070000, Burst Size: 7
|
# Write Address: 00070000, Burst Size: 7
|
# tb_core.u_sdram32 : at time 29567.0 ns ACT : Bank = 0 Row = 112
|
# tb_core.u_sdram32 : at time 30297.0 ns ACT : Bank = 0 Row = 112
|
# tb_core.u_sdram32 : at time 29607.0 ns WRITE: Bank = 0 Row = 112, Col = 0, Data = 236afd46
|
# tb_core.u_sdram32 : at time 30337.0 ns WRITE: Bank = 0 Row = 112, Col = 0, Data = 236afd46
|
# Status: Burst-No: 0 Write Address: 00070000 WriteData: 236afd46
|
# Status: Burst-No: 0 Write Address: 00070000 WriteData: 236afd46
|
# tb_core.u_sdram32 : at time 29617.0 ns WRITE: Bank = 0 Row = 112, Col = 1, Data = c63a928c
|
# tb_core.u_sdram32 : at time 30347.0 ns WRITE: Bank = 0 Row = 112, Col = 1, Data = c63a928c
|
# Status: Burst-No: 1 Write Address: 00070000 WriteData: c63a928c
|
# Status: Burst-No: 1 Write Address: 00070000 WriteData: c63a928c
|
# tb_core.u_sdram32 : at time 29627.0 ns WRITE: Bank = 0 Row = 112, Col = 2, Data = 48487d90
|
# tb_core.u_sdram32 : at time 30357.0 ns WRITE: Bank = 0 Row = 112, Col = 2, Data = 48487d90
|
# Status: Burst-No: 2 Write Address: 00070000 WriteData: 48487d90
|
# Status: Burst-No: 2 Write Address: 00070000 WriteData: 48487d90
|
# tb_core.u_sdram32 : at time 29637.0 ns WRITE: Bank = 0 Row = 112, Col = 3, Data = 0beac117
|
# tb_core.u_sdram32 : at time 30367.0 ns WRITE: Bank = 0 Row = 112, Col = 3, Data = 0beac117
|
# Status: Burst-No: 3 Write Address: 00070000 WriteData: 0beac117
|
# Status: Burst-No: 3 Write Address: 00070000 WriteData: 0beac117
|
# tb_core.u_sdram32 : at time 29647.0 ns WRITE: Bank = 0 Row = 112, Col = 4, Data = 352d616a
|
# tb_core.u_sdram32 : at time 30377.0 ns WRITE: Bank = 0 Row = 112, Col = 4, Data = 352d616a
|
# Status: Burst-No: 4 Write Address: 00070000 WriteData: 352d616a
|
# Status: Burst-No: 4 Write Address: 00070000 WriteData: 352d616a
|
# tb_core.u_sdram32 : at time 29657.0 ns WRITE: Bank = 0 Row = 112, Col = 5, Data = 427b5784
|
# tb_core.u_sdram32 : at time 30387.0 ns WRITE: Bank = 0 Row = 112, Col = 5, Data = 427b5784
|
# Status: Burst-No: 5 Write Address: 00070000 WriteData: 427b5784
|
# Status: Burst-No: 5 Write Address: 00070000 WriteData: 427b5784
|
# tb_core.u_sdram32 : at time 29667.0 ns WRITE: Bank = 0 Row = 112, Col = 6, Data = d55bbcaa
|
# tb_core.u_sdram32 : at time 30397.0 ns WRITE: Bank = 0 Row = 112, Col = 6, Data = d55bbcaa
|
# Status: Burst-No: 6 Write Address: 00070000 WriteData: d55bbcaa
|
# Status: Burst-No: 6 Write Address: 00070000 WriteData: d55bbcaa
|
# tb_core.u_sdram32 : at time 29677.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 30407.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 29737.0 ns ACT : Bank = 0 Row = 64
|
# tb_core.u_sdram32 : at time 30477.0 ns ACT : Bank = 0 Row = 64
|
# tb_core.u_sdram32 : at time 29803.0 ns READ : Bank = 0 Row = 64, Col = 0, Data = bde0d27b
|
# tb_core.u_sdram32 : at time 30543.0 ns READ : Bank = 0 Row = 64, Col = 0, Data = bde0d27b
|
# tb_core.u_sdram32 : at time 29813.0 ns READ : Bank = 0 Row = 64, Col = 1, Data = 47e2738f
|
# tb_core.u_sdram32 : at time 30553.0 ns READ : Bank = 0 Row = 64, Col = 1, Data = 47e2738f
|
# READ STATUS: Burst-No: 0 Addr: 00040000 Rxd: bde0d27b
|
# READ STATUS: Burst-No: 0 Addr: 00040000 Rxd: bde0d27b
|
# tb_core.u_sdram32 : at time 29817.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 30557.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 29823.0 ns READ : Bank = 0 Row = 64, Col = 2, Data = 81c39a03
|
# tb_core.u_sdram32 : at time 30563.0 ns READ : Bank = 0 Row = 64, Col = 2, Data = 81c39a03
|
# READ STATUS: Burst-No: 1 Addr: 00040002 Rxd: 47e2738f
|
# READ STATUS: Burst-No: 1 Addr: 00040002 Rxd: 47e2738f
|
# tb_core.u_sdram32 : at time 29833.0 ns READ : Bank = 0 Row = 64, Col = 3, Data = 71c129e3
|
# tb_core.u_sdram32 : at time 30573.0 ns READ : Bank = 0 Row = 64, Col = 3, Data = 71c129e3
|
# READ STATUS: Burst-No: 2 Addr: 00040004 Rxd: 81c39a03
|
# READ STATUS: Burst-No: 2 Addr: 00040004 Rxd: 81c39a03
|
# READ STATUS: Burst-No: 3 Addr: 00040006 Rxd: 71c129e3
|
# READ STATUS: Burst-No: 3 Addr: 00040006 Rxd: 71c129e3
|
# tb_core.u_sdram32 : at time 29927.0 ns ACT : Bank = 0 Row = 80
|
# tb_core.u_sdram32 : at time 30677.0 ns ACT : Bank = 0 Row = 80
|
# tb_core.u_sdram32 : at time 29993.0 ns READ : Bank = 0 Row = 80, Col = 0, Data = 0e92431d
|
# tb_core.u_sdram32 : at time 30743.0 ns READ : Bank = 0 Row = 80, Col = 0, Data = 0e92431d
|
# tb_core.u_sdram32 : at time 30003.0 ns READ : Bank = 0 Row = 80, Col = 1, Data = 58f93db1
|
# tb_core.u_sdram32 : at time 30753.0 ns READ : Bank = 0 Row = 80, Col = 1, Data = 58f93db1
|
# READ STATUS: Burst-No: 0 Addr: 00050000 Rxd: 0e92431d
|
# READ STATUS: Burst-No: 0 Addr: 00050000 Rxd: 0e92431d
|
# tb_core.u_sdram32 : at time 30013.0 ns READ : Bank = 0 Row = 80, Col = 2, Data = 22119f44
|
# tb_core.u_sdram32 : at time 30763.0 ns READ : Bank = 0 Row = 80, Col = 2, Data = 22119f44
|
# tb_core.u_sdram32 : at time 30017.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 30767.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 1 Addr: 00050002 Rxd: 58f93db1
|
# READ STATUS: Burst-No: 1 Addr: 00050002 Rxd: 58f93db1
|
# tb_core.u_sdram32 : at time 30023.0 ns READ : Bank = 0 Row = 80, Col = 3, Data = ca9cbc95
|
# tb_core.u_sdram32 : at time 30773.0 ns READ : Bank = 0 Row = 80, Col = 3, Data = ca9cbc95
|
# READ STATUS: Burst-No: 2 Addr: 00050004 Rxd: 22119f44
|
# READ STATUS: Burst-No: 2 Addr: 00050004 Rxd: 22119f44
|
# tb_core.u_sdram32 : at time 30033.0 ns READ : Bank = 0 Row = 80, Col = 4, Data = f01d34e0
|
# tb_core.u_sdram32 : at time 30783.0 ns READ : Bank = 0 Row = 80, Col = 4, Data = f01d34e0
|
# READ STATUS: Burst-No: 3 Addr: 00050006 Rxd: ca9cbc95
|
# READ STATUS: Burst-No: 3 Addr: 00050006 Rxd: ca9cbc95
|
# READ STATUS: Burst-No: 4 Addr: 00050008 Rxd: f01d34e0
|
# READ STATUS: Burst-No: 4 Addr: 00050008 Rxd: f01d34e0
|
# tb_core.u_sdram32 : at time 30127.0 ns ACT : Bank = 0 Row = 96
|
# tb_core.u_sdram32 : at time 30887.0 ns ACT : Bank = 0 Row = 96
|
# tb_core.u_sdram32 : at time 30193.0 ns READ : Bank = 0 Row = 96, Col = 0, Data = f6a178ed
|
# tb_core.u_sdram32 : at time 30953.0 ns READ : Bank = 0 Row = 96, Col = 0, Data = f6a178ed
|
# tb_core.u_sdram32 : at time 30203.0 ns READ : Bank = 0 Row = 96, Col = 1, Data = 297a1552
|
# tb_core.u_sdram32 : at time 30963.0 ns READ : Bank = 0 Row = 96, Col = 1, Data = 297a1552
|
# READ STATUS: Burst-No: 0 Addr: 00060000 Rxd: f6a178ed
|
# READ STATUS: Burst-No: 0 Addr: 00060000 Rxd: f6a178ed
|
# tb_core.u_sdram32 : at time 30213.0 ns READ : Bank = 0 Row = 96, Col = 2, Data = 7c1e5bf8
|
# tb_core.u_sdram32 : at time 30973.0 ns READ : Bank = 0 Row = 96, Col = 2, Data = 7c1e5bf8
|
# READ STATUS: Burst-No: 1 Addr: 00060002 Rxd: 297a1552
|
# READ STATUS: Burst-No: 1 Addr: 00060002 Rxd: 297a1552
|
# tb_core.u_sdram32 : at time 30223.0 ns READ : Bank = 0 Row = 96, Col = 3, Data = 46dcb78d
|
# tb_core.u_sdram32 : at time 30983.0 ns READ : Bank = 0 Row = 96, Col = 3, Data = 46dcb78d
|
# tb_core.u_sdram32 : at time 30227.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 30987.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 2 Addr: 00060004 Rxd: 7c1e5bf8
|
# READ STATUS: Burst-No: 2 Addr: 00060004 Rxd: 7c1e5bf8
|
# tb_core.u_sdram32 : at time 30233.0 ns READ : Bank = 0 Row = 96, Col = 4, Data = a95fc452
|
# tb_core.u_sdram32 : at time 30993.0 ns READ : Bank = 0 Row = 96, Col = 4, Data = a95fc452
|
# READ STATUS: Burst-No: 3 Addr: 00060006 Rxd: 46dcb78d
|
# READ STATUS: Burst-No: 3 Addr: 00060006 Rxd: 46dcb78d
|
# tb_core.u_sdram32 : at time 30243.0 ns READ : Bank = 0 Row = 96, Col = 5, Data = 4219e784
|
# tb_core.u_sdram32 : at time 31003.0 ns READ : Bank = 0 Row = 96, Col = 5, Data = 4219e784
|
# READ STATUS: Burst-No: 4 Addr: 00060008 Rxd: a95fc452
|
# READ STATUS: Burst-No: 4 Addr: 00060008 Rxd: a95fc452
|
# READ STATUS: Burst-No: 5 Addr: 0006000a Rxd: 4219e784
|
# READ STATUS: Burst-No: 5 Addr: 0006000a Rxd: 4219e784
|
# tb_core.u_sdram32 : at time 30337.0 ns ACT : Bank = 0 Row = 112
|
# tb_core.u_sdram32 : at time 31107.0 ns ACT : Bank = 0 Row = 112
|
# tb_core.u_sdram32 : at time 30403.0 ns READ : Bank = 0 Row = 112, Col = 0, Data = 236afd46
|
# tb_core.u_sdram32 : at time 31173.0 ns READ : Bank = 0 Row = 112, Col = 0, Data = 236afd46
|
# tb_core.u_sdram32 : at time 30413.0 ns READ : Bank = 0 Row = 112, Col = 1, Data = c63a928c
|
# tb_core.u_sdram32 : at time 31183.0 ns READ : Bank = 0 Row = 112, Col = 1, Data = c63a928c
|
# READ STATUS: Burst-No: 0 Addr: 00070000 Rxd: 236afd46
|
# READ STATUS: Burst-No: 0 Addr: 00070000 Rxd: 236afd46
|
# tb_core.u_sdram32 : at time 30423.0 ns READ : Bank = 0 Row = 112, Col = 2, Data = 48487d90
|
# tb_core.u_sdram32 : at time 31193.0 ns READ : Bank = 0 Row = 112, Col = 2, Data = 48487d90
|
# READ STATUS: Burst-No: 1 Addr: 00070002 Rxd: c63a928c
|
# READ STATUS: Burst-No: 1 Addr: 00070002 Rxd: c63a928c
|
# tb_core.u_sdram32 : at time 30433.0 ns READ : Bank = 0 Row = 112, Col = 3, Data = 0beac117
|
# tb_core.u_sdram32 : at time 31203.0 ns READ : Bank = 0 Row = 112, Col = 3, Data = 0beac117
|
# READ STATUS: Burst-No: 2 Addr: 00070004 Rxd: 48487d90
|
# READ STATUS: Burst-No: 2 Addr: 00070004 Rxd: 48487d90
|
# tb_core.u_sdram32 : at time 30443.0 ns READ : Bank = 0 Row = 112, Col = 4, Data = 352d616a
|
# tb_core.u_sdram32 : at time 31213.0 ns READ : Bank = 0 Row = 112, Col = 4, Data = 352d616a
|
# tb_core.u_sdram32 : at time 30447.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 31217.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 3 Addr: 00070006 Rxd: 0beac117
|
# READ STATUS: Burst-No: 3 Addr: 00070006 Rxd: 0beac117
|
# tb_core.u_sdram32 : at time 30453.0 ns READ : Bank = 0 Row = 112, Col = 5, Data = 427b5784
|
# tb_core.u_sdram32 : at time 31223.0 ns READ : Bank = 0 Row = 112, Col = 5, Data = 427b5784
|
# READ STATUS: Burst-No: 4 Addr: 00070008 Rxd: 352d616a
|
# READ STATUS: Burst-No: 4 Addr: 00070008 Rxd: 352d616a
|
# tb_core.u_sdram32 : at time 30463.0 ns READ : Bank = 0 Row = 112, Col = 6, Data = d55bbcaa
|
# tb_core.u_sdram32 : at time 31233.0 ns READ : Bank = 0 Row = 112, Col = 6, Data = d55bbcaa
|
# READ STATUS: Burst-No: 5 Addr: 0007000a Rxd: 427b5784
|
# READ STATUS: Burst-No: 5 Addr: 0007000a Rxd: 427b5784
|
# READ STATUS: Burst-No: 6 Addr: 0007000c Rxd: d55bbcaa
|
# READ STATUS: Burst-No: 6 Addr: 0007000c Rxd: d55bbcaa
|
# ---------------------------------------
|
# ---------------------------------------
|
# Case:5 24 Write & 24 Read With Different Bank and Row
|
# Case:5 24 Write & 24 Read With Different Bank and Row
|
# ---------------------------------------
|
# ---------------------------------------
|
# Write Address: 00000000, Burst Size: 4
|
# Write Address: 00000000, Burst Size: 4
|
# tb_core.u_sdram32 : at time 30567.0 ns ACT : Bank = 0 Row = 0
|
# tb_core.u_sdram32 : at time 31337.0 ns ACT : Bank = 0 Row = 0
|
# tb_core.u_sdram32 : at time 30607.0 ns WRITE: Bank = 0 Row = 0, Col = 0, Data = 3e6f0f7c
|
# tb_core.u_sdram32 : at time 31377.0 ns WRITE: Bank = 0 Row = 0, Col = 0, Data = 3e6f0f7c
|
# Status: Burst-No: 0 Write Address: 00000000 WriteData: 3e6f0f7c
|
# Status: Burst-No: 0 Write Address: 00000000 WriteData: 3e6f0f7c
|
# tb_core.u_sdram32 : at time 30617.0 ns WRITE: Bank = 0 Row = 0, Col = 1, Data = b0520260
|
# tb_core.u_sdram32 : at time 31387.0 ns WRITE: Bank = 0 Row = 0, Col = 1, Data = b0520260
|
# Status: Burst-No: 1 Write Address: 00000000 WriteData: b0520260
|
# Status: Burst-No: 1 Write Address: 00000000 WriteData: b0520260
|
# tb_core.u_sdram32 : at time 30627.0 ns WRITE: Bank = 0 Row = 0, Col = 2, Data = 5d4a4dba
|
# tb_core.u_sdram32 : at time 31397.0 ns WRITE: Bank = 0 Row = 0, Col = 2, Data = 5d4a4dba
|
# Status: Burst-No: 2 Write Address: 00000000 WriteData: 5d4a4dba
|
# Status: Burst-No: 2 Write Address: 00000000 WriteData: 5d4a4dba
|
# tb_core.u_sdram32 : at time 30637.0 ns WRITE: Bank = 0 Row = 0, Col = 3, Data = c5a1608b
|
# tb_core.u_sdram32 : at time 31407.0 ns WRITE: Bank = 0 Row = 0, Col = 3, Data = c5a1608b
|
# Status: Burst-No: 3 Write Address: 00000000 WriteData: c5a1608b
|
# Status: Burst-No: 3 Write Address: 00000000 WriteData: c5a1608b
|
# tb_core.u_sdram32 : at time 30647.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 31417.0 ns BST : Burst Terminate
|
# Write Address: 00000400, Burst Size: 5
|
# Write Address: 00000400, Burst Size: 5
|
# tb_core.u_sdram32 : at time 30717.0 ns ACT : Bank = 1 Row = 0
|
# tb_core.u_sdram32 : at time 31487.0 ns ACT : Bank = 1 Row = 0
|
# tb_core.u_sdram32 : at time 30757.0 ns WRITE: Bank = 1 Row = 0, Col = 0, Data = d31dfea6
|
# tb_core.u_sdram32 : at time 31527.0 ns WRITE: Bank = 1 Row = 0, Col = 0, Data = d31dfea6
|
# Status: Burst-No: 0 Write Address: 00000400 WriteData: d31dfea6
|
# Status: Burst-No: 0 Write Address: 00000400 WriteData: d31dfea6
|
# tb_core.u_sdram32 : at time 30767.0 ns WRITE: Bank = 1 Row = 0, Col = 1, Data = 92831e25
|
# tb_core.u_sdram32 : at time 31537.0 ns WRITE: Bank = 1 Row = 0, Col = 1, Data = 92831e25
|
# Status: Burst-No: 1 Write Address: 00000400 WriteData: 92831e25
|
# Status: Burst-No: 1 Write Address: 00000400 WriteData: 92831e25
|
# tb_core.u_sdram32 : at time 30777.0 ns WRITE: Bank = 1 Row = 0, Col = 2, Data = 19058332
|
# tb_core.u_sdram32 : at time 31547.0 ns WRITE: Bank = 1 Row = 0, Col = 2, Data = 19058332
|
# Status: Burst-No: 2 Write Address: 00000400 WriteData: 19058332
|
# Status: Burst-No: 2 Write Address: 00000400 WriteData: 19058332
|
# tb_core.u_sdram32 : at time 30787.0 ns WRITE: Bank = 1 Row = 0, Col = 3, Data = d10504a2
|
# tb_core.u_sdram32 : at time 31557.0 ns WRITE: Bank = 1 Row = 0, Col = 3, Data = d10504a2
|
# Status: Burst-No: 3 Write Address: 00000400 WriteData: d10504a2
|
# Status: Burst-No: 3 Write Address: 00000400 WriteData: d10504a2
|
# tb_core.u_sdram32 : at time 30797.0 ns WRITE: Bank = 1 Row = 0, Col = 4, Data = a48f7c49
|
# tb_core.u_sdram32 : at time 31567.0 ns WRITE: Bank = 1 Row = 0, Col = 4, Data = a48f7c49
|
# Status: Burst-No: 4 Write Address: 00000400 WriteData: a48f7c49
|
# Status: Burst-No: 4 Write Address: 00000400 WriteData: a48f7c49
|
# tb_core.u_sdram32 : at time 30807.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 31577.0 ns BST : Burst Terminate
|
# Write Address: 00000800, Burst Size: 6
|
# Write Address: 00000800, Burst Size: 6
|
# tb_core.u_sdram32 : at time 30877.0 ns ACT : Bank = 2 Row = 0
|
# tb_core.u_sdram32 : at time 31647.0 ns ACT : Bank = 2 Row = 0
|
# tb_core.u_sdram32 : at time 30917.0 ns WRITE: Bank = 2 Row = 0, Col = 0, Data = 8a64b014
|
# tb_core.u_sdram32 : at time 31687.0 ns WRITE: Bank = 2 Row = 0, Col = 0, Data = 8a64b014
|
# Status: Burst-No: 0 Write Address: 00000800 WriteData: 8a64b014
|
# Status: Burst-No: 0 Write Address: 00000800 WriteData: 8a64b014
|
# tb_core.u_sdram32 : at time 30927.0 ns WRITE: Bank = 2 Row = 0, Col = 1, Data = 9ec9c03d
|
# tb_core.u_sdram32 : at time 31697.0 ns WRITE: Bank = 2 Row = 0, Col = 1, Data = 9ec9c03d
|
# Status: Burst-No: 1 Write Address: 00000800 WriteData: 9ec9c03d
|
# Status: Burst-No: 1 Write Address: 00000800 WriteData: 9ec9c03d
|
# tb_core.u_sdram32 : at time 30937.0 ns WRITE: Bank = 2 Row = 0, Col = 2, Data = 25f2034b
|
# tb_core.u_sdram32 : at time 31707.0 ns WRITE: Bank = 2 Row = 0, Col = 2, Data = 25f2034b
|
# Status: Burst-No: 2 Write Address: 00000800 WriteData: 25f2034b
|
# Status: Burst-No: 2 Write Address: 00000800 WriteData: 25f2034b
|
# tb_core.u_sdram32 : at time 30947.0 ns WRITE: Bank = 2 Row = 0, Col = 3, Data = ae68305c
|
# tb_core.u_sdram32 : at time 31717.0 ns WRITE: Bank = 2 Row = 0, Col = 3, Data = ae68305c
|
# Status: Burst-No: 3 Write Address: 00000800 WriteData: ae68305c
|
# Status: Burst-No: 3 Write Address: 00000800 WriteData: ae68305c
|
# tb_core.u_sdram32 : at time 30957.0 ns WRITE: Bank = 2 Row = 0, Col = 4, Data = 23907547
|
# tb_core.u_sdram32 : at time 31727.0 ns WRITE: Bank = 2 Row = 0, Col = 4, Data = 23907547
|
# Status: Burst-No: 4 Write Address: 00000800 WriteData: 23907547
|
# Status: Burst-No: 4 Write Address: 00000800 WriteData: 23907547
|
# tb_core.u_sdram32 : at time 30967.0 ns WRITE: Bank = 2 Row = 0, Col = 5, Data = 433e9786
|
# tb_core.u_sdram32 : at time 31737.0 ns WRITE: Bank = 2 Row = 0, Col = 5, Data = 433e9786
|
# Status: Burst-No: 5 Write Address: 00000800 WriteData: 433e9786
|
# Status: Burst-No: 5 Write Address: 00000800 WriteData: 433e9786
|
# tb_core.u_sdram32 : at time 30977.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 31747.0 ns BST : Burst Terminate
|
# Write Address: 00000c00, Burst Size: 7
|
# Write Address: 00000c00, Burst Size: 7
|
# tb_core.u_sdram32 : at time 31047.0 ns ACT : Bank = 3 Row = 0
|
# tb_core.u_sdram32 : at time 31817.0 ns ACT : Bank = 3 Row = 0
|
# tb_core.u_sdram32 : at time 31087.0 ns WRITE: Bank = 3 Row = 0, Col = 0, Data = 9caf7a39
|
# tb_core.u_sdram32 : at time 31857.0 ns WRITE: Bank = 3 Row = 0, Col = 0, Data = 9caf7a39
|
# Status: Burst-No: 0 Write Address: 00000c00 WriteData: 9caf7a39
|
# Status: Burst-No: 0 Write Address: 00000c00 WriteData: 9caf7a39
|
# tb_core.u_sdram32 : at time 31097.0 ns WRITE: Bank = 3 Row = 0, Col = 1, Data = da058ab4
|
# tb_core.u_sdram32 : at time 31867.0 ns WRITE: Bank = 3 Row = 0, Col = 1, Data = da058ab4
|
# Status: Burst-No: 1 Write Address: 00000c00 WriteData: da058ab4
|
# Status: Burst-No: 1 Write Address: 00000c00 WriteData: da058ab4
|
# tb_core.u_sdram32 : at time 31107.0 ns WRITE: Bank = 3 Row = 0, Col = 2, Data = 6851e5d0
|
# tb_core.u_sdram32 : at time 31877.0 ns WRITE: Bank = 3 Row = 0, Col = 2, Data = 6851e5d0
|
# Status: Burst-No: 2 Write Address: 00000c00 WriteData: 6851e5d0
|
# Status: Burst-No: 2 Write Address: 00000c00 WriteData: 6851e5d0
|
# tb_core.u_sdram32 : at time 31117.0 ns WRITE: Bank = 3 Row = 0, Col = 3, Data = 9622502c
|
# tb_core.u_sdram32 : at time 31887.0 ns WRITE: Bank = 3 Row = 0, Col = 3, Data = 9622502c
|
# Status: Burst-No: 3 Write Address: 00000c00 WriteData: 9622502c
|
# Status: Burst-No: 3 Write Address: 00000c00 WriteData: 9622502c
|
# tb_core.u_sdram32 : at time 31127.0 ns WRITE: Bank = 3 Row = 0, Col = 4, Data = 467c458c
|
# tb_core.u_sdram32 : at time 31897.0 ns WRITE: Bank = 3 Row = 0, Col = 4, Data = 467c458c
|
# Status: Burst-No: 4 Write Address: 00000c00 WriteData: 467c458c
|
# Status: Burst-No: 4 Write Address: 00000c00 WriteData: 467c458c
|
# tb_core.u_sdram32 : at time 31137.0 ns WRITE: Bank = 3 Row = 0, Col = 5, Data = 03e9b707
|
# tb_core.u_sdram32 : at time 31907.0 ns WRITE: Bank = 3 Row = 0, Col = 5, Data = 03e9b707
|
# Status: Burst-No: 5 Write Address: 00000c00 WriteData: 03e9b707
|
# Status: Burst-No: 5 Write Address: 00000c00 WriteData: 03e9b707
|
# tb_core.u_sdram32 : at time 31147.0 ns WRITE: Bank = 3 Row = 0, Col = 6, Data = b522406a
|
# tb_core.u_sdram32 : at time 31917.0 ns WRITE: Bank = 3 Row = 0, Col = 6, Data = b522406a
|
# Status: Burst-No: 6 Write Address: 00000c00 WriteData: b522406a
|
# Status: Burst-No: 6 Write Address: 00000c00 WriteData: b522406a
|
# tb_core.u_sdram32 : at time 31157.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 31927.0 ns BST : Burst Terminate
|
# Write Address: 00001000, Burst Size: 4
|
# Write Address: 00001000, Burst Size: 4
|
# tb_core.u_sdram32 : at time 31227.0 ns ACT : Bank = 0 Row = 1
|
# tb_core.u_sdram32 : at time 31997.0 ns ACT : Bank = 0 Row = 1
|
# tb_core.u_sdram32 : at time 31267.0 ns WRITE: Bank = 0 Row = 1, Col = 0, Data = 0895f911
|
# tb_core.u_sdram32 : at time 32037.0 ns WRITE: Bank = 0 Row = 1, Col = 0, Data = 0895f911
|
# Status: Burst-No: 0 Write Address: 00001000 WriteData: 0895f911
|
# Status: Burst-No: 0 Write Address: 00001000 WriteData: 0895f911
|
# tb_core.u_sdram32 : at time 31277.0 ns WRITE: Bank = 0 Row = 1, Col = 1, Data = 746affe8
|
# tb_core.u_sdram32 : at time 32047.0 ns WRITE: Bank = 0 Row = 1, Col = 1, Data = 746affe8
|
# Status: Burst-No: 1 Write Address: 00001000 WriteData: 746affe8
|
# Status: Burst-No: 1 Write Address: 00001000 WriteData: 746affe8
|
# tb_core.u_sdram32 : at time 31287.0 ns WRITE: Bank = 0 Row = 1, Col = 2, Data = a5e79e4b
|
# tb_core.u_sdram32 : at time 32057.0 ns WRITE: Bank = 0 Row = 1, Col = 2, Data = a5e79e4b
|
# Status: Burst-No: 2 Write Address: 00001000 WriteData: a5e79e4b
|
# Status: Burst-No: 2 Write Address: 00001000 WriteData: a5e79e4b
|
# tb_core.u_sdram32 : at time 31297.0 ns WRITE: Bank = 0 Row = 1, Col = 3, Data = 39e48173
|
# tb_core.u_sdram32 : at time 32067.0 ns WRITE: Bank = 0 Row = 1, Col = 3, Data = 39e48173
|
# Status: Burst-No: 3 Write Address: 00001000 WriteData: 39e48173
|
# Status: Burst-No: 3 Write Address: 00001000 WriteData: 39e48173
|
# tb_core.u_sdram32 : at time 31307.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 32077.0 ns BST : Burst Terminate
|
# Write Address: 00001400, Burst Size: 5
|
# Write Address: 00001400, Burst Size: 5
|
# tb_core.u_sdram32 : at time 31377.0 ns ACT : Bank = 1 Row = 1
|
# tb_core.u_sdram32 : at time 32147.0 ns ACT : Bank = 1 Row = 1
|
# tb_core.u_sdram32 : at time 31417.0 ns WRITE: Bank = 1 Row = 1, Col = 0, Data = 76295bec
|
# tb_core.u_sdram32 : at time 32187.0 ns WRITE: Bank = 1 Row = 1, Col = 0, Data = 76295bec
|
# Status: Burst-No: 0 Write Address: 00001400 WriteData: 76295bec
|
# Status: Burst-No: 0 Write Address: 00001400 WriteData: 76295bec
|
# tb_core.u_sdram32 : at time 31427.0 ns WRITE: Bank = 1 Row = 1, Col = 1, Data = 11fe0523
|
# tb_core.u_sdram32 : at time 32197.0 ns WRITE: Bank = 1 Row = 1, Col = 1, Data = 11fe0523
|
# Status: Burst-No: 1 Write Address: 00001400 WriteData: 11fe0523
|
# Status: Burst-No: 1 Write Address: 00001400 WriteData: 11fe0523
|
# tb_core.u_sdram32 : at time 31437.0 ns WRITE: Bank = 1 Row = 1, Col = 2, Data = 520eefa4
|
# tb_core.u_sdram32 : at time 32207.0 ns WRITE: Bank = 1 Row = 1, Col = 2, Data = 520eefa4
|
# Status: Burst-No: 2 Write Address: 00001400 WriteData: 520eefa4
|
# Status: Burst-No: 2 Write Address: 00001400 WriteData: 520eefa4
|
# tb_core.u_sdram32 : at time 31447.0 ns WRITE: Bank = 1 Row = 1, Col = 3, Data = 64e165c9
|
# tb_core.u_sdram32 : at time 32217.0 ns WRITE: Bank = 1 Row = 1, Col = 3, Data = 64e165c9
|
# Status: Burst-No: 3 Write Address: 00001400 WriteData: 64e165c9
|
# Status: Burst-No: 3 Write Address: 00001400 WriteData: 64e165c9
|
# tb_core.u_sdram32 : at time 31457.0 ns WRITE: Bank = 1 Row = 1, Col = 4, Data = 9ca70439
|
# tb_core.u_sdram32 : at time 32227.0 ns WRITE: Bank = 1 Row = 1, Col = 4, Data = 9ca70439
|
# Status: Burst-No: 4 Write Address: 00001400 WriteData: 9ca70439
|
# Status: Burst-No: 4 Write Address: 00001400 WriteData: 9ca70439
|
# tb_core.u_sdram32 : at time 31467.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 32237.0 ns BST : Burst Terminate
|
# Write Address: 00001800, Burst Size: 6
|
# Write Address: 00001800, Burst Size: 6
|
# tb_core.u_sdram32 : at time 31537.0 ns ACT : Bank = 2 Row = 1
|
# tb_core.u_sdram32 : at time 32307.0 ns ACT : Bank = 2 Row = 1
|
# tb_core.u_sdram32 : at time 31577.0 ns WRITE: Bank = 2 Row = 1, Col = 0, Data = ef8372df
|
# tb_core.u_sdram32 : at time 32347.0 ns WRITE: Bank = 2 Row = 1, Col = 0, Data = ef8372df
|
# Status: Burst-No: 0 Write Address: 00001800 WriteData: ef8372df
|
# Status: Burst-No: 0 Write Address: 00001800 WriteData: ef8372df
|
# tb_core.u_sdram32 : at time 31587.0 ns WRITE: Bank = 2 Row = 1, Col = 1, Data = ea5814d4
|
# tb_core.u_sdram32 : at time 32357.0 ns WRITE: Bank = 2 Row = 1, Col = 1, Data = ea5814d4
|
# Status: Burst-No: 1 Write Address: 00001800 WriteData: ea5814d4
|
# Status: Burst-No: 1 Write Address: 00001800 WriteData: ea5814d4
|
# tb_core.u_sdram32 : at time 31597.0 ns WRITE: Bank = 2 Row = 1, Col = 2, Data = 33836567
|
# tb_core.u_sdram32 : at time 32367.0 ns WRITE: Bank = 2 Row = 1, Col = 2, Data = 33836567
|
# Status: Burst-No: 2 Write Address: 00001800 WriteData: 33836567
|
# Status: Burst-No: 2 Write Address: 00001800 WriteData: 33836567
|
# tb_core.u_sdram32 : at time 31607.0 ns WRITE: Bank = 2 Row = 1, Col = 3, Data = 4ea0419d
|
# tb_core.u_sdram32 : at time 32377.0 ns WRITE: Bank = 2 Row = 1, Col = 3, Data = 4ea0419d
|
# Status: Burst-No: 3 Write Address: 00001800 WriteData: 4ea0419d
|
# Status: Burst-No: 3 Write Address: 00001800 WriteData: 4ea0419d
|
# tb_core.u_sdram32 : at time 31617.0 ns WRITE: Bank = 2 Row = 1, Col = 4, Data = 583125b0
|
# tb_core.u_sdram32 : at time 32387.0 ns WRITE: Bank = 2 Row = 1, Col = 4, Data = 583125b0
|
# Status: Burst-No: 4 Write Address: 00001800 WriteData: 583125b0
|
# Status: Burst-No: 4 Write Address: 00001800 WriteData: 583125b0
|
# tb_core.u_sdram32 : at time 31627.0 ns WRITE: Bank = 2 Row = 1, Col = 5, Data = 41103982
|
# tb_core.u_sdram32 : at time 32397.0 ns WRITE: Bank = 2 Row = 1, Col = 5, Data = 41103982
|
# Status: Burst-No: 5 Write Address: 00001800 WriteData: 41103982
|
# Status: Burst-No: 5 Write Address: 00001800 WriteData: 41103982
|
# tb_core.u_sdram32 : at time 31637.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 32407.0 ns BST : Burst Terminate
|
# Write Address: 00001c00, Burst Size: 7
|
# Write Address: 00001c00, Burst Size: 7
|
# tb_core.u_sdram32 : at time 31707.0 ns ACT : Bank = 3 Row = 1
|
# tb_core.u_sdram32 : at time 32477.0 ns ACT : Bank = 3 Row = 1
|
# tb_core.u_sdram32 : at time 31747.0 ns WRITE: Bank = 3 Row = 1, Col = 0, Data = 24d2bf49
|
# tb_core.u_sdram32 : at time 32517.0 ns WRITE: Bank = 3 Row = 1, Col = 0, Data = 24d2bf49
|
# Status: Burst-No: 0 Write Address: 00001c00 WriteData: 24d2bf49
|
# Status: Burst-No: 0 Write Address: 00001c00 WriteData: 24d2bf49
|
# tb_core.u_sdram32 : at time 31757.0 ns WRITE: Bank = 3 Row = 1, Col = 1, Data = ecb91ad9
|
# tb_core.u_sdram32 : at time 32527.0 ns WRITE: Bank = 3 Row = 1, Col = 1, Data = ecb91ad9
|
# Status: Burst-No: 1 Write Address: 00001c00 WriteData: ecb91ad9
|
# Status: Burst-No: 1 Write Address: 00001c00 WriteData: ecb91ad9
|
# tb_core.u_sdram32 : at time 31767.0 ns WRITE: Bank = 3 Row = 1, Col = 2, Data = 1000b720
|
# tb_core.u_sdram32 : at time 32537.0 ns WRITE: Bank = 3 Row = 1, Col = 2, Data = 1000b720
|
# Status: Burst-No: 2 Write Address: 00001c00 WriteData: 1000b720
|
# Status: Burst-No: 2 Write Address: 00001c00 WriteData: 1000b720
|
# tb_core.u_sdram32 : at time 31777.0 ns WRITE: Bank = 3 Row = 1, Col = 3, Data = 8e054c1c
|
# tb_core.u_sdram32 : at time 32547.0 ns WRITE: Bank = 3 Row = 1, Col = 3, Data = 8e054c1c
|
# Status: Burst-No: 3 Write Address: 00001c00 WriteData: 8e054c1c
|
# Status: Burst-No: 3 Write Address: 00001c00 WriteData: 8e054c1c
|
# tb_core.u_sdram32 : at time 31787.0 ns WRITE: Bank = 3 Row = 1, Col = 4, Data = 49b16f93
|
# tb_core.u_sdram32 : at time 32557.0 ns WRITE: Bank = 3 Row = 1, Col = 4, Data = 49b16f93
|
# Status: Burst-No: 4 Write Address: 00001c00 WriteData: 49b16f93
|
# Status: Burst-No: 4 Write Address: 00001c00 WriteData: 49b16f93
|
# tb_core.u_sdram32 : at time 31797.0 ns WRITE: Bank = 3 Row = 1, Col = 5, Data = 71b461e3
|
# tb_core.u_sdram32 : at time 32567.0 ns WRITE: Bank = 3 Row = 1, Col = 5, Data = 71b461e3
|
# Status: Burst-No: 5 Write Address: 00001c00 WriteData: 71b461e3
|
# Status: Burst-No: 5 Write Address: 00001c00 WriteData: 71b461e3
|
# tb_core.u_sdram32 : at time 31807.0 ns WRITE: Bank = 3 Row = 1, Col = 6, Data = 954b822a
|
# tb_core.u_sdram32 : at time 32577.0 ns WRITE: Bank = 3 Row = 1, Col = 6, Data = 954b822a
|
# Status: Burst-No: 6 Write Address: 00001c00 WriteData: 954b822a
|
# Status: Burst-No: 6 Write Address: 00001c00 WriteData: 954b822a
|
# tb_core.u_sdram32 : at time 31817.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 32587.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 31877.0 ns ACT : Bank = 0 Row = 0
|
# tb_core.u_sdram32 : at time 32657.0 ns ACT : Bank = 0 Row = 0
|
# tb_core.u_sdram32 : at time 31943.0 ns READ : Bank = 0 Row = 0, Col = 0, Data = 3e6f0f7c
|
# tb_core.u_sdram32 : at time 32723.0 ns READ : Bank = 0 Row = 0, Col = 0, Data = 3e6f0f7c
|
# tb_core.u_sdram32 : at time 31953.0 ns READ : Bank = 0 Row = 0, Col = 1, Data = b0520260
|
# tb_core.u_sdram32 : at time 32733.0 ns READ : Bank = 0 Row = 0, Col = 1, Data = b0520260
|
# READ STATUS: Burst-No: 0 Addr: 00000000 Rxd: 3e6f0f7c
|
# READ STATUS: Burst-No: 0 Addr: 00000000 Rxd: 3e6f0f7c
|
# tb_core.u_sdram32 : at time 31957.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 32737.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 31963.0 ns READ : Bank = 0 Row = 0, Col = 2, Data = 5d4a4dba
|
# tb_core.u_sdram32 : at time 32743.0 ns READ : Bank = 0 Row = 0, Col = 2, Data = 5d4a4dba
|
# READ STATUS: Burst-No: 1 Addr: 00000002 Rxd: b0520260
|
# READ STATUS: Burst-No: 1 Addr: 00000002 Rxd: b0520260
|
# tb_core.u_sdram32 : at time 31973.0 ns READ : Bank = 0 Row = 0, Col = 3, Data = c5a1608b
|
# tb_core.u_sdram32 : at time 32753.0 ns READ : Bank = 0 Row = 0, Col = 3, Data = c5a1608b
|
# READ STATUS: Burst-No: 2 Addr: 00000004 Rxd: 5d4a4dba
|
# READ STATUS: Burst-No: 2 Addr: 00000004 Rxd: 5d4a4dba
|
# READ STATUS: Burst-No: 3 Addr: 00000006 Rxd: c5a1608b
|
# READ STATUS: Burst-No: 3 Addr: 00000006 Rxd: c5a1608b
|
# tb_core.u_sdram32 : at time 32067.0 ns ACT : Bank = 1 Row = 0
|
# tb_core.u_sdram32 : at time 32857.0 ns ACT : Bank = 1 Row = 0
|
# tb_core.u_sdram32 : at time 32133.0 ns READ : Bank = 1 Row = 0, Col = 0, Data = d31dfea6
|
# tb_core.u_sdram32 : at time 32923.0 ns READ : Bank = 1 Row = 0, Col = 0, Data = d31dfea6
|
# tb_core.u_sdram32 : at time 32143.0 ns READ : Bank = 1 Row = 0, Col = 1, Data = 92831e25
|
# tb_core.u_sdram32 : at time 32933.0 ns READ : Bank = 1 Row = 0, Col = 1, Data = 92831e25
|
# READ STATUS: Burst-No: 0 Addr: 00000400 Rxd: d31dfea6
|
# READ STATUS: Burst-No: 0 Addr: 00000400 Rxd: d31dfea6
|
# tb_core.u_sdram32 : at time 32153.0 ns READ : Bank = 1 Row = 0, Col = 2, Data = 19058332
|
# tb_core.u_sdram32 : at time 32943.0 ns READ : Bank = 1 Row = 0, Col = 2, Data = 19058332
|
# tb_core.u_sdram32 : at time 32157.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 32947.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 1 Addr: 00000402 Rxd: 92831e25
|
# READ STATUS: Burst-No: 1 Addr: 00000402 Rxd: 92831e25
|
# tb_core.u_sdram32 : at time 32163.0 ns READ : Bank = 1 Row = 0, Col = 3, Data = d10504a2
|
# tb_core.u_sdram32 : at time 32953.0 ns READ : Bank = 1 Row = 0, Col = 3, Data = d10504a2
|
# READ STATUS: Burst-No: 2 Addr: 00000404 Rxd: 19058332
|
# READ STATUS: Burst-No: 2 Addr: 00000404 Rxd: 19058332
|
# tb_core.u_sdram32 : at time 32173.0 ns READ : Bank = 1 Row = 0, Col = 4, Data = a48f7c49
|
# tb_core.u_sdram32 : at time 32963.0 ns READ : Bank = 1 Row = 0, Col = 4, Data = a48f7c49
|
# READ STATUS: Burst-No: 3 Addr: 00000406 Rxd: d10504a2
|
# READ STATUS: Burst-No: 3 Addr: 00000406 Rxd: d10504a2
|
# READ STATUS: Burst-No: 4 Addr: 00000408 Rxd: a48f7c49
|
# READ STATUS: Burst-No: 4 Addr: 00000408 Rxd: a48f7c49
|
# tb_core.u_sdram32 : at time 32267.0 ns ACT : Bank = 2 Row = 0
|
# tb_core.u_sdram32 : at time 33067.0 ns ACT : Bank = 2 Row = 0
|
# tb_core.u_sdram32 : at time 32333.0 ns READ : Bank = 2 Row = 0, Col = 0, Data = 8a64b014
|
# tb_core.u_sdram32 : at time 33133.0 ns READ : Bank = 2 Row = 0, Col = 0, Data = 8a64b014
|
# tb_core.u_sdram32 : at time 32343.0 ns READ : Bank = 2 Row = 0, Col = 1, Data = 9ec9c03d
|
# tb_core.u_sdram32 : at time 33143.0 ns READ : Bank = 2 Row = 0, Col = 1, Data = 9ec9c03d
|
# READ STATUS: Burst-No: 0 Addr: 00000800 Rxd: 8a64b014
|
# READ STATUS: Burst-No: 0 Addr: 00000800 Rxd: 8a64b014
|
# tb_core.u_sdram32 : at time 32353.0 ns READ : Bank = 2 Row = 0, Col = 2, Data = 25f2034b
|
# tb_core.u_sdram32 : at time 33153.0 ns READ : Bank = 2 Row = 0, Col = 2, Data = 25f2034b
|
# READ STATUS: Burst-No: 1 Addr: 00000802 Rxd: 9ec9c03d
|
# READ STATUS: Burst-No: 1 Addr: 00000802 Rxd: 9ec9c03d
|
# tb_core.u_sdram32 : at time 32363.0 ns READ : Bank = 2 Row = 0, Col = 3, Data = ae68305c
|
# tb_core.u_sdram32 : at time 33163.0 ns READ : Bank = 2 Row = 0, Col = 3, Data = ae68305c
|
# tb_core.u_sdram32 : at time 32367.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 33167.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 2 Addr: 00000804 Rxd: 25f2034b
|
# READ STATUS: Burst-No: 2 Addr: 00000804 Rxd: 25f2034b
|
# tb_core.u_sdram32 : at time 32373.0 ns READ : Bank = 2 Row = 0, Col = 4, Data = 23907547
|
# tb_core.u_sdram32 : at time 33173.0 ns READ : Bank = 2 Row = 0, Col = 4, Data = 23907547
|
# READ STATUS: Burst-No: 3 Addr: 00000806 Rxd: ae68305c
|
# READ STATUS: Burst-No: 3 Addr: 00000806 Rxd: ae68305c
|
# tb_core.u_sdram32 : at time 32383.0 ns READ : Bank = 2 Row = 0, Col = 5, Data = 433e9786
|
# tb_core.u_sdram32 : at time 33183.0 ns READ : Bank = 2 Row = 0, Col = 5, Data = 433e9786
|
# READ STATUS: Burst-No: 4 Addr: 00000808 Rxd: 23907547
|
# READ STATUS: Burst-No: 4 Addr: 00000808 Rxd: 23907547
|
# READ STATUS: Burst-No: 5 Addr: 0000080a Rxd: 433e9786
|
# READ STATUS: Burst-No: 5 Addr: 0000080a Rxd: 433e9786
|
# tb_core.u_sdram32 : at time 32477.0 ns ACT : Bank = 3 Row = 0
|
# tb_core.u_sdram32 : at time 33287.0 ns ACT : Bank = 3 Row = 0
|
# tb_core.u_sdram32 : at time 32543.0 ns READ : Bank = 3 Row = 0, Col = 0, Data = 9caf7a39
|
# tb_core.u_sdram32 : at time 33353.0 ns READ : Bank = 3 Row = 0, Col = 0, Data = 9caf7a39
|
# tb_core.u_sdram32 : at time 32553.0 ns READ : Bank = 3 Row = 0, Col = 1, Data = da058ab4
|
# tb_core.u_sdram32 : at time 33363.0 ns READ : Bank = 3 Row = 0, Col = 1, Data = da058ab4
|
# READ STATUS: Burst-No: 0 Addr: 00000c00 Rxd: 9caf7a39
|
# READ STATUS: Burst-No: 0 Addr: 00000c00 Rxd: 9caf7a39
|
# tb_core.u_sdram32 : at time 32563.0 ns READ : Bank = 3 Row = 0, Col = 2, Data = 6851e5d0
|
# tb_core.u_sdram32 : at time 33373.0 ns READ : Bank = 3 Row = 0, Col = 2, Data = 6851e5d0
|
# READ STATUS: Burst-No: 1 Addr: 00000c02 Rxd: da058ab4
|
# READ STATUS: Burst-No: 1 Addr: 00000c02 Rxd: da058ab4
|
# tb_core.u_sdram32 : at time 32573.0 ns READ : Bank = 3 Row = 0, Col = 3, Data = 9622502c
|
# tb_core.u_sdram32 : at time 33383.0 ns READ : Bank = 3 Row = 0, Col = 3, Data = 9622502c
|
# READ STATUS: Burst-No: 2 Addr: 00000c04 Rxd: 6851e5d0
|
# READ STATUS: Burst-No: 2 Addr: 00000c04 Rxd: 6851e5d0
|
# tb_core.u_sdram32 : at time 32583.0 ns READ : Bank = 3 Row = 0, Col = 4, Data = 467c458c
|
# tb_core.u_sdram32 : at time 33393.0 ns READ : Bank = 3 Row = 0, Col = 4, Data = 467c458c
|
# tb_core.u_sdram32 : at time 32587.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 33397.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 3 Addr: 00000c06 Rxd: 9622502c
|
# READ STATUS: Burst-No: 3 Addr: 00000c06 Rxd: 9622502c
|
# tb_core.u_sdram32 : at time 32593.0 ns READ : Bank = 3 Row = 0, Col = 5, Data = 03e9b707
|
# tb_core.u_sdram32 : at time 33403.0 ns READ : Bank = 3 Row = 0, Col = 5, Data = 03e9b707
|
# READ STATUS: Burst-No: 4 Addr: 00000c08 Rxd: 467c458c
|
# READ STATUS: Burst-No: 4 Addr: 00000c08 Rxd: 467c458c
|
# tb_core.u_sdram32 : at time 32603.0 ns READ : Bank = 3 Row = 0, Col = 6, Data = b522406a
|
# tb_core.u_sdram32 : at time 33413.0 ns READ : Bank = 3 Row = 0, Col = 6, Data = b522406a
|
# READ STATUS: Burst-No: 5 Addr: 00000c0a Rxd: 03e9b707
|
# READ STATUS: Burst-No: 5 Addr: 00000c0a Rxd: 03e9b707
|
# READ STATUS: Burst-No: 6 Addr: 00000c0c Rxd: b522406a
|
# READ STATUS: Burst-No: 6 Addr: 00000c0c Rxd: b522406a
|
# tb_core.u_sdram32 : at time 32697.0 ns ACT : Bank = 0 Row = 1
|
# tb_core.u_sdram32 : at time 33517.0 ns ACT : Bank = 0 Row = 1
|
# tb_core.u_sdram32 : at time 32763.0 ns READ : Bank = 0 Row = 1, Col = 0, Data = 0895f911
|
# tb_core.u_sdram32 : at time 33583.0 ns READ : Bank = 0 Row = 1, Col = 0, Data = 0895f911
|
# tb_core.u_sdram32 : at time 32773.0 ns READ : Bank = 0 Row = 1, Col = 1, Data = 746affe8
|
# tb_core.u_sdram32 : at time 33593.0 ns READ : Bank = 0 Row = 1, Col = 1, Data = 746affe8
|
# READ STATUS: Burst-No: 0 Addr: 00001000 Rxd: 0895f911
|
# READ STATUS: Burst-No: 0 Addr: 00001000 Rxd: 0895f911
|
# tb_core.u_sdram32 : at time 32777.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 33597.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 32783.0 ns READ : Bank = 0 Row = 1, Col = 2, Data = a5e79e4b
|
# tb_core.u_sdram32 : at time 33603.0 ns READ : Bank = 0 Row = 1, Col = 2, Data = a5e79e4b
|
# READ STATUS: Burst-No: 1 Addr: 00001002 Rxd: 746affe8
|
# READ STATUS: Burst-No: 1 Addr: 00001002 Rxd: 746affe8
|
# tb_core.u_sdram32 : at time 32793.0 ns READ : Bank = 0 Row = 1, Col = 3, Data = 39e48173
|
# tb_core.u_sdram32 : at time 33613.0 ns READ : Bank = 0 Row = 1, Col = 3, Data = 39e48173
|
# READ STATUS: Burst-No: 2 Addr: 00001004 Rxd: a5e79e4b
|
# READ STATUS: Burst-No: 2 Addr: 00001004 Rxd: a5e79e4b
|
# READ STATUS: Burst-No: 3 Addr: 00001006 Rxd: 39e48173
|
# READ STATUS: Burst-No: 3 Addr: 00001006 Rxd: 39e48173
|
# tb_core.u_sdram32 : at time 32887.0 ns ACT : Bank = 1 Row = 1
|
# tb_core.u_sdram32 : at time 33717.0 ns ACT : Bank = 1 Row = 1
|
# tb_core.u_sdram32 : at time 32953.0 ns READ : Bank = 1 Row = 1, Col = 0, Data = 76295bec
|
# tb_core.u_sdram32 : at time 33783.0 ns READ : Bank = 1 Row = 1, Col = 0, Data = 76295bec
|
# tb_core.u_sdram32 : at time 32963.0 ns READ : Bank = 1 Row = 1, Col = 1, Data = 11fe0523
|
# tb_core.u_sdram32 : at time 33793.0 ns READ : Bank = 1 Row = 1, Col = 1, Data = 11fe0523
|
# READ STATUS: Burst-No: 0 Addr: 00001400 Rxd: 76295bec
|
# READ STATUS: Burst-No: 0 Addr: 00001400 Rxd: 76295bec
|
# tb_core.u_sdram32 : at time 32973.0 ns READ : Bank = 1 Row = 1, Col = 2, Data = 520eefa4
|
# tb_core.u_sdram32 : at time 33803.0 ns READ : Bank = 1 Row = 1, Col = 2, Data = 520eefa4
|
# tb_core.u_sdram32 : at time 32977.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 33807.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 1 Addr: 00001402 Rxd: 11fe0523
|
# READ STATUS: Burst-No: 1 Addr: 00001402 Rxd: 11fe0523
|
# tb_core.u_sdram32 : at time 32983.0 ns READ : Bank = 1 Row = 1, Col = 3, Data = 64e165c9
|
# tb_core.u_sdram32 : at time 33813.0 ns READ : Bank = 1 Row = 1, Col = 3, Data = 64e165c9
|
# READ STATUS: Burst-No: 2 Addr: 00001404 Rxd: 520eefa4
|
# READ STATUS: Burst-No: 2 Addr: 00001404 Rxd: 520eefa4
|
# tb_core.u_sdram32 : at time 32993.0 ns READ : Bank = 1 Row = 1, Col = 4, Data = 9ca70439
|
# tb_core.u_sdram32 : at time 33823.0 ns READ : Bank = 1 Row = 1, Col = 4, Data = 9ca70439
|
# READ STATUS: Burst-No: 3 Addr: 00001406 Rxd: 64e165c9
|
# READ STATUS: Burst-No: 3 Addr: 00001406 Rxd: 64e165c9
|
# READ STATUS: Burst-No: 4 Addr: 00001408 Rxd: 9ca70439
|
# READ STATUS: Burst-No: 4 Addr: 00001408 Rxd: 9ca70439
|
# tb_core.u_sdram32 : at time 33087.0 ns ACT : Bank = 2 Row = 1
|
# tb_core.u_sdram32 : at time 33927.0 ns ACT : Bank = 2 Row = 1
|
# tb_core.u_sdram32 : at time 33153.0 ns READ : Bank = 2 Row = 1, Col = 0, Data = ef8372df
|
# tb_core.u_sdram32 : at time 33993.0 ns READ : Bank = 2 Row = 1, Col = 0, Data = ef8372df
|
# tb_core.u_sdram32 : at time 33163.0 ns READ : Bank = 2 Row = 1, Col = 1, Data = ea5814d4
|
# tb_core.u_sdram32 : at time 34003.0 ns READ : Bank = 2 Row = 1, Col = 1, Data = ea5814d4
|
# READ STATUS: Burst-No: 0 Addr: 00001800 Rxd: ef8372df
|
# READ STATUS: Burst-No: 0 Addr: 00001800 Rxd: ef8372df
|
# tb_core.u_sdram32 : at time 33173.0 ns READ : Bank = 2 Row = 1, Col = 2, Data = 33836567
|
# tb_core.u_sdram32 : at time 34013.0 ns READ : Bank = 2 Row = 1, Col = 2, Data = 33836567
|
# READ STATUS: Burst-No: 1 Addr: 00001802 Rxd: ea5814d4
|
# READ STATUS: Burst-No: 1 Addr: 00001802 Rxd: ea5814d4
|
# tb_core.u_sdram32 : at time 33183.0 ns READ : Bank = 2 Row = 1, Col = 3, Data = 4ea0419d
|
# tb_core.u_sdram32 : at time 34023.0 ns READ : Bank = 2 Row = 1, Col = 3, Data = 4ea0419d
|
# tb_core.u_sdram32 : at time 33187.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 34027.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 2 Addr: 00001804 Rxd: 33836567
|
# READ STATUS: Burst-No: 2 Addr: 00001804 Rxd: 33836567
|
# tb_core.u_sdram32 : at time 33193.0 ns READ : Bank = 2 Row = 1, Col = 4, Data = 583125b0
|
# tb_core.u_sdram32 : at time 34033.0 ns READ : Bank = 2 Row = 1, Col = 4, Data = 583125b0
|
# READ STATUS: Burst-No: 3 Addr: 00001806 Rxd: 4ea0419d
|
# READ STATUS: Burst-No: 3 Addr: 00001806 Rxd: 4ea0419d
|
# tb_core.u_sdram32 : at time 33203.0 ns READ : Bank = 2 Row = 1, Col = 5, Data = 41103982
|
# tb_core.u_sdram32 : at time 34043.0 ns READ : Bank = 2 Row = 1, Col = 5, Data = 41103982
|
# READ STATUS: Burst-No: 4 Addr: 00001808 Rxd: 583125b0
|
# READ STATUS: Burst-No: 4 Addr: 00001808 Rxd: 583125b0
|
# READ STATUS: Burst-No: 5 Addr: 0000180a Rxd: 41103982
|
# READ STATUS: Burst-No: 5 Addr: 0000180a Rxd: 41103982
|
# tb_core.u_sdram32 : at time 33297.0 ns ACT : Bank = 3 Row = 1
|
# tb_core.u_sdram32 : at time 34147.0 ns ACT : Bank = 3 Row = 1
|
# tb_core.u_sdram32 : at time 33363.0 ns READ : Bank = 3 Row = 1, Col = 0, Data = 24d2bf49
|
# tb_core.u_sdram32 : at time 34213.0 ns READ : Bank = 3 Row = 1, Col = 0, Data = 24d2bf49
|
# tb_core.u_sdram32 : at time 33373.0 ns READ : Bank = 3 Row = 1, Col = 1, Data = ecb91ad9
|
# tb_core.u_sdram32 : at time 34223.0 ns READ : Bank = 3 Row = 1, Col = 1, Data = ecb91ad9
|
# READ STATUS: Burst-No: 0 Addr: 00001c00 Rxd: 24d2bf49
|
# READ STATUS: Burst-No: 0 Addr: 00001c00 Rxd: 24d2bf49
|
# tb_core.u_sdram32 : at time 33383.0 ns READ : Bank = 3 Row = 1, Col = 2, Data = 1000b720
|
# tb_core.u_sdram32 : at time 34233.0 ns READ : Bank = 3 Row = 1, Col = 2, Data = 1000b720
|
# READ STATUS: Burst-No: 1 Addr: 00001c02 Rxd: ecb91ad9
|
# READ STATUS: Burst-No: 1 Addr: 00001c02 Rxd: ecb91ad9
|
# tb_core.u_sdram32 : at time 33393.0 ns READ : Bank = 3 Row = 1, Col = 3, Data = 8e054c1c
|
# tb_core.u_sdram32 : at time 34243.0 ns READ : Bank = 3 Row = 1, Col = 3, Data = 8e054c1c
|
# READ STATUS: Burst-No: 2 Addr: 00001c04 Rxd: 1000b720
|
# READ STATUS: Burst-No: 2 Addr: 00001c04 Rxd: 1000b720
|
# tb_core.u_sdram32 : at time 33403.0 ns READ : Bank = 3 Row = 1, Col = 4, Data = 49b16f93
|
# tb_core.u_sdram32 : at time 34253.0 ns READ : Bank = 3 Row = 1, Col = 4, Data = 49b16f93
|
# tb_core.u_sdram32 : at time 33407.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 34257.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 3 Addr: 00001c06 Rxd: 8e054c1c
|
# READ STATUS: Burst-No: 3 Addr: 00001c06 Rxd: 8e054c1c
|
# tb_core.u_sdram32 : at time 33413.0 ns READ : Bank = 3 Row = 1, Col = 5, Data = 71b461e3
|
# tb_core.u_sdram32 : at time 34263.0 ns READ : Bank = 3 Row = 1, Col = 5, Data = 71b461e3
|
# READ STATUS: Burst-No: 4 Addr: 00001c08 Rxd: 49b16f93
|
# READ STATUS: Burst-No: 4 Addr: 00001c08 Rxd: 49b16f93
|
# tb_core.u_sdram32 : at time 33423.0 ns READ : Bank = 3 Row = 1, Col = 6, Data = 954b822a
|
# tb_core.u_sdram32 : at time 34273.0 ns READ : Bank = 3 Row = 1, Col = 6, Data = 954b822a
|
# READ STATUS: Burst-No: 5 Addr: 00001c0a Rxd: 71b461e3
|
# READ STATUS: Burst-No: 5 Addr: 00001c0a Rxd: 71b461e3
|
# READ STATUS: Burst-No: 6 Addr: 00001c0c Rxd: 954b822a
|
# READ STATUS: Burst-No: 6 Addr: 00001c0c Rxd: 954b822a
|
# Write Address: 00002000, Burst Size: 4
|
# Write Address: 00002000, Burst Size: 4
|
# tb_core.u_sdram32 : at time 33527.0 ns ACT : Bank = 0 Row = 2
|
# tb_core.u_sdram32 : at time 34377.0 ns ACT : Bank = 0 Row = 2
|
# tb_core.u_sdram32 : at time 33567.0 ns WRITE: Bank = 0 Row = 2, Col = 0, Data = e471f8c8
|
# tb_core.u_sdram32 : at time 34417.0 ns WRITE: Bank = 0 Row = 2, Col = 0, Data = e471f8c8
|
# Status: Burst-No: 0 Write Address: 00002000 WriteData: e471f8c8
|
# Status: Burst-No: 0 Write Address: 00002000 WriteData: e471f8c8
|
# tb_core.u_sdram32 : at time 33577.0 ns WRITE: Bank = 0 Row = 2, Col = 1, Data = aed72e5d
|
# tb_core.u_sdram32 : at time 34427.0 ns WRITE: Bank = 0 Row = 2, Col = 1, Data = aed72e5d
|
# Status: Burst-No: 1 Write Address: 00002000 WriteData: aed72e5d
|
# Status: Burst-No: 1 Write Address: 00002000 WriteData: aed72e5d
|
# tb_core.u_sdram32 : at time 33587.0 ns WRITE: Bank = 0 Row = 2, Col = 2, Data = 1d3f9d3a
|
# tb_core.u_sdram32 : at time 34437.0 ns WRITE: Bank = 0 Row = 2, Col = 2, Data = 1d3f9d3a
|
# Status: Burst-No: 2 Write Address: 00002000 WriteData: 1d3f9d3a
|
# Status: Burst-No: 2 Write Address: 00002000 WriteData: 1d3f9d3a
|
# tb_core.u_sdram32 : at time 33597.0 ns WRITE: Bank = 0 Row = 2, Col = 3, Data = 4226a984
|
# tb_core.u_sdram32 : at time 34447.0 ns WRITE: Bank = 0 Row = 2, Col = 3, Data = 4226a984
|
# Status: Burst-No: 3 Write Address: 00002000 WriteData: 4226a984
|
# Status: Burst-No: 3 Write Address: 00002000 WriteData: 4226a984
|
# tb_core.u_sdram32 : at time 33607.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 34457.0 ns BST : Burst Terminate
|
# Write Address: 00002400, Burst Size: 5
|
# Write Address: 00002400, Burst Size: 5
|
# tb_core.u_sdram32 : at time 33677.0 ns ACT : Bank = 1 Row = 2
|
# tb_core.u_sdram32 : at time 34527.0 ns ACT : Bank = 1 Row = 2
|
# tb_core.u_sdram32 : at time 33717.0 ns WRITE: Bank = 1 Row = 2, Col = 0, Data = 95a9a82b
|
# tb_core.u_sdram32 : at time 34567.0 ns WRITE: Bank = 1 Row = 2, Col = 0, Data = 95a9a82b
|
# Status: Burst-No: 0 Write Address: 00002400 WriteData: 95a9a82b
|
# Status: Burst-No: 0 Write Address: 00002400 WriteData: 95a9a82b
|
# tb_core.u_sdram32 : at time 33727.0 ns WRITE: Bank = 1 Row = 2, Col = 1, Data = 1c8d7f39
|
# tb_core.u_sdram32 : at time 34577.0 ns WRITE: Bank = 1 Row = 2, Col = 1, Data = 1c8d7f39
|
# Status: Burst-No: 1 Write Address: 00002400 WriteData: 1c8d7f39
|
# Status: Burst-No: 1 Write Address: 00002400 WriteData: 1c8d7f39
|
# tb_core.u_sdram32 : at time 33737.0 ns WRITE: Bank = 1 Row = 2, Col = 2, Data = 897f1c12
|
# tb_core.u_sdram32 : at time 34587.0 ns WRITE: Bank = 1 Row = 2, Col = 2, Data = 897f1c12
|
# Status: Burst-No: 2 Write Address: 00002400 WriteData: 897f1c12
|
# Status: Burst-No: 2 Write Address: 00002400 WriteData: 897f1c12
|
# tb_core.u_sdram32 : at time 33747.0 ns WRITE: Bank = 1 Row = 2, Col = 3, Data = a97f0052
|
# tb_core.u_sdram32 : at time 34597.0 ns WRITE: Bank = 1 Row = 2, Col = 3, Data = a97f0052
|
# Status: Burst-No: 3 Write Address: 00002400 WriteData: a97f0052
|
# Status: Burst-No: 3 Write Address: 00002400 WriteData: a97f0052
|
# tb_core.u_sdram32 : at time 33757.0 ns WRITE: Bank = 1 Row = 2, Col = 4, Data = 2c848959
|
# tb_core.u_sdram32 : at time 34607.0 ns WRITE: Bank = 1 Row = 2, Col = 4, Data = 2c848959
|
# Status: Burst-No: 4 Write Address: 00002400 WriteData: 2c848959
|
# Status: Burst-No: 4 Write Address: 00002400 WriteData: 2c848959
|
# tb_core.u_sdram32 : at time 33767.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 34617.0 ns BST : Burst Terminate
|
# Write Address: 00002800, Burst Size: 6
|
# Write Address: 00002800, Burst Size: 6
|
# tb_core.u_sdram32 : at time 33837.0 ns ACT : Bank = 2 Row = 2
|
# tb_core.u_sdram32 : at time 34687.0 ns ACT : Bank = 2 Row = 2
|
# tb_core.u_sdram32 : at time 33877.0 ns WRITE: Bank = 2 Row = 2, Col = 0, Data = e82b96d0
|
# tb_core.u_sdram32 : at time 34727.0 ns WRITE: Bank = 2 Row = 2, Col = 0, Data = e82b96d0
|
# Status: Burst-No: 0 Write Address: 00002800 WriteData: e82b96d0
|
# Status: Burst-No: 0 Write Address: 00002800 WriteData: e82b96d0
|
# tb_core.u_sdram32 : at time 33887.0 ns WRITE: Bank = 2 Row = 2, Col = 1, Data = b759ea6e
|
# tb_core.u_sdram32 : at time 34737.0 ns WRITE: Bank = 2 Row = 2, Col = 1, Data = b759ea6e
|
# Status: Burst-No: 1 Write Address: 00002800 WriteData: b759ea6e
|
# Status: Burst-No: 1 Write Address: 00002800 WriteData: b759ea6e
|
# tb_core.u_sdram32 : at time 33897.0 ns WRITE: Bank = 2 Row = 2, Col = 2, Data = 4bf52997
|
# tb_core.u_sdram32 : at time 34747.0 ns WRITE: Bank = 2 Row = 2, Col = 2, Data = 4bf52997
|
# Status: Burst-No: 2 Write Address: 00002800 WriteData: 4bf52997
|
# Status: Burst-No: 2 Write Address: 00002800 WriteData: 4bf52997
|
# tb_core.u_sdram32 : at time 33907.0 ns WRITE: Bank = 2 Row = 2, Col = 3, Data = 6d8b87db
|
# tb_core.u_sdram32 : at time 34757.0 ns WRITE: Bank = 2 Row = 2, Col = 3, Data = 6d8b87db
|
# Status: Burst-No: 3 Write Address: 00002800 WriteData: 6d8b87db
|
# Status: Burst-No: 3 Write Address: 00002800 WriteData: 6d8b87db
|
# tb_core.u_sdram32 : at time 33917.0 ns WRITE: Bank = 2 Row = 2, Col = 4, Data = 535277a6
|
# tb_core.u_sdram32 : at time 34767.0 ns WRITE: Bank = 2 Row = 2, Col = 4, Data = 535277a6
|
# Status: Burst-No: 4 Write Address: 00002800 WriteData: 535277a6
|
# Status: Burst-No: 4 Write Address: 00002800 WriteData: 535277a6
|
# tb_core.u_sdram32 : at time 33927.0 ns WRITE: Bank = 2 Row = 2, Col = 5, Data = 5d85d3bb
|
# tb_core.u_sdram32 : at time 34777.0 ns WRITE: Bank = 2 Row = 2, Col = 5, Data = 5d85d3bb
|
# Status: Burst-No: 5 Write Address: 00002800 WriteData: 5d85d3bb
|
# Status: Burst-No: 5 Write Address: 00002800 WriteData: 5d85d3bb
|
# tb_core.u_sdram32 : at time 33937.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 34787.0 ns BST : Burst Terminate
|
# Write Address: 00002c00, Burst Size: 7
|
# Write Address: 00002c00, Burst Size: 7
|
# tb_core.u_sdram32 : at time 34007.0 ns ACT : Bank = 3 Row = 2
|
# tb_core.u_sdram32 : at time 34857.0 ns ACT : Bank = 3 Row = 2
|
# tb_core.u_sdram32 : at time 34047.0 ns WRITE: Bank = 3 Row = 2, Col = 0, Data = 80797c00
|
# tb_core.u_sdram32 : at time 34897.0 ns WRITE: Bank = 3 Row = 2, Col = 0, Data = 80797c00
|
# Status: Burst-No: 0 Write Address: 00002c00 WriteData: 80797c00
|
# Status: Burst-No: 0 Write Address: 00002c00 WriteData: 80797c00
|
# tb_core.u_sdram32 : at time 34057.0 ns WRITE: Bank = 3 Row = 2, Col = 1, Data = 87e44c0f
|
# tb_core.u_sdram32 : at time 34907.0 ns WRITE: Bank = 3 Row = 2, Col = 1, Data = 87e44c0f
|
# Status: Burst-No: 1 Write Address: 00002c00 WriteData: 87e44c0f
|
# Status: Burst-No: 1 Write Address: 00002c00 WriteData: 87e44c0f
|
# tb_core.u_sdram32 : at time 34067.0 ns WRITE: Bank = 3 Row = 2, Col = 2, Data = b4e8d669
|
# tb_core.u_sdram32 : at time 34917.0 ns WRITE: Bank = 3 Row = 2, Col = 2, Data = b4e8d669
|
# Status: Burst-No: 2 Write Address: 00002c00 WriteData: b4e8d669
|
# Status: Burst-No: 2 Write Address: 00002c00 WriteData: b4e8d669
|
# tb_core.u_sdram32 : at time 34077.0 ns WRITE: Bank = 3 Row = 2, Col = 3, Data = 8653620c
|
# tb_core.u_sdram32 : at time 34927.0 ns WRITE: Bank = 3 Row = 2, Col = 3, Data = 8653620c
|
# Status: Burst-No: 3 Write Address: 00002c00 WriteData: 8653620c
|
# Status: Burst-No: 3 Write Address: 00002c00 WriteData: 8653620c
|
# tb_core.u_sdram32 : at time 34087.0 ns WRITE: Bank = 3 Row = 2, Col = 4, Data = 2ca81959
|
# tb_core.u_sdram32 : at time 34937.0 ns WRITE: Bank = 3 Row = 2, Col = 4, Data = 2ca81959
|
# Status: Burst-No: 4 Write Address: 00002c00 WriteData: 2ca81959
|
# Status: Burst-No: 4 Write Address: 00002c00 WriteData: 2ca81959
|
# tb_core.u_sdram32 : at time 34097.0 ns WRITE: Bank = 3 Row = 2, Col = 5, Data = 62fd49c5
|
# tb_core.u_sdram32 : at time 34947.0 ns WRITE: Bank = 3 Row = 2, Col = 5, Data = 62fd49c5
|
# Status: Burst-No: 5 Write Address: 00002c00 WriteData: 62fd49c5
|
# Status: Burst-No: 5 Write Address: 00002c00 WriteData: 62fd49c5
|
# tb_core.u_sdram32 : at time 34107.0 ns WRITE: Bank = 3 Row = 2, Col = 6, Data = 67d735cf
|
# tb_core.u_sdram32 : at time 34957.0 ns WRITE: Bank = 3 Row = 2, Col = 6, Data = 67d735cf
|
# Status: Burst-No: 6 Write Address: 00002c00 WriteData: 67d735cf
|
# Status: Burst-No: 6 Write Address: 00002c00 WriteData: 67d735cf
|
# tb_core.u_sdram32 : at time 34117.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 34967.0 ns BST : Burst Terminate
|
# Write Address: 00003000, Burst Size: 4
|
# Write Address: 00003000, Burst Size: 4
|
# tb_core.u_sdram32 : at time 34187.0 ns ACT : Bank = 0 Row = 3
|
# tb_core.u_sdram32 : at time 35037.0 ns ACT : Bank = 0 Row = 3
|
# tb_core.u_sdram32 : at time 34227.0 ns WRITE: Bank = 0 Row = 3, Col = 0, Data = 4839e590
|
# tb_core.u_sdram32 : at time 35077.0 ns WRITE: Bank = 0 Row = 3, Col = 0, Data = 4839e590
|
# Status: Burst-No: 0 Write Address: 00003000 WriteData: 4839e590
|
# Status: Burst-No: 0 Write Address: 00003000 WriteData: 4839e590
|
# tb_core.u_sdram32 : at time 34237.0 ns WRITE: Bank = 0 Row = 3, Col = 1, Data = a8e4d851
|
# tb_core.u_sdram32 : at time 35087.0 ns WRITE: Bank = 0 Row = 3, Col = 1, Data = a8e4d851
|
# Status: Burst-No: 1 Write Address: 00003000 WriteData: a8e4d851
|
# Status: Burst-No: 1 Write Address: 00003000 WriteData: a8e4d851
|
# tb_core.u_sdram32 : at time 34247.0 ns WRITE: Bank = 0 Row = 3, Col = 2, Data = b4f9a469
|
# tb_core.u_sdram32 : at time 35097.0 ns WRITE: Bank = 0 Row = 3, Col = 2, Data = b4f9a469
|
# Status: Burst-No: 2 Write Address: 00003000 WriteData: b4f9a469
|
# Status: Burst-No: 2 Write Address: 00003000 WriteData: b4f9a469
|
# tb_core.u_sdram32 : at time 34257.0 ns WRITE: Bank = 0 Row = 3, Col = 3, Data = 3b83cd77
|
# tb_core.u_sdram32 : at time 35107.0 ns WRITE: Bank = 0 Row = 3, Col = 3, Data = 3b83cd77
|
# Status: Burst-No: 3 Write Address: 00003000 WriteData: 3b83cd77
|
# Status: Burst-No: 3 Write Address: 00003000 WriteData: 3b83cd77
|
# tb_core.u_sdram32 : at time 34267.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 35117.0 ns BST : Burst Terminate
|
# Write Address: 00003400, Burst Size: 5
|
# Write Address: 00003400, Burst Size: 5
|
# tb_core.u_sdram32 : at time 34337.0 ns ACT : Bank = 1 Row = 3
|
# tb_core.u_sdram32 : at time 35187.0 ns ACT : Bank = 1 Row = 3
|
# tb_core.u_sdram32 : at time 34377.0 ns WRITE: Bank = 1 Row = 3, Col = 0, Data = 2523654a
|
# tb_core.u_sdram32 : at time 35227.0 ns WRITE: Bank = 1 Row = 3, Col = 0, Data = 2523654a
|
# Status: Burst-No: 0 Write Address: 00003400 WriteData: 2523654a
|
# Status: Burst-No: 0 Write Address: 00003400 WriteData: 2523654a
|
# tb_core.u_sdram32 : at time 34387.0 ns WRITE: Bank = 1 Row = 3, Col = 1, Data = ec3758d8
|
# tb_core.u_sdram32 : at time 35237.0 ns WRITE: Bank = 1 Row = 3, Col = 1, Data = ec3758d8
|
# Status: Burst-No: 1 Write Address: 00003400 WriteData: ec3758d8
|
# Status: Burst-No: 1 Write Address: 00003400 WriteData: ec3758d8
|
# tb_core.u_sdram32 : at time 34397.0 ns WRITE: Bank = 1 Row = 3, Col = 2, Data = 4ddd4d9b
|
# tb_core.u_sdram32 : at time 35247.0 ns WRITE: Bank = 1 Row = 3, Col = 2, Data = 4ddd4d9b
|
# Status: Burst-No: 2 Write Address: 00003400 WriteData: 4ddd4d9b
|
# Status: Burst-No: 2 Write Address: 00003400 WriteData: 4ddd4d9b
|
# tb_core.u_sdram32 : at time 34407.0 ns WRITE: Bank = 1 Row = 3, Col = 3, Data = e20e9ac4
|
# tb_core.u_sdram32 : at time 35257.0 ns WRITE: Bank = 1 Row = 3, Col = 3, Data = e20e9ac4
|
# Status: Burst-No: 3 Write Address: 00003400 WriteData: e20e9ac4
|
# Status: Burst-No: 3 Write Address: 00003400 WriteData: e20e9ac4
|
# tb_core.u_sdram32 : at time 34417.0 ns WRITE: Bank = 1 Row = 3, Col = 4, Data = 5c78b1b8
|
# tb_core.u_sdram32 : at time 35267.0 ns WRITE: Bank = 1 Row = 3, Col = 4, Data = 5c78b1b8
|
# Status: Burst-No: 4 Write Address: 00003400 WriteData: 5c78b1b8
|
# Status: Burst-No: 4 Write Address: 00003400 WriteData: 5c78b1b8
|
# tb_core.u_sdram32 : at time 34427.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 35277.0 ns BST : Burst Terminate
|
# Write Address: 00003800, Burst Size: 6
|
# Write Address: 00003800, Burst Size: 6
|
# tb_core.u_sdram32 : at time 34497.0 ns ACT : Bank = 2 Row = 3
|
# tb_core.u_sdram32 : at time 35347.0 ns ACT : Bank = 2 Row = 3
|
# tb_core.u_sdram32 : at time 34537.0 ns WRITE: Bank = 2 Row = 3, Col = 0, Data = dbe6f2b7
|
# tb_core.u_sdram32 : at time 35387.0 ns WRITE: Bank = 2 Row = 3, Col = 0, Data = dbe6f2b7
|
# Status: Burst-No: 0 Write Address: 00003800 WriteData: dbe6f2b7
|
# Status: Burst-No: 0 Write Address: 00003800 WriteData: dbe6f2b7
|
# tb_core.u_sdram32 : at time 34547.0 ns WRITE: Bank = 2 Row = 3, Col = 1, Data = c378ee86
|
# tb_core.u_sdram32 : at time 35397.0 ns WRITE: Bank = 2 Row = 3, Col = 1, Data = c378ee86
|
# Status: Burst-No: 1 Write Address: 00003800 WriteData: c378ee86
|
# Status: Burst-No: 1 Write Address: 00003800 WriteData: c378ee86
|
# tb_core.u_sdram32 : at time 34557.0 ns WRITE: Bank = 2 Row = 3, Col = 2, Data = 984d5a30
|
# tb_core.u_sdram32 : at time 35407.0 ns WRITE: Bank = 2 Row = 3, Col = 2, Data = 984d5a30
|
# Status: Burst-No: 2 Write Address: 00003800 WriteData: 984d5a30
|
# Status: Burst-No: 2 Write Address: 00003800 WriteData: 984d5a30
|
# tb_core.u_sdram32 : at time 34567.0 ns WRITE: Bank = 2 Row = 3, Col = 3, Data = 3bed5377
|
# tb_core.u_sdram32 : at time 35417.0 ns WRITE: Bank = 2 Row = 3, Col = 3, Data = 3bed5377
|
# Status: Burst-No: 3 Write Address: 00003800 WriteData: 3bed5377
|
# Status: Burst-No: 3 Write Address: 00003800 WriteData: 3bed5377
|
# tb_core.u_sdram32 : at time 34577.0 ns WRITE: Bank = 2 Row = 3, Col = 4, Data = 5ad6c7b5
|
# tb_core.u_sdram32 : at time 35427.0 ns WRITE: Bank = 2 Row = 3, Col = 4, Data = 5ad6c7b5
|
# Status: Burst-No: 4 Write Address: 00003800 WriteData: 5ad6c7b5
|
# Status: Burst-No: 4 Write Address: 00003800 WriteData: 5ad6c7b5
|
# tb_core.u_sdram32 : at time 34587.0 ns WRITE: Bank = 2 Row = 3, Col = 5, Data = 6a15f5d4
|
# tb_core.u_sdram32 : at time 35437.0 ns WRITE: Bank = 2 Row = 3, Col = 5, Data = 6a15f5d4
|
# Status: Burst-No: 5 Write Address: 00003800 WriteData: 6a15f5d4
|
# Status: Burst-No: 5 Write Address: 00003800 WriteData: 6a15f5d4
|
# tb_core.u_sdram32 : at time 34597.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 35447.0 ns BST : Burst Terminate
|
# Write Address: 00003c00, Burst Size: 7
|
# Write Address: 00003c00, Burst Size: 7
|
# tb_core.u_sdram32 : at time 34667.0 ns ACT : Bank = 3 Row = 3
|
# tb_core.u_sdram32 : at time 35517.0 ns ACT : Bank = 3 Row = 3
|
# tb_core.u_sdram32 : at time 34707.0 ns WRITE: Bank = 3 Row = 3, Col = 0, Data = 03878707
|
# tb_core.u_sdram32 : at time 35557.0 ns WRITE: Bank = 3 Row = 3, Col = 0, Data = 03878707
|
# Status: Burst-No: 0 Write Address: 00003c00 WriteData: 03878707
|
# Status: Burst-No: 0 Write Address: 00003c00 WriteData: 03878707
|
# tb_core.u_sdram32 : at time 34717.0 ns WRITE: Bank = 3 Row = 3, Col = 1, Data = 3b0b9776
|
# tb_core.u_sdram32 : at time 35567.0 ns WRITE: Bank = 3 Row = 3, Col = 1, Data = 3b0b9776
|
# Status: Burst-No: 1 Write Address: 00003c00 WriteData: 3b0b9776
|
# Status: Burst-No: 1 Write Address: 00003c00 WriteData: 3b0b9776
|
# tb_core.u_sdram32 : at time 34727.0 ns WRITE: Bank = 3 Row = 3, Col = 2, Data = 74a1ade9
|
# tb_core.u_sdram32 : at time 35577.0 ns WRITE: Bank = 3 Row = 3, Col = 2, Data = 74a1ade9
|
# Status: Burst-No: 2 Write Address: 00003c00 WriteData: 74a1ade9
|
# Status: Burst-No: 2 Write Address: 00003c00 WriteData: 74a1ade9
|
# tb_core.u_sdram32 : at time 34737.0 ns WRITE: Bank = 3 Row = 3, Col = 3, Data = 45e28b8b
|
# tb_core.u_sdram32 : at time 35587.0 ns WRITE: Bank = 3 Row = 3, Col = 3, Data = 45e28b8b
|
# Status: Burst-No: 3 Write Address: 00003c00 WriteData: 45e28b8b
|
# Status: Burst-No: 3 Write Address: 00003c00 WriteData: 45e28b8b
|
# tb_core.u_sdram32 : at time 34747.0 ns WRITE: Bank = 3 Row = 3, Col = 4, Data = 00f25f01
|
# tb_core.u_sdram32 : at time 35597.0 ns WRITE: Bank = 3 Row = 3, Col = 4, Data = 00f25f01
|
# Status: Burst-No: 4 Write Address: 00003c00 WriteData: 00f25f01
|
# Status: Burst-No: 4 Write Address: 00003c00 WriteData: 00f25f01
|
# tb_core.u_sdram32 : at time 34757.0 ns WRITE: Bank = 3 Row = 3, Col = 5, Data = 6d808bdb
|
# tb_core.u_sdram32 : at time 35607.0 ns WRITE: Bank = 3 Row = 3, Col = 5, Data = 6d808bdb
|
# Status: Burst-No: 5 Write Address: 00003c00 WriteData: 6d808bdb
|
# Status: Burst-No: 5 Write Address: 00003c00 WriteData: 6d808bdb
|
# tb_core.u_sdram32 : at time 34767.0 ns WRITE: Bank = 3 Row = 3, Col = 6, Data = c0764280
|
# tb_core.u_sdram32 : at time 35617.0 ns WRITE: Bank = 3 Row = 3, Col = 6, Data = c0764280
|
# Status: Burst-No: 6 Write Address: 00003c00 WriteData: c0764280
|
# Status: Burst-No: 6 Write Address: 00003c00 WriteData: c0764280
|
# tb_core.u_sdram32 : at time 34777.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 35627.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 34837.0 ns ACT : Bank = 0 Row = 2
|
# tb_core.u_sdram32 : at time 35697.0 ns ACT : Bank = 0 Row = 2
|
# tb_core.u_sdram32 : at time 34903.0 ns READ : Bank = 0 Row = 2, Col = 0, Data = e471f8c8
|
# tb_core.u_sdram32 : at time 35763.0 ns READ : Bank = 0 Row = 2, Col = 0, Data = e471f8c8
|
# tb_core.u_sdram32 : at time 34913.0 ns READ : Bank = 0 Row = 2, Col = 1, Data = aed72e5d
|
# tb_core.u_sdram32 : at time 35773.0 ns READ : Bank = 0 Row = 2, Col = 1, Data = aed72e5d
|
# READ STATUS: Burst-No: 0 Addr: 00002000 Rxd: e471f8c8
|
# READ STATUS: Burst-No: 0 Addr: 00002000 Rxd: e471f8c8
|
# tb_core.u_sdram32 : at time 34917.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 35777.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 34923.0 ns READ : Bank = 0 Row = 2, Col = 2, Data = 1d3f9d3a
|
# tb_core.u_sdram32 : at time 35783.0 ns READ : Bank = 0 Row = 2, Col = 2, Data = 1d3f9d3a
|
# READ STATUS: Burst-No: 1 Addr: 00002002 Rxd: aed72e5d
|
# READ STATUS: Burst-No: 1 Addr: 00002002 Rxd: aed72e5d
|
# tb_core.u_sdram32 : at time 34933.0 ns READ : Bank = 0 Row = 2, Col = 3, Data = 4226a984
|
# tb_core.u_sdram32 : at time 35793.0 ns READ : Bank = 0 Row = 2, Col = 3, Data = 4226a984
|
# READ STATUS: Burst-No: 2 Addr: 00002004 Rxd: 1d3f9d3a
|
# READ STATUS: Burst-No: 2 Addr: 00002004 Rxd: 1d3f9d3a
|
# READ STATUS: Burst-No: 3 Addr: 00002006 Rxd: 4226a984
|
# READ STATUS: Burst-No: 3 Addr: 00002006 Rxd: 4226a984
|
# tb_core.u_sdram32 : at time 35027.0 ns ACT : Bank = 1 Row = 2
|
# tb_core.u_sdram32 : at time 35897.0 ns ACT : Bank = 1 Row = 2
|
# tb_core.u_sdram32 : at time 35093.0 ns READ : Bank = 1 Row = 2, Col = 0, Data = 95a9a82b
|
# tb_core.u_sdram32 : at time 35963.0 ns READ : Bank = 1 Row = 2, Col = 0, Data = 95a9a82b
|
# tb_core.u_sdram32 : at time 35103.0 ns READ : Bank = 1 Row = 2, Col = 1, Data = 1c8d7f39
|
# tb_core.u_sdram32 : at time 35973.0 ns READ : Bank = 1 Row = 2, Col = 1, Data = 1c8d7f39
|
# READ STATUS: Burst-No: 0 Addr: 00002400 Rxd: 95a9a82b
|
# READ STATUS: Burst-No: 0 Addr: 00002400 Rxd: 95a9a82b
|
# tb_core.u_sdram32 : at time 35113.0 ns READ : Bank = 1 Row = 2, Col = 2, Data = 897f1c12
|
# tb_core.u_sdram32 : at time 35983.0 ns READ : Bank = 1 Row = 2, Col = 2, Data = 897f1c12
|
# tb_core.u_sdram32 : at time 35117.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 35987.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 1 Addr: 00002402 Rxd: 1c8d7f39
|
# READ STATUS: Burst-No: 1 Addr: 00002402 Rxd: 1c8d7f39
|
# tb_core.u_sdram32 : at time 35123.0 ns READ : Bank = 1 Row = 2, Col = 3, Data = a97f0052
|
# tb_core.u_sdram32 : at time 35993.0 ns READ : Bank = 1 Row = 2, Col = 3, Data = a97f0052
|
# READ STATUS: Burst-No: 2 Addr: 00002404 Rxd: 897f1c12
|
# READ STATUS: Burst-No: 2 Addr: 00002404 Rxd: 897f1c12
|
# tb_core.u_sdram32 : at time 35133.0 ns READ : Bank = 1 Row = 2, Col = 4, Data = 2c848959
|
# tb_core.u_sdram32 : at time 36003.0 ns READ : Bank = 1 Row = 2, Col = 4, Data = 2c848959
|
# READ STATUS: Burst-No: 3 Addr: 00002406 Rxd: a97f0052
|
# READ STATUS: Burst-No: 3 Addr: 00002406 Rxd: a97f0052
|
# READ STATUS: Burst-No: 4 Addr: 00002408 Rxd: 2c848959
|
# READ STATUS: Burst-No: 4 Addr: 00002408 Rxd: 2c848959
|
# tb_core.u_sdram32 : at time 35227.0 ns ACT : Bank = 2 Row = 2
|
# tb_core.u_sdram32 : at time 36107.0 ns ACT : Bank = 2 Row = 2
|
# tb_core.u_sdram32 : at time 35293.0 ns READ : Bank = 2 Row = 2, Col = 0, Data = e82b96d0
|
# tb_core.u_sdram32 : at time 36173.0 ns READ : Bank = 2 Row = 2, Col = 0, Data = e82b96d0
|
# tb_core.u_sdram32 : at time 35303.0 ns READ : Bank = 2 Row = 2, Col = 1, Data = b759ea6e
|
# tb_core.u_sdram32 : at time 36183.0 ns READ : Bank = 2 Row = 2, Col = 1, Data = b759ea6e
|
# READ STATUS: Burst-No: 0 Addr: 00002800 Rxd: e82b96d0
|
# READ STATUS: Burst-No: 0 Addr: 00002800 Rxd: e82b96d0
|
# tb_core.u_sdram32 : at time 35313.0 ns READ : Bank = 2 Row = 2, Col = 2, Data = 4bf52997
|
# tb_core.u_sdram32 : at time 36193.0 ns READ : Bank = 2 Row = 2, Col = 2, Data = 4bf52997
|
# READ STATUS: Burst-No: 1 Addr: 00002802 Rxd: b759ea6e
|
# READ STATUS: Burst-No: 1 Addr: 00002802 Rxd: b759ea6e
|
# tb_core.u_sdram32 : at time 35323.0 ns READ : Bank = 2 Row = 2, Col = 3, Data = 6d8b87db
|
# tb_core.u_sdram32 : at time 36203.0 ns READ : Bank = 2 Row = 2, Col = 3, Data = 6d8b87db
|
# tb_core.u_sdram32 : at time 35327.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 36207.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 2 Addr: 00002804 Rxd: 4bf52997
|
# READ STATUS: Burst-No: 2 Addr: 00002804 Rxd: 4bf52997
|
# tb_core.u_sdram32 : at time 35333.0 ns READ : Bank = 2 Row = 2, Col = 4, Data = 535277a6
|
# tb_core.u_sdram32 : at time 36213.0 ns READ : Bank = 2 Row = 2, Col = 4, Data = 535277a6
|
# READ STATUS: Burst-No: 3 Addr: 00002806 Rxd: 6d8b87db
|
# READ STATUS: Burst-No: 3 Addr: 00002806 Rxd: 6d8b87db
|
# tb_core.u_sdram32 : at time 35343.0 ns READ : Bank = 2 Row = 2, Col = 5, Data = 5d85d3bb
|
# tb_core.u_sdram32 : at time 36223.0 ns READ : Bank = 2 Row = 2, Col = 5, Data = 5d85d3bb
|
# READ STATUS: Burst-No: 4 Addr: 00002808 Rxd: 535277a6
|
# READ STATUS: Burst-No: 4 Addr: 00002808 Rxd: 535277a6
|
# READ STATUS: Burst-No: 5 Addr: 0000280a Rxd: 5d85d3bb
|
# READ STATUS: Burst-No: 5 Addr: 0000280a Rxd: 5d85d3bb
|
# tb_core.u_sdram32 : at time 35437.0 ns ACT : Bank = 3 Row = 2
|
# tb_core.u_sdram32 : at time 36327.0 ns ACT : Bank = 3 Row = 2
|
# tb_core.u_sdram32 : at time 35503.0 ns READ : Bank = 3 Row = 2, Col = 0, Data = 80797c00
|
# tb_core.u_sdram32 : at time 36393.0 ns READ : Bank = 3 Row = 2, Col = 0, Data = 80797c00
|
# tb_core.u_sdram32 : at time 35513.0 ns READ : Bank = 3 Row = 2, Col = 1, Data = 87e44c0f
|
# tb_core.u_sdram32 : at time 36403.0 ns READ : Bank = 3 Row = 2, Col = 1, Data = 87e44c0f
|
# READ STATUS: Burst-No: 0 Addr: 00002c00 Rxd: 80797c00
|
# READ STATUS: Burst-No: 0 Addr: 00002c00 Rxd: 80797c00
|
# tb_core.u_sdram32 : at time 35523.0 ns READ : Bank = 3 Row = 2, Col = 2, Data = b4e8d669
|
# tb_core.u_sdram32 : at time 36413.0 ns READ : Bank = 3 Row = 2, Col = 2, Data = b4e8d669
|
# READ STATUS: Burst-No: 1 Addr: 00002c02 Rxd: 87e44c0f
|
# READ STATUS: Burst-No: 1 Addr: 00002c02 Rxd: 87e44c0f
|
# tb_core.u_sdram32 : at time 35533.0 ns READ : Bank = 3 Row = 2, Col = 3, Data = 8653620c
|
# tb_core.u_sdram32 : at time 36423.0 ns READ : Bank = 3 Row = 2, Col = 3, Data = 8653620c
|
# READ STATUS: Burst-No: 2 Addr: 00002c04 Rxd: b4e8d669
|
# READ STATUS: Burst-No: 2 Addr: 00002c04 Rxd: b4e8d669
|
# tb_core.u_sdram32 : at time 35543.0 ns READ : Bank = 3 Row = 2, Col = 4, Data = 2ca81959
|
# tb_core.u_sdram32 : at time 36433.0 ns READ : Bank = 3 Row = 2, Col = 4, Data = 2ca81959
|
# tb_core.u_sdram32 : at time 35547.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 36437.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 3 Addr: 00002c06 Rxd: 8653620c
|
# READ STATUS: Burst-No: 3 Addr: 00002c06 Rxd: 8653620c
|
# tb_core.u_sdram32 : at time 35553.0 ns READ : Bank = 3 Row = 2, Col = 5, Data = 62fd49c5
|
# tb_core.u_sdram32 : at time 36443.0 ns READ : Bank = 3 Row = 2, Col = 5, Data = 62fd49c5
|
# READ STATUS: Burst-No: 4 Addr: 00002c08 Rxd: 2ca81959
|
# READ STATUS: Burst-No: 4 Addr: 00002c08 Rxd: 2ca81959
|
# tb_core.u_sdram32 : at time 35563.0 ns READ : Bank = 3 Row = 2, Col = 6, Data = 67d735cf
|
# tb_core.u_sdram32 : at time 36453.0 ns READ : Bank = 3 Row = 2, Col = 6, Data = 67d735cf
|
# READ STATUS: Burst-No: 5 Addr: 00002c0a Rxd: 62fd49c5
|
# READ STATUS: Burst-No: 5 Addr: 00002c0a Rxd: 62fd49c5
|
# READ STATUS: Burst-No: 6 Addr: 00002c0c Rxd: 67d735cf
|
# READ STATUS: Burst-No: 6 Addr: 00002c0c Rxd: 67d735cf
|
# tb_core.u_sdram32 : at time 35657.0 ns ACT : Bank = 0 Row = 3
|
# tb_core.u_sdram32 : at time 36557.0 ns ACT : Bank = 0 Row = 3
|
# tb_core.u_sdram32 : at time 35723.0 ns READ : Bank = 0 Row = 3, Col = 0, Data = 4839e590
|
# tb_core.u_sdram32 : at time 36623.0 ns READ : Bank = 0 Row = 3, Col = 0, Data = 4839e590
|
# tb_core.u_sdram32 : at time 35733.0 ns READ : Bank = 0 Row = 3, Col = 1, Data = a8e4d851
|
# tb_core.u_sdram32 : at time 36633.0 ns READ : Bank = 0 Row = 3, Col = 1, Data = a8e4d851
|
# READ STATUS: Burst-No: 0 Addr: 00003000 Rxd: 4839e590
|
# READ STATUS: Burst-No: 0 Addr: 00003000 Rxd: 4839e590
|
# tb_core.u_sdram32 : at time 35737.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 36637.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 35743.0 ns READ : Bank = 0 Row = 3, Col = 2, Data = b4f9a469
|
# tb_core.u_sdram32 : at time 36643.0 ns READ : Bank = 0 Row = 3, Col = 2, Data = b4f9a469
|
# READ STATUS: Burst-No: 1 Addr: 00003002 Rxd: a8e4d851
|
# READ STATUS: Burst-No: 1 Addr: 00003002 Rxd: a8e4d851
|
# tb_core.u_sdram32 : at time 35753.0 ns READ : Bank = 0 Row = 3, Col = 3, Data = 3b83cd77
|
# tb_core.u_sdram32 : at time 36653.0 ns READ : Bank = 0 Row = 3, Col = 3, Data = 3b83cd77
|
# READ STATUS: Burst-No: 2 Addr: 00003004 Rxd: b4f9a469
|
# READ STATUS: Burst-No: 2 Addr: 00003004 Rxd: b4f9a469
|
# READ STATUS: Burst-No: 3 Addr: 00003006 Rxd: 3b83cd77
|
# READ STATUS: Burst-No: 3 Addr: 00003006 Rxd: 3b83cd77
|
# tb_core.u_sdram32 : at time 35847.0 ns ACT : Bank = 1 Row = 3
|
# tb_core.u_sdram32 : at time 36757.0 ns ACT : Bank = 1 Row = 3
|
# tb_core.u_sdram32 : at time 35913.0 ns READ : Bank = 1 Row = 3, Col = 0, Data = 2523654a
|
# tb_core.u_sdram32 : at time 36823.0 ns READ : Bank = 1 Row = 3, Col = 0, Data = 2523654a
|
# tb_core.u_sdram32 : at time 35923.0 ns READ : Bank = 1 Row = 3, Col = 1, Data = ec3758d8
|
# tb_core.u_sdram32 : at time 36833.0 ns READ : Bank = 1 Row = 3, Col = 1, Data = ec3758d8
|
# READ STATUS: Burst-No: 0 Addr: 00003400 Rxd: 2523654a
|
# READ STATUS: Burst-No: 0 Addr: 00003400 Rxd: 2523654a
|
# tb_core.u_sdram32 : at time 35933.0 ns READ : Bank = 1 Row = 3, Col = 2, Data = 4ddd4d9b
|
# tb_core.u_sdram32 : at time 36843.0 ns READ : Bank = 1 Row = 3, Col = 2, Data = 4ddd4d9b
|
# tb_core.u_sdram32 : at time 35937.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 36847.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 1 Addr: 00003402 Rxd: ec3758d8
|
# READ STATUS: Burst-No: 1 Addr: 00003402 Rxd: ec3758d8
|
# tb_core.u_sdram32 : at time 35943.0 ns READ : Bank = 1 Row = 3, Col = 3, Data = e20e9ac4
|
# tb_core.u_sdram32 : at time 36853.0 ns READ : Bank = 1 Row = 3, Col = 3, Data = e20e9ac4
|
# READ STATUS: Burst-No: 2 Addr: 00003404 Rxd: 4ddd4d9b
|
# READ STATUS: Burst-No: 2 Addr: 00003404 Rxd: 4ddd4d9b
|
# tb_core.u_sdram32 : at time 35953.0 ns READ : Bank = 1 Row = 3, Col = 4, Data = 5c78b1b8
|
# tb_core.u_sdram32 : at time 36863.0 ns READ : Bank = 1 Row = 3, Col = 4, Data = 5c78b1b8
|
# READ STATUS: Burst-No: 3 Addr: 00003406 Rxd: e20e9ac4
|
# READ STATUS: Burst-No: 3 Addr: 00003406 Rxd: e20e9ac4
|
# READ STATUS: Burst-No: 4 Addr: 00003408 Rxd: 5c78b1b8
|
# READ STATUS: Burst-No: 4 Addr: 00003408 Rxd: 5c78b1b8
|
# tb_core.u_sdram32 : at time 36047.0 ns ACT : Bank = 2 Row = 3
|
# tb_core.u_sdram32 : at time 36967.0 ns ACT : Bank = 2 Row = 3
|
# tb_core.u_sdram32 : at time 36113.0 ns READ : Bank = 2 Row = 3, Col = 0, Data = dbe6f2b7
|
# tb_core.u_sdram32 : at time 37033.0 ns READ : Bank = 2 Row = 3, Col = 0, Data = dbe6f2b7
|
# tb_core.u_sdram32 : at time 36123.0 ns READ : Bank = 2 Row = 3, Col = 1, Data = c378ee86
|
# tb_core.u_sdram32 : at time 37043.0 ns READ : Bank = 2 Row = 3, Col = 1, Data = c378ee86
|
# READ STATUS: Burst-No: 0 Addr: 00003800 Rxd: dbe6f2b7
|
# READ STATUS: Burst-No: 0 Addr: 00003800 Rxd: dbe6f2b7
|
# tb_core.u_sdram32 : at time 36133.0 ns READ : Bank = 2 Row = 3, Col = 2, Data = 984d5a30
|
# tb_core.u_sdram32 : at time 37053.0 ns READ : Bank = 2 Row = 3, Col = 2, Data = 984d5a30
|
# READ STATUS: Burst-No: 1 Addr: 00003802 Rxd: c378ee86
|
# READ STATUS: Burst-No: 1 Addr: 00003802 Rxd: c378ee86
|
# tb_core.u_sdram32 : at time 36143.0 ns READ : Bank = 2 Row = 3, Col = 3, Data = 3bed5377
|
# tb_core.u_sdram32 : at time 37063.0 ns READ : Bank = 2 Row = 3, Col = 3, Data = 3bed5377
|
# tb_core.u_sdram32 : at time 36147.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 37067.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 2 Addr: 00003804 Rxd: 984d5a30
|
# READ STATUS: Burst-No: 2 Addr: 00003804 Rxd: 984d5a30
|
# tb_core.u_sdram32 : at time 36153.0 ns READ : Bank = 2 Row = 3, Col = 4, Data = 5ad6c7b5
|
# tb_core.u_sdram32 : at time 37073.0 ns READ : Bank = 2 Row = 3, Col = 4, Data = 5ad6c7b5
|
# READ STATUS: Burst-No: 3 Addr: 00003806 Rxd: 3bed5377
|
# READ STATUS: Burst-No: 3 Addr: 00003806 Rxd: 3bed5377
|
# tb_core.u_sdram32 : at time 36163.0 ns READ : Bank = 2 Row = 3, Col = 5, Data = 6a15f5d4
|
# tb_core.u_sdram32 : at time 37083.0 ns READ : Bank = 2 Row = 3, Col = 5, Data = 6a15f5d4
|
# READ STATUS: Burst-No: 4 Addr: 00003808 Rxd: 5ad6c7b5
|
# READ STATUS: Burst-No: 4 Addr: 00003808 Rxd: 5ad6c7b5
|
# READ STATUS: Burst-No: 5 Addr: 0000380a Rxd: 6a15f5d4
|
# READ STATUS: Burst-No: 5 Addr: 0000380a Rxd: 6a15f5d4
|
# tb_core.u_sdram32 : at time 36257.0 ns ACT : Bank = 3 Row = 3
|
# tb_core.u_sdram32 : at time 37187.0 ns ACT : Bank = 3 Row = 3
|
# tb_core.u_sdram32 : at time 36323.0 ns READ : Bank = 3 Row = 3, Col = 0, Data = 03878707
|
# tb_core.u_sdram32 : at time 37253.0 ns READ : Bank = 3 Row = 3, Col = 0, Data = 03878707
|
# tb_core.u_sdram32 : at time 36333.0 ns READ : Bank = 3 Row = 3, Col = 1, Data = 3b0b9776
|
# tb_core.u_sdram32 : at time 37263.0 ns READ : Bank = 3 Row = 3, Col = 1, Data = 3b0b9776
|
# READ STATUS: Burst-No: 0 Addr: 00003c00 Rxd: 03878707
|
# READ STATUS: Burst-No: 0 Addr: 00003c00 Rxd: 03878707
|
# tb_core.u_sdram32 : at time 36343.0 ns READ : Bank = 3 Row = 3, Col = 2, Data = 74a1ade9
|
# tb_core.u_sdram32 : at time 37273.0 ns READ : Bank = 3 Row = 3, Col = 2, Data = 74a1ade9
|
# READ STATUS: Burst-No: 1 Addr: 00003c02 Rxd: 3b0b9776
|
# READ STATUS: Burst-No: 1 Addr: 00003c02 Rxd: 3b0b9776
|
# tb_core.u_sdram32 : at time 36353.0 ns READ : Bank = 3 Row = 3, Col = 3, Data = 45e28b8b
|
# tb_core.u_sdram32 : at time 37283.0 ns READ : Bank = 3 Row = 3, Col = 3, Data = 45e28b8b
|
# READ STATUS: Burst-No: 2 Addr: 00003c04 Rxd: 74a1ade9
|
# READ STATUS: Burst-No: 2 Addr: 00003c04 Rxd: 74a1ade9
|
# tb_core.u_sdram32 : at time 36363.0 ns READ : Bank = 3 Row = 3, Col = 4, Data = 00f25f01
|
# tb_core.u_sdram32 : at time 37293.0 ns READ : Bank = 3 Row = 3, Col = 4, Data = 00f25f01
|
# tb_core.u_sdram32 : at time 36367.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 37297.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 3 Addr: 00003c06 Rxd: 45e28b8b
|
# READ STATUS: Burst-No: 3 Addr: 00003c06 Rxd: 45e28b8b
|
# tb_core.u_sdram32 : at time 36373.0 ns READ : Bank = 3 Row = 3, Col = 5, Data = 6d808bdb
|
# tb_core.u_sdram32 : at time 37303.0 ns READ : Bank = 3 Row = 3, Col = 5, Data = 6d808bdb
|
# READ STATUS: Burst-No: 4 Addr: 00003c08 Rxd: 00f25f01
|
# READ STATUS: Burst-No: 4 Addr: 00003c08 Rxd: 00f25f01
|
# tb_core.u_sdram32 : at time 36383.0 ns READ : Bank = 3 Row = 3, Col = 6, Data = c0764280
|
# tb_core.u_sdram32 : at time 37313.0 ns READ : Bank = 3 Row = 3, Col = 6, Data = c0764280
|
# READ STATUS: Burst-No: 5 Addr: 00003c0a Rxd: 6d808bdb
|
# READ STATUS: Burst-No: 5 Addr: 00003c0a Rxd: 6d808bdb
|
# READ STATUS: Burst-No: 6 Addr: 00003c0c Rxd: c0764280
|
# READ STATUS: Burst-No: 6 Addr: 00003c0c Rxd: c0764280
|
# Write Address: 00002000, Burst Size: 4
|
# Write Address: 00002000, Burst Size: 4
|
# tb_core.u_sdram32 : at time 36487.0 ns ACT : Bank = 0 Row = 2
|
# tb_core.u_sdram32 : at time 37417.0 ns ACT : Bank = 0 Row = 2
|
# tb_core.u_sdram32 : at time 36527.0 ns WRITE: Bank = 0 Row = 2, Col = 0, Data = 611d9fc2
|
# tb_core.u_sdram32 : at time 37457.0 ns WRITE: Bank = 0 Row = 2, Col = 0, Data = 611d9fc2
|
# Status: Burst-No: 0 Write Address: 00002000 WriteData: 611d9fc2
|
# Status: Burst-No: 0 Write Address: 00002000 WriteData: 611d9fc2
|
# tb_core.u_sdram32 : at time 36537.0 ns WRITE: Bank = 0 Row = 2, Col = 1, Data = e2ecdac5
|
# tb_core.u_sdram32 : at time 37467.0 ns WRITE: Bank = 0 Row = 2, Col = 1, Data = e2ecdac5
|
# Status: Burst-No: 1 Write Address: 00002000 WriteData: e2ecdac5
|
# Status: Burst-No: 1 Write Address: 00002000 WriteData: e2ecdac5
|
# tb_core.u_sdram32 : at time 36547.0 ns WRITE: Bank = 0 Row = 2, Col = 2, Data = 9827fa30
|
# tb_core.u_sdram32 : at time 37477.0 ns WRITE: Bank = 0 Row = 2, Col = 2, Data = 9827fa30
|
# Status: Burst-No: 2 Write Address: 00002000 WriteData: 9827fa30
|
# Status: Burst-No: 2 Write Address: 00002000 WriteData: 9827fa30
|
# tb_core.u_sdram32 : at time 36557.0 ns WRITE: Bank = 0 Row = 2, Col = 3, Data = d7b2e4af
|
# tb_core.u_sdram32 : at time 37487.0 ns WRITE: Bank = 0 Row = 2, Col = 3, Data = d7b2e4af
|
# Status: Burst-No: 3 Write Address: 00002000 WriteData: d7b2e4af
|
# Status: Burst-No: 3 Write Address: 00002000 WriteData: d7b2e4af
|
# tb_core.u_sdram32 : at time 36567.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 37497.0 ns BST : Burst Terminate
|
# Write Address: 00002404, Burst Size: 5
|
# Write Address: 00002404, Burst Size: 5
|
# tb_core.u_sdram32 : at time 36637.0 ns ACT : Bank = 1 Row = 2
|
# tb_core.u_sdram32 : at time 37567.0 ns ACT : Bank = 1 Row = 2
|
# tb_core.u_sdram32 : at time 36677.0 ns WRITE: Bank = 1 Row = 2, Col = 1, Data = b302da66
|
# tb_core.u_sdram32 : at time 37607.0 ns WRITE: Bank = 1 Row = 2, Col = 1, Data = b302da66
|
# Status: Burst-No: 0 Write Address: 00002404 WriteData: b302da66
|
# Status: Burst-No: 0 Write Address: 00002404 WriteData: b302da66
|
# tb_core.u_sdram32 : at time 36687.0 ns WRITE: Bank = 1 Row = 2, Col = 2, Data = 57fbb9af
|
# tb_core.u_sdram32 : at time 37617.0 ns WRITE: Bank = 1 Row = 2, Col = 2, Data = 57fbb9af
|
# Status: Burst-No: 1 Write Address: 00002404 WriteData: 57fbb9af
|
# Status: Burst-No: 1 Write Address: 00002404 WriteData: 57fbb9af
|
# tb_core.u_sdram32 : at time 36697.0 ns WRITE: Bank = 1 Row = 2, Col = 3, Data = f4d86ee9
|
# tb_core.u_sdram32 : at time 37627.0 ns WRITE: Bank = 1 Row = 2, Col = 3, Data = f4d86ee9
|
# Status: Burst-No: 2 Write Address: 00002404 WriteData: f4d86ee9
|
# Status: Burst-No: 2 Write Address: 00002404 WriteData: f4d86ee9
|
# tb_core.u_sdram32 : at time 36707.0 ns WRITE: Bank = 1 Row = 2, Col = 4, Data = 7c41aff8
|
# tb_core.u_sdram32 : at time 37637.0 ns WRITE: Bank = 1 Row = 2, Col = 4, Data = 7c41aff8
|
# Status: Burst-No: 3 Write Address: 00002404 WriteData: 7c41aff8
|
# Status: Burst-No: 3 Write Address: 00002404 WriteData: 7c41aff8
|
# tb_core.u_sdram32 : at time 36717.0 ns WRITE: Bank = 1 Row = 2, Col = 5, Data = 8376ac06
|
# tb_core.u_sdram32 : at time 37647.0 ns WRITE: Bank = 1 Row = 2, Col = 5, Data = 8376ac06
|
# Status: Burst-No: 4 Write Address: 00002404 WriteData: 8376ac06
|
# Status: Burst-No: 4 Write Address: 00002404 WriteData: 8376ac06
|
# tb_core.u_sdram32 : at time 36727.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 37657.0 ns BST : Burst Terminate
|
# Write Address: 00002808, Burst Size: 6
|
# Write Address: 00002808, Burst Size: 6
|
# tb_core.u_sdram32 : at time 36797.0 ns ACT : Bank = 2 Row = 2
|
# tb_core.u_sdram32 : at time 37727.0 ns ACT : Bank = 2 Row = 2
|
# tb_core.u_sdram32 : at time 36837.0 ns WRITE: Bank = 2 Row = 2, Col = 2, Data = f78576ef
|
# tb_core.u_sdram32 : at time 37767.0 ns WRITE: Bank = 2 Row = 2, Col = 2, Data = f78576ef
|
# Status: Burst-No: 0 Write Address: 00002808 WriteData: f78576ef
|
# Status: Burst-No: 0 Write Address: 00002808 WriteData: f78576ef
|
# tb_core.u_sdram32 : at time 36847.0 ns WRITE: Bank = 2 Row = 2, Col = 3, Data = 70ef37e1
|
# tb_core.u_sdram32 : at time 37777.0 ns WRITE: Bank = 2 Row = 2, Col = 3, Data = 70ef37e1
|
# Status: Burst-No: 1 Write Address: 00002808 WriteData: 70ef37e1
|
# Status: Burst-No: 1 Write Address: 00002808 WriteData: 70ef37e1
|
# tb_core.u_sdram32 : at time 36857.0 ns WRITE: Bank = 2 Row = 2, Col = 4, Data = cab47c95
|
# tb_core.u_sdram32 : at time 37787.0 ns WRITE: Bank = 2 Row = 2, Col = 4, Data = cab47c95
|
# Status: Burst-No: 2 Write Address: 00002808 WriteData: cab47c95
|
# Status: Burst-No: 2 Write Address: 00002808 WriteData: cab47c95
|
# tb_core.u_sdram32 : at time 36867.0 ns WRITE: Bank = 2 Row = 2, Col = 5, Data = f7723eee
|
# tb_core.u_sdram32 : at time 37797.0 ns WRITE: Bank = 2 Row = 2, Col = 5, Data = f7723eee
|
# Status: Burst-No: 3 Write Address: 00002808 WriteData: f7723eee
|
# Status: Burst-No: 3 Write Address: 00002808 WriteData: f7723eee
|
# tb_core.u_sdram32 : at time 36877.0 ns WRITE: Bank = 2 Row = 2, Col = 6, Data = 304e4d60
|
# tb_core.u_sdram32 : at time 37807.0 ns WRITE: Bank = 2 Row = 2, Col = 6, Data = 304e4d60
|
# Status: Burst-No: 4 Write Address: 00002808 WriteData: 304e4d60
|
# Status: Burst-No: 4 Write Address: 00002808 WriteData: 304e4d60
|
# tb_core.u_sdram32 : at time 36887.0 ns WRITE: Bank = 2 Row = 2, Col = 7, Data = f29c5ee5
|
# tb_core.u_sdram32 : at time 37817.0 ns WRITE: Bank = 2 Row = 2, Col = 7, Data = f29c5ee5
|
# Status: Burst-No: 5 Write Address: 00002808 WriteData: f29c5ee5
|
# Status: Burst-No: 5 Write Address: 00002808 WriteData: f29c5ee5
|
# tb_core.u_sdram32 : at time 36897.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 37827.0 ns BST : Burst Terminate
|
# Write Address: 00002c0c, Burst Size: 7
|
# Write Address: 00002c0c, Burst Size: 7
|
# tb_core.u_sdram32 : at time 36967.0 ns ACT : Bank = 3 Row = 2
|
# tb_core.u_sdram32 : at time 37897.0 ns ACT : Bank = 3 Row = 2
|
# tb_core.u_sdram32 : at time 37007.0 ns WRITE: Bank = 3 Row = 2, Col = 3, Data = 9420ea28
|
# tb_core.u_sdram32 : at time 37937.0 ns WRITE: Bank = 3 Row = 2, Col = 3, Data = 9420ea28
|
# Status: Burst-No: 0 Write Address: 00002c0c WriteData: 9420ea28
|
# Status: Burst-No: 0 Write Address: 00002c0c WriteData: 9420ea28
|
# tb_core.u_sdram32 : at time 37017.0 ns WRITE: Bank = 3 Row = 2, Col = 4, Data = 322f7d64
|
# tb_core.u_sdram32 : at time 37947.0 ns WRITE: Bank = 3 Row = 2, Col = 4, Data = 322f7d64
|
# Status: Burst-No: 1 Write Address: 00002c0c WriteData: 322f7d64
|
# Status: Burst-No: 1 Write Address: 00002c0c WriteData: 322f7d64
|
# tb_core.u_sdram32 : at time 37027.0 ns WRITE: Bank = 3 Row = 2, Col = 5, Data = 14b43729
|
# tb_core.u_sdram32 : at time 37957.0 ns WRITE: Bank = 3 Row = 2, Col = 5, Data = 14b43729
|
# Status: Burst-No: 2 Write Address: 00002c0c WriteData: 14b43729
|
# Status: Burst-No: 2 Write Address: 00002c0c WriteData: 14b43729
|
# tb_core.u_sdram32 : at time 37037.0 ns WRITE: Bank = 3 Row = 2, Col = 6, Data = f0eeaee1
|
# tb_core.u_sdram32 : at time 37967.0 ns WRITE: Bank = 3 Row = 2, Col = 6, Data = f0eeaee1
|
# Status: Burst-No: 3 Write Address: 00002c0c WriteData: f0eeaee1
|
# Status: Burst-No: 3 Write Address: 00002c0c WriteData: f0eeaee1
|
# tb_core.u_sdram32 : at time 37047.0 ns WRITE: Bank = 3 Row = 2, Col = 7, Data = bbbc5277
|
# tb_core.u_sdram32 : at time 37977.0 ns WRITE: Bank = 3 Row = 2, Col = 7, Data = bbbc5277
|
# Status: Burst-No: 4 Write Address: 00002c0c WriteData: bbbc5277
|
# Status: Burst-No: 4 Write Address: 00002c0c WriteData: bbbc5277
|
# tb_core.u_sdram32 : at time 37057.0 ns WRITE: Bank = 3 Row = 2, Col = 8, Data = 3715156e
|
# tb_core.u_sdram32 : at time 37987.0 ns WRITE: Bank = 3 Row = 2, Col = 8, Data = 3715156e
|
# Status: Burst-No: 5 Write Address: 00002c0c WriteData: 3715156e
|
# Status: Burst-No: 5 Write Address: 00002c0c WriteData: 3715156e
|
# tb_core.u_sdram32 : at time 37067.0 ns WRITE: Bank = 3 Row = 2, Col = 9, Data = 40aaf581
|
# tb_core.u_sdram32 : at time 37997.0 ns WRITE: Bank = 3 Row = 2, Col = 9, Data = 40aaf581
|
# Status: Burst-No: 6 Write Address: 00002c0c WriteData: 40aaf581
|
# Status: Burst-No: 6 Write Address: 00002c0c WriteData: 40aaf581
|
# tb_core.u_sdram32 : at time 37077.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 38007.0 ns BST : Burst Terminate
|
# Write Address: 00003010, Burst Size: 4
|
# Write Address: 00003010, Burst Size: 4
|
# tb_core.u_sdram32 : at time 37147.0 ns ACT : Bank = 0 Row = 3
|
# tb_core.u_sdram32 : at time 38077.0 ns ACT : Bank = 0 Row = 3
|
# tb_core.u_sdram32 : at time 37187.0 ns WRITE: Bank = 0 Row = 3, Col = 4, Data = 6a9fb9d5
|
# tb_core.u_sdram32 : at time 38117.0 ns WRITE: Bank = 0 Row = 3, Col = 4, Data = 6a9fb9d5
|
# Status: Burst-No: 0 Write Address: 00003010 WriteData: 6a9fb9d5
|
# Status: Burst-No: 0 Write Address: 00003010 WriteData: 6a9fb9d5
|
# tb_core.u_sdram32 : at time 37197.0 ns WRITE: Bank = 0 Row = 3, Col = 5, Data = 3437d568
|
# tb_core.u_sdram32 : at time 38127.0 ns WRITE: Bank = 0 Row = 3, Col = 5, Data = 3437d568
|
# Status: Burst-No: 1 Write Address: 00003010 WriteData: 3437d568
|
# Status: Burst-No: 1 Write Address: 00003010 WriteData: 3437d568
|
# tb_core.u_sdram32 : at time 37207.0 ns WRITE: Bank = 0 Row = 3, Col = 6, Data = 786271f0
|
# tb_core.u_sdram32 : at time 38137.0 ns WRITE: Bank = 0 Row = 3, Col = 6, Data = 786271f0
|
# Status: Burst-No: 2 Write Address: 00003010 WriteData: 786271f0
|
# Status: Burst-No: 2 Write Address: 00003010 WriteData: 786271f0
|
# tb_core.u_sdram32 : at time 37217.0 ns WRITE: Bank = 0 Row = 3, Col = 7, Data = d57800aa
|
# tb_core.u_sdram32 : at time 38147.0 ns WRITE: Bank = 0 Row = 3, Col = 7, Data = d57800aa
|
# Status: Burst-No: 3 Write Address: 00003010 WriteData: d57800aa
|
# Status: Burst-No: 3 Write Address: 00003010 WriteData: d57800aa
|
# tb_core.u_sdram32 : at time 37227.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 38157.0 ns BST : Burst Terminate
|
# Write Address: 00003414, Burst Size: 5
|
# Write Address: 00003414, Burst Size: 5
|
# tb_core.u_sdram32 : at time 37297.0 ns ACT : Bank = 1 Row = 3
|
# tb_core.u_sdram32 : at time 38227.0 ns ACT : Bank = 1 Row = 3
|
# tb_core.u_sdram32 : at time 37337.0 ns WRITE: Bank = 1 Row = 3, Col = 5, Data = 079fc30f
|
# tb_core.u_sdram32 : at time 38267.0 ns WRITE: Bank = 1 Row = 3, Col = 5, Data = 079fc30f
|
# Status: Burst-No: 0 Write Address: 00003414 WriteData: 079fc30f
|
# Status: Burst-No: 0 Write Address: 00003414 WriteData: 079fc30f
|
# tb_core.u_sdram32 : at time 37347.0 ns WRITE: Bank = 1 Row = 3, Col = 6, Data = f8dc48f1
|
# tb_core.u_sdram32 : at time 38277.0 ns WRITE: Bank = 1 Row = 3, Col = 6, Data = f8dc48f1
|
# Status: Burst-No: 1 Write Address: 00003414 WriteData: f8dc48f1
|
# Status: Burst-No: 1 Write Address: 00003414 WriteData: f8dc48f1
|
# tb_core.u_sdram32 : at time 37357.0 ns WRITE: Bank = 1 Row = 3, Col = 7, Data = be9bbc7d
|
# tb_core.u_sdram32 : at time 38287.0 ns WRITE: Bank = 1 Row = 3, Col = 7, Data = be9bbc7d
|
# Status: Burst-No: 2 Write Address: 00003414 WriteData: be9bbc7d
|
# Status: Burst-No: 2 Write Address: 00003414 WriteData: be9bbc7d
|
# tb_core.u_sdram32 : at time 37367.0 ns WRITE: Bank = 1 Row = 3, Col = 8, Data = 472e958e
|
# tb_core.u_sdram32 : at time 38297.0 ns WRITE: Bank = 1 Row = 3, Col = 8, Data = 472e958e
|
# Status: Burst-No: 3 Write Address: 00003414 WriteData: 472e958e
|
# Status: Burst-No: 3 Write Address: 00003414 WriteData: 472e958e
|
# tb_core.u_sdram32 : at time 37377.0 ns WRITE: Bank = 1 Row = 3, Col = 9, Data = f161dce2
|
# tb_core.u_sdram32 : at time 38307.0 ns WRITE: Bank = 1 Row = 3, Col = 9, Data = f161dce2
|
# Status: Burst-No: 4 Write Address: 00003414 WriteData: f161dce2
|
# Status: Burst-No: 4 Write Address: 00003414 WriteData: f161dce2
|
# tb_core.u_sdram32 : at time 37387.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 38317.0 ns BST : Burst Terminate
|
# Write Address: 00003818, Burst Size: 6
|
# Write Address: 00003818, Burst Size: 6
|
# tb_core.u_sdram32 : at time 37457.0 ns ACT : Bank = 2 Row = 3
|
# tb_core.u_sdram32 : at time 38387.0 ns ACT : Bank = 2 Row = 3
|
# tb_core.u_sdram32 : at time 37497.0 ns WRITE: Bank = 2 Row = 3, Col = 6, Data = 1e664d3c
|
# tb_core.u_sdram32 : at time 38427.0 ns WRITE: Bank = 2 Row = 3, Col = 6, Data = 1e664d3c
|
# Status: Burst-No: 0 Write Address: 00003818 WriteData: 1e664d3c
|
# Status: Burst-No: 0 Write Address: 00003818 WriteData: 1e664d3c
|
# tb_core.u_sdram32 : at time 37507.0 ns WRITE: Bank = 2 Row = 3, Col = 7, Data = d4b5e6a9
|
# tb_core.u_sdram32 : at time 38437.0 ns WRITE: Bank = 2 Row = 3, Col = 7, Data = d4b5e6a9
|
# Status: Burst-No: 1 Write Address: 00003818 WriteData: d4b5e6a9
|
# Status: Burst-No: 1 Write Address: 00003818 WriteData: d4b5e6a9
|
# tb_core.u_sdram32 : at time 37517.0 ns WRITE: Bank = 2 Row = 3, Col = 8, Data = 77ebb1ef
|
# tb_core.u_sdram32 : at time 38447.0 ns WRITE: Bank = 2 Row = 3, Col = 8, Data = 77ebb1ef
|
# Status: Burst-No: 2 Write Address: 00003818 WriteData: 77ebb1ef
|
# Status: Burst-No: 2 Write Address: 00003818 WriteData: 77ebb1ef
|
# tb_core.u_sdram32 : at time 37527.0 ns WRITE: Bank = 2 Row = 3, Col = 9, Data = ade7d05b
|
# tb_core.u_sdram32 : at time 38457.0 ns WRITE: Bank = 2 Row = 3, Col = 9, Data = ade7d05b
|
# Status: Burst-No: 3 Write Address: 00003818 WriteData: ade7d05b
|
# Status: Burst-No: 3 Write Address: 00003818 WriteData: ade7d05b
|
# tb_core.u_sdram32 : at time 37537.0 ns WRITE: Bank = 2 Row = 3, Col = 10, Data = d7a23caf
|
# tb_core.u_sdram32 : at time 38467.0 ns WRITE: Bank = 2 Row = 3, Col = 10, Data = d7a23caf
|
# Status: Burst-No: 4 Write Address: 00003818 WriteData: d7a23caf
|
# Status: Burst-No: 4 Write Address: 00003818 WriteData: d7a23caf
|
# tb_core.u_sdram32 : at time 37547.0 ns WRITE: Bank = 2 Row = 3, Col = 11, Data = 25029b4a
|
# tb_core.u_sdram32 : at time 38477.0 ns WRITE: Bank = 2 Row = 3, Col = 11, Data = 25029b4a
|
# Status: Burst-No: 5 Write Address: 00003818 WriteData: 25029b4a
|
# Status: Burst-No: 5 Write Address: 00003818 WriteData: 25029b4a
|
# tb_core.u_sdram32 : at time 37557.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 38487.0 ns BST : Burst Terminate
|
# Write Address: 00003c1c, Burst Size: 7
|
# Write Address: 00003c1c, Burst Size: 7
|
# tb_core.u_sdram32 : at time 37627.0 ns ACT : Bank = 3 Row = 3
|
# tb_core.u_sdram32 : at time 38557.0 ns ACT : Bank = 3 Row = 3
|
# tb_core.u_sdram32 : at time 37667.0 ns WRITE: Bank = 3 Row = 3, Col = 7, Data = 5cd20db9
|
# tb_core.u_sdram32 : at time 38597.0 ns WRITE: Bank = 3 Row = 3, Col = 7, Data = 5cd20db9
|
# Status: Burst-No: 0 Write Address: 00003c1c WriteData: 5cd20db9
|
# Status: Burst-No: 0 Write Address: 00003c1c WriteData: 5cd20db9
|
# tb_core.u_sdram32 : at time 37677.0 ns WRITE: Bank = 3 Row = 3, Col = 8, Data = 098e2d13
|
# tb_core.u_sdram32 : at time 38607.0 ns WRITE: Bank = 3 Row = 3, Col = 8, Data = 098e2d13
|
# Status: Burst-No: 1 Write Address: 00003c1c WriteData: 098e2d13
|
# Status: Burst-No: 1 Write Address: 00003c1c WriteData: 098e2d13
|
# tb_core.u_sdram32 : at time 37687.0 ns WRITE: Bank = 3 Row = 3, Col = 9, Data = 09c83513
|
# tb_core.u_sdram32 : at time 38617.0 ns WRITE: Bank = 3 Row = 3, Col = 9, Data = 09c83513
|
# Status: Burst-No: 2 Write Address: 00003c1c WriteData: 09c83513
|
# Status: Burst-No: 2 Write Address: 00003c1c WriteData: 09c83513
|
# tb_core.u_sdram32 : at time 37697.0 ns WRITE: Bank = 3 Row = 3, Col = 10, Data = 32dc4165
|
# tb_core.u_sdram32 : at time 38627.0 ns WRITE: Bank = 3 Row = 3, Col = 10, Data = 32dc4165
|
# Status: Burst-No: 3 Write Address: 00003c1c WriteData: 32dc4165
|
# Status: Burst-No: 3 Write Address: 00003c1c WriteData: 32dc4165
|
# tb_core.u_sdram32 : at time 37707.0 ns WRITE: Bank = 3 Row = 3, Col = 11, Data = 28c62751
|
# tb_core.u_sdram32 : at time 38637.0 ns WRITE: Bank = 3 Row = 3, Col = 11, Data = 28c62751
|
# Status: Burst-No: 4 Write Address: 00003c1c WriteData: 28c62751
|
# Status: Burst-No: 4 Write Address: 00003c1c WriteData: 28c62751
|
# tb_core.u_sdram32 : at time 37717.0 ns WRITE: Bank = 3 Row = 3, Col = 12, Data = db983ab7
|
# tb_core.u_sdram32 : at time 38647.0 ns WRITE: Bank = 3 Row = 3, Col = 12, Data = db983ab7
|
# Status: Burst-No: 5 Write Address: 00003c1c WriteData: db983ab7
|
# Status: Burst-No: 5 Write Address: 00003c1c WriteData: db983ab7
|
# tb_core.u_sdram32 : at time 37727.0 ns WRITE: Bank = 3 Row = 3, Col = 13, Data = cc981099
|
# tb_core.u_sdram32 : at time 38657.0 ns WRITE: Bank = 3 Row = 3, Col = 13, Data = cc981099
|
# Status: Burst-No: 6 Write Address: 00003c1c WriteData: cc981099
|
# Status: Burst-No: 6 Write Address: 00003c1c WriteData: cc981099
|
# tb_core.u_sdram32 : at time 37737.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 38667.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 37797.0 ns ACT : Bank = 0 Row = 2
|
# tb_core.u_sdram32 : at time 38737.0 ns ACT : Bank = 0 Row = 2
|
# tb_core.u_sdram32 : at time 37863.0 ns READ : Bank = 0 Row = 2, Col = 0, Data = 611d9fc2
|
# tb_core.u_sdram32 : at time 38803.0 ns READ : Bank = 0 Row = 2, Col = 0, Data = 611d9fc2
|
# tb_core.u_sdram32 : at time 37873.0 ns READ : Bank = 0 Row = 2, Col = 1, Data = e2ecdac5
|
# tb_core.u_sdram32 : at time 38813.0 ns READ : Bank = 0 Row = 2, Col = 1, Data = e2ecdac5
|
# READ STATUS: Burst-No: 0 Addr: 00002000 Rxd: 611d9fc2
|
# READ STATUS: Burst-No: 0 Addr: 00002000 Rxd: 611d9fc2
|
# tb_core.u_sdram32 : at time 37877.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 38817.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 37883.0 ns READ : Bank = 0 Row = 2, Col = 2, Data = 9827fa30
|
# tb_core.u_sdram32 : at time 38823.0 ns READ : Bank = 0 Row = 2, Col = 2, Data = 9827fa30
|
# READ STATUS: Burst-No: 1 Addr: 00002002 Rxd: e2ecdac5
|
# READ STATUS: Burst-No: 1 Addr: 00002002 Rxd: e2ecdac5
|
# tb_core.u_sdram32 : at time 37893.0 ns READ : Bank = 0 Row = 2, Col = 3, Data = d7b2e4af
|
# tb_core.u_sdram32 : at time 38833.0 ns READ : Bank = 0 Row = 2, Col = 3, Data = d7b2e4af
|
# READ STATUS: Burst-No: 2 Addr: 00002004 Rxd: 9827fa30
|
# READ STATUS: Burst-No: 2 Addr: 00002004 Rxd: 9827fa30
|
# READ STATUS: Burst-No: 3 Addr: 00002006 Rxd: d7b2e4af
|
# READ STATUS: Burst-No: 3 Addr: 00002006 Rxd: d7b2e4af
|
# tb_core.u_sdram32 : at time 37987.0 ns ACT : Bank = 1 Row = 2
|
# tb_core.u_sdram32 : at time 38937.0 ns ACT : Bank = 1 Row = 2
|
# tb_core.u_sdram32 : at time 38053.0 ns READ : Bank = 1 Row = 2, Col = 1, Data = b302da66
|
# tb_core.u_sdram32 : at time 39003.0 ns READ : Bank = 1 Row = 2, Col = 1, Data = b302da66
|
# tb_core.u_sdram32 : at time 38063.0 ns READ : Bank = 1 Row = 2, Col = 2, Data = 57fbb9af
|
# tb_core.u_sdram32 : at time 39013.0 ns READ : Bank = 1 Row = 2, Col = 2, Data = 57fbb9af
|
# READ STATUS: Burst-No: 0 Addr: 00002404 Rxd: b302da66
|
# READ STATUS: Burst-No: 0 Addr: 00002404 Rxd: b302da66
|
# tb_core.u_sdram32 : at time 38073.0 ns READ : Bank = 1 Row = 2, Col = 3, Data = f4d86ee9
|
# tb_core.u_sdram32 : at time 39023.0 ns READ : Bank = 1 Row = 2, Col = 3, Data = f4d86ee9
|
# tb_core.u_sdram32 : at time 38077.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 39027.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 1 Addr: 00002406 Rxd: 57fbb9af
|
# READ STATUS: Burst-No: 1 Addr: 00002406 Rxd: 57fbb9af
|
# tb_core.u_sdram32 : at time 38083.0 ns READ : Bank = 1 Row = 2, Col = 4, Data = 7c41aff8
|
# tb_core.u_sdram32 : at time 39033.0 ns READ : Bank = 1 Row = 2, Col = 4, Data = 7c41aff8
|
# READ STATUS: Burst-No: 2 Addr: 00002408 Rxd: f4d86ee9
|
# READ STATUS: Burst-No: 2 Addr: 00002408 Rxd: f4d86ee9
|
# tb_core.u_sdram32 : at time 38093.0 ns READ : Bank = 1 Row = 2, Col = 5, Data = 8376ac06
|
# tb_core.u_sdram32 : at time 39043.0 ns READ : Bank = 1 Row = 2, Col = 5, Data = 8376ac06
|
# READ STATUS: Burst-No: 3 Addr: 0000240a Rxd: 7c41aff8
|
# READ STATUS: Burst-No: 3 Addr: 0000240a Rxd: 7c41aff8
|
# READ STATUS: Burst-No: 4 Addr: 0000240c Rxd: 8376ac06
|
# READ STATUS: Burst-No: 4 Addr: 0000240c Rxd: 8376ac06
|
# tb_core.u_sdram32 : at time 38187.0 ns ACT : Bank = 2 Row = 2
|
# tb_core.u_sdram32 : at time 39147.0 ns ACT : Bank = 2 Row = 2
|
# tb_core.u_sdram32 : at time 38253.0 ns READ : Bank = 2 Row = 2, Col = 2, Data = f78576ef
|
# tb_core.u_sdram32 : at time 39213.0 ns READ : Bank = 2 Row = 2, Col = 2, Data = f78576ef
|
# tb_core.u_sdram32 : at time 38263.0 ns READ : Bank = 2 Row = 2, Col = 3, Data = 70ef37e1
|
# tb_core.u_sdram32 : at time 39223.0 ns READ : Bank = 2 Row = 2, Col = 3, Data = 70ef37e1
|
# READ STATUS: Burst-No: 0 Addr: 00002808 Rxd: f78576ef
|
# READ STATUS: Burst-No: 0 Addr: 00002808 Rxd: f78576ef
|
# tb_core.u_sdram32 : at time 38273.0 ns READ : Bank = 2 Row = 2, Col = 4, Data = cab47c95
|
# tb_core.u_sdram32 : at time 39233.0 ns READ : Bank = 2 Row = 2, Col = 4, Data = cab47c95
|
# READ STATUS: Burst-No: 1 Addr: 0000280a Rxd: 70ef37e1
|
# READ STATUS: Burst-No: 1 Addr: 0000280a Rxd: 70ef37e1
|
# tb_core.u_sdram32 : at time 38283.0 ns READ : Bank = 2 Row = 2, Col = 5, Data = f7723eee
|
# tb_core.u_sdram32 : at time 39243.0 ns READ : Bank = 2 Row = 2, Col = 5, Data = f7723eee
|
# tb_core.u_sdram32 : at time 38287.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 39247.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 2 Addr: 0000280c Rxd: cab47c95
|
# READ STATUS: Burst-No: 2 Addr: 0000280c Rxd: cab47c95
|
# tb_core.u_sdram32 : at time 38293.0 ns READ : Bank = 2 Row = 2, Col = 6, Data = 304e4d60
|
# tb_core.u_sdram32 : at time 39253.0 ns READ : Bank = 2 Row = 2, Col = 6, Data = 304e4d60
|
# READ STATUS: Burst-No: 3 Addr: 0000280e Rxd: f7723eee
|
# READ STATUS: Burst-No: 3 Addr: 0000280e Rxd: f7723eee
|
# tb_core.u_sdram32 : at time 38303.0 ns READ : Bank = 2 Row = 2, Col = 7, Data = f29c5ee5
|
# tb_core.u_sdram32 : at time 39263.0 ns READ : Bank = 2 Row = 2, Col = 7, Data = f29c5ee5
|
# READ STATUS: Burst-No: 4 Addr: 00002810 Rxd: 304e4d60
|
# READ STATUS: Burst-No: 4 Addr: 00002810 Rxd: 304e4d60
|
# READ STATUS: Burst-No: 5 Addr: 00002812 Rxd: f29c5ee5
|
# READ STATUS: Burst-No: 5 Addr: 00002812 Rxd: f29c5ee5
|
# tb_core.u_sdram32 : at time 38397.0 ns ACT : Bank = 3 Row = 2
|
# tb_core.u_sdram32 : at time 39367.0 ns ACT : Bank = 3 Row = 2
|
# tb_core.u_sdram32 : at time 38463.0 ns READ : Bank = 3 Row = 2, Col = 3, Data = 9420ea28
|
# tb_core.u_sdram32 : at time 39433.0 ns READ : Bank = 3 Row = 2, Col = 3, Data = 9420ea28
|
# tb_core.u_sdram32 : at time 38473.0 ns READ : Bank = 3 Row = 2, Col = 4, Data = 322f7d64
|
# tb_core.u_sdram32 : at time 39443.0 ns READ : Bank = 3 Row = 2, Col = 4, Data = 322f7d64
|
# READ STATUS: Burst-No: 0 Addr: 00002c0c Rxd: 9420ea28
|
# READ STATUS: Burst-No: 0 Addr: 00002c0c Rxd: 9420ea28
|
# tb_core.u_sdram32 : at time 38483.0 ns READ : Bank = 3 Row = 2, Col = 5, Data = 14b43729
|
# tb_core.u_sdram32 : at time 39453.0 ns READ : Bank = 3 Row = 2, Col = 5, Data = 14b43729
|
# READ STATUS: Burst-No: 1 Addr: 00002c0e Rxd: 322f7d64
|
# READ STATUS: Burst-No: 1 Addr: 00002c0e Rxd: 322f7d64
|
# tb_core.u_sdram32 : at time 38493.0 ns READ : Bank = 3 Row = 2, Col = 6, Data = f0eeaee1
|
# tb_core.u_sdram32 : at time 39463.0 ns READ : Bank = 3 Row = 2, Col = 6, Data = f0eeaee1
|
# READ STATUS: Burst-No: 2 Addr: 00002c10 Rxd: 14b43729
|
# READ STATUS: Burst-No: 2 Addr: 00002c10 Rxd: 14b43729
|
# tb_core.u_sdram32 : at time 38503.0 ns READ : Bank = 3 Row = 2, Col = 7, Data = bbbc5277
|
# tb_core.u_sdram32 : at time 39473.0 ns READ : Bank = 3 Row = 2, Col = 7, Data = bbbc5277
|
# tb_core.u_sdram32 : at time 38507.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 39477.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 3 Addr: 00002c12 Rxd: f0eeaee1
|
# READ STATUS: Burst-No: 3 Addr: 00002c12 Rxd: f0eeaee1
|
# tb_core.u_sdram32 : at time 38513.0 ns READ : Bank = 3 Row = 2, Col = 8, Data = 3715156e
|
# tb_core.u_sdram32 : at time 39483.0 ns READ : Bank = 3 Row = 2, Col = 8, Data = 3715156e
|
# READ STATUS: Burst-No: 4 Addr: 00002c14 Rxd: bbbc5277
|
# READ STATUS: Burst-No: 4 Addr: 00002c14 Rxd: bbbc5277
|
# tb_core.u_sdram32 : at time 38523.0 ns READ : Bank = 3 Row = 2, Col = 9, Data = 40aaf581
|
# tb_core.u_sdram32 : at time 39493.0 ns READ : Bank = 3 Row = 2, Col = 9, Data = 40aaf581
|
# READ STATUS: Burst-No: 5 Addr: 00002c16 Rxd: 3715156e
|
# READ STATUS: Burst-No: 5 Addr: 00002c16 Rxd: 3715156e
|
# READ STATUS: Burst-No: 6 Addr: 00002c18 Rxd: 40aaf581
|
# READ STATUS: Burst-No: 6 Addr: 00002c18 Rxd: 40aaf581
|
# tb_core.u_sdram32 : at time 38617.0 ns ACT : Bank = 0 Row = 3
|
# tb_core.u_sdram32 : at time 39597.0 ns ACT : Bank = 0 Row = 3
|
# tb_core.u_sdram32 : at time 38683.0 ns READ : Bank = 0 Row = 3, Col = 4, Data = 6a9fb9d5
|
# tb_core.u_sdram32 : at time 39663.0 ns READ : Bank = 0 Row = 3, Col = 4, Data = 6a9fb9d5
|
# tb_core.u_sdram32 : at time 38693.0 ns READ : Bank = 0 Row = 3, Col = 5, Data = 3437d568
|
# tb_core.u_sdram32 : at time 39673.0 ns READ : Bank = 0 Row = 3, Col = 5, Data = 3437d568
|
# READ STATUS: Burst-No: 0 Addr: 00003010 Rxd: 6a9fb9d5
|
# READ STATUS: Burst-No: 0 Addr: 00003010 Rxd: 6a9fb9d5
|
# tb_core.u_sdram32 : at time 38697.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 39677.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 38703.0 ns READ : Bank = 0 Row = 3, Col = 6, Data = 786271f0
|
# tb_core.u_sdram32 : at time 39683.0 ns READ : Bank = 0 Row = 3, Col = 6, Data = 786271f0
|
# READ STATUS: Burst-No: 1 Addr: 00003012 Rxd: 3437d568
|
# READ STATUS: Burst-No: 1 Addr: 00003012 Rxd: 3437d568
|
# tb_core.u_sdram32 : at time 38713.0 ns READ : Bank = 0 Row = 3, Col = 7, Data = d57800aa
|
# tb_core.u_sdram32 : at time 39693.0 ns READ : Bank = 0 Row = 3, Col = 7, Data = d57800aa
|
# READ STATUS: Burst-No: 2 Addr: 00003014 Rxd: 786271f0
|
# READ STATUS: Burst-No: 2 Addr: 00003014 Rxd: 786271f0
|
# READ STATUS: Burst-No: 3 Addr: 00003016 Rxd: d57800aa
|
# READ STATUS: Burst-No: 3 Addr: 00003016 Rxd: d57800aa
|
# tb_core.u_sdram32 : at time 38807.0 ns ACT : Bank = 1 Row = 3
|
# tb_core.u_sdram32 : at time 39797.0 ns ACT : Bank = 1 Row = 3
|
# tb_core.u_sdram32 : at time 38873.0 ns READ : Bank = 1 Row = 3, Col = 5, Data = 079fc30f
|
# tb_core.u_sdram32 : at time 39863.0 ns READ : Bank = 1 Row = 3, Col = 5, Data = 079fc30f
|
# tb_core.u_sdram32 : at time 38883.0 ns READ : Bank = 1 Row = 3, Col = 6, Data = f8dc48f1
|
# tb_core.u_sdram32 : at time 39873.0 ns READ : Bank = 1 Row = 3, Col = 6, Data = f8dc48f1
|
# READ STATUS: Burst-No: 0 Addr: 00003414 Rxd: 079fc30f
|
# READ STATUS: Burst-No: 0 Addr: 00003414 Rxd: 079fc30f
|
# tb_core.u_sdram32 : at time 38893.0 ns READ : Bank = 1 Row = 3, Col = 7, Data = be9bbc7d
|
# tb_core.u_sdram32 : at time 39883.0 ns READ : Bank = 1 Row = 3, Col = 7, Data = be9bbc7d
|
# tb_core.u_sdram32 : at time 38897.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 39887.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 1 Addr: 00003416 Rxd: f8dc48f1
|
# READ STATUS: Burst-No: 1 Addr: 00003416 Rxd: f8dc48f1
|
# tb_core.u_sdram32 : at time 38903.0 ns READ : Bank = 1 Row = 3, Col = 8, Data = 472e958e
|
# tb_core.u_sdram32 : at time 39893.0 ns READ : Bank = 1 Row = 3, Col = 8, Data = 472e958e
|
# READ STATUS: Burst-No: 2 Addr: 00003418 Rxd: be9bbc7d
|
# READ STATUS: Burst-No: 2 Addr: 00003418 Rxd: be9bbc7d
|
# tb_core.u_sdram32 : at time 38913.0 ns READ : Bank = 1 Row = 3, Col = 9, Data = f161dce2
|
# tb_core.u_sdram32 : at time 39903.0 ns READ : Bank = 1 Row = 3, Col = 9, Data = f161dce2
|
# READ STATUS: Burst-No: 3 Addr: 0000341a Rxd: 472e958e
|
# READ STATUS: Burst-No: 3 Addr: 0000341a Rxd: 472e958e
|
# READ STATUS: Burst-No: 4 Addr: 0000341c Rxd: f161dce2
|
# READ STATUS: Burst-No: 4 Addr: 0000341c Rxd: f161dce2
|
# tb_core.u_sdram32 : at time 39007.0 ns ACT : Bank = 2 Row = 3
|
# tb_core.u_sdram32 : at time 40007.0 ns ACT : Bank = 2 Row = 3
|
# tb_core.u_sdram32 : at time 39073.0 ns READ : Bank = 2 Row = 3, Col = 6, Data = 1e664d3c
|
# tb_core.u_sdram32 : at time 40073.0 ns READ : Bank = 2 Row = 3, Col = 6, Data = 1e664d3c
|
# tb_core.u_sdram32 : at time 39083.0 ns READ : Bank = 2 Row = 3, Col = 7, Data = d4b5e6a9
|
# tb_core.u_sdram32 : at time 40083.0 ns READ : Bank = 2 Row = 3, Col = 7, Data = d4b5e6a9
|
# READ STATUS: Burst-No: 0 Addr: 00003818 Rxd: 1e664d3c
|
# READ STATUS: Burst-No: 0 Addr: 00003818 Rxd: 1e664d3c
|
# tb_core.u_sdram32 : at time 39093.0 ns READ : Bank = 2 Row = 3, Col = 8, Data = 77ebb1ef
|
# tb_core.u_sdram32 : at time 40093.0 ns READ : Bank = 2 Row = 3, Col = 8, Data = 77ebb1ef
|
# READ STATUS: Burst-No: 1 Addr: 0000381a Rxd: d4b5e6a9
|
# READ STATUS: Burst-No: 1 Addr: 0000381a Rxd: d4b5e6a9
|
# tb_core.u_sdram32 : at time 39103.0 ns READ : Bank = 2 Row = 3, Col = 9, Data = ade7d05b
|
# tb_core.u_sdram32 : at time 40103.0 ns READ : Bank = 2 Row = 3, Col = 9, Data = ade7d05b
|
# tb_core.u_sdram32 : at time 39107.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 40107.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 2 Addr: 0000381c Rxd: 77ebb1ef
|
# READ STATUS: Burst-No: 2 Addr: 0000381c Rxd: 77ebb1ef
|
# tb_core.u_sdram32 : at time 39113.0 ns READ : Bank = 2 Row = 3, Col = 10, Data = d7a23caf
|
# tb_core.u_sdram32 : at time 40113.0 ns READ : Bank = 2 Row = 3, Col = 10, Data = d7a23caf
|
# READ STATUS: Burst-No: 3 Addr: 0000381e Rxd: ade7d05b
|
# READ STATUS: Burst-No: 3 Addr: 0000381e Rxd: ade7d05b
|
# tb_core.u_sdram32 : at time 39123.0 ns READ : Bank = 2 Row = 3, Col = 11, Data = 25029b4a
|
# tb_core.u_sdram32 : at time 40123.0 ns READ : Bank = 2 Row = 3, Col = 11, Data = 25029b4a
|
# READ STATUS: Burst-No: 4 Addr: 00003820 Rxd: d7a23caf
|
# READ STATUS: Burst-No: 4 Addr: 00003820 Rxd: d7a23caf
|
# READ STATUS: Burst-No: 5 Addr: 00003822 Rxd: 25029b4a
|
# READ STATUS: Burst-No: 5 Addr: 00003822 Rxd: 25029b4a
|
# tb_core.u_sdram32 : at time 39217.0 ns ACT : Bank = 3 Row = 3
|
# tb_core.u_sdram32 : at time 40227.0 ns ACT : Bank = 3 Row = 3
|
# tb_core.u_sdram32 : at time 39283.0 ns READ : Bank = 3 Row = 3, Col = 7, Data = 5cd20db9
|
# tb_core.u_sdram32 : at time 40293.0 ns READ : Bank = 3 Row = 3, Col = 7, Data = 5cd20db9
|
# tb_core.u_sdram32 : at time 39293.0 ns READ : Bank = 3 Row = 3, Col = 8, Data = 098e2d13
|
# tb_core.u_sdram32 : at time 40303.0 ns READ : Bank = 3 Row = 3, Col = 8, Data = 098e2d13
|
# READ STATUS: Burst-No: 0 Addr: 00003c1c Rxd: 5cd20db9
|
# READ STATUS: Burst-No: 0 Addr: 00003c1c Rxd: 5cd20db9
|
# tb_core.u_sdram32 : at time 39303.0 ns READ : Bank = 3 Row = 3, Col = 9, Data = 09c83513
|
# tb_core.u_sdram32 : at time 40313.0 ns READ : Bank = 3 Row = 3, Col = 9, Data = 09c83513
|
# READ STATUS: Burst-No: 1 Addr: 00003c1e Rxd: 098e2d13
|
# READ STATUS: Burst-No: 1 Addr: 00003c1e Rxd: 098e2d13
|
# tb_core.u_sdram32 : at time 39313.0 ns READ : Bank = 3 Row = 3, Col = 10, Data = 32dc4165
|
# tb_core.u_sdram32 : at time 40323.0 ns READ : Bank = 3 Row = 3, Col = 10, Data = 32dc4165
|
# READ STATUS: Burst-No: 2 Addr: 00003c20 Rxd: 09c83513
|
# READ STATUS: Burst-No: 2 Addr: 00003c20 Rxd: 09c83513
|
# tb_core.u_sdram32 : at time 39323.0 ns READ : Bank = 3 Row = 3, Col = 11, Data = 28c62751
|
# tb_core.u_sdram32 : at time 40333.0 ns READ : Bank = 3 Row = 3, Col = 11, Data = 28c62751
|
# tb_core.u_sdram32 : at time 39327.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 40337.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 3 Addr: 00003c22 Rxd: 32dc4165
|
# READ STATUS: Burst-No: 3 Addr: 00003c22 Rxd: 32dc4165
|
# tb_core.u_sdram32 : at time 39333.0 ns READ : Bank = 3 Row = 3, Col = 12, Data = db983ab7
|
# tb_core.u_sdram32 : at time 40343.0 ns READ : Bank = 3 Row = 3, Col = 12, Data = db983ab7
|
# READ STATUS: Burst-No: 4 Addr: 00003c24 Rxd: 28c62751
|
# READ STATUS: Burst-No: 4 Addr: 00003c24 Rxd: 28c62751
|
# tb_core.u_sdram32 : at time 39343.0 ns READ : Bank = 3 Row = 3, Col = 13, Data = cc981099
|
# tb_core.u_sdram32 : at time 40353.0 ns READ : Bank = 3 Row = 3, Col = 13, Data = cc981099
|
# READ STATUS: Burst-No: 5 Addr: 00003c26 Rxd: db983ab7
|
# READ STATUS: Burst-No: 5 Addr: 00003c26 Rxd: db983ab7
|
# READ STATUS: Burst-No: 6 Addr: 00003c28 Rxd: cc981099
|
# READ STATUS: Burst-No: 6 Addr: 00003c28 Rxd: cc981099
|
# ---------------------------------------------------
|
# ---------------------------------------------------
|
# Case: 6 Random 2 write and 2 read random
|
# Case: 6 Random 2 write and 2 read random
|
# ---------------------------------------------------
|
# ---------------------------------------------------
|
# Write Address: 0012083a, Burst Size: 2
|
# Write Address: 0012083a, Burst Size: 2
|
# tb_core.u_sdram32 : at time 39447.0 ns ACT : Bank = 2 Row = 288
|
# tb_core.u_sdram32 : at time 40457.0 ns ACT : Bank = 2 Row = 288
|
# tb_core.u_sdram32 : at time 39487.0 ns WRITE: Bank = 2 Row = 288, Col = 14, Data = 317c0762
|
# tb_core.u_sdram32 : at time 40497.0 ns WRITE: Bank = 2 Row = 288, Col = 14, Data = 317c0762
|
# Status: Burst-No: 0 Write Address: 0012083a WriteData: 317c0762
|
# Status: Burst-No: 0 Write Address: 0012083a WriteData: 317c0762
|
# tb_core.u_sdram32 : at time 39497.0 ns WRITE: Bank = 2 Row = 288, Col = 15, Data = f2356ae4
|
# tb_core.u_sdram32 : at time 40507.0 ns WRITE: Bank = 2 Row = 288, Col = 15, Data = f2356ae4
|
# Status: Burst-No: 1 Write Address: 0012083a WriteData: f2356ae4
|
# Status: Burst-No: 1 Write Address: 0012083a WriteData: f2356ae4
|
# tb_core.u_sdram32 : at time 39507.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 40517.0 ns BST : Burst Terminate
|
# Write Address: 0013dd2a, Burst Size: 14
|
# Write Address: 0013dd2a, Burst Size: 14
|
# tb_core.u_sdram32 : at time 39667.0 ns ACT : Bank = 3 Row = 317
|
# tb_core.u_sdram32 : at time 40677.0 ns ACT : Bank = 3 Row = 317
|
# tb_core.u_sdram32 : at time 39707.0 ns WRITE: Bank = 3 Row = 317, Col = 74, Data = 2cee5f59
|
# tb_core.u_sdram32 : at time 40717.0 ns WRITE: Bank = 3 Row = 317, Col = 74, Data = 2cee5f59
|
# Status: Burst-No: 0 Write Address: 0013dd2a WriteData: 2cee5f59
|
# Status: Burst-No: 0 Write Address: 0013dd2a WriteData: 2cee5f59
|
# tb_core.u_sdram32 : at time 39717.0 ns WRITE: Bank = 3 Row = 317, Col = 75, Data = 72c3a3e5
|
# tb_core.u_sdram32 : at time 40727.0 ns WRITE: Bank = 3 Row = 317, Col = 75, Data = 72c3a3e5
|
# Status: Burst-No: 1 Write Address: 0013dd2a WriteData: 72c3a3e5
|
# Status: Burst-No: 1 Write Address: 0013dd2a WriteData: 72c3a3e5
|
# tb_core.u_sdram32 : at time 39727.0 ns WRITE: Bank = 3 Row = 317, Col = 76, Data = 76de6bed
|
# tb_core.u_sdram32 : at time 40737.0 ns WRITE: Bank = 3 Row = 317, Col = 76, Data = 76de6bed
|
# Status: Burst-No: 2 Write Address: 0013dd2a WriteData: 76de6bed
|
# Status: Burst-No: 2 Write Address: 0013dd2a WriteData: 76de6bed
|
# tb_core.u_sdram32 : at time 39737.0 ns WRITE: Bank = 3 Row = 317, Col = 77, Data = e4a800c9
|
# tb_core.u_sdram32 : at time 40747.0 ns WRITE: Bank = 3 Row = 317, Col = 77, Data = e4a800c9
|
# Status: Burst-No: 3 Write Address: 0013dd2a WriteData: e4a800c9
|
# Status: Burst-No: 3 Write Address: 0013dd2a WriteData: e4a800c9
|
# tb_core.u_sdram32 : at time 39747.0 ns WRITE: Bank = 3 Row = 317, Col = 78, Data = a0aecc41
|
# tb_core.u_sdram32 : at time 40757.0 ns WRITE: Bank = 3 Row = 317, Col = 78, Data = a0aecc41
|
# Status: Burst-No: 4 Write Address: 0013dd2a WriteData: a0aecc41
|
# Status: Burst-No: 4 Write Address: 0013dd2a WriteData: a0aecc41
|
# tb_core.u_sdram32 : at time 39757.0 ns WRITE: Bank = 3 Row = 317, Col = 79, Data = 57c1d1af
|
# tb_core.u_sdram32 : at time 40767.0 ns WRITE: Bank = 3 Row = 317, Col = 79, Data = 57c1d1af
|
# Status: Burst-No: 5 Write Address: 0013dd2a WriteData: 57c1d1af
|
# Status: Burst-No: 5 Write Address: 0013dd2a WriteData: 57c1d1af
|
# tb_core.u_sdram32 : at time 39767.0 ns WRITE: Bank = 3 Row = 317, Col = 80, Data = eda71cdb
|
# tb_core.u_sdram32 : at time 40777.0 ns WRITE: Bank = 3 Row = 317, Col = 80, Data = eda71cdb
|
# Status: Burst-No: 6 Write Address: 0013dd2a WriteData: eda71cdb
|
# Status: Burst-No: 6 Write Address: 0013dd2a WriteData: eda71cdb
|
# tb_core.u_sdram32 : at time 39777.0 ns WRITE: Bank = 3 Row = 317, Col = 81, Data = e696e8cd
|
# tb_core.u_sdram32 : at time 40787.0 ns WRITE: Bank = 3 Row = 317, Col = 81, Data = e696e8cd
|
# Status: Burst-No: 7 Write Address: 0013dd2a WriteData: e696e8cd
|
# Status: Burst-No: 7 Write Address: 0013dd2a WriteData: e696e8cd
|
# tb_core.u_sdram32 : at time 39787.0 ns WRITE: Bank = 3 Row = 317, Col = 82, Data = 38139f70
|
# tb_core.u_sdram32 : at time 40797.0 ns WRITE: Bank = 3 Row = 317, Col = 82, Data = 38139f70
|
# Status: Burst-No: 8 Write Address: 0013dd2a WriteData: 38139f70
|
# Status: Burst-No: 8 Write Address: 0013dd2a WriteData: 38139f70
|
# tb_core.u_sdram32 : at time 39797.0 ns WRITE: Bank = 3 Row = 317, Col = 83, Data = 8326d406
|
# tb_core.u_sdram32 : at time 40807.0 ns WRITE: Bank = 3 Row = 317, Col = 83, Data = 8326d406
|
# Status: Burst-No: 9 Write Address: 0013dd2a WriteData: 8326d406
|
# Status: Burst-No: 9 Write Address: 0013dd2a WriteData: 8326d406
|
# tb_core.u_sdram32 : at time 39807.0 ns WRITE: Bank = 3 Row = 317, Col = 84, Data = d14820a2
|
# tb_core.u_sdram32 : at time 40817.0 ns WRITE: Bank = 3 Row = 317, Col = 84, Data = d14820a2
|
# Status: Burst-No: 10 Write Address: 0013dd2a WriteData: d14820a2
|
# Status: Burst-No: 10 Write Address: 0013dd2a WriteData: d14820a2
|
# tb_core.u_sdram32 : at time 39817.0 ns WRITE: Bank = 3 Row = 317, Col = 85, Data = 5e983dbd
|
# tb_core.u_sdram32 : at time 40827.0 ns WRITE: Bank = 3 Row = 317, Col = 85, Data = 5e983dbd
|
# Status: Burst-No: 11 Write Address: 0013dd2a WriteData: 5e983dbd
|
# Status: Burst-No: 11 Write Address: 0013dd2a WriteData: 5e983dbd
|
# tb_core.u_sdram32 : at time 39827.0 ns WRITE: Bank = 3 Row = 317, Col = 86, Data = b555de6a
|
# tb_core.u_sdram32 : at time 40837.0 ns WRITE: Bank = 3 Row = 317, Col = 86, Data = b555de6a
|
# Status: Burst-No: 12 Write Address: 0013dd2a WriteData: b555de6a
|
# Status: Burst-No: 12 Write Address: 0013dd2a WriteData: b555de6a
|
# tb_core.u_sdram32 : at time 39837.0 ns WRITE: Bank = 3 Row = 317, Col = 87, Data = 6e3d47dc
|
# tb_core.u_sdram32 : at time 40847.0 ns WRITE: Bank = 3 Row = 317, Col = 87, Data = 6e3d47dc
|
# Status: Burst-No: 13 Write Address: 0013dd2a WriteData: 6e3d47dc
|
# Status: Burst-No: 13 Write Address: 0013dd2a WriteData: 6e3d47dc
|
# tb_core.u_sdram32 : at time 39847.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 40857.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 39997.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 40997.0 ns AREF : Auto Refresh
|
# tb_core.u_sdram32 : at time 40003.0 ns READ : Bank = 2 Row = 288, Col = 14, Data = 317c0762
|
# tb_core.u_sdram32 : at time 41087.0 ns AREF : Auto Refresh
|
# tb_core.u_sdram32 : at time 40013.0 ns READ : Bank = 2 Row = 288, Col = 15, Data = f2356ae4
|
# tb_core.u_sdram32 : at time 41177.0 ns AREF : Auto Refresh
|
|
# tb_core.u_sdram32 : at time 41267.0 ns AREF : Auto Refresh
|
|
# tb_core.u_sdram32 : at time 41357.0 ns AREF : Auto Refresh
|
|
# tb_core.u_sdram32 : at time 41447.0 ns AREF : Auto Refresh
|
|
# tb_core.u_sdram32 : at time 41537.0 ns ACT : Bank = 2 Row = 288
|
|
# tb_core.u_sdram32 : at time 41597.0 ns BST : Burst Terminate
|
|
# tb_core.u_sdram32 : at time 41603.0 ns READ : Bank = 2 Row = 288, Col = 14, Data = 317c0762
|
|
# tb_core.u_sdram32 : at time 41613.0 ns READ : Bank = 2 Row = 288, Col = 15, Data = f2356ae4
|
# READ STATUS: Burst-No: 0 Addr: 0012083a Rxd: 317c0762
|
# READ STATUS: Burst-No: 0 Addr: 0012083a Rxd: 317c0762
|
# READ STATUS: Burst-No: 1 Addr: 0012083c Rxd: f2356ae4
|
# READ STATUS: Burst-No: 1 Addr: 0012083c Rxd: f2356ae4
|
# tb_core.u_sdram32 : at time 40203.0 ns READ : Bank = 3 Row = 317, Col = 74, Data = 2cee5f59
|
# tb_core.u_sdram32 : at time 41807.0 ns ACT : Bank = 3 Row = 317
|
# tb_core.u_sdram32 : at time 40213.0 ns READ : Bank = 3 Row = 317, Col = 75, Data = 72c3a3e5
|
# tb_core.u_sdram32 : at time 41873.0 ns READ : Bank = 3 Row = 317, Col = 74, Data = 2cee5f59
|
|
# tb_core.u_sdram32 : at time 41883.0 ns READ : Bank = 3 Row = 317, Col = 75, Data = 72c3a3e5
|
# READ STATUS: Burst-No: 0 Addr: 0013dd2a Rxd: 2cee5f59
|
# READ STATUS: Burst-No: 0 Addr: 0013dd2a Rxd: 2cee5f59
|
# tb_core.u_sdram32 : at time 40223.0 ns READ : Bank = 3 Row = 317, Col = 76, Data = 76de6bed
|
# tb_core.u_sdram32 : at time 41893.0 ns READ : Bank = 3 Row = 317, Col = 76, Data = 76de6bed
|
# READ STATUS: Burst-No: 1 Addr: 0013dd2c Rxd: 72c3a3e5
|
# READ STATUS: Burst-No: 1 Addr: 0013dd2c Rxd: 72c3a3e5
|
# tb_core.u_sdram32 : at time 40233.0 ns READ : Bank = 3 Row = 317, Col = 77, Data = e4a800c9
|
# tb_core.u_sdram32 : at time 41903.0 ns READ : Bank = 3 Row = 317, Col = 77, Data = e4a800c9
|
# READ STATUS: Burst-No: 2 Addr: 0013dd2e Rxd: 76de6bed
|
# READ STATUS: Burst-No: 2 Addr: 0013dd2e Rxd: 76de6bed
|
# tb_core.u_sdram32 : at time 40243.0 ns READ : Bank = 3 Row = 317, Col = 78, Data = a0aecc41
|
# tb_core.u_sdram32 : at time 41913.0 ns READ : Bank = 3 Row = 317, Col = 78, Data = a0aecc41
|
# READ STATUS: Burst-No: 3 Addr: 0013dd30 Rxd: e4a800c9
|
# READ STATUS: Burst-No: 3 Addr: 0013dd30 Rxd: e4a800c9
|
# tb_core.u_sdram32 : at time 40253.0 ns READ : Bank = 3 Row = 317, Col = 79, Data = 57c1d1af
|
# tb_core.u_sdram32 : at time 41923.0 ns READ : Bank = 3 Row = 317, Col = 79, Data = 57c1d1af
|
# READ STATUS: Burst-No: 4 Addr: 0013dd32 Rxd: a0aecc41
|
# READ STATUS: Burst-No: 4 Addr: 0013dd32 Rxd: a0aecc41
|
# tb_core.u_sdram32 : at time 40263.0 ns READ : Bank = 3 Row = 317, Col = 80, Data = eda71cdb
|
# tb_core.u_sdram32 : at time 41933.0 ns READ : Bank = 3 Row = 317, Col = 80, Data = eda71cdb
|
# READ STATUS: Burst-No: 5 Addr: 0013dd34 Rxd: 57c1d1af
|
# READ STATUS: Burst-No: 5 Addr: 0013dd34 Rxd: 57c1d1af
|
# tb_core.u_sdram32 : at time 40273.0 ns READ : Bank = 3 Row = 317, Col = 81, Data = e696e8cd
|
# tb_core.u_sdram32 : at time 41943.0 ns READ : Bank = 3 Row = 317, Col = 81, Data = e696e8cd
|
# READ STATUS: Burst-No: 6 Addr: 0013dd36 Rxd: eda71cdb
|
# READ STATUS: Burst-No: 6 Addr: 0013dd36 Rxd: eda71cdb
|
# tb_core.u_sdram32 : at time 40283.0 ns READ : Bank = 3 Row = 317, Col = 82, Data = 38139f70
|
# tb_core.u_sdram32 : at time 41953.0 ns READ : Bank = 3 Row = 317, Col = 82, Data = 38139f70
|
# READ STATUS: Burst-No: 7 Addr: 0013dd38 Rxd: e696e8cd
|
# READ STATUS: Burst-No: 7 Addr: 0013dd38 Rxd: e696e8cd
|
# tb_core.u_sdram32 : at time 40293.0 ns READ : Bank = 3 Row = 317, Col = 83, Data = 8326d406
|
# tb_core.u_sdram32 : at time 41963.0 ns READ : Bank = 3 Row = 317, Col = 83, Data = 8326d406
|
# READ STATUS: Burst-No: 8 Addr: 0013dd3a Rxd: 38139f70
|
# READ STATUS: Burst-No: 8 Addr: 0013dd3a Rxd: 38139f70
|
# tb_core.u_sdram32 : at time 40303.0 ns READ : Bank = 3 Row = 317, Col = 84, Data = d14820a2
|
# tb_core.u_sdram32 : at time 41973.0 ns READ : Bank = 3 Row = 317, Col = 84, Data = d14820a2
|
# READ STATUS: Burst-No: 9 Addr: 0013dd3c Rxd: 8326d406
|
# READ STATUS: Burst-No: 9 Addr: 0013dd3c Rxd: 8326d406
|
# tb_core.u_sdram32 : at time 40313.0 ns READ : Bank = 3 Row = 317, Col = 85, Data = 5e983dbd
|
# tb_core.u_sdram32 : at time 41983.0 ns READ : Bank = 3 Row = 317, Col = 85, Data = 5e983dbd
|
# tb_core.u_sdram32 : at time 40317.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 41987.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 10 Addr: 0013dd3e Rxd: d14820a2
|
# READ STATUS: Burst-No: 10 Addr: 0013dd3e Rxd: d14820a2
|
# tb_core.u_sdram32 : at time 40323.0 ns READ : Bank = 3 Row = 317, Col = 86, Data = b555de6a
|
# tb_core.u_sdram32 : at time 41993.0 ns READ : Bank = 3 Row = 317, Col = 86, Data = b555de6a
|
# READ STATUS: Burst-No: 11 Addr: 0013dd40 Rxd: 5e983dbd
|
# READ STATUS: Burst-No: 11 Addr: 0013dd40 Rxd: 5e983dbd
|
# tb_core.u_sdram32 : at time 40333.0 ns READ : Bank = 3 Row = 317, Col = 87, Data = 6e3d47dc
|
# tb_core.u_sdram32 : at time 42003.0 ns READ : Bank = 3 Row = 317, Col = 87, Data = 6e3d47dc
|
# READ STATUS: Burst-No: 12 Addr: 0013dd42 Rxd: b555de6a
|
# READ STATUS: Burst-No: 12 Addr: 0013dd42 Rxd: b555de6a
|
# READ STATUS: Burst-No: 13 Addr: 0013dd44 Rxd: 6e3d47dc
|
# READ STATUS: Burst-No: 13 Addr: 0013dd44 Rxd: 6e3d47dc
|
# Write Address: 002c5e50, Burst Size: 12
|
# Write Address: 002c5e50, Burst Size: 12
|
# tb_core.u_sdram32 : at time 40527.0 ns ACT : Bank = 3 Row = 709
|
# tb_core.u_sdram32 : at time 42197.0 ns ACT : Bank = 3 Row = 709
|
# tb_core.u_sdram32 : at time 40567.0 ns WRITE: Bank = 3 Row = 709, Col = 148, Data = 929d5825
|
# tb_core.u_sdram32 : at time 42237.0 ns WRITE: Bank = 3 Row = 709, Col = 148, Data = 929d5825
|
# Status: Burst-No: 0 Write Address: 002c5e50 WriteData: 929d5825
|
# Status: Burst-No: 0 Write Address: 002c5e50 WriteData: 929d5825
|
# tb_core.u_sdram32 : at time 40577.0 ns WRITE: Bank = 3 Row = 709, Col = 149, Data = bc3f8478
|
# tb_core.u_sdram32 : at time 42247.0 ns WRITE: Bank = 3 Row = 709, Col = 149, Data = bc3f8478
|
# Status: Burst-No: 1 Write Address: 002c5e50 WriteData: bc3f8478
|
# Status: Burst-No: 1 Write Address: 002c5e50 WriteData: bc3f8478
|
# tb_core.u_sdram32 : at time 40587.0 ns WRITE: Bank = 3 Row = 709, Col = 150, Data = 7b7b89f6
|
# tb_core.u_sdram32 : at time 42257.0 ns WRITE: Bank = 3 Row = 709, Col = 150, Data = 7b7b89f6
|
# Status: Burst-No: 2 Write Address: 002c5e50 WriteData: 7b7b89f6
|
# Status: Burst-No: 2 Write Address: 002c5e50 WriteData: 7b7b89f6
|
# tb_core.u_sdram32 : at time 40597.0 ns WRITE: Bank = 3 Row = 709, Col = 151, Data = ae23ce5c
|
# tb_core.u_sdram32 : at time 42267.0 ns WRITE: Bank = 3 Row = 709, Col = 151, Data = ae23ce5c
|
# Status: Burst-No: 3 Write Address: 002c5e50 WriteData: ae23ce5c
|
# Status: Burst-No: 3 Write Address: 002c5e50 WriteData: ae23ce5c
|
# tb_core.u_sdram32 : at time 40607.0 ns WRITE: Bank = 3 Row = 709, Col = 152, Data = 11cc9b23
|
# tb_core.u_sdram32 : at time 42277.0 ns WRITE: Bank = 3 Row = 709, Col = 152, Data = 11cc9b23
|
# Status: Burst-No: 4 Write Address: 002c5e50 WriteData: 11cc9b23
|
# Status: Burst-No: 4 Write Address: 002c5e50 WriteData: 11cc9b23
|
# tb_core.u_sdram32 : at time 40617.0 ns WRITE: Bank = 3 Row = 709, Col = 153, Data = 3cb3ab79
|
# tb_core.u_sdram32 : at time 42287.0 ns WRITE: Bank = 3 Row = 709, Col = 153, Data = 3cb3ab79
|
# Status: Burst-No: 5 Write Address: 002c5e50 WriteData: 3cb3ab79
|
# Status: Burst-No: 5 Write Address: 002c5e50 WriteData: 3cb3ab79
|
# tb_core.u_sdram32 : at time 40627.0 ns WRITE: Bank = 3 Row = 709, Col = 154, Data = 644605c8
|
# tb_core.u_sdram32 : at time 42297.0 ns WRITE: Bank = 3 Row = 709, Col = 154, Data = 644605c8
|
# Status: Burst-No: 6 Write Address: 002c5e50 WriteData: 644605c8
|
# Status: Burst-No: 6 Write Address: 002c5e50 WriteData: 644605c8
|
# tb_core.u_sdram32 : at time 40637.0 ns WRITE: Bank = 3 Row = 709, Col = 155, Data = ddd146bb
|
# tb_core.u_sdram32 : at time 42307.0 ns WRITE: Bank = 3 Row = 709, Col = 155, Data = ddd146bb
|
# Status: Burst-No: 7 Write Address: 002c5e50 WriteData: ddd146bb
|
# Status: Burst-No: 7 Write Address: 002c5e50 WriteData: ddd146bb
|
# tb_core.u_sdram32 : at time 40647.0 ns WRITE: Bank = 3 Row = 709, Col = 156, Data = 870cee0e
|
# tb_core.u_sdram32 : at time 42317.0 ns WRITE: Bank = 3 Row = 709, Col = 156, Data = 870cee0e
|
# Status: Burst-No: 8 Write Address: 002c5e50 WriteData: 870cee0e
|
# Status: Burst-No: 8 Write Address: 002c5e50 WriteData: 870cee0e
|
# tb_core.u_sdram32 : at time 40657.0 ns WRITE: Bank = 3 Row = 709, Col = 157, Data = b9879473
|
# tb_core.u_sdram32 : at time 42327.0 ns WRITE: Bank = 3 Row = 709, Col = 157, Data = b9879473
|
# Status: Burst-No: 9 Write Address: 002c5e50 WriteData: b9879473
|
# Status: Burst-No: 9 Write Address: 002c5e50 WriteData: b9879473
|
# tb_core.u_sdram32 : at time 40667.0 ns WRITE: Bank = 3 Row = 709, Col = 158, Data = 0671030c
|
# tb_core.u_sdram32 : at time 42337.0 ns WRITE: Bank = 3 Row = 709, Col = 158, Data = 0671030c
|
# Status: Burst-No: 10 Write Address: 002c5e50 WriteData: 0671030c
|
# Status: Burst-No: 10 Write Address: 002c5e50 WriteData: 0671030c
|
# tb_core.u_sdram32 : at time 40677.0 ns WRITE: Bank = 3 Row = 709, Col = 159, Data = e70f98ce
|
# tb_core.u_sdram32 : at time 42347.0 ns WRITE: Bank = 3 Row = 709, Col = 159, Data = e70f98ce
|
# Status: Burst-No: 11 Write Address: 002c5e50 WriteData: e70f98ce
|
# Status: Burst-No: 11 Write Address: 002c5e50 WriteData: e70f98ce
|
# tb_core.u_sdram32 : at time 40687.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 42357.0 ns BST : Burst Terminate
|
# Write Address: 001a61d4, Burst Size: 10
|
# Write Address: 001a61d4, Burst Size: 10
|
# tb_core.u_sdram32 : at time 40847.0 ns ACT : Bank = 0 Row = 422
|
# tb_core.u_sdram32 : at time 42517.0 ns ACT : Bank = 0 Row = 422
|
# tb_core.u_sdram32 : at time 40887.0 ns WRITE: Bank = 0 Row = 422, Col = 117, Data = 5ca26fb9
|
# tb_core.u_sdram32 : at time 42557.0 ns WRITE: Bank = 0 Row = 422, Col = 117, Data = 5ca26fb9
|
# Status: Burst-No: 0 Write Address: 001a61d4 WriteData: 5ca26fb9
|
# Status: Burst-No: 0 Write Address: 001a61d4 WriteData: 5ca26fb9
|
# tb_core.u_sdram32 : at time 40897.0 ns WRITE: Bank = 0 Row = 422, Col = 118, Data = d9b8c0b3
|
# tb_core.u_sdram32 : at time 42567.0 ns WRITE: Bank = 0 Row = 422, Col = 118, Data = d9b8c0b3
|
# Status: Burst-No: 1 Write Address: 001a61d4 WriteData: d9b8c0b3
|
# Status: Burst-No: 1 Write Address: 001a61d4 WriteData: d9b8c0b3
|
# tb_core.u_sdram32 : at time 40907.0 ns WRITE: Bank = 0 Row = 422, Col = 119, Data = 7a4fbff4
|
# tb_core.u_sdram32 : at time 42577.0 ns WRITE: Bank = 0 Row = 422, Col = 119, Data = 7a4fbff4
|
# Status: Burst-No: 2 Write Address: 001a61d4 WriteData: 7a4fbff4
|
# Status: Burst-No: 2 Write Address: 001a61d4 WriteData: 7a4fbff4
|
# tb_core.u_sdram32 : at time 40917.0 ns WRITE: Bank = 0 Row = 422, Col = 120, Data = baf4e275
|
# tb_core.u_sdram32 : at time 42587.0 ns WRITE: Bank = 0 Row = 422, Col = 120, Data = baf4e275
|
# Status: Burst-No: 3 Write Address: 001a61d4 WriteData: baf4e275
|
# Status: Burst-No: 3 Write Address: 001a61d4 WriteData: baf4e275
|
# tb_core.u_sdram32 : at time 40927.0 ns WRITE: Bank = 0 Row = 422, Col = 121, Data = 066cf10c
|
# tb_core.u_sdram32 : at time 42597.0 ns WRITE: Bank = 0 Row = 422, Col = 121, Data = 066cf10c
|
# Status: Burst-No: 4 Write Address: 001a61d4 WriteData: 066cf10c
|
# Status: Burst-No: 4 Write Address: 001a61d4 WriteData: 066cf10c
|
# tb_core.u_sdram32 : at time 40937.0 ns WRITE: Bank = 0 Row = 422, Col = 122, Data = 9cfc7a39
|
# tb_core.u_sdram32 : at time 42607.0 ns WRITE: Bank = 0 Row = 422, Col = 122, Data = 9cfc7a39
|
# Status: Burst-No: 5 Write Address: 001a61d4 WriteData: 9cfc7a39
|
# Status: Burst-No: 5 Write Address: 001a61d4 WriteData: 9cfc7a39
|
# tb_core.u_sdram32 : at time 40947.0 ns WRITE: Bank = 0 Row = 422, Col = 123, Data = 01729302
|
# tb_core.u_sdram32 : at time 42617.0 ns WRITE: Bank = 0 Row = 422, Col = 123, Data = 01729302
|
# Status: Burst-No: 6 Write Address: 001a61d4 WriteData: 01729302
|
# Status: Burst-No: 6 Write Address: 001a61d4 WriteData: 01729302
|
# tb_core.u_sdram32 : at time 40957.0 ns WRITE: Bank = 0 Row = 422, Col = 124, Data = 8aecbe15
|
# tb_core.u_sdram32 : at time 42627.0 ns WRITE: Bank = 0 Row = 422, Col = 124, Data = 8aecbe15
|
# Status: Burst-No: 7 Write Address: 001a61d4 WriteData: 8aecbe15
|
# Status: Burst-No: 7 Write Address: 001a61d4 WriteData: 8aecbe15
|
# tb_core.u_sdram32 : at time 40967.0 ns WRITE: Bank = 0 Row = 422, Col = 125, Data = 02fbf905
|
# tb_core.u_sdram32 : at time 42637.0 ns WRITE: Bank = 0 Row = 422, Col = 125, Data = 02fbf905
|
# Status: Burst-No: 8 Write Address: 001a61d4 WriteData: 02fbf905
|
# Status: Burst-No: 8 Write Address: 001a61d4 WriteData: 02fbf905
|
# tb_core.u_sdram32 : at time 40977.0 ns WRITE: Bank = 0 Row = 422, Col = 126, Data = 271c434e
|
# tb_core.u_sdram32 : at time 42647.0 ns WRITE: Bank = 0 Row = 422, Col = 126, Data = 271c434e
|
# Status: Burst-No: 9 Write Address: 001a61d4 WriteData: 271c434e
|
# Status: Burst-No: 9 Write Address: 001a61d4 WriteData: 271c434e
|
# tb_core.u_sdram32 : at time 40987.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 42657.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 41037.0 ns AREF : Auto Refresh
|
# tb_core.u_sdram32 : at time 42813.0 ns READ : Bank = 3 Row = 709, Col = 148, Data = 929d5825
|
# tb_core.u_sdram32 : at time 41127.0 ns AREF : Auto Refresh
|
# tb_core.u_sdram32 : at time 42823.0 ns READ : Bank = 3 Row = 709, Col = 149, Data = bc3f8478
|
# tb_core.u_sdram32 : at time 41217.0 ns AREF : Auto Refresh
|
|
# tb_core.u_sdram32 : at time 41307.0 ns AREF : Auto Refresh
|
|
# tb_core.u_sdram32 : at time 41397.0 ns AREF : Auto Refresh
|
|
# tb_core.u_sdram32 : at time 41487.0 ns AREF : Auto Refresh
|
|
# tb_core.u_sdram32 : at time 41617.0 ns ACT : Bank = 3 Row = 709
|
|
# tb_core.u_sdram32 : at time 41683.0 ns READ : Bank = 3 Row = 709, Col = 148, Data = 929d5825
|
|
# tb_core.u_sdram32 : at time 41693.0 ns READ : Bank = 3 Row = 709, Col = 149, Data = bc3f8478
|
|
# READ STATUS: Burst-No: 0 Addr: 002c5e50 Rxd: 929d5825
|
# READ STATUS: Burst-No: 0 Addr: 002c5e50 Rxd: 929d5825
|
# tb_core.u_sdram32 : at time 41703.0 ns READ : Bank = 3 Row = 709, Col = 150, Data = 7b7b89f6
|
# tb_core.u_sdram32 : at time 42833.0 ns READ : Bank = 3 Row = 709, Col = 150, Data = 7b7b89f6
|
# READ STATUS: Burst-No: 1 Addr: 002c5e52 Rxd: bc3f8478
|
# READ STATUS: Burst-No: 1 Addr: 002c5e52 Rxd: bc3f8478
|
# tb_core.u_sdram32 : at time 41713.0 ns READ : Bank = 3 Row = 709, Col = 151, Data = ae23ce5c
|
# tb_core.u_sdram32 : at time 42843.0 ns READ : Bank = 3 Row = 709, Col = 151, Data = ae23ce5c
|
# READ STATUS: Burst-No: 2 Addr: 002c5e54 Rxd: 7b7b89f6
|
# READ STATUS: Burst-No: 2 Addr: 002c5e54 Rxd: 7b7b89f6
|
# tb_core.u_sdram32 : at time 41723.0 ns READ : Bank = 3 Row = 709, Col = 152, Data = 11cc9b23
|
# tb_core.u_sdram32 : at time 42853.0 ns READ : Bank = 3 Row = 709, Col = 152, Data = 11cc9b23
|
# READ STATUS: Burst-No: 3 Addr: 002c5e56 Rxd: ae23ce5c
|
# READ STATUS: Burst-No: 3 Addr: 002c5e56 Rxd: ae23ce5c
|
# tb_core.u_sdram32 : at time 41733.0 ns READ : Bank = 3 Row = 709, Col = 153, Data = 3cb3ab79
|
# tb_core.u_sdram32 : at time 42863.0 ns READ : Bank = 3 Row = 709, Col = 153, Data = 3cb3ab79
|
# READ STATUS: Burst-No: 4 Addr: 002c5e58 Rxd: 11cc9b23
|
# READ STATUS: Burst-No: 4 Addr: 002c5e58 Rxd: 11cc9b23
|
# tb_core.u_sdram32 : at time 41743.0 ns READ : Bank = 3 Row = 709, Col = 154, Data = 644605c8
|
# tb_core.u_sdram32 : at time 42873.0 ns READ : Bank = 3 Row = 709, Col = 154, Data = 644605c8
|
# READ STATUS: Burst-No: 5 Addr: 002c5e5a Rxd: 3cb3ab79
|
# READ STATUS: Burst-No: 5 Addr: 002c5e5a Rxd: 3cb3ab79
|
# tb_core.u_sdram32 : at time 41753.0 ns READ : Bank = 3 Row = 709, Col = 155, Data = ddd146bb
|
# tb_core.u_sdram32 : at time 42883.0 ns READ : Bank = 3 Row = 709, Col = 155, Data = ddd146bb
|
# READ STATUS: Burst-No: 6 Addr: 002c5e5c Rxd: 644605c8
|
# READ STATUS: Burst-No: 6 Addr: 002c5e5c Rxd: 644605c8
|
# tb_core.u_sdram32 : at time 41763.0 ns READ : Bank = 3 Row = 709, Col = 156, Data = 870cee0e
|
# tb_core.u_sdram32 : at time 42893.0 ns READ : Bank = 3 Row = 709, Col = 156, Data = 870cee0e
|
# READ STATUS: Burst-No: 7 Addr: 002c5e5e Rxd: ddd146bb
|
# READ STATUS: Burst-No: 7 Addr: 002c5e5e Rxd: ddd146bb
|
# tb_core.u_sdram32 : at time 41773.0 ns READ : Bank = 3 Row = 709, Col = 157, Data = b9879473
|
# tb_core.u_sdram32 : at time 42903.0 ns READ : Bank = 3 Row = 709, Col = 157, Data = b9879473
|
# tb_core.u_sdram32 : at time 41777.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 42907.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 8 Addr: 002c5e60 Rxd: 870cee0e
|
# READ STATUS: Burst-No: 8 Addr: 002c5e60 Rxd: 870cee0e
|
# tb_core.u_sdram32 : at time 41783.0 ns READ : Bank = 3 Row = 709, Col = 158, Data = 0671030c
|
# tb_core.u_sdram32 : at time 42913.0 ns READ : Bank = 3 Row = 709, Col = 158, Data = 0671030c
|
# READ STATUS: Burst-No: 9 Addr: 002c5e62 Rxd: b9879473
|
# READ STATUS: Burst-No: 9 Addr: 002c5e62 Rxd: b9879473
|
# tb_core.u_sdram32 : at time 41793.0 ns READ : Bank = 3 Row = 709, Col = 159, Data = e70f98ce
|
# tb_core.u_sdram32 : at time 42923.0 ns READ : Bank = 3 Row = 709, Col = 159, Data = e70f98ce
|
# READ STATUS: Burst-No: 10 Addr: 002c5e64 Rxd: 0671030c
|
# READ STATUS: Burst-No: 10 Addr: 002c5e64 Rxd: 0671030c
|
# READ STATUS: Burst-No: 11 Addr: 002c5e66 Rxd: e70f98ce
|
# READ STATUS: Burst-No: 11 Addr: 002c5e66 Rxd: e70f98ce
|
# tb_core.u_sdram32 : at time 41987.0 ns ACT : Bank = 0 Row = 422
|
# tb_core.u_sdram32 : at time 43103.0 ns READ : Bank = 0 Row = 422, Col = 117, Data = 5ca26fb9
|
# tb_core.u_sdram32 : at time 42053.0 ns READ : Bank = 0 Row = 422, Col = 117, Data = 5ca26fb9
|
# tb_core.u_sdram32 : at time 43113.0 ns READ : Bank = 0 Row = 422, Col = 118, Data = d9b8c0b3
|
# tb_core.u_sdram32 : at time 42063.0 ns READ : Bank = 0 Row = 422, Col = 118, Data = d9b8c0b3
|
|
# READ STATUS: Burst-No: 0 Addr: 001a61d4 Rxd: 5ca26fb9
|
# READ STATUS: Burst-No: 0 Addr: 001a61d4 Rxd: 5ca26fb9
|
# tb_core.u_sdram32 : at time 42073.0 ns READ : Bank = 0 Row = 422, Col = 119, Data = 7a4fbff4
|
# tb_core.u_sdram32 : at time 43123.0 ns READ : Bank = 0 Row = 422, Col = 119, Data = 7a4fbff4
|
# READ STATUS: Burst-No: 1 Addr: 001a61d6 Rxd: d9b8c0b3
|
# READ STATUS: Burst-No: 1 Addr: 001a61d6 Rxd: d9b8c0b3
|
# tb_core.u_sdram32 : at time 42083.0 ns READ : Bank = 0 Row = 422, Col = 120, Data = baf4e275
|
# tb_core.u_sdram32 : at time 43133.0 ns READ : Bank = 0 Row = 422, Col = 120, Data = baf4e275
|
# READ STATUS: Burst-No: 2 Addr: 001a61d8 Rxd: 7a4fbff4
|
# READ STATUS: Burst-No: 2 Addr: 001a61d8 Rxd: 7a4fbff4
|
# tb_core.u_sdram32 : at time 42093.0 ns READ : Bank = 0 Row = 422, Col = 121, Data = 066cf10c
|
# tb_core.u_sdram32 : at time 43143.0 ns READ : Bank = 0 Row = 422, Col = 121, Data = 066cf10c
|
# READ STATUS: Burst-No: 3 Addr: 001a61da Rxd: baf4e275
|
# READ STATUS: Burst-No: 3 Addr: 001a61da Rxd: baf4e275
|
# tb_core.u_sdram32 : at time 42103.0 ns READ : Bank = 0 Row = 422, Col = 122, Data = 9cfc7a39
|
# tb_core.u_sdram32 : at time 43153.0 ns READ : Bank = 0 Row = 422, Col = 122, Data = 9cfc7a39
|
# READ STATUS: Burst-No: 4 Addr: 001a61dc Rxd: 066cf10c
|
# READ STATUS: Burst-No: 4 Addr: 001a61dc Rxd: 066cf10c
|
# tb_core.u_sdram32 : at time 42113.0 ns READ : Bank = 0 Row = 422, Col = 123, Data = 01729302
|
# tb_core.u_sdram32 : at time 43163.0 ns READ : Bank = 0 Row = 422, Col = 123, Data = 01729302
|
# READ STATUS: Burst-No: 5 Addr: 001a61de Rxd: 9cfc7a39
|
# READ STATUS: Burst-No: 5 Addr: 001a61de Rxd: 9cfc7a39
|
# tb_core.u_sdram32 : at time 42123.0 ns READ : Bank = 0 Row = 422, Col = 124, Data = 8aecbe15
|
# tb_core.u_sdram32 : at time 43173.0 ns READ : Bank = 0 Row = 422, Col = 124, Data = 8aecbe15
|
# tb_core.u_sdram32 : at time 42127.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 43177.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 6 Addr: 001a61e0 Rxd: 01729302
|
# READ STATUS: Burst-No: 6 Addr: 001a61e0 Rxd: 01729302
|
# tb_core.u_sdram32 : at time 42133.0 ns READ : Bank = 0 Row = 422, Col = 125, Data = 02fbf905
|
# tb_core.u_sdram32 : at time 43183.0 ns READ : Bank = 0 Row = 422, Col = 125, Data = 02fbf905
|
# READ STATUS: Burst-No: 7 Addr: 001a61e2 Rxd: 8aecbe15
|
# READ STATUS: Burst-No: 7 Addr: 001a61e2 Rxd: 8aecbe15
|
# tb_core.u_sdram32 : at time 42143.0 ns READ : Bank = 0 Row = 422, Col = 126, Data = 271c434e
|
# tb_core.u_sdram32 : at time 43193.0 ns READ : Bank = 0 Row = 422, Col = 126, Data = 271c434e
|
# READ STATUS: Burst-No: 8 Addr: 001a61e4 Rxd: 02fbf905
|
# READ STATUS: Burst-No: 8 Addr: 001a61e4 Rxd: 02fbf905
|
# READ STATUS: Burst-No: 9 Addr: 001a61e6 Rxd: 271c434e
|
# READ STATUS: Burst-No: 9 Addr: 001a61e6 Rxd: 271c434e
|
# Write Address: 003f2902, Burst Size: 9
|
# Write Address: 003f2902, Burst Size: 9
|
# tb_core.u_sdram32 : at time 42337.0 ns ACT : Bank = 2 Row = 1010
|
# tb_core.u_sdram32 : at time 43387.0 ns ACT : Bank = 2 Row = 1010
|
# tb_core.u_sdram32 : at time 42377.0 ns WRITE: Bank = 2 Row = 1010, Col = 64, Data = 847fb208
|
# tb_core.u_sdram32 : at time 43427.0 ns WRITE: Bank = 2 Row = 1010, Col = 64, Data = 847fb208
|
# Status: Burst-No: 0 Write Address: 003f2902 WriteData: 847fb208
|
# Status: Burst-No: 0 Write Address: 003f2902 WriteData: 847fb208
|
# tb_core.u_sdram32 : at time 42387.0 ns WRITE: Bank = 2 Row = 1010, Col = 65, Data = 46e7538d
|
# tb_core.u_sdram32 : at time 43437.0 ns WRITE: Bank = 2 Row = 1010, Col = 65, Data = 46e7538d
|
# Status: Burst-No: 1 Write Address: 003f2902 WriteData: 46e7538d
|
# Status: Burst-No: 1 Write Address: 003f2902 WriteData: 46e7538d
|
# tb_core.u_sdram32 : at time 42397.0 ns WRITE: Bank = 2 Row = 1010, Col = 66, Data = d7b48eaf
|
# tb_core.u_sdram32 : at time 43447.0 ns WRITE: Bank = 2 Row = 1010, Col = 66, Data = d7b48eaf
|
# Status: Burst-No: 2 Write Address: 003f2902 WriteData: d7b48eaf
|
# Status: Burst-No: 2 Write Address: 003f2902 WriteData: d7b48eaf
|
# tb_core.u_sdram32 : at time 42407.0 ns WRITE: Bank = 2 Row = 1010, Col = 67, Data = 747331e8
|
# tb_core.u_sdram32 : at time 43457.0 ns WRITE: Bank = 2 Row = 1010, Col = 67, Data = 747331e8
|
# Status: Burst-No: 3 Write Address: 003f2902 WriteData: 747331e8
|
# Status: Burst-No: 3 Write Address: 003f2902 WriteData: 747331e8
|
# tb_core.u_sdram32 : at time 42417.0 ns WRITE: Bank = 2 Row = 1010, Col = 68, Data = 48590990
|
# tb_core.u_sdram32 : at time 43467.0 ns WRITE: Bank = 2 Row = 1010, Col = 68, Data = 48590990
|
# Status: Burst-No: 4 Write Address: 003f2902 WriteData: 48590990
|
# Status: Burst-No: 4 Write Address: 003f2902 WriteData: 48590990
|
# tb_core.u_sdram32 : at time 42427.0 ns WRITE: Bank = 2 Row = 1010, Col = 69, Data = 7af6abf5
|
# tb_core.u_sdram32 : at time 43477.0 ns WRITE: Bank = 2 Row = 1010, Col = 69, Data = 7af6abf5
|
# Status: Burst-No: 5 Write Address: 003f2902 WriteData: 7af6abf5
|
# Status: Burst-No: 5 Write Address: 003f2902 WriteData: 7af6abf5
|
# tb_core.u_sdram32 : at time 42437.0 ns WRITE: Bank = 2 Row = 1010, Col = 70, Data = a620904c
|
# tb_core.u_sdram32 : at time 43487.0 ns WRITE: Bank = 2 Row = 1010, Col = 70, Data = a620904c
|
# Status: Burst-No: 6 Write Address: 003f2902 WriteData: a620904c
|
# Status: Burst-No: 6 Write Address: 003f2902 WriteData: a620904c
|
# tb_core.u_sdram32 : at time 42447.0 ns WRITE: Bank = 2 Row = 1010, Col = 71, Data = 3d82bd7b
|
# tb_core.u_sdram32 : at time 43497.0 ns WRITE: Bank = 2 Row = 1010, Col = 71, Data = 3d82bd7b
|
# Status: Burst-No: 7 Write Address: 003f2902 WriteData: 3d82bd7b
|
# Status: Burst-No: 7 Write Address: 003f2902 WriteData: 3d82bd7b
|
# tb_core.u_sdram32 : at time 42457.0 ns WRITE: Bank = 2 Row = 1010, Col = 72, Data = a005a640
|
# tb_core.u_sdram32 : at time 43507.0 ns WRITE: Bank = 2 Row = 1010, Col = 72, Data = a005a640
|
# Status: Burst-No: 8 Write Address: 003f2902 WriteData: a005a640
|
# Status: Burst-No: 8 Write Address: 003f2902 WriteData: a005a640
|
# tb_core.u_sdram32 : at time 42467.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 43517.0 ns BST : Burst Terminate
|
# Write Address: 00290325, Burst Size: 14
|
# Write Address: 00290325, Burst Size: 14
|
# tb_core.u_sdram32 : at time 42627.0 ns ACT : Bank = 0 Row = 656
|
# tb_core.u_sdram32 : at time 43677.0 ns ACT : Bank = 0 Row = 656
|
# tb_core.u_sdram32 : at time 42667.0 ns WRITE: Bank = 0 Row = 656, Col = 201, Data = b87c1070
|
# tb_core.u_sdram32 : at time 43717.0 ns WRITE: Bank = 0 Row = 656, Col = 201, Data = b87c1070
|
# Status: Burst-No: 0 Write Address: 00290325 WriteData: b87c1070
|
# Status: Burst-No: 0 Write Address: 00290325 WriteData: b87c1070
|
# tb_core.u_sdram32 : at time 42677.0 ns WRITE: Bank = 0 Row = 656, Col = 202, Data = 16cbf92d
|
# tb_core.u_sdram32 : at time 43727.0 ns WRITE: Bank = 0 Row = 656, Col = 202, Data = 16cbf92d
|
# Status: Burst-No: 1 Write Address: 00290325 WriteData: 16cbf92d
|
# Status: Burst-No: 1 Write Address: 00290325 WriteData: 16cbf92d
|
# tb_core.u_sdram32 : at time 42687.0 ns WRITE: Bank = 0 Row = 656, Col = 203, Data = 94ded829
|
# tb_core.u_sdram32 : at time 43737.0 ns WRITE: Bank = 0 Row = 656, Col = 203, Data = 94ded829
|
# Status: Burst-No: 2 Write Address: 00290325 WriteData: 94ded829
|
# Status: Burst-No: 2 Write Address: 00290325 WriteData: 94ded829
|
# tb_core.u_sdram32 : at time 42697.0 ns WRITE: Bank = 0 Row = 656, Col = 204, Data = 5e2551bc
|
# tb_core.u_sdram32 : at time 43747.0 ns WRITE: Bank = 0 Row = 656, Col = 204, Data = 5e2551bc
|
# Status: Burst-No: 3 Write Address: 00290325 WriteData: 5e2551bc
|
# Status: Burst-No: 3 Write Address: 00290325 WriteData: 5e2551bc
|
# tb_core.u_sdram32 : at time 42707.0 ns WRITE: Bank = 0 Row = 656, Col = 205, Data = 987b0830
|
# tb_core.u_sdram32 : at time 43757.0 ns WRITE: Bank = 0 Row = 656, Col = 205, Data = 987b0830
|
# Status: Burst-No: 4 Write Address: 00290325 WriteData: 987b0830
|
# Status: Burst-No: 4 Write Address: 00290325 WriteData: 987b0830
|
# tb_core.u_sdram32 : at time 42717.0 ns WRITE: Bank = 0 Row = 656, Col = 206, Data = 60272dc0
|
# tb_core.u_sdram32 : at time 43767.0 ns WRITE: Bank = 0 Row = 656, Col = 206, Data = 60272dc0
|
# Status: Burst-No: 5 Write Address: 00290325 WriteData: 60272dc0
|
# Status: Burst-No: 5 Write Address: 00290325 WriteData: 60272dc0
|
# tb_core.u_sdram32 : at time 42727.0 ns WRITE: Bank = 0 Row = 656, Col = 207, Data = 28766950
|
# tb_core.u_sdram32 : at time 43777.0 ns WRITE: Bank = 0 Row = 656, Col = 207, Data = 28766950
|
# Status: Burst-No: 6 Write Address: 00290325 WriteData: 28766950
|
# Status: Burst-No: 6 Write Address: 00290325 WriteData: 28766950
|
# tb_core.u_sdram32 : at time 42737.0 ns WRITE: Bank = 0 Row = 656, Col = 208, Data = d0cf6aa1
|
# tb_core.u_sdram32 : at time 43787.0 ns WRITE: Bank = 0 Row = 656, Col = 208, Data = d0cf6aa1
|
# Status: Burst-No: 7 Write Address: 00290325 WriteData: d0cf6aa1
|
# Status: Burst-No: 7 Write Address: 00290325 WriteData: d0cf6aa1
|
# tb_core.u_sdram32 : at time 42747.0 ns WRITE: Bank = 0 Row = 656, Col = 209, Data = 26bf3f4d
|
# tb_core.u_sdram32 : at time 43797.0 ns WRITE: Bank = 0 Row = 656, Col = 209, Data = 26bf3f4d
|
# Status: Burst-No: 8 Write Address: 00290325 WriteData: 26bf3f4d
|
# Status: Burst-No: 8 Write Address: 00290325 WriteData: 26bf3f4d
|
# tb_core.u_sdram32 : at time 42757.0 ns WRITE: Bank = 0 Row = 656, Col = 210, Data = faf32ef5
|
# tb_core.u_sdram32 : at time 43807.0 ns WRITE: Bank = 0 Row = 656, Col = 210, Data = faf32ef5
|
# Status: Burst-No: 9 Write Address: 00290325 WriteData: faf32ef5
|
# Status: Burst-No: 9 Write Address: 00290325 WriteData: faf32ef5
|
# tb_core.u_sdram32 : at time 42767.0 ns WRITE: Bank = 0 Row = 656, Col = 211, Data = 7a87aff5
|
# tb_core.u_sdram32 : at time 43817.0 ns WRITE: Bank = 0 Row = 656, Col = 211, Data = 7a87aff5
|
# Status: Burst-No: 10 Write Address: 00290325 WriteData: 7a87aff5
|
# Status: Burst-No: 10 Write Address: 00290325 WriteData: 7a87aff5
|
# tb_core.u_sdram32 : at time 42777.0 ns WRITE: Bank = 0 Row = 656, Col = 212, Data = aeeacc5d
|
# tb_core.u_sdram32 : at time 43827.0 ns WRITE: Bank = 0 Row = 656, Col = 212, Data = aeeacc5d
|
# Status: Burst-No: 11 Write Address: 00290325 WriteData: aeeacc5d
|
# Status: Burst-No: 11 Write Address: 00290325 WriteData: aeeacc5d
|
# tb_core.u_sdram32 : at time 42787.0 ns WRITE: Bank = 0 Row = 656, Col = 213, Data = ca481294
|
# tb_core.u_sdram32 : at time 43837.0 ns WRITE: Bank = 0 Row = 656, Col = 213, Data = ca481294
|
# Status: Burst-No: 12 Write Address: 00290325 WriteData: ca481294
|
# Status: Burst-No: 12 Write Address: 00290325 WriteData: ca481294
|
# tb_core.u_sdram32 : at time 42797.0 ns WRITE: Bank = 0 Row = 656, Col = 214, Data = b558a66a
|
# tb_core.u_sdram32 : at time 43847.0 ns WRITE: Bank = 0 Row = 656, Col = 214, Data = b558a66a
|
# Status: Burst-No: 13 Write Address: 00290325 WriteData: b558a66a
|
# Status: Burst-No: 13 Write Address: 00290325 WriteData: b558a66a
|
# tb_core.u_sdram32 : at time 42807.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 43857.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 42963.0 ns READ : Bank = 2 Row = 1010, Col = 64, Data = 847fb208
|
# tb_core.u_sdram32 : at time 44013.0 ns READ : Bank = 2 Row = 1010, Col = 64, Data = 847fb208
|
# tb_core.u_sdram32 : at time 42973.0 ns READ : Bank = 2 Row = 1010, Col = 65, Data = 46e7538d
|
# tb_core.u_sdram32 : at time 44023.0 ns READ : Bank = 2 Row = 1010, Col = 65, Data = 46e7538d
|
# READ STATUS: Burst-No: 0 Addr: 003f2902 Rxd: 847fb208
|
# READ STATUS: Burst-No: 0 Addr: 003f2902 Rxd: 847fb208
|
# tb_core.u_sdram32 : at time 42983.0 ns READ : Bank = 2 Row = 1010, Col = 66, Data = d7b48eaf
|
# tb_core.u_sdram32 : at time 44033.0 ns READ : Bank = 2 Row = 1010, Col = 66, Data = d7b48eaf
|
# READ STATUS: Burst-No: 1 Addr: 003f2904 Rxd: 46e7538d
|
# READ STATUS: Burst-No: 1 Addr: 003f2904 Rxd: 46e7538d
|
# tb_core.u_sdram32 : at time 42993.0 ns READ : Bank = 2 Row = 1010, Col = 67, Data = 747331e8
|
# tb_core.u_sdram32 : at time 44043.0 ns READ : Bank = 2 Row = 1010, Col = 67, Data = 747331e8
|
# READ STATUS: Burst-No: 2 Addr: 003f2906 Rxd: d7b48eaf
|
# READ STATUS: Burst-No: 2 Addr: 003f2906 Rxd: d7b48eaf
|
# tb_core.u_sdram32 : at time 43003.0 ns READ : Bank = 2 Row = 1010, Col = 68, Data = 48590990
|
# tb_core.u_sdram32 : at time 44053.0 ns READ : Bank = 2 Row = 1010, Col = 68, Data = 48590990
|
# READ STATUS: Burst-No: 3 Addr: 003f2908 Rxd: 747331e8
|
# READ STATUS: Burst-No: 3 Addr: 003f2908 Rxd: 747331e8
|
# tb_core.u_sdram32 : at time 43013.0 ns READ : Bank = 2 Row = 1010, Col = 69, Data = 7af6abf5
|
# tb_core.u_sdram32 : at time 44063.0 ns READ : Bank = 2 Row = 1010, Col = 69, Data = 7af6abf5
|
# READ STATUS: Burst-No: 4 Addr: 003f290a Rxd: 48590990
|
# READ STATUS: Burst-No: 4 Addr: 003f290a Rxd: 48590990
|
# tb_core.u_sdram32 : at time 43023.0 ns READ : Bank = 2 Row = 1010, Col = 70, Data = a620904c
|
# tb_core.u_sdram32 : at time 44073.0 ns READ : Bank = 2 Row = 1010, Col = 70, Data = a620904c
|
# tb_core.u_sdram32 : at time 43027.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 44077.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 5 Addr: 003f290c Rxd: 7af6abf5
|
# READ STATUS: Burst-No: 5 Addr: 003f290c Rxd: 7af6abf5
|
# tb_core.u_sdram32 : at time 43033.0 ns READ : Bank = 2 Row = 1010, Col = 71, Data = 3d82bd7b
|
# tb_core.u_sdram32 : at time 44083.0 ns READ : Bank = 2 Row = 1010, Col = 71, Data = 3d82bd7b
|
# READ STATUS: Burst-No: 6 Addr: 003f290e Rxd: a620904c
|
# READ STATUS: Burst-No: 6 Addr: 003f290e Rxd: a620904c
|
# tb_core.u_sdram32 : at time 43043.0 ns READ : Bank = 2 Row = 1010, Col = 72, Data = a005a640
|
# tb_core.u_sdram32 : at time 44093.0 ns READ : Bank = 2 Row = 1010, Col = 72, Data = a005a640
|
# READ STATUS: Burst-No: 7 Addr: 003f2910 Rxd: 3d82bd7b
|
# READ STATUS: Burst-No: 7 Addr: 003f2910 Rxd: 3d82bd7b
|
# READ STATUS: Burst-No: 8 Addr: 003f2912 Rxd: a005a640
|
# READ STATUS: Burst-No: 8 Addr: 003f2912 Rxd: a005a640
|
# tb_core.u_sdram32 : at time 43223.0 ns READ : Bank = 0 Row = 656, Col = 201, Data = b87c1070
|
# tb_core.u_sdram32 : at time 44273.0 ns READ : Bank = 0 Row = 656, Col = 201, Data = b87c1070
|
# tb_core.u_sdram32 : at time 43233.0 ns READ : Bank = 0 Row = 656, Col = 202, Data = 16cbf92d
|
# tb_core.u_sdram32 : at time 44283.0 ns READ : Bank = 0 Row = 656, Col = 202, Data = 16cbf92d
|
# READ STATUS: Burst-No: 0 Addr: 00290325 Rxd: b87c1070
|
# READ STATUS: Burst-No: 0 Addr: 00290325 Rxd: b87c1070
|
# tb_core.u_sdram32 : at time 43243.0 ns READ : Bank = 0 Row = 656, Col = 203, Data = 94ded829
|
# tb_core.u_sdram32 : at time 44293.0 ns READ : Bank = 0 Row = 656, Col = 203, Data = 94ded829
|
# READ STATUS: Burst-No: 1 Addr: 00290327 Rxd: 16cbf92d
|
# READ STATUS: Burst-No: 1 Addr: 00290327 Rxd: 16cbf92d
|
# tb_core.u_sdram32 : at time 43253.0 ns READ : Bank = 0 Row = 656, Col = 204, Data = 5e2551bc
|
# tb_core.u_sdram32 : at time 44303.0 ns READ : Bank = 0 Row = 656, Col = 204, Data = 5e2551bc
|
# READ STATUS: Burst-No: 2 Addr: 00290329 Rxd: 94ded829
|
# READ STATUS: Burst-No: 2 Addr: 00290329 Rxd: 94ded829
|
# tb_core.u_sdram32 : at time 43263.0 ns READ : Bank = 0 Row = 656, Col = 205, Data = 987b0830
|
# tb_core.u_sdram32 : at time 44313.0 ns READ : Bank = 0 Row = 656, Col = 205, Data = 987b0830
|
# READ STATUS: Burst-No: 3 Addr: 0029032b Rxd: 5e2551bc
|
# READ STATUS: Burst-No: 3 Addr: 0029032b Rxd: 5e2551bc
|
# tb_core.u_sdram32 : at time 43273.0 ns READ : Bank = 0 Row = 656, Col = 206, Data = 60272dc0
|
# tb_core.u_sdram32 : at time 44323.0 ns READ : Bank = 0 Row = 656, Col = 206, Data = 60272dc0
|
# READ STATUS: Burst-No: 4 Addr: 0029032d Rxd: 987b0830
|
# READ STATUS: Burst-No: 4 Addr: 0029032d Rxd: 987b0830
|
# tb_core.u_sdram32 : at time 43283.0 ns READ : Bank = 0 Row = 656, Col = 207, Data = 28766950
|
# tb_core.u_sdram32 : at time 44333.0 ns READ : Bank = 0 Row = 656, Col = 207, Data = 28766950
|
# READ STATUS: Burst-No: 5 Addr: 0029032f Rxd: 60272dc0
|
# READ STATUS: Burst-No: 5 Addr: 0029032f Rxd: 60272dc0
|
# tb_core.u_sdram32 : at time 43293.0 ns READ : Bank = 0 Row = 656, Col = 208, Data = d0cf6aa1
|
# tb_core.u_sdram32 : at time 44343.0 ns READ : Bank = 0 Row = 656, Col = 208, Data = d0cf6aa1
|
# READ STATUS: Burst-No: 6 Addr: 00290331 Rxd: 28766950
|
# READ STATUS: Burst-No: 6 Addr: 00290331 Rxd: 28766950
|
# tb_core.u_sdram32 : at time 43303.0 ns READ : Bank = 0 Row = 656, Col = 209, Data = 26bf3f4d
|
# tb_core.u_sdram32 : at time 44353.0 ns READ : Bank = 0 Row = 656, Col = 209, Data = 26bf3f4d
|
# READ STATUS: Burst-No: 7 Addr: 00290333 Rxd: d0cf6aa1
|
# READ STATUS: Burst-No: 7 Addr: 00290333 Rxd: d0cf6aa1
|
# tb_core.u_sdram32 : at time 43313.0 ns READ : Bank = 0 Row = 656, Col = 210, Data = faf32ef5
|
# tb_core.u_sdram32 : at time 44363.0 ns READ : Bank = 0 Row = 656, Col = 210, Data = faf32ef5
|
# READ STATUS: Burst-No: 8 Addr: 00290335 Rxd: 26bf3f4d
|
# READ STATUS: Burst-No: 8 Addr: 00290335 Rxd: 26bf3f4d
|
# tb_core.u_sdram32 : at time 43323.0 ns READ : Bank = 0 Row = 656, Col = 211, Data = 7a87aff5
|
# tb_core.u_sdram32 : at time 44373.0 ns READ : Bank = 0 Row = 656, Col = 211, Data = 7a87aff5
|
# READ STATUS: Burst-No: 9 Addr: 00290337 Rxd: faf32ef5
|
# READ STATUS: Burst-No: 9 Addr: 00290337 Rxd: faf32ef5
|
# tb_core.u_sdram32 : at time 43333.0 ns READ : Bank = 0 Row = 656, Col = 212, Data = aeeacc5d
|
# tb_core.u_sdram32 : at time 44383.0 ns READ : Bank = 0 Row = 656, Col = 212, Data = aeeacc5d
|
# tb_core.u_sdram32 : at time 43337.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 44387.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 10 Addr: 00290339 Rxd: 7a87aff5
|
# READ STATUS: Burst-No: 10 Addr: 00290339 Rxd: 7a87aff5
|
# tb_core.u_sdram32 : at time 43343.0 ns READ : Bank = 0 Row = 656, Col = 213, Data = ca481294
|
# tb_core.u_sdram32 : at time 44393.0 ns READ : Bank = 0 Row = 656, Col = 213, Data = ca481294
|
# READ STATUS: Burst-No: 11 Addr: 0029033b Rxd: aeeacc5d
|
# READ STATUS: Burst-No: 11 Addr: 0029033b Rxd: aeeacc5d
|
# tb_core.u_sdram32 : at time 43353.0 ns READ : Bank = 0 Row = 656, Col = 214, Data = b558a66a
|
# tb_core.u_sdram32 : at time 44403.0 ns READ : Bank = 0 Row = 656, Col = 214, Data = b558a66a
|
# READ STATUS: Burst-No: 12 Addr: 0029033d Rxd: ca481294
|
# READ STATUS: Burst-No: 12 Addr: 0029033d Rxd: ca481294
|
# READ STATUS: Burst-No: 13 Addr: 0029033f Rxd: b558a66a
|
# READ STATUS: Burst-No: 13 Addr: 0029033f Rxd: b558a66a
|
# Write Address: 002065bc, Burst Size: 9
|
# Write Address: 002065bc, Burst Size: 9
|
# tb_core.u_sdram32 : at time 43547.0 ns ACT : Bank = 1 Row = 518
|
# tb_core.u_sdram32 : at time 44597.0 ns ACT : Bank = 1 Row = 518
|
# tb_core.u_sdram32 : at time 43587.0 ns WRITE: Bank = 1 Row = 518, Col = 111, Data = cf309c9e
|
# tb_core.u_sdram32 : at time 44637.0 ns WRITE: Bank = 1 Row = 518, Col = 111, Data = cf309c9e
|
# Status: Burst-No: 0 Write Address: 002065bc WriteData: cf309c9e
|
# Status: Burst-No: 0 Write Address: 002065bc WriteData: cf309c9e
|
# tb_core.u_sdram32 : at time 43597.0 ns WRITE: Bank = 1 Row = 518, Col = 112, Data = fd7906fa
|
# tb_core.u_sdram32 : at time 44647.0 ns WRITE: Bank = 1 Row = 518, Col = 112, Data = fd7906fa
|
# Status: Burst-No: 1 Write Address: 002065bc WriteData: fd7906fa
|
# Status: Burst-No: 1 Write Address: 002065bc WriteData: fd7906fa
|
# tb_core.u_sdram32 : at time 43607.0 ns WRITE: Bank = 1 Row = 518, Col = 113, Data = 23400b46
|
# tb_core.u_sdram32 : at time 44657.0 ns WRITE: Bank = 1 Row = 518, Col = 113, Data = 23400b46
|
# Status: Burst-No: 2 Write Address: 002065bc WriteData: 23400b46
|
# Status: Burst-No: 2 Write Address: 002065bc WriteData: 23400b46
|
# tb_core.u_sdram32 : at time 43617.0 ns WRITE: Bank = 1 Row = 518, Col = 114, Data = 83fa6407
|
# tb_core.u_sdram32 : at time 44667.0 ns WRITE: Bank = 1 Row = 518, Col = 114, Data = 83fa6407
|
# Status: Burst-No: 3 Write Address: 002065bc WriteData: 83fa6407
|
# Status: Burst-No: 3 Write Address: 002065bc WriteData: 83fa6407
|
# tb_core.u_sdram32 : at time 43627.0 ns WRITE: Bank = 1 Row = 518, Col = 115, Data = c9cbbc93
|
# tb_core.u_sdram32 : at time 44677.0 ns WRITE: Bank = 1 Row = 518, Col = 115, Data = c9cbbc93
|
# Status: Burst-No: 4 Write Address: 002065bc WriteData: c9cbbc93
|
# Status: Burst-No: 4 Write Address: 002065bc WriteData: c9cbbc93
|
# tb_core.u_sdram32 : at time 43637.0 ns WRITE: Bank = 1 Row = 518, Col = 116, Data = aada7455
|
# tb_core.u_sdram32 : at time 44687.0 ns WRITE: Bank = 1 Row = 518, Col = 116, Data = aada7455
|
# Status: Burst-No: 5 Write Address: 002065bc WriteData: aada7455
|
# Status: Burst-No: 5 Write Address: 002065bc WriteData: aada7455
|
# tb_core.u_sdram32 : at time 43647.0 ns WRITE: Bank = 1 Row = 518, Col = 117, Data = 5bd3dbb7
|
# tb_core.u_sdram32 : at time 44697.0 ns WRITE: Bank = 1 Row = 518, Col = 117, Data = 5bd3dbb7
|
# Status: Burst-No: 6 Write Address: 002065bc WriteData: 5bd3dbb7
|
# Status: Burst-No: 6 Write Address: 002065bc WriteData: 5bd3dbb7
|
# tb_core.u_sdram32 : at time 43657.0 ns WRITE: Bank = 1 Row = 518, Col = 118, Data = 22d5f145
|
# tb_core.u_sdram32 : at time 44707.0 ns WRITE: Bank = 1 Row = 518, Col = 118, Data = 22d5f145
|
# Status: Burst-No: 7 Write Address: 002065bc WriteData: 22d5f145
|
# Status: Burst-No: 7 Write Address: 002065bc WriteData: 22d5f145
|
# tb_core.u_sdram32 : at time 43667.0 ns WRITE: Bank = 1 Row = 518, Col = 119, Data = b1800a63
|
# tb_core.u_sdram32 : at time 44717.0 ns WRITE: Bank = 1 Row = 518, Col = 119, Data = b1800a63
|
# Status: Burst-No: 8 Write Address: 002065bc WriteData: b1800a63
|
# Status: Burst-No: 8 Write Address: 002065bc WriteData: b1800a63
|
# tb_core.u_sdram32 : at time 43677.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 44727.0 ns BST : Burst Terminate
|
# Write Address: 0013e059, Burst Size: 7
|
# Write Address: 0013e059, Burst Size: 7
|
# tb_core.u_sdram32 : at time 43837.0 ns ACT : Bank = 0 Row = 318
|
# tb_core.u_sdram32 : at time 44887.0 ns ACT : Bank = 0 Row = 318
|
# tb_core.u_sdram32 : at time 43877.0 ns WRITE: Bank = 0 Row = 318, Col = 22, Data = b4497668
|
# tb_core.u_sdram32 : at time 44927.0 ns WRITE: Bank = 0 Row = 318, Col = 22, Data = b4497668
|
# Status: Burst-No: 0 Write Address: 0013e059 WriteData: b4497668
|
# Status: Burst-No: 0 Write Address: 0013e059 WriteData: b4497668
|
# tb_core.u_sdram32 : at time 43887.0 ns WRITE: Bank = 0 Row = 318, Col = 23, Data = 8f63e41e
|
# tb_core.u_sdram32 : at time 44937.0 ns WRITE: Bank = 0 Row = 318, Col = 23, Data = 8f63e41e
|
# Status: Burst-No: 1 Write Address: 0013e059 WriteData: 8f63e41e
|
# Status: Burst-No: 1 Write Address: 0013e059 WriteData: 8f63e41e
|
# tb_core.u_sdram32 : at time 43897.0 ns WRITE: Bank = 0 Row = 318, Col = 24, Data = c838f490
|
# tb_core.u_sdram32 : at time 44947.0 ns WRITE: Bank = 0 Row = 318, Col = 24, Data = c838f490
|
# Status: Burst-No: 2 Write Address: 0013e059 WriteData: c838f490
|
# Status: Burst-No: 2 Write Address: 0013e059 WriteData: c838f490
|
# tb_core.u_sdram32 : at time 43907.0 ns WRITE: Bank = 0 Row = 318, Col = 25, Data = 2d19a55a
|
# tb_core.u_sdram32 : at time 44957.0 ns WRITE: Bank = 0 Row = 318, Col = 25, Data = 2d19a55a
|
# Status: Burst-No: 3 Write Address: 0013e059 WriteData: 2d19a55a
|
# Status: Burst-No: 3 Write Address: 0013e059 WriteData: 2d19a55a
|
# tb_core.u_sdram32 : at time 43917.0 ns WRITE: Bank = 0 Row = 318, Col = 26, Data = 0e43851c
|
# tb_core.u_sdram32 : at time 44967.0 ns WRITE: Bank = 0 Row = 318, Col = 26, Data = 0e43851c
|
# Status: Burst-No: 4 Write Address: 0013e059 WriteData: 0e43851c
|
# Status: Burst-No: 4 Write Address: 0013e059 WriteData: 0e43851c
|
# tb_core.u_sdram32 : at time 43927.0 ns WRITE: Bank = 0 Row = 318, Col = 27, Data = 5c9967b9
|
# tb_core.u_sdram32 : at time 44977.0 ns WRITE: Bank = 0 Row = 318, Col = 27, Data = 5c9967b9
|
# Status: Burst-No: 5 Write Address: 0013e059 WriteData: 5c9967b9
|
# Status: Burst-No: 5 Write Address: 0013e059 WriteData: 5c9967b9
|
# tb_core.u_sdram32 : at time 43937.0 ns WRITE: Bank = 0 Row = 318, Col = 28, Data = 55861fab
|
# tb_core.u_sdram32 : at time 44987.0 ns WRITE: Bank = 0 Row = 318, Col = 28, Data = 55861fab
|
# Status: Burst-No: 6 Write Address: 0013e059 WriteData: 55861fab
|
# Status: Burst-No: 6 Write Address: 0013e059 WriteData: 55861fab
|
# tb_core.u_sdram32 : at time 43947.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 44997.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 44103.0 ns READ : Bank = 1 Row = 518, Col = 111, Data = cf309c9e
|
# tb_core.u_sdram32 : at time 45153.0 ns READ : Bank = 1 Row = 518, Col = 111, Data = cf309c9e
|
# tb_core.u_sdram32 : at time 44113.0 ns READ : Bank = 1 Row = 518, Col = 112, Data = fd7906fa
|
# tb_core.u_sdram32 : at time 45163.0 ns READ : Bank = 1 Row = 518, Col = 112, Data = fd7906fa
|
# READ STATUS: Burst-No: 0 Addr: 002065bc Rxd: cf309c9e
|
# READ STATUS: Burst-No: 0 Addr: 002065bc Rxd: cf309c9e
|
# tb_core.u_sdram32 : at time 44123.0 ns READ : Bank = 1 Row = 518, Col = 113, Data = 23400b46
|
# tb_core.u_sdram32 : at time 45173.0 ns READ : Bank = 1 Row = 518, Col = 113, Data = 23400b46
|
# READ STATUS: Burst-No: 1 Addr: 002065be Rxd: fd7906fa
|
# READ STATUS: Burst-No: 1 Addr: 002065be Rxd: fd7906fa
|
# tb_core.u_sdram32 : at time 44133.0 ns READ : Bank = 1 Row = 518, Col = 114, Data = 83fa6407
|
# tb_core.u_sdram32 : at time 45183.0 ns READ : Bank = 1 Row = 518, Col = 114, Data = 83fa6407
|
# READ STATUS: Burst-No: 2 Addr: 002065c0 Rxd: 23400b46
|
# READ STATUS: Burst-No: 2 Addr: 002065c0 Rxd: 23400b46
|
# tb_core.u_sdram32 : at time 44143.0 ns READ : Bank = 1 Row = 518, Col = 115, Data = c9cbbc93
|
# tb_core.u_sdram32 : at time 45193.0 ns READ : Bank = 1 Row = 518, Col = 115, Data = c9cbbc93
|
# READ STATUS: Burst-No: 3 Addr: 002065c2 Rxd: 83fa6407
|
# READ STATUS: Burst-No: 3 Addr: 002065c2 Rxd: 83fa6407
|
# tb_core.u_sdram32 : at time 44153.0 ns READ : Bank = 1 Row = 518, Col = 116, Data = aada7455
|
# tb_core.u_sdram32 : at time 45203.0 ns READ : Bank = 1 Row = 518, Col = 116, Data = aada7455
|
# READ STATUS: Burst-No: 4 Addr: 002065c4 Rxd: c9cbbc93
|
# READ STATUS: Burst-No: 4 Addr: 002065c4 Rxd: c9cbbc93
|
# tb_core.u_sdram32 : at time 44163.0 ns READ : Bank = 1 Row = 518, Col = 117, Data = 5bd3dbb7
|
# tb_core.u_sdram32 : at time 45213.0 ns READ : Bank = 1 Row = 518, Col = 117, Data = 5bd3dbb7
|
# tb_core.u_sdram32 : at time 44167.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 45217.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 5 Addr: 002065c6 Rxd: aada7455
|
# READ STATUS: Burst-No: 5 Addr: 002065c6 Rxd: aada7455
|
# tb_core.u_sdram32 : at time 44173.0 ns READ : Bank = 1 Row = 518, Col = 118, Data = 22d5f145
|
# tb_core.u_sdram32 : at time 45223.0 ns READ : Bank = 1 Row = 518, Col = 118, Data = 22d5f145
|
# READ STATUS: Burst-No: 6 Addr: 002065c8 Rxd: 5bd3dbb7
|
# READ STATUS: Burst-No: 6 Addr: 002065c8 Rxd: 5bd3dbb7
|
# tb_core.u_sdram32 : at time 44183.0 ns READ : Bank = 1 Row = 518, Col = 119, Data = b1800a63
|
# tb_core.u_sdram32 : at time 45233.0 ns READ : Bank = 1 Row = 518, Col = 119, Data = b1800a63
|
# READ STATUS: Burst-No: 7 Addr: 002065ca Rxd: 22d5f145
|
# READ STATUS: Burst-No: 7 Addr: 002065ca Rxd: 22d5f145
|
# READ STATUS: Burst-No: 8 Addr: 002065cc Rxd: b1800a63
|
# READ STATUS: Burst-No: 8 Addr: 002065cc Rxd: b1800a63
|
# tb_core.u_sdram32 : at time 44363.0 ns READ : Bank = 0 Row = 318, Col = 22, Data = b4497668
|
# tb_core.u_sdram32 : at time 45413.0 ns READ : Bank = 0 Row = 318, Col = 22, Data = b4497668
|
# tb_core.u_sdram32 : at time 44373.0 ns READ : Bank = 0 Row = 318, Col = 23, Data = 8f63e41e
|
# tb_core.u_sdram32 : at time 45423.0 ns READ : Bank = 0 Row = 318, Col = 23, Data = 8f63e41e
|
# READ STATUS: Burst-No: 0 Addr: 0013e059 Rxd: b4497668
|
# READ STATUS: Burst-No: 0 Addr: 0013e059 Rxd: b4497668
|
# tb_core.u_sdram32 : at time 44383.0 ns READ : Bank = 0 Row = 318, Col = 24, Data = c838f490
|
# tb_core.u_sdram32 : at time 45433.0 ns READ : Bank = 0 Row = 318, Col = 24, Data = c838f490
|
# READ STATUS: Burst-No: 1 Addr: 0013e05b Rxd: 8f63e41e
|
# READ STATUS: Burst-No: 1 Addr: 0013e05b Rxd: 8f63e41e
|
# tb_core.u_sdram32 : at time 44393.0 ns READ : Bank = 0 Row = 318, Col = 25, Data = 2d19a55a
|
# tb_core.u_sdram32 : at time 45443.0 ns READ : Bank = 0 Row = 318, Col = 25, Data = 2d19a55a
|
# READ STATUS: Burst-No: 2 Addr: 0013e05d Rxd: c838f490
|
# READ STATUS: Burst-No: 2 Addr: 0013e05d Rxd: c838f490
|
# tb_core.u_sdram32 : at time 44403.0 ns READ : Bank = 0 Row = 318, Col = 26, Data = 0e43851c
|
# tb_core.u_sdram32 : at time 45453.0 ns READ : Bank = 0 Row = 318, Col = 26, Data = 0e43851c
|
# tb_core.u_sdram32 : at time 44407.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 45457.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 3 Addr: 0013e05f Rxd: 2d19a55a
|
# READ STATUS: Burst-No: 3 Addr: 0013e05f Rxd: 2d19a55a
|
# tb_core.u_sdram32 : at time 44413.0 ns READ : Bank = 0 Row = 318, Col = 27, Data = 5c9967b9
|
# tb_core.u_sdram32 : at time 45463.0 ns READ : Bank = 0 Row = 318, Col = 27, Data = 5c9967b9
|
# READ STATUS: Burst-No: 4 Addr: 0013e061 Rxd: 0e43851c
|
# READ STATUS: Burst-No: 4 Addr: 0013e061 Rxd: 0e43851c
|
# tb_core.u_sdram32 : at time 44423.0 ns READ : Bank = 0 Row = 318, Col = 28, Data = 55861fab
|
# tb_core.u_sdram32 : at time 45473.0 ns READ : Bank = 0 Row = 318, Col = 28, Data = 55861fab
|
# READ STATUS: Burst-No: 5 Addr: 0013e063 Rxd: 5c9967b9
|
# READ STATUS: Burst-No: 5 Addr: 0013e063 Rxd: 5c9967b9
|
# READ STATUS: Burst-No: 6 Addr: 0013e065 Rxd: 55861fab
|
# READ STATUS: Burst-No: 6 Addr: 0013e065 Rxd: 55861fab
|
# Write Address: 0026d9d0, Burst Size: 16
|
# Write Address: 0026d9d0, Burst Size: 16
|
# tb_core.u_sdram32 : at time 44617.0 ns ACT : Bank = 2 Row = 621
|
# tb_core.u_sdram32 : at time 45667.0 ns ACT : Bank = 2 Row = 621
|
# tb_core.u_sdram32 : at time 44657.0 ns WRITE: Bank = 2 Row = 621, Col = 116, Data = 6c6a6dd8
|
# tb_core.u_sdram32 : at time 45707.0 ns WRITE: Bank = 2 Row = 621, Col = 116, Data = 6c6a6dd8
|
# Status: Burst-No: 0 Write Address: 0026d9d0 WriteData: 6c6a6dd8
|
# Status: Burst-No: 0 Write Address: 0026d9d0 WriteData: 6c6a6dd8
|
# tb_core.u_sdram32 : at time 44667.0 ns WRITE: Bank = 2 Row = 621, Col = 117, Data = a2cc8845
|
# tb_core.u_sdram32 : at time 45717.0 ns WRITE: Bank = 2 Row = 621, Col = 117, Data = a2cc8845
|
# Status: Burst-No: 1 Write Address: 0026d9d0 WriteData: a2cc8845
|
# Status: Burst-No: 1 Write Address: 0026d9d0 WriteData: a2cc8845
|
# tb_core.u_sdram32 : at time 44677.0 ns WRITE: Bank = 2 Row = 621, Col = 118, Data = 46d6a78d
|
# tb_core.u_sdram32 : at time 45727.0 ns WRITE: Bank = 2 Row = 621, Col = 118, Data = 46d6a78d
|
# Status: Burst-No: 2 Write Address: 0026d9d0 WriteData: 46d6a78d
|
# Status: Burst-No: 2 Write Address: 0026d9d0 WriteData: 46d6a78d
|
# tb_core.u_sdram32 : at time 44687.0 ns WRITE: Bank = 2 Row = 621, Col = 119, Data = 45f3238b
|
# tb_core.u_sdram32 : at time 45737.0 ns WRITE: Bank = 2 Row = 621, Col = 119, Data = 45f3238b
|
# Status: Burst-No: 3 Write Address: 0026d9d0 WriteData: 45f3238b
|
# Status: Burst-No: 3 Write Address: 0026d9d0 WriteData: 45f3238b
|
# tb_core.u_sdram32 : at time 44697.0 ns WRITE: Bank = 2 Row = 621, Col = 120, Data = 7e2491fc
|
# tb_core.u_sdram32 : at time 45747.0 ns WRITE: Bank = 2 Row = 621, Col = 120, Data = 7e2491fc
|
# Status: Burst-No: 4 Write Address: 0026d9d0 WriteData: 7e2491fc
|
# Status: Burst-No: 4 Write Address: 0026d9d0 WriteData: 7e2491fc
|
# tb_core.u_sdram32 : at time 44707.0 ns WRITE: Bank = 2 Row = 621, Col = 121, Data = 6e1e1fdc
|
# tb_core.u_sdram32 : at time 45757.0 ns WRITE: Bank = 2 Row = 621, Col = 121, Data = 6e1e1fdc
|
# Status: Burst-No: 5 Write Address: 0026d9d0 WriteData: 6e1e1fdc
|
# Status: Burst-No: 5 Write Address: 0026d9d0 WriteData: 6e1e1fdc
|
# tb_core.u_sdram32 : at time 44717.0 ns WRITE: Bank = 2 Row = 621, Col = 122, Data = d27f0aa4
|
# tb_core.u_sdram32 : at time 45767.0 ns WRITE: Bank = 2 Row = 621, Col = 122, Data = d27f0aa4
|
# Status: Burst-No: 6 Write Address: 0026d9d0 WriteData: d27f0aa4
|
# Status: Burst-No: 6 Write Address: 0026d9d0 WriteData: d27f0aa4
|
# tb_core.u_sdram32 : at time 44727.0 ns WRITE: Bank = 2 Row = 621, Col = 123, Data = 0c978d19
|
# tb_core.u_sdram32 : at time 45777.0 ns WRITE: Bank = 2 Row = 621, Col = 123, Data = 0c978d19
|
# Status: Burst-No: 7 Write Address: 0026d9d0 WriteData: 0c978d19
|
# Status: Burst-No: 7 Write Address: 0026d9d0 WriteData: 0c978d19
|
# tb_core.u_sdram32 : at time 44737.0 ns WRITE: Bank = 2 Row = 621, Col = 124, Data = 52b533a5
|
# tb_core.u_sdram32 : at time 45787.0 ns WRITE: Bank = 2 Row = 621, Col = 124, Data = 52b533a5
|
# Status: Burst-No: 8 Write Address: 0026d9d0 WriteData: 52b533a5
|
# Status: Burst-No: 8 Write Address: 0026d9d0 WriteData: 52b533a5
|
# tb_core.u_sdram32 : at time 44747.0 ns WRITE: Bank = 2 Row = 621, Col = 125, Data = 9f398e3e
|
# tb_core.u_sdram32 : at time 45797.0 ns WRITE: Bank = 2 Row = 621, Col = 125, Data = 9f398e3e
|
# Status: Burst-No: 9 Write Address: 0026d9d0 WriteData: 9f398e3e
|
# Status: Burst-No: 9 Write Address: 0026d9d0 WriteData: 9f398e3e
|
# tb_core.u_sdram32 : at time 44757.0 ns WRITE: Bank = 2 Row = 621, Col = 126, Data = f98bc0f3
|
# tb_core.u_sdram32 : at time 45807.0 ns WRITE: Bank = 2 Row = 621, Col = 126, Data = f98bc0f3
|
# Status: Burst-No: 10 Write Address: 0026d9d0 WriteData: f98bc0f3
|
# Status: Burst-No: 10 Write Address: 0026d9d0 WriteData: f98bc0f3
|
# tb_core.u_sdram32 : at time 44767.0 ns WRITE: Bank = 2 Row = 621, Col = 127, Data = ac782c58
|
# tb_core.u_sdram32 : at time 45817.0 ns WRITE: Bank = 2 Row = 621, Col = 127, Data = ac782c58
|
# Status: Burst-No: 11 Write Address: 0026d9d0 WriteData: ac782c58
|
# Status: Burst-No: 11 Write Address: 0026d9d0 WriteData: ac782c58
|
# tb_core.u_sdram32 : at time 44777.0 ns WRITE: Bank = 2 Row = 621, Col = 128, Data = 62056bc4
|
# tb_core.u_sdram32 : at time 45827.0 ns WRITE: Bank = 2 Row = 621, Col = 128, Data = 62056bc4
|
# Status: Burst-No: 12 Write Address: 0026d9d0 WriteData: 62056bc4
|
# Status: Burst-No: 12 Write Address: 0026d9d0 WriteData: 62056bc4
|
# tb_core.u_sdram32 : at time 44787.0 ns WRITE: Bank = 2 Row = 621, Col = 129, Data = 2e36435c
|
# tb_core.u_sdram32 : at time 45837.0 ns WRITE: Bank = 2 Row = 621, Col = 129, Data = 2e36435c
|
# Status: Burst-No: 13 Write Address: 0026d9d0 WriteData: 2e36435c
|
# Status: Burst-No: 13 Write Address: 0026d9d0 WriteData: 2e36435c
|
# tb_core.u_sdram32 : at time 44797.0 ns WRITE: Bank = 2 Row = 621, Col = 130, Data = 033a4506
|
# tb_core.u_sdram32 : at time 45847.0 ns WRITE: Bank = 2 Row = 621, Col = 130, Data = 033a4506
|
# Status: Burst-No: 14 Write Address: 0026d9d0 WriteData: 033a4506
|
# Status: Burst-No: 14 Write Address: 0026d9d0 WriteData: 033a4506
|
# tb_core.u_sdram32 : at time 44807.0 ns WRITE: Bank = 2 Row = 621, Col = 131, Data = cd1d509a
|
# tb_core.u_sdram32 : at time 45857.0 ns WRITE: Bank = 2 Row = 621, Col = 131, Data = cd1d509a
|
# Status: Burst-No: 15 Write Address: 0026d9d0 WriteData: cd1d509a
|
# Status: Burst-No: 15 Write Address: 0026d9d0 WriteData: cd1d509a
|
# tb_core.u_sdram32 : at time 44817.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 45867.0 ns BST : Burst Terminate
|
# Write Address: 00161918, Burst Size: 6
|
# Write Address: 00161918, Burst Size: 6
|
# tb_core.u_sdram32 : at time 44977.0 ns ACT : Bank = 2 Row = 353
|
# tb_core.u_sdram32 : at time 46027.0 ns ACT : Bank = 2 Row = 353
|
# tb_core.u_sdram32 : at time 45017.0 ns WRITE: Bank = 2 Row = 353, Col = 70, Data = 5515d1aa
|
# tb_core.u_sdram32 : at time 46067.0 ns WRITE: Bank = 2 Row = 353, Col = 70, Data = 5515d1aa
|
# Status: Burst-No: 0 Write Address: 00161918 WriteData: 5515d1aa
|
# Status: Burst-No: 0 Write Address: 00161918 WriteData: 5515d1aa
|
# tb_core.u_sdram32 : at time 45027.0 ns WRITE: Bank = 2 Row = 353, Col = 71, Data = 0d12031a
|
# tb_core.u_sdram32 : at time 46077.0 ns WRITE: Bank = 2 Row = 353, Col = 71, Data = 0d12031a
|
# Status: Burst-No: 1 Write Address: 00161918 WriteData: 0d12031a
|
# Status: Burst-No: 1 Write Address: 00161918 WriteData: 0d12031a
|
# tb_core.u_sdram32 : at time 45037.0 ns WRITE: Bank = 2 Row = 353, Col = 72, Data = 61dbd5c3
|
# tb_core.u_sdram32 : at time 46087.0 ns WRITE: Bank = 2 Row = 353, Col = 72, Data = 61dbd5c3
|
# Status: Burst-No: 2 Write Address: 00161918 WriteData: 61dbd5c3
|
# Status: Burst-No: 2 Write Address: 00161918 WriteData: 61dbd5c3
|
# tb_core.u_sdram32 : at time 45047.0 ns WRITE: Bank = 2 Row = 353, Col = 73, Data = 5934e9b2
|
# tb_core.u_sdram32 : at time 46097.0 ns WRITE: Bank = 2 Row = 353, Col = 73, Data = 5934e9b2
|
# Status: Burst-No: 3 Write Address: 00161918 WriteData: 5934e9b2
|
# Status: Burst-No: 3 Write Address: 00161918 WriteData: 5934e9b2
|
# tb_core.u_sdram32 : at time 45057.0 ns WRITE: Bank = 2 Row = 353, Col = 74, Data = 0633630c
|
# tb_core.u_sdram32 : at time 46107.0 ns WRITE: Bank = 2 Row = 353, Col = 74, Data = 0633630c
|
# Status: Burst-No: 4 Write Address: 00161918 WriteData: 0633630c
|
# Status: Burst-No: 4 Write Address: 00161918 WriteData: 0633630c
|
# tb_core.u_sdram32 : at time 45067.0 ns WRITE: Bank = 2 Row = 353, Col = 75, Data = f4f00ee9
|
# tb_core.u_sdram32 : at time 46117.0 ns WRITE: Bank = 2 Row = 353, Col = 75, Data = f4f00ee9
|
# Status: Burst-No: 5 Write Address: 00161918 WriteData: f4f00ee9
|
# Status: Burst-No: 5 Write Address: 00161918 WriteData: f4f00ee9
|
# tb_core.u_sdram32 : at time 45077.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 46127.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 45237.0 ns ACT : Bank = 2 Row = 621
|
# tb_core.u_sdram32 : at time 46287.0 ns ACT : Bank = 2 Row = 621
|
# tb_core.u_sdram32 : at time 45303.0 ns READ : Bank = 2 Row = 621, Col = 116, Data = 6c6a6dd8
|
# tb_core.u_sdram32 : at time 46353.0 ns READ : Bank = 2 Row = 621, Col = 116, Data = 6c6a6dd8
|
# tb_core.u_sdram32 : at time 45313.0 ns READ : Bank = 2 Row = 621, Col = 117, Data = a2cc8845
|
# tb_core.u_sdram32 : at time 46363.0 ns READ : Bank = 2 Row = 621, Col = 117, Data = a2cc8845
|
# READ STATUS: Burst-No: 0 Addr: 0026d9d0 Rxd: 6c6a6dd8
|
# READ STATUS: Burst-No: 0 Addr: 0026d9d0 Rxd: 6c6a6dd8
|
# tb_core.u_sdram32 : at time 45323.0 ns READ : Bank = 2 Row = 621, Col = 118, Data = 46d6a78d
|
# tb_core.u_sdram32 : at time 46373.0 ns READ : Bank = 2 Row = 621, Col = 118, Data = 46d6a78d
|
# READ STATUS: Burst-No: 1 Addr: 0026d9d2 Rxd: a2cc8845
|
# READ STATUS: Burst-No: 1 Addr: 0026d9d2 Rxd: a2cc8845
|
# tb_core.u_sdram32 : at time 45333.0 ns READ : Bank = 2 Row = 621, Col = 119, Data = 45f3238b
|
# tb_core.u_sdram32 : at time 46383.0 ns READ : Bank = 2 Row = 621, Col = 119, Data = 45f3238b
|
# READ STATUS: Burst-No: 2 Addr: 0026d9d4 Rxd: 46d6a78d
|
# READ STATUS: Burst-No: 2 Addr: 0026d9d4 Rxd: 46d6a78d
|
# tb_core.u_sdram32 : at time 45343.0 ns READ : Bank = 2 Row = 621, Col = 120, Data = 7e2491fc
|
# tb_core.u_sdram32 : at time 46393.0 ns READ : Bank = 2 Row = 621, Col = 120, Data = 7e2491fc
|
# READ STATUS: Burst-No: 3 Addr: 0026d9d6 Rxd: 45f3238b
|
# READ STATUS: Burst-No: 3 Addr: 0026d9d6 Rxd: 45f3238b
|
# tb_core.u_sdram32 : at time 45353.0 ns READ : Bank = 2 Row = 621, Col = 121, Data = 6e1e1fdc
|
# tb_core.u_sdram32 : at time 46403.0 ns READ : Bank = 2 Row = 621, Col = 121, Data = 6e1e1fdc
|
# READ STATUS: Burst-No: 4 Addr: 0026d9d8 Rxd: 7e2491fc
|
# READ STATUS: Burst-No: 4 Addr: 0026d9d8 Rxd: 7e2491fc
|
# tb_core.u_sdram32 : at time 45363.0 ns READ : Bank = 2 Row = 621, Col = 122, Data = d27f0aa4
|
# tb_core.u_sdram32 : at time 46413.0 ns READ : Bank = 2 Row = 621, Col = 122, Data = d27f0aa4
|
# READ STATUS: Burst-No: 5 Addr: 0026d9da Rxd: 6e1e1fdc
|
# READ STATUS: Burst-No: 5 Addr: 0026d9da Rxd: 6e1e1fdc
|
# tb_core.u_sdram32 : at time 45373.0 ns READ : Bank = 2 Row = 621, Col = 123, Data = 0c978d19
|
# tb_core.u_sdram32 : at time 46423.0 ns READ : Bank = 2 Row = 621, Col = 123, Data = 0c978d19
|
# READ STATUS: Burst-No: 6 Addr: 0026d9dc Rxd: d27f0aa4
|
# READ STATUS: Burst-No: 6 Addr: 0026d9dc Rxd: d27f0aa4
|
# tb_core.u_sdram32 : at time 45383.0 ns READ : Bank = 2 Row = 621, Col = 124, Data = 52b533a5
|
# tb_core.u_sdram32 : at time 46433.0 ns READ : Bank = 2 Row = 621, Col = 124, Data = 52b533a5
|
# READ STATUS: Burst-No: 7 Addr: 0026d9de Rxd: 0c978d19
|
# READ STATUS: Burst-No: 7 Addr: 0026d9de Rxd: 0c978d19
|
# tb_core.u_sdram32 : at time 45393.0 ns READ : Bank = 2 Row = 621, Col = 125, Data = 9f398e3e
|
# tb_core.u_sdram32 : at time 46443.0 ns READ : Bank = 2 Row = 621, Col = 125, Data = 9f398e3e
|
# READ STATUS: Burst-No: 8 Addr: 0026d9e0 Rxd: 52b533a5
|
# READ STATUS: Burst-No: 8 Addr: 0026d9e0 Rxd: 52b533a5
|
# tb_core.u_sdram32 : at time 45403.0 ns READ : Bank = 2 Row = 621, Col = 126, Data = f98bc0f3
|
# tb_core.u_sdram32 : at time 46453.0 ns READ : Bank = 2 Row = 621, Col = 126, Data = f98bc0f3
|
# READ STATUS: Burst-No: 9 Addr: 0026d9e2 Rxd: 9f398e3e
|
# READ STATUS: Burst-No: 9 Addr: 0026d9e2 Rxd: 9f398e3e
|
# tb_core.u_sdram32 : at time 45413.0 ns READ : Bank = 2 Row = 621, Col = 127, Data = ac782c58
|
# tb_core.u_sdram32 : at time 46463.0 ns READ : Bank = 2 Row = 621, Col = 127, Data = ac782c58
|
# READ STATUS: Burst-No: 10 Addr: 0026d9e4 Rxd: f98bc0f3
|
# READ STATUS: Burst-No: 10 Addr: 0026d9e4 Rxd: f98bc0f3
|
# tb_core.u_sdram32 : at time 45423.0 ns READ : Bank = 2 Row = 621, Col = 128, Data = 62056bc4
|
# tb_core.u_sdram32 : at time 46473.0 ns READ : Bank = 2 Row = 621, Col = 128, Data = 62056bc4
|
# READ STATUS: Burst-No: 11 Addr: 0026d9e6 Rxd: ac782c58
|
# READ STATUS: Burst-No: 11 Addr: 0026d9e6 Rxd: ac782c58
|
# tb_core.u_sdram32 : at time 45433.0 ns READ : Bank = 2 Row = 621, Col = 129, Data = 2e36435c
|
# tb_core.u_sdram32 : at time 46483.0 ns READ : Bank = 2 Row = 621, Col = 129, Data = 2e36435c
|
# tb_core.u_sdram32 : at time 45437.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 46487.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 12 Addr: 0026d9e8 Rxd: 62056bc4
|
# READ STATUS: Burst-No: 12 Addr: 0026d9e8 Rxd: 62056bc4
|
# tb_core.u_sdram32 : at time 45443.0 ns READ : Bank = 2 Row = 621, Col = 130, Data = 033a4506
|
# tb_core.u_sdram32 : at time 46493.0 ns READ : Bank = 2 Row = 621, Col = 130, Data = 033a4506
|
# READ STATUS: Burst-No: 13 Addr: 0026d9ea Rxd: 2e36435c
|
# READ STATUS: Burst-No: 13 Addr: 0026d9ea Rxd: 2e36435c
|
# tb_core.u_sdram32 : at time 45453.0 ns READ : Bank = 2 Row = 621, Col = 131, Data = cd1d509a
|
# tb_core.u_sdram32 : at time 46503.0 ns READ : Bank = 2 Row = 621, Col = 131, Data = cd1d509a
|
# READ STATUS: Burst-No: 14 Addr: 0026d9ec Rxd: 033a4506
|
# READ STATUS: Burst-No: 14 Addr: 0026d9ec Rxd: 033a4506
|
# READ STATUS: Burst-No: 15 Addr: 0026d9ee Rxd: cd1d509a
|
# READ STATUS: Burst-No: 15 Addr: 0026d9ee Rxd: cd1d509a
|
# tb_core.u_sdram32 : at time 45647.0 ns ACT : Bank = 2 Row = 353
|
# tb_core.u_sdram32 : at time 46697.0 ns ACT : Bank = 2 Row = 353
|
# tb_core.u_sdram32 : at time 45713.0 ns READ : Bank = 2 Row = 353, Col = 70, Data = 5515d1aa
|
# tb_core.u_sdram32 : at time 46763.0 ns READ : Bank = 2 Row = 353, Col = 70, Data = 5515d1aa
|
# tb_core.u_sdram32 : at time 45723.0 ns READ : Bank = 2 Row = 353, Col = 71, Data = 0d12031a
|
# tb_core.u_sdram32 : at time 46773.0 ns READ : Bank = 2 Row = 353, Col = 71, Data = 0d12031a
|
# READ STATUS: Burst-No: 0 Addr: 00161918 Rxd: 5515d1aa
|
# READ STATUS: Burst-No: 0 Addr: 00161918 Rxd: 5515d1aa
|
# tb_core.u_sdram32 : at time 45733.0 ns READ : Bank = 2 Row = 353, Col = 72, Data = 61dbd5c3
|
# tb_core.u_sdram32 : at time 46783.0 ns READ : Bank = 2 Row = 353, Col = 72, Data = 61dbd5c3
|
# READ STATUS: Burst-No: 1 Addr: 0016191a Rxd: 0d12031a
|
# READ STATUS: Burst-No: 1 Addr: 0016191a Rxd: 0d12031a
|
# tb_core.u_sdram32 : at time 45743.0 ns READ : Bank = 2 Row = 353, Col = 73, Data = 5934e9b2
|
# tb_core.u_sdram32 : at time 46793.0 ns READ : Bank = 2 Row = 353, Col = 73, Data = 5934e9b2
|
# tb_core.u_sdram32 : at time 45747.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 46797.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 2 Addr: 0016191c Rxd: 61dbd5c3
|
# READ STATUS: Burst-No: 2 Addr: 0016191c Rxd: 61dbd5c3
|
# tb_core.u_sdram32 : at time 45753.0 ns READ : Bank = 2 Row = 353, Col = 74, Data = 0633630c
|
# tb_core.u_sdram32 : at time 46803.0 ns READ : Bank = 2 Row = 353, Col = 74, Data = 0633630c
|
# READ STATUS: Burst-No: 3 Addr: 0016191e Rxd: 5934e9b2
|
# READ STATUS: Burst-No: 3 Addr: 0016191e Rxd: 5934e9b2
|
# tb_core.u_sdram32 : at time 45763.0 ns READ : Bank = 2 Row = 353, Col = 75, Data = f4f00ee9
|
# tb_core.u_sdram32 : at time 46813.0 ns READ : Bank = 2 Row = 353, Col = 75, Data = f4f00ee9
|
# READ STATUS: Burst-No: 4 Addr: 00161920 Rxd: 0633630c
|
# READ STATUS: Burst-No: 4 Addr: 00161920 Rxd: 0633630c
|
# READ STATUS: Burst-No: 5 Addr: 00161922 Rxd: f4f00ee9
|
# READ STATUS: Burst-No: 5 Addr: 00161922 Rxd: f4f00ee9
|
# Write Address: 001afdc3, Burst Size: 12
|
# Write Address: 001afdc3, Burst Size: 12
|
# tb_core.u_sdram32 : at time 45957.0 ns ACT : Bank = 3 Row = 431
|
# tb_core.u_sdram32 : at time 47007.0 ns ACT : Bank = 3 Row = 431
|
# tb_core.u_sdram32 : at time 45997.0 ns WRITE: Bank = 3 Row = 431, Col = 112, Data = 7c2db9f8
|
# tb_core.u_sdram32 : at time 47047.0 ns WRITE: Bank = 3 Row = 431, Col = 112, Data = 7c2db9f8
|
# Status: Burst-No: 0 Write Address: 001afdc3 WriteData: 7c2db9f8
|
# Status: Burst-No: 0 Write Address: 001afdc3 WriteData: 7c2db9f8
|
# tb_core.u_sdram32 : at time 46007.0 ns WRITE: Bank = 3 Row = 431, Col = 113, Data = 792c03f2
|
# tb_core.u_sdram32 : at time 47057.0 ns WRITE: Bank = 3 Row = 431, Col = 113, Data = 792c03f2
|
# Status: Burst-No: 1 Write Address: 001afdc3 WriteData: 792c03f2
|
# Status: Burst-No: 1 Write Address: 001afdc3 WriteData: 792c03f2
|
# tb_core.u_sdram32 : at time 46017.0 ns WRITE: Bank = 3 Row = 431, Col = 114, Data = 4483ad89
|
# tb_core.u_sdram32 : at time 47067.0 ns WRITE: Bank = 3 Row = 431, Col = 114, Data = 4483ad89
|
# Status: Burst-No: 2 Write Address: 001afdc3 WriteData: 4483ad89
|
# Status: Burst-No: 2 Write Address: 001afdc3 WriteData: 4483ad89
|
# tb_core.u_sdram32 : at time 46027.0 ns WRITE: Bank = 3 Row = 431, Col = 115, Data = 378c736f
|
# tb_core.u_sdram32 : at time 47077.0 ns WRITE: Bank = 3 Row = 431, Col = 115, Data = 378c736f
|
# Status: Burst-No: 3 Write Address: 001afdc3 WriteData: 378c736f
|
# Status: Burst-No: 3 Write Address: 001afdc3 WriteData: 378c736f
|
# tb_core.u_sdram32 : at time 46037.0 ns WRITE: Bank = 3 Row = 431, Col = 116, Data = 0de14b1b
|
# tb_core.u_sdram32 : at time 47087.0 ns WRITE: Bank = 3 Row = 431, Col = 116, Data = 0de14b1b
|
# Status: Burst-No: 4 Write Address: 001afdc3 WriteData: 0de14b1b
|
# Status: Burst-No: 4 Write Address: 001afdc3 WriteData: 0de14b1b
|
# tb_core.u_sdram32 : at time 46047.0 ns WRITE: Bank = 3 Row = 431, Col = 117, Data = d6a128ad
|
# tb_core.u_sdram32 : at time 47097.0 ns WRITE: Bank = 3 Row = 431, Col = 117, Data = d6a128ad
|
# Status: Burst-No: 5 Write Address: 001afdc3 WriteData: d6a128ad
|
# Status: Burst-No: 5 Write Address: 001afdc3 WriteData: d6a128ad
|
# tb_core.u_sdram32 : at time 46057.0 ns WRITE: Bank = 3 Row = 431, Col = 118, Data = 344dc168
|
# tb_core.u_sdram32 : at time 47107.0 ns WRITE: Bank = 3 Row = 431, Col = 118, Data = 344dc168
|
# Status: Burst-No: 6 Write Address: 001afdc3 WriteData: 344dc168
|
# Status: Burst-No: 6 Write Address: 001afdc3 WriteData: 344dc168
|
# tb_core.u_sdram32 : at time 46067.0 ns WRITE: Bank = 3 Row = 431, Col = 119, Data = 92f91225
|
# tb_core.u_sdram32 : at time 47117.0 ns WRITE: Bank = 3 Row = 431, Col = 119, Data = 92f91225
|
# Status: Burst-No: 7 Write Address: 001afdc3 WriteData: 92f91225
|
# Status: Burst-No: 7 Write Address: 001afdc3 WriteData: 92f91225
|
# tb_core.u_sdram32 : at time 46077.0 ns WRITE: Bank = 3 Row = 431, Col = 120, Data = 67e857cf
|
# tb_core.u_sdram32 : at time 47127.0 ns WRITE: Bank = 3 Row = 431, Col = 120, Data = 67e857cf
|
# Status: Burst-No: 8 Write Address: 001afdc3 WriteData: 67e857cf
|
# Status: Burst-No: 8 Write Address: 001afdc3 WriteData: 67e857cf
|
# tb_core.u_sdram32 : at time 46087.0 ns WRITE: Bank = 3 Row = 431, Col = 121, Data = 55dd8dab
|
# tb_core.u_sdram32 : at time 47137.0 ns WRITE: Bank = 3 Row = 431, Col = 121, Data = 55dd8dab
|
# Status: Burst-No: 9 Write Address: 001afdc3 WriteData: 55dd8dab
|
# Status: Burst-No: 9 Write Address: 001afdc3 WriteData: 55dd8dab
|
# tb_core.u_sdram32 : at time 46097.0 ns WRITE: Bank = 3 Row = 431, Col = 122, Data = 8d94d21b
|
# tb_core.u_sdram32 : at time 47147.0 ns WRITE: Bank = 3 Row = 431, Col = 122, Data = 8d94d21b
|
# Status: Burst-No: 10 Write Address: 001afdc3 WriteData: 8d94d21b
|
# Status: Burst-No: 10 Write Address: 001afdc3 WriteData: 8d94d21b
|
# tb_core.u_sdram32 : at time 46107.0 ns WRITE: Bank = 3 Row = 431, Col = 123, Data = c03b3e80
|
# tb_core.u_sdram32 : at time 47157.0 ns WRITE: Bank = 3 Row = 431, Col = 123, Data = c03b3e80
|
# Status: Burst-No: 11 Write Address: 001afdc3 WriteData: c03b3e80
|
# Status: Burst-No: 11 Write Address: 001afdc3 WriteData: c03b3e80
|
# tb_core.u_sdram32 : at time 46117.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 47167.0 ns BST : Burst Terminate
|
# Write Address: 0016d95d, Burst Size: 3
|
# Write Address: 0016d95d, Burst Size: 3
|
# tb_core.u_sdram32 : at time 46277.0 ns ACT : Bank = 2 Row = 365
|
# tb_core.u_sdram32 : at time 47327.0 ns ACT : Bank = 2 Row = 365
|
# tb_core.u_sdram32 : at time 46317.0 ns WRITE: Bank = 2 Row = 365, Col = 87, Data = 82344204
|
# tb_core.u_sdram32 : at time 47367.0 ns WRITE: Bank = 2 Row = 365, Col = 87, Data = 82344204
|
# Status: Burst-No: 0 Write Address: 0016d95d WriteData: 82344204
|
# Status: Burst-No: 0 Write Address: 0016d95d WriteData: 82344204
|
# tb_core.u_sdram32 : at time 46327.0 ns WRITE: Bank = 2 Row = 365, Col = 88, Data = 2ba7a557
|
# tb_core.u_sdram32 : at time 47377.0 ns WRITE: Bank = 2 Row = 365, Col = 88, Data = 2ba7a557
|
# Status: Burst-No: 1 Write Address: 0016d95d WriteData: 2ba7a557
|
# Status: Burst-No: 1 Write Address: 0016d95d WriteData: 2ba7a557
|
# tb_core.u_sdram32 : at time 46337.0 ns WRITE: Bank = 2 Row = 365, Col = 89, Data = 1b368b36
|
# tb_core.u_sdram32 : at time 47387.0 ns WRITE: Bank = 2 Row = 365, Col = 89, Data = 1b368b36
|
# Status: Burst-No: 2 Write Address: 0016d95d WriteData: 1b368b36
|
# Status: Burst-No: 2 Write Address: 0016d95d WriteData: 1b368b36
|
# tb_core.u_sdram32 : at time 46347.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 47397.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 46503.0 ns READ : Bank = 3 Row = 431, Col = 112, Data = 7c2db9f8
|
# tb_core.u_sdram32 : at time 47553.0 ns READ : Bank = 3 Row = 431, Col = 112, Data = 7c2db9f8
|
# tb_core.u_sdram32 : at time 46513.0 ns READ : Bank = 3 Row = 431, Col = 113, Data = 792c03f2
|
# tb_core.u_sdram32 : at time 47563.0 ns READ : Bank = 3 Row = 431, Col = 113, Data = 792c03f2
|
# READ STATUS: Burst-No: 0 Addr: 001afdc3 Rxd: 7c2db9f8
|
# READ STATUS: Burst-No: 0 Addr: 001afdc3 Rxd: 7c2db9f8
|
# tb_core.u_sdram32 : at time 46523.0 ns READ : Bank = 3 Row = 431, Col = 114, Data = 4483ad89
|
# tb_core.u_sdram32 : at time 47573.0 ns READ : Bank = 3 Row = 431, Col = 114, Data = 4483ad89
|
# READ STATUS: Burst-No: 1 Addr: 001afdc5 Rxd: 792c03f2
|
# READ STATUS: Burst-No: 1 Addr: 001afdc5 Rxd: 792c03f2
|
# tb_core.u_sdram32 : at time 46533.0 ns READ : Bank = 3 Row = 431, Col = 115, Data = 378c736f
|
# tb_core.u_sdram32 : at time 47583.0 ns READ : Bank = 3 Row = 431, Col = 115, Data = 378c736f
|
# READ STATUS: Burst-No: 2 Addr: 001afdc7 Rxd: 4483ad89
|
# READ STATUS: Burst-No: 2 Addr: 001afdc7 Rxd: 4483ad89
|
# tb_core.u_sdram32 : at time 46543.0 ns READ : Bank = 3 Row = 431, Col = 116, Data = 0de14b1b
|
# tb_core.u_sdram32 : at time 47593.0 ns READ : Bank = 3 Row = 431, Col = 116, Data = 0de14b1b
|
# READ STATUS: Burst-No: 3 Addr: 001afdc9 Rxd: 378c736f
|
# READ STATUS: Burst-No: 3 Addr: 001afdc9 Rxd: 378c736f
|
# tb_core.u_sdram32 : at time 46553.0 ns READ : Bank = 3 Row = 431, Col = 117, Data = d6a128ad
|
# tb_core.u_sdram32 : at time 47603.0 ns READ : Bank = 3 Row = 431, Col = 117, Data = d6a128ad
|
# READ STATUS: Burst-No: 4 Addr: 001afdcb Rxd: 0de14b1b
|
# READ STATUS: Burst-No: 4 Addr: 001afdcb Rxd: 0de14b1b
|
# tb_core.u_sdram32 : at time 46563.0 ns READ : Bank = 3 Row = 431, Col = 118, Data = 344dc168
|
# tb_core.u_sdram32 : at time 47613.0 ns READ : Bank = 3 Row = 431, Col = 118, Data = 344dc168
|
# READ STATUS: Burst-No: 5 Addr: 001afdcd Rxd: d6a128ad
|
# READ STATUS: Burst-No: 5 Addr: 001afdcd Rxd: d6a128ad
|
# tb_core.u_sdram32 : at time 46573.0 ns READ : Bank = 3 Row = 431, Col = 119, Data = 92f91225
|
# tb_core.u_sdram32 : at time 47623.0 ns READ : Bank = 3 Row = 431, Col = 119, Data = 92f91225
|
# READ STATUS: Burst-No: 6 Addr: 001afdcf Rxd: 344dc168
|
# READ STATUS: Burst-No: 6 Addr: 001afdcf Rxd: 344dc168
|
# tb_core.u_sdram32 : at time 46583.0 ns READ : Bank = 3 Row = 431, Col = 120, Data = 67e857cf
|
# tb_core.u_sdram32 : at time 47633.0 ns READ : Bank = 3 Row = 431, Col = 120, Data = 67e857cf
|
# READ STATUS: Burst-No: 7 Addr: 001afdd1 Rxd: 92f91225
|
# READ STATUS: Burst-No: 7 Addr: 001afdd1 Rxd: 92f91225
|
# tb_core.u_sdram32 : at time 46593.0 ns READ : Bank = 3 Row = 431, Col = 121, Data = 55dd8dab
|
# tb_core.u_sdram32 : at time 47643.0 ns READ : Bank = 3 Row = 431, Col = 121, Data = 55dd8dab
|
# tb_core.u_sdram32 : at time 46597.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 47647.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 8 Addr: 001afdd3 Rxd: 67e857cf
|
# READ STATUS: Burst-No: 8 Addr: 001afdd3 Rxd: 67e857cf
|
# tb_core.u_sdram32 : at time 46603.0 ns READ : Bank = 3 Row = 431, Col = 122, Data = 8d94d21b
|
# tb_core.u_sdram32 : at time 47653.0 ns READ : Bank = 3 Row = 431, Col = 122, Data = 8d94d21b
|
# READ STATUS: Burst-No: 9 Addr: 001afdd5 Rxd: 55dd8dab
|
# READ STATUS: Burst-No: 9 Addr: 001afdd5 Rxd: 55dd8dab
|
# tb_core.u_sdram32 : at time 46613.0 ns READ : Bank = 3 Row = 431, Col = 123, Data = c03b3e80
|
# tb_core.u_sdram32 : at time 47663.0 ns READ : Bank = 3 Row = 431, Col = 123, Data = c03b3e80
|
# READ STATUS: Burst-No: 10 Addr: 001afdd7 Rxd: 8d94d21b
|
# READ STATUS: Burst-No: 10 Addr: 001afdd7 Rxd: 8d94d21b
|
# READ STATUS: Burst-No: 11 Addr: 001afdd9 Rxd: c03b3e80
|
# READ STATUS: Burst-No: 11 Addr: 001afdd9 Rxd: c03b3e80
|
# tb_core.u_sdram32 : at time 46803.0 ns READ : Bank = 2 Row = 365, Col = 87, Data = 82344204
|
# tb_core.u_sdram32 : at time 47853.0 ns READ : Bank = 2 Row = 365, Col = 87, Data = 82344204
|
# tb_core.u_sdram32 : at time 46807.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 47857.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 46813.0 ns READ : Bank = 2 Row = 365, Col = 88, Data = 2ba7a557
|
# tb_core.u_sdram32 : at time 47863.0 ns READ : Bank = 2 Row = 365, Col = 88, Data = 2ba7a557
|
# READ STATUS: Burst-No: 0 Addr: 0016d95d Rxd: 82344204
|
# READ STATUS: Burst-No: 0 Addr: 0016d95d Rxd: 82344204
|
# tb_core.u_sdram32 : at time 46823.0 ns READ : Bank = 2 Row = 365, Col = 89, Data = 1b368b36
|
# tb_core.u_sdram32 : at time 47873.0 ns READ : Bank = 2 Row = 365, Col = 89, Data = 1b368b36
|
# READ STATUS: Burst-No: 1 Addr: 0016d95f Rxd: 2ba7a557
|
# READ STATUS: Burst-No: 1 Addr: 0016d95f Rxd: 2ba7a557
|
# READ STATUS: Burst-No: 2 Addr: 0016d961 Rxd: 1b368b36
|
# READ STATUS: Burst-No: 2 Addr: 0016d961 Rxd: 1b368b36
|
# Write Address: 002a0332, Burst Size: 10
|
# Write Address: 002a0332, Burst Size: 10
|
# tb_core.u_sdram32 : at time 47017.0 ns ACT : Bank = 0 Row = 672
|
# tb_core.u_sdram32 : at time 48067.0 ns ACT : Bank = 0 Row = 672
|
# tb_core.u_sdram32 : at time 47057.0 ns WRITE: Bank = 0 Row = 672, Col = 204, Data = f24baee4
|
# tb_core.u_sdram32 : at time 48107.0 ns WRITE: Bank = 0 Row = 672, Col = 204, Data = f24baee4
|
# Status: Burst-No: 0 Write Address: 002a0332 WriteData: f24baee4
|
# Status: Burst-No: 0 Write Address: 002a0332 WriteData: f24baee4
|
# tb_core.u_sdram32 : at time 47067.0 ns WRITE: Bank = 0 Row = 672, Col = 205, Data = 8b42ec16
|
# tb_core.u_sdram32 : at time 48117.0 ns WRITE: Bank = 0 Row = 672, Col = 205, Data = 8b42ec16
|
# Status: Burst-No: 1 Write Address: 002a0332 WriteData: 8b42ec16
|
# Status: Burst-No: 1 Write Address: 002a0332 WriteData: 8b42ec16
|
# tb_core.u_sdram32 : at time 47077.0 ns WRITE: Bank = 0 Row = 672, Col = 206, Data = d57fecaa
|
# tb_core.u_sdram32 : at time 48127.0 ns WRITE: Bank = 0 Row = 672, Col = 206, Data = d57fecaa
|
# Status: Burst-No: 2 Write Address: 002a0332 WriteData: d57fecaa
|
# Status: Burst-No: 2 Write Address: 002a0332 WriteData: d57fecaa
|
# tb_core.u_sdram32 : at time 47087.0 ns WRITE: Bank = 0 Row = 672, Col = 207, Data = 605065c0
|
# tb_core.u_sdram32 : at time 48137.0 ns WRITE: Bank = 0 Row = 672, Col = 207, Data = 605065c0
|
# Status: Burst-No: 3 Write Address: 002a0332 WriteData: 605065c0
|
# Status: Burst-No: 3 Write Address: 002a0332 WriteData: 605065c0
|
# tb_core.u_sdram32 : at time 47097.0 ns WRITE: Bank = 0 Row = 672, Col = 208, Data = 9759882e
|
# tb_core.u_sdram32 : at time 48147.0 ns WRITE: Bank = 0 Row = 672, Col = 208, Data = 9759882e
|
# Status: Burst-No: 4 Write Address: 002a0332 WriteData: 9759882e
|
# Status: Burst-No: 4 Write Address: 002a0332 WriteData: 9759882e
|
# tb_core.u_sdram32 : at time 47107.0 ns WRITE: Bank = 0 Row = 672, Col = 209, Data = 4665378c
|
# tb_core.u_sdram32 : at time 48157.0 ns WRITE: Bank = 0 Row = 672, Col = 209, Data = 4665378c
|
# Status: Burst-No: 5 Write Address: 002a0332 WriteData: 4665378c
|
# Status: Burst-No: 5 Write Address: 002a0332 WriteData: 4665378c
|
# tb_core.u_sdram32 : at time 47117.0 ns WRITE: Bank = 0 Row = 672, Col = 210, Data = b8c0c271
|
# tb_core.u_sdram32 : at time 48167.0 ns WRITE: Bank = 0 Row = 672, Col = 210, Data = b8c0c271
|
# Status: Burst-No: 6 Write Address: 002a0332 WriteData: b8c0c271
|
# Status: Burst-No: 6 Write Address: 002a0332 WriteData: b8c0c271
|
# tb_core.u_sdram32 : at time 47127.0 ns WRITE: Bank = 0 Row = 672, Col = 211, Data = 7dfe8ffb
|
# tb_core.u_sdram32 : at time 48177.0 ns WRITE: Bank = 0 Row = 672, Col = 211, Data = 7dfe8ffb
|
# Status: Burst-No: 7 Write Address: 002a0332 WriteData: 7dfe8ffb
|
# Status: Burst-No: 7 Write Address: 002a0332 WriteData: 7dfe8ffb
|
# tb_core.u_sdram32 : at time 47137.0 ns WRITE: Bank = 0 Row = 672, Col = 212, Data = 5e5421bc
|
# tb_core.u_sdram32 : at time 48187.0 ns WRITE: Bank = 0 Row = 672, Col = 212, Data = 5e5421bc
|
# Status: Burst-No: 8 Write Address: 002a0332 WriteData: 5e5421bc
|
# Status: Burst-No: 8 Write Address: 002a0332 WriteData: 5e5421bc
|
# tb_core.u_sdram32 : at time 47147.0 ns WRITE: Bank = 0 Row = 672, Col = 213, Data = ee7068dc
|
# tb_core.u_sdram32 : at time 48197.0 ns WRITE: Bank = 0 Row = 672, Col = 213, Data = ee7068dc
|
# Status: Burst-No: 9 Write Address: 002a0332 WriteData: ee7068dc
|
# Status: Burst-No: 9 Write Address: 002a0332 WriteData: ee7068dc
|
# tb_core.u_sdram32 : at time 47157.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 48207.0 ns BST : Burst Terminate
|
# Write Address: 002c5717, Burst Size: 2
|
# Write Address: 002c5717, Burst Size: 2
|
# tb_core.u_sdram32 : at time 47317.0 ns ACT : Bank = 1 Row = 709
|
# tb_core.u_sdram32 : at time 48367.0 ns ACT : Bank = 1 Row = 709
|
# tb_core.u_sdram32 : at time 47357.0 ns WRITE: Bank = 1 Row = 709, Col = 197, Data = 75fb21eb
|
# tb_core.u_sdram32 : at time 48407.0 ns WRITE: Bank = 1 Row = 709, Col = 197, Data = 75fb21eb
|
# Status: Burst-No: 0 Write Address: 002c5717 WriteData: 75fb21eb
|
# Status: Burst-No: 0 Write Address: 002c5717 WriteData: 75fb21eb
|
# tb_core.u_sdram32 : at time 47367.0 ns WRITE: Bank = 1 Row = 709, Col = 198, Data = 5a9d3bb5
|
# tb_core.u_sdram32 : at time 48417.0 ns WRITE: Bank = 1 Row = 709, Col = 198, Data = 5a9d3bb5
|
# Status: Burst-No: 1 Write Address: 002c5717 WriteData: 5a9d3bb5
|
# Status: Burst-No: 1 Write Address: 002c5717 WriteData: 5a9d3bb5
|
# tb_core.u_sdram32 : at time 47377.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 48427.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 47523.0 ns READ : Bank = 0 Row = 672, Col = 204, Data = f24baee4
|
# tb_core.u_sdram32 : at time 48573.0 ns READ : Bank = 0 Row = 672, Col = 204, Data = f24baee4
|
# tb_core.u_sdram32 : at time 47533.0 ns READ : Bank = 0 Row = 672, Col = 205, Data = 8b42ec16
|
# tb_core.u_sdram32 : at time 48583.0 ns READ : Bank = 0 Row = 672, Col = 205, Data = 8b42ec16
|
# READ STATUS: Burst-No: 0 Addr: 002a0332 Rxd: f24baee4
|
# READ STATUS: Burst-No: 0 Addr: 002a0332 Rxd: f24baee4
|
# tb_core.u_sdram32 : at time 47543.0 ns READ : Bank = 0 Row = 672, Col = 206, Data = d57fecaa
|
# tb_core.u_sdram32 : at time 48593.0 ns READ : Bank = 0 Row = 672, Col = 206, Data = d57fecaa
|
# READ STATUS: Burst-No: 1 Addr: 002a0334 Rxd: 8b42ec16
|
# READ STATUS: Burst-No: 1 Addr: 002a0334 Rxd: 8b42ec16
|
# tb_core.u_sdram32 : at time 47553.0 ns READ : Bank = 0 Row = 672, Col = 207, Data = 605065c0
|
# tb_core.u_sdram32 : at time 48603.0 ns READ : Bank = 0 Row = 672, Col = 207, Data = 605065c0
|
# READ STATUS: Burst-No: 2 Addr: 002a0336 Rxd: d57fecaa
|
# READ STATUS: Burst-No: 2 Addr: 002a0336 Rxd: d57fecaa
|
# tb_core.u_sdram32 : at time 47563.0 ns READ : Bank = 0 Row = 672, Col = 208, Data = 9759882e
|
# tb_core.u_sdram32 : at time 48613.0 ns READ : Bank = 0 Row = 672, Col = 208, Data = 9759882e
|
# READ STATUS: Burst-No: 3 Addr: 002a0338 Rxd: 605065c0
|
# READ STATUS: Burst-No: 3 Addr: 002a0338 Rxd: 605065c0
|
# tb_core.u_sdram32 : at time 47573.0 ns READ : Bank = 0 Row = 672, Col = 209, Data = 4665378c
|
# tb_core.u_sdram32 : at time 48623.0 ns READ : Bank = 0 Row = 672, Col = 209, Data = 4665378c
|
# READ STATUS: Burst-No: 4 Addr: 002a033a Rxd: 9759882e
|
# READ STATUS: Burst-No: 4 Addr: 002a033a Rxd: 9759882e
|
# tb_core.u_sdram32 : at time 47583.0 ns READ : Bank = 0 Row = 672, Col = 210, Data = b8c0c271
|
# tb_core.u_sdram32 : at time 48633.0 ns READ : Bank = 0 Row = 672, Col = 210, Data = b8c0c271
|
# READ STATUS: Burst-No: 5 Addr: 002a033c Rxd: 4665378c
|
# READ STATUS: Burst-No: 5 Addr: 002a033c Rxd: 4665378c
|
# tb_core.u_sdram32 : at time 47593.0 ns READ : Bank = 0 Row = 672, Col = 211, Data = 7dfe8ffb
|
# tb_core.u_sdram32 : at time 48643.0 ns READ : Bank = 0 Row = 672, Col = 211, Data = 7dfe8ffb
|
# tb_core.u_sdram32 : at time 47597.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 48647.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 6 Addr: 002a033e Rxd: b8c0c271
|
# READ STATUS: Burst-No: 6 Addr: 002a033e Rxd: b8c0c271
|
# tb_core.u_sdram32 : at time 47603.0 ns READ : Bank = 0 Row = 672, Col = 212, Data = 5e5421bc
|
# tb_core.u_sdram32 : at time 48653.0 ns READ : Bank = 0 Row = 672, Col = 212, Data = 5e5421bc
|
# READ STATUS: Burst-No: 7 Addr: 002a0340 Rxd: 7dfe8ffb
|
# READ STATUS: Burst-No: 7 Addr: 002a0340 Rxd: 7dfe8ffb
|
# tb_core.u_sdram32 : at time 47613.0 ns READ : Bank = 0 Row = 672, Col = 213, Data = ee7068dc
|
# tb_core.u_sdram32 : at time 48663.0 ns READ : Bank = 0 Row = 672, Col = 213, Data = ee7068dc
|
# READ STATUS: Burst-No: 8 Addr: 002a0342 Rxd: 5e5421bc
|
# READ STATUS: Burst-No: 8 Addr: 002a0342 Rxd: 5e5421bc
|
# READ STATUS: Burst-No: 9 Addr: 002a0344 Rxd: ee7068dc
|
# READ STATUS: Burst-No: 9 Addr: 002a0344 Rxd: ee7068dc
|
# tb_core.u_sdram32 : at time 47797.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 48847.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 47803.0 ns READ : Bank = 1 Row = 709, Col = 197, Data = 75fb21eb
|
# tb_core.u_sdram32 : at time 48853.0 ns READ : Bank = 1 Row = 709, Col = 197, Data = 75fb21eb
|
# tb_core.u_sdram32 : at time 47813.0 ns READ : Bank = 1 Row = 709, Col = 198, Data = 5a9d3bb5
|
# tb_core.u_sdram32 : at time 48863.0 ns READ : Bank = 1 Row = 709, Col = 198, Data = 5a9d3bb5
|
# READ STATUS: Burst-No: 0 Addr: 002c5717 Rxd: 75fb21eb
|
# READ STATUS: Burst-No: 0 Addr: 002c5717 Rxd: 75fb21eb
|
# READ STATUS: Burst-No: 1 Addr: 002c5719 Rxd: 5a9d3bb5
|
# READ STATUS: Burst-No: 1 Addr: 002c5719 Rxd: 5a9d3bb5
|
# Write Address: 003d2e89, Burst Size: 16
|
# Write Address: 003d2e89, Burst Size: 16
|
# tb_core.u_sdram32 : at time 48007.0 ns ACT : Bank = 3 Row = 978
|
# tb_core.u_sdram32 : at time 49057.0 ns ACT : Bank = 3 Row = 978
|
# tb_core.u_sdram32 : at time 48047.0 ns WRITE: Bank = 3 Row = 978, Col = 162, Data = dff6f6bf
|
# tb_core.u_sdram32 : at time 49097.0 ns WRITE: Bank = 3 Row = 978, Col = 162, Data = dff6f6bf
|
# Status: Burst-No: 0 Write Address: 003d2e89 WriteData: dff6f6bf
|
# Status: Burst-No: 0 Write Address: 003d2e89 WriteData: dff6f6bf
|
# tb_core.u_sdram32 : at time 48057.0 ns WRITE: Bank = 3 Row = 978, Col = 163, Data = d8462ab0
|
# tb_core.u_sdram32 : at time 49107.0 ns WRITE: Bank = 3 Row = 978, Col = 163, Data = d8462ab0
|
# Status: Burst-No: 1 Write Address: 003d2e89 WriteData: d8462ab0
|
# Status: Burst-No: 1 Write Address: 003d2e89 WriteData: d8462ab0
|
# tb_core.u_sdram32 : at time 48067.0 ns WRITE: Bank = 3 Row = 978, Col = 164, Data = e9b49ad3
|
# tb_core.u_sdram32 : at time 49117.0 ns WRITE: Bank = 3 Row = 978, Col = 164, Data = e9b49ad3
|
# Status: Burst-No: 2 Write Address: 003d2e89 WriteData: e9b49ad3
|
# Status: Burst-No: 2 Write Address: 003d2e89 WriteData: e9b49ad3
|
# tb_core.u_sdram32 : at time 48077.0 ns WRITE: Bank = 3 Row = 978, Col = 165, Data = eb1d02d6
|
# tb_core.u_sdram32 : at time 49127.0 ns WRITE: Bank = 3 Row = 978, Col = 165, Data = eb1d02d6
|
# Status: Burst-No: 3 Write Address: 003d2e89 WriteData: eb1d02d6
|
# Status: Burst-No: 3 Write Address: 003d2e89 WriteData: eb1d02d6
|
# tb_core.u_sdram32 : at time 48087.0 ns WRITE: Bank = 3 Row = 978, Col = 166, Data = c144cc82
|
# tb_core.u_sdram32 : at time 49137.0 ns WRITE: Bank = 3 Row = 978, Col = 166, Data = c144cc82
|
# Status: Burst-No: 4 Write Address: 003d2e89 WriteData: c144cc82
|
# Status: Burst-No: 4 Write Address: 003d2e89 WriteData: c144cc82
|
# tb_core.u_sdram32 : at time 48097.0 ns WRITE: Bank = 3 Row = 978, Col = 167, Data = 0d63751a
|
# tb_core.u_sdram32 : at time 49147.0 ns WRITE: Bank = 3 Row = 978, Col = 167, Data = 0d63751a
|
# Status: Burst-No: 5 Write Address: 003d2e89 WriteData: 0d63751a
|
# Status: Burst-No: 5 Write Address: 003d2e89 WriteData: 0d63751a
|
# tb_core.u_sdram32 : at time 48107.0 ns WRITE: Bank = 3 Row = 978, Col = 168, Data = 38e6a771
|
# tb_core.u_sdram32 : at time 49157.0 ns WRITE: Bank = 3 Row = 978, Col = 168, Data = 38e6a771
|
# Status: Burst-No: 6 Write Address: 003d2e89 WriteData: 38e6a771
|
# Status: Burst-No: 6 Write Address: 003d2e89 WriteData: 38e6a771
|
# tb_core.u_sdram32 : at time 48117.0 ns WRITE: Bank = 3 Row = 978, Col = 169, Data = eb8804d7
|
# tb_core.u_sdram32 : at time 49167.0 ns WRITE: Bank = 3 Row = 978, Col = 169, Data = eb8804d7
|
# Status: Burst-No: 7 Write Address: 003d2e89 WriteData: eb8804d7
|
# Status: Burst-No: 7 Write Address: 003d2e89 WriteData: eb8804d7
|
# tb_core.u_sdram32 : at time 48127.0 ns WRITE: Bank = 3 Row = 978, Col = 170, Data = 87628e0e
|
# tb_core.u_sdram32 : at time 49177.0 ns WRITE: Bank = 3 Row = 978, Col = 170, Data = 87628e0e
|
# Status: Burst-No: 8 Write Address: 003d2e89 WriteData: 87628e0e
|
# Status: Burst-No: 8 Write Address: 003d2e89 WriteData: 87628e0e
|
# tb_core.u_sdram32 : at time 48137.0 ns WRITE: Bank = 3 Row = 978, Col = 171, Data = f8c714f1
|
# tb_core.u_sdram32 : at time 49187.0 ns WRITE: Bank = 3 Row = 978, Col = 171, Data = f8c714f1
|
# Status: Burst-No: 9 Write Address: 003d2e89 WriteData: f8c714f1
|
# Status: Burst-No: 9 Write Address: 003d2e89 WriteData: f8c714f1
|
# tb_core.u_sdram32 : at time 48147.0 ns WRITE: Bank = 3 Row = 978, Col = 172, Data = 66861dcd
|
# tb_core.u_sdram32 : at time 49197.0 ns WRITE: Bank = 3 Row = 978, Col = 172, Data = 66861dcd
|
# Status: Burst-No: 10 Write Address: 003d2e89 WriteData: 66861dcd
|
# Status: Burst-No: 10 Write Address: 003d2e89 WriteData: 66861dcd
|
# tb_core.u_sdram32 : at time 48157.0 ns WRITE: Bank = 3 Row = 978, Col = 173, Data = 02bd4305
|
# tb_core.u_sdram32 : at time 49207.0 ns WRITE: Bank = 3 Row = 978, Col = 173, Data = 02bd4305
|
# Status: Burst-No: 11 Write Address: 003d2e89 WriteData: 02bd4305
|
# Status: Burst-No: 11 Write Address: 003d2e89 WriteData: 02bd4305
|
# tb_core.u_sdram32 : at time 48167.0 ns WRITE: Bank = 3 Row = 978, Col = 174, Data = 0e3aeb1c
|
# tb_core.u_sdram32 : at time 49217.0 ns WRITE: Bank = 3 Row = 978, Col = 174, Data = 0e3aeb1c
|
# Status: Burst-No: 12 Write Address: 003d2e89 WriteData: 0e3aeb1c
|
# Status: Burst-No: 12 Write Address: 003d2e89 WriteData: 0e3aeb1c
|
# tb_core.u_sdram32 : at time 48177.0 ns WRITE: Bank = 3 Row = 978, Col = 175, Data = 4c18c798
|
# tb_core.u_sdram32 : at time 49227.0 ns WRITE: Bank = 3 Row = 978, Col = 175, Data = 4c18c798
|
# Status: Burst-No: 13 Write Address: 003d2e89 WriteData: 4c18c798
|
# Status: Burst-No: 13 Write Address: 003d2e89 WriteData: 4c18c798
|
# tb_core.u_sdram32 : at time 48187.0 ns WRITE: Bank = 3 Row = 978, Col = 176, Data = f67088ec
|
# tb_core.u_sdram32 : at time 49237.0 ns WRITE: Bank = 3 Row = 978, Col = 176, Data = f67088ec
|
# Status: Burst-No: 14 Write Address: 003d2e89 WriteData: f67088ec
|
# Status: Burst-No: 14 Write Address: 003d2e89 WriteData: f67088ec
|
# tb_core.u_sdram32 : at time 48197.0 ns WRITE: Bank = 3 Row = 978, Col = 177, Data = 9541d62a
|
# tb_core.u_sdram32 : at time 49247.0 ns WRITE: Bank = 3 Row = 978, Col = 177, Data = 9541d62a
|
# Status: Burst-No: 15 Write Address: 003d2e89 WriteData: 9541d62a
|
# Status: Burst-No: 15 Write Address: 003d2e89 WriteData: 9541d62a
|
# tb_core.u_sdram32 : at time 48207.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 49257.0 ns BST : Burst Terminate
|
# Write Address: 00114a65, Burst Size: 8
|
# Write Address: 00114a65, Burst Size: 8
|
# tb_core.u_sdram32 : at time 48367.0 ns ACT : Bank = 2 Row = 276
|
# tb_core.u_sdram32 : at time 49417.0 ns ACT : Bank = 2 Row = 276
|
# tb_core.u_sdram32 : at time 48407.0 ns WRITE: Bank = 2 Row = 276, Col = 153, Data = 81fa3603
|
# tb_core.u_sdram32 : at time 49457.0 ns WRITE: Bank = 2 Row = 276, Col = 153, Data = 81fa3603
|
# Status: Burst-No: 0 Write Address: 00114a65 WriteData: 81fa3603
|
# Status: Burst-No: 0 Write Address: 00114a65 WriteData: 81fa3603
|
# tb_core.u_sdram32 : at time 48417.0 ns WRITE: Bank = 2 Row = 276, Col = 154, Data = ff729efe
|
# tb_core.u_sdram32 : at time 49467.0 ns WRITE: Bank = 2 Row = 276, Col = 154, Data = ff729efe
|
# Status: Burst-No: 1 Write Address: 00114a65 WriteData: ff729efe
|
# Status: Burst-No: 1 Write Address: 00114a65 WriteData: ff729efe
|
# tb_core.u_sdram32 : at time 48427.0 ns WRITE: Bank = 2 Row = 276, Col = 155, Data = feaddcfd
|
# tb_core.u_sdram32 : at time 49477.0 ns WRITE: Bank = 2 Row = 276, Col = 155, Data = feaddcfd
|
# Status: Burst-No: 2 Write Address: 00114a65 WriteData: feaddcfd
|
# Status: Burst-No: 2 Write Address: 00114a65 WriteData: feaddcfd
|
# tb_core.u_sdram32 : at time 48437.0 ns WRITE: Bank = 2 Row = 276, Col = 156, Data = 9f7a0e3e
|
# tb_core.u_sdram32 : at time 49487.0 ns WRITE: Bank = 2 Row = 276, Col = 156, Data = 9f7a0e3e
|
# Status: Burst-No: 3 Write Address: 00114a65 WriteData: 9f7a0e3e
|
# Status: Burst-No: 3 Write Address: 00114a65 WriteData: 9f7a0e3e
|
# tb_core.u_sdram32 : at time 48447.0 ns WRITE: Bank = 2 Row = 276, Col = 157, Data = f43a34e8
|
# tb_core.u_sdram32 : at time 49497.0 ns WRITE: Bank = 2 Row = 276, Col = 157, Data = f43a34e8
|
# Status: Burst-No: 4 Write Address: 00114a65 WriteData: f43a34e8
|
# Status: Burst-No: 4 Write Address: 00114a65 WriteData: f43a34e8
|
# tb_core.u_sdram32 : at time 48457.0 ns WRITE: Bank = 2 Row = 276, Col = 158, Data = ba603874
|
# tb_core.u_sdram32 : at time 49507.0 ns WRITE: Bank = 2 Row = 276, Col = 158, Data = ba603874
|
# Status: Burst-No: 5 Write Address: 00114a65 WriteData: ba603874
|
# Status: Burst-No: 5 Write Address: 00114a65 WriteData: ba603874
|
# tb_core.u_sdram32 : at time 48467.0 ns WRITE: Bank = 2 Row = 276, Col = 159, Data = 580989b0
|
# tb_core.u_sdram32 : at time 49517.0 ns WRITE: Bank = 2 Row = 276, Col = 159, Data = 580989b0
|
# Status: Burst-No: 6 Write Address: 00114a65 WriteData: 580989b0
|
# Status: Burst-No: 6 Write Address: 00114a65 WriteData: 580989b0
|
# tb_core.u_sdram32 : at time 48477.0 ns WRITE: Bank = 2 Row = 276, Col = 160, Data = 8361dc06
|
# tb_core.u_sdram32 : at time 49527.0 ns WRITE: Bank = 2 Row = 276, Col = 160, Data = 8361dc06
|
# Status: Burst-No: 7 Write Address: 00114a65 WriteData: 8361dc06
|
# Status: Burst-No: 7 Write Address: 00114a65 WriteData: 8361dc06
|
# tb_core.u_sdram32 : at time 48487.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 49537.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 48643.0 ns READ : Bank = 3 Row = 978, Col = 162, Data = dff6f6bf
|
# tb_core.u_sdram32 : at time 49693.0 ns READ : Bank = 3 Row = 978, Col = 162, Data = dff6f6bf
|
# tb_core.u_sdram32 : at time 48653.0 ns READ : Bank = 3 Row = 978, Col = 163, Data = d8462ab0
|
# tb_core.u_sdram32 : at time 49703.0 ns READ : Bank = 3 Row = 978, Col = 163, Data = d8462ab0
|
# READ STATUS: Burst-No: 0 Addr: 003d2e89 Rxd: dff6f6bf
|
# READ STATUS: Burst-No: 0 Addr: 003d2e89 Rxd: dff6f6bf
|
# tb_core.u_sdram32 : at time 48663.0 ns READ : Bank = 3 Row = 978, Col = 164, Data = e9b49ad3
|
# tb_core.u_sdram32 : at time 49713.0 ns READ : Bank = 3 Row = 978, Col = 164, Data = e9b49ad3
|
# READ STATUS: Burst-No: 1 Addr: 003d2e8b Rxd: d8462ab0
|
# READ STATUS: Burst-No: 1 Addr: 003d2e8b Rxd: d8462ab0
|
# tb_core.u_sdram32 : at time 48673.0 ns READ : Bank = 3 Row = 978, Col = 165, Data = eb1d02d6
|
# tb_core.u_sdram32 : at time 49723.0 ns READ : Bank = 3 Row = 978, Col = 165, Data = eb1d02d6
|
# READ STATUS: Burst-No: 2 Addr: 003d2e8d Rxd: e9b49ad3
|
# READ STATUS: Burst-No: 2 Addr: 003d2e8d Rxd: e9b49ad3
|
# tb_core.u_sdram32 : at time 48683.0 ns READ : Bank = 3 Row = 978, Col = 166, Data = c144cc82
|
# tb_core.u_sdram32 : at time 49733.0 ns READ : Bank = 3 Row = 978, Col = 166, Data = c144cc82
|
# READ STATUS: Burst-No: 3 Addr: 003d2e8f Rxd: eb1d02d6
|
# READ STATUS: Burst-No: 3 Addr: 003d2e8f Rxd: eb1d02d6
|
# tb_core.u_sdram32 : at time 48693.0 ns READ : Bank = 3 Row = 978, Col = 167, Data = 0d63751a
|
# tb_core.u_sdram32 : at time 49743.0 ns READ : Bank = 3 Row = 978, Col = 167, Data = 0d63751a
|
# READ STATUS: Burst-No: 4 Addr: 003d2e91 Rxd: c144cc82
|
# READ STATUS: Burst-No: 4 Addr: 003d2e91 Rxd: c144cc82
|
# tb_core.u_sdram32 : at time 48703.0 ns READ : Bank = 3 Row = 978, Col = 168, Data = 38e6a771
|
# tb_core.u_sdram32 : at time 49753.0 ns READ : Bank = 3 Row = 978, Col = 168, Data = 38e6a771
|
# READ STATUS: Burst-No: 5 Addr: 003d2e93 Rxd: 0d63751a
|
# READ STATUS: Burst-No: 5 Addr: 003d2e93 Rxd: 0d63751a
|
# tb_core.u_sdram32 : at time 48713.0 ns READ : Bank = 3 Row = 978, Col = 169, Data = eb8804d7
|
# tb_core.u_sdram32 : at time 49763.0 ns READ : Bank = 3 Row = 978, Col = 169, Data = eb8804d7
|
# READ STATUS: Burst-No: 6 Addr: 003d2e95 Rxd: 38e6a771
|
# READ STATUS: Burst-No: 6 Addr: 003d2e95 Rxd: 38e6a771
|
# tb_core.u_sdram32 : at time 48723.0 ns READ : Bank = 3 Row = 978, Col = 170, Data = 87628e0e
|
# tb_core.u_sdram32 : at time 49773.0 ns READ : Bank = 3 Row = 978, Col = 170, Data = 87628e0e
|
# READ STATUS: Burst-No: 7 Addr: 003d2e97 Rxd: eb8804d7
|
# READ STATUS: Burst-No: 7 Addr: 003d2e97 Rxd: eb8804d7
|
# tb_core.u_sdram32 : at time 48733.0 ns READ : Bank = 3 Row = 978, Col = 171, Data = f8c714f1
|
# tb_core.u_sdram32 : at time 49783.0 ns READ : Bank = 3 Row = 978, Col = 171, Data = f8c714f1
|
# READ STATUS: Burst-No: 8 Addr: 003d2e99 Rxd: 87628e0e
|
# READ STATUS: Burst-No: 8 Addr: 003d2e99 Rxd: 87628e0e
|
# tb_core.u_sdram32 : at time 48743.0 ns READ : Bank = 3 Row = 978, Col = 172, Data = 66861dcd
|
# tb_core.u_sdram32 : at time 49793.0 ns READ : Bank = 3 Row = 978, Col = 172, Data = 66861dcd
|
# READ STATUS: Burst-No: 9 Addr: 003d2e9b Rxd: f8c714f1
|
# READ STATUS: Burst-No: 9 Addr: 003d2e9b Rxd: f8c714f1
|
# tb_core.u_sdram32 : at time 48753.0 ns READ : Bank = 3 Row = 978, Col = 173, Data = 02bd4305
|
# tb_core.u_sdram32 : at time 49803.0 ns READ : Bank = 3 Row = 978, Col = 173, Data = 02bd4305
|
# READ STATUS: Burst-No: 10 Addr: 003d2e9d Rxd: 66861dcd
|
# READ STATUS: Burst-No: 10 Addr: 003d2e9d Rxd: 66861dcd
|
# tb_core.u_sdram32 : at time 48763.0 ns READ : Bank = 3 Row = 978, Col = 174, Data = 0e3aeb1c
|
# tb_core.u_sdram32 : at time 49813.0 ns READ : Bank = 3 Row = 978, Col = 174, Data = 0e3aeb1c
|
# READ STATUS: Burst-No: 11 Addr: 003d2e9f Rxd: 02bd4305
|
# READ STATUS: Burst-No: 11 Addr: 003d2e9f Rxd: 02bd4305
|
# tb_core.u_sdram32 : at time 48773.0 ns READ : Bank = 3 Row = 978, Col = 175, Data = 4c18c798
|
# tb_core.u_sdram32 : at time 49823.0 ns READ : Bank = 3 Row = 978, Col = 175, Data = 4c18c798
|
# tb_core.u_sdram32 : at time 48777.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 49827.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 12 Addr: 003d2ea1 Rxd: 0e3aeb1c
|
# READ STATUS: Burst-No: 12 Addr: 003d2ea1 Rxd: 0e3aeb1c
|
# tb_core.u_sdram32 : at time 48783.0 ns READ : Bank = 3 Row = 978, Col = 176, Data = f67088ec
|
# tb_core.u_sdram32 : at time 49833.0 ns READ : Bank = 3 Row = 978, Col = 176, Data = f67088ec
|
# READ STATUS: Burst-No: 13 Addr: 003d2ea3 Rxd: 4c18c798
|
# READ STATUS: Burst-No: 13 Addr: 003d2ea3 Rxd: 4c18c798
|
# tb_core.u_sdram32 : at time 48793.0 ns READ : Bank = 3 Row = 978, Col = 177, Data = 9541d62a
|
# tb_core.u_sdram32 : at time 49843.0 ns READ : Bank = 3 Row = 978, Col = 177, Data = 9541d62a
|
# READ STATUS: Burst-No: 14 Addr: 003d2ea5 Rxd: f67088ec
|
# READ STATUS: Burst-No: 14 Addr: 003d2ea5 Rxd: f67088ec
|
# READ STATUS: Burst-No: 15 Addr: 003d2ea7 Rxd: 9541d62a
|
# READ STATUS: Burst-No: 15 Addr: 003d2ea7 Rxd: 9541d62a
|
# tb_core.u_sdram32 : at time 48983.0 ns READ : Bank = 2 Row = 276, Col = 153, Data = 81fa3603
|
# tb_core.u_sdram32 : at time 50033.0 ns READ : Bank = 2 Row = 276, Col = 153, Data = 81fa3603
|
# tb_core.u_sdram32 : at time 48993.0 ns READ : Bank = 2 Row = 276, Col = 154, Data = ff729efe
|
# tb_core.u_sdram32 : at time 50043.0 ns READ : Bank = 2 Row = 276, Col = 154, Data = ff729efe
|
# READ STATUS: Burst-No: 0 Addr: 00114a65 Rxd: 81fa3603
|
# READ STATUS: Burst-No: 0 Addr: 00114a65 Rxd: 81fa3603
|
# tb_core.u_sdram32 : at time 49003.0 ns READ : Bank = 2 Row = 276, Col = 155, Data = feaddcfd
|
# tb_core.u_sdram32 : at time 50053.0 ns READ : Bank = 2 Row = 276, Col = 155, Data = feaddcfd
|
# READ STATUS: Burst-No: 1 Addr: 00114a67 Rxd: ff729efe
|
# READ STATUS: Burst-No: 1 Addr: 00114a67 Rxd: ff729efe
|
# tb_core.u_sdram32 : at time 49013.0 ns READ : Bank = 2 Row = 276, Col = 156, Data = 9f7a0e3e
|
# tb_core.u_sdram32 : at time 50063.0 ns READ : Bank = 2 Row = 276, Col = 156, Data = 9f7a0e3e
|
# READ STATUS: Burst-No: 2 Addr: 00114a69 Rxd: feaddcfd
|
# READ STATUS: Burst-No: 2 Addr: 00114a69 Rxd: feaddcfd
|
# tb_core.u_sdram32 : at time 49023.0 ns READ : Bank = 2 Row = 276, Col = 157, Data = f43a34e8
|
# tb_core.u_sdram32 : at time 50073.0 ns READ : Bank = 2 Row = 276, Col = 157, Data = f43a34e8
|
# READ STATUS: Burst-No: 3 Addr: 00114a6b Rxd: 9f7a0e3e
|
# READ STATUS: Burst-No: 3 Addr: 00114a6b Rxd: 9f7a0e3e
|
# tb_core.u_sdram32 : at time 49033.0 ns READ : Bank = 2 Row = 276, Col = 158, Data = ba603874
|
# tb_core.u_sdram32 : at time 50083.0 ns READ : Bank = 2 Row = 276, Col = 158, Data = ba603874
|
# tb_core.u_sdram32 : at time 49037.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 50087.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 4 Addr: 00114a6d Rxd: f43a34e8
|
# READ STATUS: Burst-No: 4 Addr: 00114a6d Rxd: f43a34e8
|
# tb_core.u_sdram32 : at time 49043.0 ns READ : Bank = 2 Row = 276, Col = 159, Data = 580989b0
|
# tb_core.u_sdram32 : at time 50093.0 ns READ : Bank = 2 Row = 276, Col = 159, Data = 580989b0
|
# READ STATUS: Burst-No: 5 Addr: 00114a6f Rxd: ba603874
|
# READ STATUS: Burst-No: 5 Addr: 00114a6f Rxd: ba603874
|
# tb_core.u_sdram32 : at time 49053.0 ns READ : Bank = 2 Row = 276, Col = 160, Data = 8361dc06
|
# tb_core.u_sdram32 : at time 50103.0 ns READ : Bank = 2 Row = 276, Col = 160, Data = 8361dc06
|
# READ STATUS: Burst-No: 6 Addr: 00114a71 Rxd: 580989b0
|
# READ STATUS: Burst-No: 6 Addr: 00114a71 Rxd: 580989b0
|
# READ STATUS: Burst-No: 7 Addr: 00114a73 Rxd: 8361dc06
|
# READ STATUS: Burst-No: 7 Addr: 00114a73 Rxd: 8361dc06
|
# Write Address: 00164d12, Burst Size: 9
|
# Write Address: 00164d12, Burst Size: 9
|
# tb_core.u_sdram32 : at time 49247.0 ns ACT : Bank = 3 Row = 356
|
# tb_core.u_sdram32 : at time 50297.0 ns ACT : Bank = 3 Row = 356
|
# tb_core.u_sdram32 : at time 49287.0 ns WRITE: Bank = 3 Row = 356, Col = 68, Data = e2ba00c5
|
# tb_core.u_sdram32 : at time 50337.0 ns WRITE: Bank = 3 Row = 356, Col = 68, Data = e2ba00c5
|
# Status: Burst-No: 0 Write Address: 00164d12 WriteData: e2ba00c5
|
# Status: Burst-No: 0 Write Address: 00164d12 WriteData: e2ba00c5
|
# tb_core.u_sdram32 : at time 49297.0 ns WRITE: Bank = 3 Row = 356, Col = 69, Data = ff202efe
|
# tb_core.u_sdram32 : at time 50347.0 ns WRITE: Bank = 3 Row = 356, Col = 69, Data = ff202efe
|
# Status: Burst-No: 1 Write Address: 00164d12 WriteData: ff202efe
|
# Status: Burst-No: 1 Write Address: 00164d12 WriteData: ff202efe
|
# tb_core.u_sdram32 : at time 49307.0 ns WRITE: Bank = 3 Row = 356, Col = 70, Data = 1b0f0d36
|
# tb_core.u_sdram32 : at time 50357.0 ns WRITE: Bank = 3 Row = 356, Col = 70, Data = 1b0f0d36
|
# Status: Burst-No: 2 Write Address: 00164d12 WriteData: 1b0f0d36
|
# Status: Burst-No: 2 Write Address: 00164d12 WriteData: 1b0f0d36
|
# tb_core.u_sdram32 : at time 49317.0 ns WRITE: Bank = 3 Row = 356, Col = 71, Data = 799f09f3
|
# tb_core.u_sdram32 : at time 50367.0 ns WRITE: Bank = 3 Row = 356, Col = 71, Data = 799f09f3
|
# Status: Burst-No: 3 Write Address: 00164d12 WriteData: 799f09f3
|
# Status: Burst-No: 3 Write Address: 00164d12 WriteData: 799f09f3
|
# tb_core.u_sdram32 : at time 49327.0 ns WRITE: Bank = 3 Row = 356, Col = 72, Data = 7dddabfb
|
# tb_core.u_sdram32 : at time 50377.0 ns WRITE: Bank = 3 Row = 356, Col = 72, Data = 7dddabfb
|
# Status: Burst-No: 4 Write Address: 00164d12 WriteData: 7dddabfb
|
# Status: Burst-No: 4 Write Address: 00164d12 WriteData: 7dddabfb
|
# tb_core.u_sdram32 : at time 49337.0 ns WRITE: Bank = 3 Row = 356, Col = 73, Data = b58d7c6b
|
# tb_core.u_sdram32 : at time 50387.0 ns WRITE: Bank = 3 Row = 356, Col = 73, Data = b58d7c6b
|
# Status: Burst-No: 5 Write Address: 00164d12 WriteData: b58d7c6b
|
# Status: Burst-No: 5 Write Address: 00164d12 WriteData: b58d7c6b
|
# tb_core.u_sdram32 : at time 49347.0 ns WRITE: Bank = 3 Row = 356, Col = 74, Data = 0bcbbf17
|
# tb_core.u_sdram32 : at time 50397.0 ns WRITE: Bank = 3 Row = 356, Col = 74, Data = 0bcbbf17
|
# Status: Burst-No: 6 Write Address: 00164d12 WriteData: 0bcbbf17
|
# Status: Burst-No: 6 Write Address: 00164d12 WriteData: 0bcbbf17
|
# tb_core.u_sdram32 : at time 49357.0 ns WRITE: Bank = 3 Row = 356, Col = 75, Data = 87d0360f
|
# tb_core.u_sdram32 : at time 50407.0 ns WRITE: Bank = 3 Row = 356, Col = 75, Data = 87d0360f
|
# Status: Burst-No: 7 Write Address: 00164d12 WriteData: 87d0360f
|
# Status: Burst-No: 7 Write Address: 00164d12 WriteData: 87d0360f
|
# tb_core.u_sdram32 : at time 49367.0 ns WRITE: Bank = 3 Row = 356, Col = 76, Data = 8a47b614
|
# tb_core.u_sdram32 : at time 50417.0 ns WRITE: Bank = 3 Row = 356, Col = 76, Data = 8a47b614
|
# Status: Burst-No: 8 Write Address: 00164d12 WriteData: 8a47b614
|
# Status: Burst-No: 8 Write Address: 00164d12 WriteData: 8a47b614
|
# tb_core.u_sdram32 : at time 49377.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 50427.0 ns BST : Burst Terminate
|
# Write Address: 0000052a, Burst Size: 7
|
# Write Address: 0000052a, Burst Size: 7
|
# tb_core.u_sdram32 : at time 49537.0 ns ACT : Bank = 1 Row = 0
|
# tb_core.u_sdram32 : at time 50587.0 ns ACT : Bank = 1 Row = 0
|
# tb_core.u_sdram32 : at time 49577.0 ns WRITE: Bank = 1 Row = 0, Col = 74, Data = ea7626d4
|
# tb_core.u_sdram32 : at time 50627.0 ns WRITE: Bank = 1 Row = 0, Col = 74, Data = ea7626d4
|
# Status: Burst-No: 0 Write Address: 0000052a WriteData: ea7626d4
|
# Status: Burst-No: 0 Write Address: 0000052a WriteData: ea7626d4
|
# tb_core.u_sdram32 : at time 49587.0 ns WRITE: Bank = 1 Row = 0, Col = 75, Data = e5ac10cb
|
# tb_core.u_sdram32 : at time 50637.0 ns WRITE: Bank = 1 Row = 0, Col = 75, Data = e5ac10cb
|
# Status: Burst-No: 1 Write Address: 0000052a WriteData: e5ac10cb
|
# Status: Burst-No: 1 Write Address: 0000052a WriteData: e5ac10cb
|
# tb_core.u_sdram32 : at time 49597.0 ns WRITE: Bank = 1 Row = 0, Col = 76, Data = b587c26b
|
# tb_core.u_sdram32 : at time 50647.0 ns WRITE: Bank = 1 Row = 0, Col = 76, Data = b587c26b
|
# Status: Burst-No: 2 Write Address: 0000052a WriteData: b587c26b
|
# Status: Burst-No: 2 Write Address: 0000052a WriteData: b587c26b
|
# tb_core.u_sdram32 : at time 49607.0 ns WRITE: Bank = 1 Row = 0, Col = 77, Data = 0277eb04
|
# tb_core.u_sdram32 : at time 50657.0 ns WRITE: Bank = 1 Row = 0, Col = 77, Data = 0277eb04
|
# Status: Burst-No: 3 Write Address: 0000052a WriteData: 0277eb04
|
# Status: Burst-No: 3 Write Address: 0000052a WriteData: 0277eb04
|
# tb_core.u_sdram32 : at time 49617.0 ns WRITE: Bank = 1 Row = 0, Col = 78, Data = fa4832f4
|
# tb_core.u_sdram32 : at time 50667.0 ns WRITE: Bank = 1 Row = 0, Col = 78, Data = fa4832f4
|
# Status: Burst-No: 4 Write Address: 0000052a WriteData: fa4832f4
|
# Status: Burst-No: 4 Write Address: 0000052a WriteData: fa4832f4
|
# tb_core.u_sdram32 : at time 49627.0 ns WRITE: Bank = 1 Row = 0, Col = 79, Data = 468b618d
|
# tb_core.u_sdram32 : at time 50677.0 ns WRITE: Bank = 1 Row = 0, Col = 79, Data = 468b618d
|
# Status: Burst-No: 5 Write Address: 0000052a WriteData: 468b618d
|
# Status: Burst-No: 5 Write Address: 0000052a WriteData: 468b618d
|
# tb_core.u_sdram32 : at time 49637.0 ns WRITE: Bank = 1 Row = 0, Col = 80, Data = f0ea70e1
|
# tb_core.u_sdram32 : at time 50687.0 ns WRITE: Bank = 1 Row = 0, Col = 80, Data = f0ea70e1
|
# Status: Burst-No: 6 Write Address: 0000052a WriteData: f0ea70e1
|
# Status: Burst-No: 6 Write Address: 0000052a WriteData: f0ea70e1
|
# tb_core.u_sdram32 : at time 49647.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 50697.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 49803.0 ns READ : Bank = 3 Row = 356, Col = 68, Data = e2ba00c5
|
# tb_core.u_sdram32 : at time 50853.0 ns READ : Bank = 3 Row = 356, Col = 68, Data = e2ba00c5
|
# tb_core.u_sdram32 : at time 49813.0 ns READ : Bank = 3 Row = 356, Col = 69, Data = ff202efe
|
# tb_core.u_sdram32 : at time 50863.0 ns READ : Bank = 3 Row = 356, Col = 69, Data = ff202efe
|
# READ STATUS: Burst-No: 0 Addr: 00164d12 Rxd: e2ba00c5
|
# READ STATUS: Burst-No: 0 Addr: 00164d12 Rxd: e2ba00c5
|
# tb_core.u_sdram32 : at time 49823.0 ns READ : Bank = 3 Row = 356, Col = 70, Data = 1b0f0d36
|
# tb_core.u_sdram32 : at time 50873.0 ns READ : Bank = 3 Row = 356, Col = 70, Data = 1b0f0d36
|
# READ STATUS: Burst-No: 1 Addr: 00164d14 Rxd: ff202efe
|
# READ STATUS: Burst-No: 1 Addr: 00164d14 Rxd: ff202efe
|
# tb_core.u_sdram32 : at time 49833.0 ns READ : Bank = 3 Row = 356, Col = 71, Data = 799f09f3
|
# tb_core.u_sdram32 : at time 50883.0 ns READ : Bank = 3 Row = 356, Col = 71, Data = 799f09f3
|
# READ STATUS: Burst-No: 2 Addr: 00164d16 Rxd: 1b0f0d36
|
# READ STATUS: Burst-No: 2 Addr: 00164d16 Rxd: 1b0f0d36
|
# tb_core.u_sdram32 : at time 49843.0 ns READ : Bank = 3 Row = 356, Col = 72, Data = 7dddabfb
|
# tb_core.u_sdram32 : at time 50893.0 ns READ : Bank = 3 Row = 356, Col = 72, Data = 7dddabfb
|
# READ STATUS: Burst-No: 3 Addr: 00164d18 Rxd: 799f09f3
|
# READ STATUS: Burst-No: 3 Addr: 00164d18 Rxd: 799f09f3
|
# tb_core.u_sdram32 : at time 49853.0 ns READ : Bank = 3 Row = 356, Col = 73, Data = b58d7c6b
|
# tb_core.u_sdram32 : at time 50903.0 ns READ : Bank = 3 Row = 356, Col = 73, Data = b58d7c6b
|
# READ STATUS: Burst-No: 4 Addr: 00164d1a Rxd: 7dddabfb
|
# READ STATUS: Burst-No: 4 Addr: 00164d1a Rxd: 7dddabfb
|
# tb_core.u_sdram32 : at time 49863.0 ns READ : Bank = 3 Row = 356, Col = 74, Data = 0bcbbf17
|
# tb_core.u_sdram32 : at time 50913.0 ns READ : Bank = 3 Row = 356, Col = 74, Data = 0bcbbf17
|
# tb_core.u_sdram32 : at time 49867.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 50917.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 5 Addr: 00164d1c Rxd: b58d7c6b
|
# READ STATUS: Burst-No: 5 Addr: 00164d1c Rxd: b58d7c6b
|
# tb_core.u_sdram32 : at time 49873.0 ns READ : Bank = 3 Row = 356, Col = 75, Data = 87d0360f
|
# tb_core.u_sdram32 : at time 50923.0 ns READ : Bank = 3 Row = 356, Col = 75, Data = 87d0360f
|
# READ STATUS: Burst-No: 6 Addr: 00164d1e Rxd: 0bcbbf17
|
# READ STATUS: Burst-No: 6 Addr: 00164d1e Rxd: 0bcbbf17
|
# tb_core.u_sdram32 : at time 49883.0 ns READ : Bank = 3 Row = 356, Col = 76, Data = 8a47b614
|
# tb_core.u_sdram32 : at time 50933.0 ns READ : Bank = 3 Row = 356, Col = 76, Data = 8a47b614
|
# READ STATUS: Burst-No: 7 Addr: 00164d20 Rxd: 87d0360f
|
# READ STATUS: Burst-No: 7 Addr: 00164d20 Rxd: 87d0360f
|
# READ STATUS: Burst-No: 8 Addr: 00164d22 Rxd: 8a47b614
|
# READ STATUS: Burst-No: 8 Addr: 00164d22 Rxd: 8a47b614
|
# tb_core.u_sdram32 : at time 50073.0 ns READ : Bank = 1 Row = 0, Col = 74, Data = ea7626d4
|
# tb_core.u_sdram32 : at time 51123.0 ns READ : Bank = 1 Row = 0, Col = 74, Data = ea7626d4
|
# tb_core.u_sdram32 : at time 50083.0 ns READ : Bank = 1 Row = 0, Col = 75, Data = e5ac10cb
|
# tb_core.u_sdram32 : at time 51133.0 ns READ : Bank = 1 Row = 0, Col = 75, Data = e5ac10cb
|
# READ STATUS: Burst-No: 0 Addr: 0000052a Rxd: ea7626d4
|
# READ STATUS: Burst-No: 0 Addr: 0000052a Rxd: ea7626d4
|
# tb_core.u_sdram32 : at time 50093.0 ns READ : Bank = 1 Row = 0, Col = 76, Data = b587c26b
|
# tb_core.u_sdram32 : at time 51143.0 ns READ : Bank = 1 Row = 0, Col = 76, Data = b587c26b
|
# READ STATUS: Burst-No: 1 Addr: 0000052c Rxd: e5ac10cb
|
# READ STATUS: Burst-No: 1 Addr: 0000052c Rxd: e5ac10cb
|
# tb_core.u_sdram32 : at time 50103.0 ns READ : Bank = 1 Row = 0, Col = 77, Data = 0277eb04
|
# tb_core.u_sdram32 : at time 51153.0 ns READ : Bank = 1 Row = 0, Col = 77, Data = 0277eb04
|
# READ STATUS: Burst-No: 2 Addr: 0000052e Rxd: b587c26b
|
# READ STATUS: Burst-No: 2 Addr: 0000052e Rxd: b587c26b
|
# tb_core.u_sdram32 : at time 50113.0 ns READ : Bank = 1 Row = 0, Col = 78, Data = fa4832f4
|
# tb_core.u_sdram32 : at time 51163.0 ns READ : Bank = 1 Row = 0, Col = 78, Data = fa4832f4
|
# tb_core.u_sdram32 : at time 50117.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 51167.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 3 Addr: 00000530 Rxd: 0277eb04
|
# READ STATUS: Burst-No: 3 Addr: 00000530 Rxd: 0277eb04
|
# tb_core.u_sdram32 : at time 50123.0 ns READ : Bank = 1 Row = 0, Col = 79, Data = 468b618d
|
# tb_core.u_sdram32 : at time 51173.0 ns READ : Bank = 1 Row = 0, Col = 79, Data = 468b618d
|
# READ STATUS: Burst-No: 4 Addr: 00000532 Rxd: fa4832f4
|
# READ STATUS: Burst-No: 4 Addr: 00000532 Rxd: fa4832f4
|
# tb_core.u_sdram32 : at time 50133.0 ns READ : Bank = 1 Row = 0, Col = 80, Data = f0ea70e1
|
# tb_core.u_sdram32 : at time 51183.0 ns READ : Bank = 1 Row = 0, Col = 80, Data = f0ea70e1
|
# READ STATUS: Burst-No: 5 Addr: 00000534 Rxd: 468b618d
|
# READ STATUS: Burst-No: 5 Addr: 00000534 Rxd: 468b618d
|
# READ STATUS: Burst-No: 6 Addr: 00000536 Rxd: f0ea70e1
|
# READ STATUS: Burst-No: 6 Addr: 00000536 Rxd: f0ea70e1
|
# Write Address: 0023bd85, Burst Size: 10
|
# Write Address: 0023bd85, Burst Size: 10
|
# tb_core.u_sdram32 : at time 50327.0 ns ACT : Bank = 3 Row = 571
|
# tb_core.u_sdram32 : at time 51377.0 ns ACT : Bank = 3 Row = 571
|
# tb_core.u_sdram32 : at time 50367.0 ns WRITE: Bank = 3 Row = 571, Col = 97, Data = e4df16c9
|
# tb_core.u_sdram32 : at time 51417.0 ns WRITE: Bank = 3 Row = 571, Col = 97, Data = e4df16c9
|
# Status: Burst-No: 0 Write Address: 0023bd85 WriteData: e4df16c9
|
# Status: Burst-No: 0 Write Address: 0023bd85 WriteData: e4df16c9
|
# tb_core.u_sdram32 : at time 50377.0 ns WRITE: Bank = 3 Row = 571, Col = 98, Data = b05f8e60
|
# tb_core.u_sdram32 : at time 51427.0 ns WRITE: Bank = 3 Row = 571, Col = 98, Data = b05f8e60
|
# Status: Burst-No: 1 Write Address: 0023bd85 WriteData: b05f8e60
|
# Status: Burst-No: 1 Write Address: 0023bd85 WriteData: b05f8e60
|
# tb_core.u_sdram32 : at time 50387.0 ns WRITE: Bank = 3 Row = 571, Col = 99, Data = a3643246
|
# tb_core.u_sdram32 : at time 51437.0 ns WRITE: Bank = 3 Row = 571, Col = 99, Data = a3643246
|
# Status: Burst-No: 2 Write Address: 0023bd85 WriteData: a3643246
|
# Status: Burst-No: 2 Write Address: 0023bd85 WriteData: a3643246
|
# tb_core.u_sdram32 : at time 50397.0 ns WRITE: Bank = 3 Row = 571, Col = 100, Data = 1e74cb3c
|
# tb_core.u_sdram32 : at time 51447.0 ns WRITE: Bank = 3 Row = 571, Col = 100, Data = 1e74cb3c
|
# Status: Burst-No: 3 Write Address: 0023bd85 WriteData: 1e74cb3c
|
# Status: Burst-No: 3 Write Address: 0023bd85 WriteData: 1e74cb3c
|
# tb_core.u_sdram32 : at time 50407.0 ns WRITE: Bank = 3 Row = 571, Col = 101, Data = 1b855f37
|
# tb_core.u_sdram32 : at time 51457.0 ns WRITE: Bank = 3 Row = 571, Col = 101, Data = 1b855f37
|
# Status: Burst-No: 4 Write Address: 0023bd85 WriteData: 1b855f37
|
# Status: Burst-No: 4 Write Address: 0023bd85 WriteData: 1b855f37
|
# tb_core.u_sdram32 : at time 50417.0 ns WRITE: Bank = 3 Row = 571, Col = 102, Data = 2c0c5558
|
# tb_core.u_sdram32 : at time 51467.0 ns WRITE: Bank = 3 Row = 571, Col = 102, Data = 2c0c5558
|
# Status: Burst-No: 5 Write Address: 0023bd85 WriteData: 2c0c5558
|
# Status: Burst-No: 5 Write Address: 0023bd85 WriteData: 2c0c5558
|
# tb_core.u_sdram32 : at time 50427.0 ns WRITE: Bank = 3 Row = 571, Col = 103, Data = 39d65773
|
# tb_core.u_sdram32 : at time 51477.0 ns WRITE: Bank = 3 Row = 571, Col = 103, Data = 39d65773
|
# Status: Burst-No: 6 Write Address: 0023bd85 WriteData: 39d65773
|
# Status: Burst-No: 6 Write Address: 0023bd85 WriteData: 39d65773
|
# tb_core.u_sdram32 : at time 50437.0 ns WRITE: Bank = 3 Row = 571, Col = 104, Data = 8778d20e
|
# tb_core.u_sdram32 : at time 51487.0 ns WRITE: Bank = 3 Row = 571, Col = 104, Data = 8778d20e
|
# Status: Burst-No: 7 Write Address: 0023bd85 WriteData: 8778d20e
|
# Status: Burst-No: 7 Write Address: 0023bd85 WriteData: 8778d20e
|
# tb_core.u_sdram32 : at time 50447.0 ns WRITE: Bank = 3 Row = 571, Col = 105, Data = 6e6d23dc
|
# tb_core.u_sdram32 : at time 51497.0 ns WRITE: Bank = 3 Row = 571, Col = 105, Data = 6e6d23dc
|
# Status: Burst-No: 8 Write Address: 0023bd85 WriteData: 6e6d23dc
|
# Status: Burst-No: 8 Write Address: 0023bd85 WriteData: 6e6d23dc
|
# tb_core.u_sdram32 : at time 50457.0 ns WRITE: Bank = 3 Row = 571, Col = 106, Data = 183fc330
|
# tb_core.u_sdram32 : at time 51507.0 ns WRITE: Bank = 3 Row = 571, Col = 106, Data = 183fc330
|
# Status: Burst-No: 9 Write Address: 0023bd85 WriteData: 183fc330
|
# Status: Burst-No: 9 Write Address: 0023bd85 WriteData: 183fc330
|
# tb_core.u_sdram32 : at time 50467.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 51517.0 ns BST : Burst Terminate
|
# Write Address: 0005f5d0, Burst Size: 1
|
# Write Address: 0005f5d0, Burst Size: 1
|
# tb_core.u_sdram32 : at time 50627.0 ns ACT : Bank = 1 Row = 95
|
# tb_core.u_sdram32 : at time 51677.0 ns ACT : Bank = 1 Row = 95
|
# tb_core.u_sdram32 : at time 50667.0 ns WRITE: Bank = 1 Row = 95, Col = 116, Data = 21820f43
|
# tb_core.u_sdram32 : at time 51717.0 ns WRITE: Bank = 1 Row = 95, Col = 116, Data = 21820f43
|
# Status: Burst-No: 0 Write Address: 0005f5d0 WriteData: 21820f43
|
# Status: Burst-No: 0 Write Address: 0005f5d0 WriteData: 21820f43
|
# tb_core.u_sdram32 : at time 50677.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 51727.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 50833.0 ns READ : Bank = 3 Row = 571, Col = 97, Data = e4df16c9
|
# tb_core.u_sdram32 : at time 51883.0 ns READ : Bank = 3 Row = 571, Col = 97, Data = e4df16c9
|
# tb_core.u_sdram32 : at time 50843.0 ns READ : Bank = 3 Row = 571, Col = 98, Data = b05f8e60
|
# tb_core.u_sdram32 : at time 51893.0 ns READ : Bank = 3 Row = 571, Col = 98, Data = b05f8e60
|
# READ STATUS: Burst-No: 0 Addr: 0023bd85 Rxd: e4df16c9
|
# READ STATUS: Burst-No: 0 Addr: 0023bd85 Rxd: e4df16c9
|
# tb_core.u_sdram32 : at time 50853.0 ns READ : Bank = 3 Row = 571, Col = 99, Data = a3643246
|
# tb_core.u_sdram32 : at time 51903.0 ns READ : Bank = 3 Row = 571, Col = 99, Data = a3643246
|
# READ STATUS: Burst-No: 1 Addr: 0023bd87 Rxd: b05f8e60
|
# READ STATUS: Burst-No: 1 Addr: 0023bd87 Rxd: b05f8e60
|
# tb_core.u_sdram32 : at time 50863.0 ns READ : Bank = 3 Row = 571, Col = 100, Data = 1e74cb3c
|
# tb_core.u_sdram32 : at time 51913.0 ns READ : Bank = 3 Row = 571, Col = 100, Data = 1e74cb3c
|
# READ STATUS: Burst-No: 2 Addr: 0023bd89 Rxd: a3643246
|
# READ STATUS: Burst-No: 2 Addr: 0023bd89 Rxd: a3643246
|
# tb_core.u_sdram32 : at time 50873.0 ns READ : Bank = 3 Row = 571, Col = 101, Data = 1b855f37
|
# tb_core.u_sdram32 : at time 51923.0 ns READ : Bank = 3 Row = 571, Col = 101, Data = 1b855f37
|
# READ STATUS: Burst-No: 3 Addr: 0023bd8b Rxd: 1e74cb3c
|
# READ STATUS: Burst-No: 3 Addr: 0023bd8b Rxd: 1e74cb3c
|
# tb_core.u_sdram32 : at time 50883.0 ns READ : Bank = 3 Row = 571, Col = 102, Data = 2c0c5558
|
# tb_core.u_sdram32 : at time 51933.0 ns READ : Bank = 3 Row = 571, Col = 102, Data = 2c0c5558
|
# READ STATUS: Burst-No: 4 Addr: 0023bd8d Rxd: 1b855f37
|
# READ STATUS: Burst-No: 4 Addr: 0023bd8d Rxd: 1b855f37
|
# tb_core.u_sdram32 : at time 50893.0 ns READ : Bank = 3 Row = 571, Col = 103, Data = 39d65773
|
# tb_core.u_sdram32 : at time 51943.0 ns READ : Bank = 3 Row = 571, Col = 103, Data = 39d65773
|
# READ STATUS: Burst-No: 5 Addr: 0023bd8f Rxd: 2c0c5558
|
# READ STATUS: Burst-No: 5 Addr: 0023bd8f Rxd: 2c0c5558
|
# tb_core.u_sdram32 : at time 50903.0 ns READ : Bank = 3 Row = 571, Col = 104, Data = 8778d20e
|
# tb_core.u_sdram32 : at time 51953.0 ns READ : Bank = 3 Row = 571, Col = 104, Data = 8778d20e
|
# tb_core.u_sdram32 : at time 50907.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 51957.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 6 Addr: 0023bd91 Rxd: 39d65773
|
# READ STATUS: Burst-No: 6 Addr: 0023bd91 Rxd: 39d65773
|
# tb_core.u_sdram32 : at time 50913.0 ns READ : Bank = 3 Row = 571, Col = 105, Data = 6e6d23dc
|
# tb_core.u_sdram32 : at time 51963.0 ns READ : Bank = 3 Row = 571, Col = 105, Data = 6e6d23dc
|
# READ STATUS: Burst-No: 7 Addr: 0023bd93 Rxd: 8778d20e
|
# READ STATUS: Burst-No: 7 Addr: 0023bd93 Rxd: 8778d20e
|
# tb_core.u_sdram32 : at time 50923.0 ns READ : Bank = 3 Row = 571, Col = 106, Data = 183fc330
|
# tb_core.u_sdram32 : at time 51973.0 ns READ : Bank = 3 Row = 571, Col = 106, Data = 183fc330
|
# READ STATUS: Burst-No: 8 Addr: 0023bd95 Rxd: 6e6d23dc
|
# READ STATUS: Burst-No: 8 Addr: 0023bd95 Rxd: 6e6d23dc
|
# READ STATUS: Burst-No: 9 Addr: 0023bd97 Rxd: 183fc330
|
# READ STATUS: Burst-No: 9 Addr: 0023bd97 Rxd: 183fc330
|
# tb_core.u_sdram32 : at time 51097.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 52147.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 51113.0 ns READ : Bank = 1 Row = 95, Col = 116, Data = 21820f43
|
# tb_core.u_sdram32 : at time 52163.0 ns READ : Bank = 1 Row = 95, Col = 116, Data = 21820f43
|
# READ STATUS: Burst-No: 0 Addr: 0005f5d0 Rxd: 21820f43
|
# READ STATUS: Burst-No: 0 Addr: 0005f5d0 Rxd: 21820f43
|
# Write Address: 002e91f8, Burst Size: 2
|
# Write Address: 002e91f8, Burst Size: 2
|
# tb_core.u_sdram32 : at time 51307.0 ns ACT : Bank = 0 Row = 745
|
# tb_core.u_sdram32 : at time 52357.0 ns ACT : Bank = 0 Row = 745
|
# tb_core.u_sdram32 : at time 51347.0 ns WRITE: Bank = 0 Row = 745, Col = 126, Data = 29c01f53
|
# tb_core.u_sdram32 : at time 52397.0 ns WRITE: Bank = 0 Row = 745, Col = 126, Data = 29c01f53
|
# Status: Burst-No: 0 Write Address: 002e91f8 WriteData: 29c01f53
|
# Status: Burst-No: 0 Write Address: 002e91f8 WriteData: 29c01f53
|
# tb_core.u_sdram32 : at time 51357.0 ns WRITE: Bank = 0 Row = 745, Col = 127, Data = 4c588f98
|
# tb_core.u_sdram32 : at time 52407.0 ns WRITE: Bank = 0 Row = 745, Col = 127, Data = 4c588f98
|
# Status: Burst-No: 1 Write Address: 002e91f8 WriteData: 4c588f98
|
# Status: Burst-No: 1 Write Address: 002e91f8 WriteData: 4c588f98
|
# tb_core.u_sdram32 : at time 51367.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 52417.0 ns BST : Burst Terminate
|
# Write Address: 002f3d5f, Burst Size: 8
|
# Write Address: 002f3d5f, Burst Size: 8
|
# tb_core.u_sdram32 : at time 51527.0 ns ACT : Bank = 3 Row = 755
|
# tb_core.u_sdram32 : at time 52577.0 ns ACT : Bank = 3 Row = 755
|
# tb_core.u_sdram32 : at time 51567.0 ns WRITE: Bank = 3 Row = 755, Col = 87, Data = fd5f5afa
|
# tb_core.u_sdram32 : at time 52617.0 ns WRITE: Bank = 3 Row = 755, Col = 87, Data = fd5f5afa
|
# Status: Burst-No: 0 Write Address: 002f3d5f WriteData: fd5f5afa
|
# Status: Burst-No: 0 Write Address: 002f3d5f WriteData: fd5f5afa
|
# tb_core.u_sdram32 : at time 51577.0 ns WRITE: Bank = 3 Row = 755, Col = 88, Data = 1699d12d
|
# tb_core.u_sdram32 : at time 52627.0 ns WRITE: Bank = 3 Row = 755, Col = 88, Data = 1699d12d
|
# Status: Burst-No: 1 Write Address: 002f3d5f WriteData: 1699d12d
|
# Status: Burst-No: 1 Write Address: 002f3d5f WriteData: 1699d12d
|
# tb_core.u_sdram32 : at time 51587.0 ns WRITE: Bank = 3 Row = 755, Col = 89, Data = b8760270
|
# tb_core.u_sdram32 : at time 52637.0 ns WRITE: Bank = 3 Row = 755, Col = 89, Data = b8760270
|
# Status: Burst-No: 2 Write Address: 002f3d5f WriteData: b8760270
|
# Status: Burst-No: 2 Write Address: 002f3d5f WriteData: b8760270
|
# tb_core.u_sdram32 : at time 51597.0 ns WRITE: Bank = 3 Row = 755, Col = 90, Data = b5b4e86b
|
# tb_core.u_sdram32 : at time 52647.0 ns WRITE: Bank = 3 Row = 755, Col = 90, Data = b5b4e86b
|
# Status: Burst-No: 3 Write Address: 002f3d5f WriteData: b5b4e86b
|
# Status: Burst-No: 3 Write Address: 002f3d5f WriteData: b5b4e86b
|
# tb_core.u_sdram32 : at time 51607.0 ns WRITE: Bank = 3 Row = 755, Col = 91, Data = 98d73831
|
# tb_core.u_sdram32 : at time 52657.0 ns WRITE: Bank = 3 Row = 755, Col = 91, Data = 98d73831
|
# Status: Burst-No: 4 Write Address: 002f3d5f WriteData: 98d73831
|
# Status: Burst-No: 4 Write Address: 002f3d5f WriteData: 98d73831
|
# tb_core.u_sdram32 : at time 51617.0 ns WRITE: Bank = 3 Row = 755, Col = 92, Data = 892fc012
|
# tb_core.u_sdram32 : at time 52667.0 ns WRITE: Bank = 3 Row = 755, Col = 92, Data = 892fc012
|
# Status: Burst-No: 5 Write Address: 002f3d5f WriteData: 892fc012
|
# Status: Burst-No: 5 Write Address: 002f3d5f WriteData: 892fc012
|
# tb_core.u_sdram32 : at time 51627.0 ns WRITE: Bank = 3 Row = 755, Col = 93, Data = 0650df0c
|
# tb_core.u_sdram32 : at time 52677.0 ns WRITE: Bank = 3 Row = 755, Col = 93, Data = 0650df0c
|
# Status: Burst-No: 6 Write Address: 002f3d5f WriteData: 0650df0c
|
# Status: Burst-No: 6 Write Address: 002f3d5f WriteData: 0650df0c
|
# tb_core.u_sdram32 : at time 51637.0 ns WRITE: Bank = 3 Row = 755, Col = 94, Data = 06db6b0d
|
# tb_core.u_sdram32 : at time 52687.0 ns WRITE: Bank = 3 Row = 755, Col = 94, Data = 06db6b0d
|
# Status: Burst-No: 7 Write Address: 002f3d5f WriteData: 06db6b0d
|
# Status: Burst-No: 7 Write Address: 002f3d5f WriteData: 06db6b0d
|
# tb_core.u_sdram32 : at time 51647.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 52697.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 51787.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 52837.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 51793.0 ns READ : Bank = 0 Row = 745, Col = 126, Data = 29c01f53
|
# tb_core.u_sdram32 : at time 52843.0 ns READ : Bank = 0 Row = 745, Col = 126, Data = 29c01f53
|
# tb_core.u_sdram32 : at time 51803.0 ns READ : Bank = 0 Row = 745, Col = 127, Data = 4c588f98
|
# tb_core.u_sdram32 : at time 52853.0 ns READ : Bank = 0 Row = 745, Col = 127, Data = 4c588f98
|
# READ STATUS: Burst-No: 0 Addr: 002e91f8 Rxd: 29c01f53
|
# READ STATUS: Burst-No: 0 Addr: 002e91f8 Rxd: 29c01f53
|
# READ STATUS: Burst-No: 1 Addr: 002e91fa Rxd: 4c588f98
|
# READ STATUS: Burst-No: 1 Addr: 002e91fa Rxd: 4c588f98
|
# tb_core.u_sdram32 : at time 51993.0 ns READ : Bank = 3 Row = 755, Col = 87, Data = fd5f5afa
|
# tb_core.u_sdram32 : at time 53043.0 ns READ : Bank = 3 Row = 755, Col = 87, Data = fd5f5afa
|
# tb_core.u_sdram32 : at time 52003.0 ns READ : Bank = 3 Row = 755, Col = 88, Data = 1699d12d
|
# tb_core.u_sdram32 : at time 53053.0 ns READ : Bank = 3 Row = 755, Col = 88, Data = 1699d12d
|
# READ STATUS: Burst-No: 0 Addr: 002f3d5f Rxd: fd5f5afa
|
# READ STATUS: Burst-No: 0 Addr: 002f3d5f Rxd: fd5f5afa
|
# tb_core.u_sdram32 : at time 52013.0 ns READ : Bank = 3 Row = 755, Col = 89, Data = b8760270
|
# tb_core.u_sdram32 : at time 53063.0 ns READ : Bank = 3 Row = 755, Col = 89, Data = b8760270
|
# READ STATUS: Burst-No: 1 Addr: 002f3d61 Rxd: 1699d12d
|
# READ STATUS: Burst-No: 1 Addr: 002f3d61 Rxd: 1699d12d
|
# tb_core.u_sdram32 : at time 52023.0 ns READ : Bank = 3 Row = 755, Col = 90, Data = b5b4e86b
|
# tb_core.u_sdram32 : at time 53073.0 ns READ : Bank = 3 Row = 755, Col = 90, Data = b5b4e86b
|
# READ STATUS: Burst-No: 2 Addr: 002f3d63 Rxd: b8760270
|
# READ STATUS: Burst-No: 2 Addr: 002f3d63 Rxd: b8760270
|
# tb_core.u_sdram32 : at time 52033.0 ns READ : Bank = 3 Row = 755, Col = 91, Data = 98d73831
|
# tb_core.u_sdram32 : at time 53083.0 ns READ : Bank = 3 Row = 755, Col = 91, Data = 98d73831
|
# READ STATUS: Burst-No: 3 Addr: 002f3d65 Rxd: b5b4e86b
|
# READ STATUS: Burst-No: 3 Addr: 002f3d65 Rxd: b5b4e86b
|
# tb_core.u_sdram32 : at time 52043.0 ns READ : Bank = 3 Row = 755, Col = 92, Data = 892fc012
|
# tb_core.u_sdram32 : at time 53093.0 ns READ : Bank = 3 Row = 755, Col = 92, Data = 892fc012
|
# tb_core.u_sdram32 : at time 52047.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 53097.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 4 Addr: 002f3d67 Rxd: 98d73831
|
# READ STATUS: Burst-No: 4 Addr: 002f3d67 Rxd: 98d73831
|
# tb_core.u_sdram32 : at time 52053.0 ns READ : Bank = 3 Row = 755, Col = 93, Data = 0650df0c
|
# tb_core.u_sdram32 : at time 53103.0 ns READ : Bank = 3 Row = 755, Col = 93, Data = 0650df0c
|
# READ STATUS: Burst-No: 5 Addr: 002f3d69 Rxd: 892fc012
|
# READ STATUS: Burst-No: 5 Addr: 002f3d69 Rxd: 892fc012
|
# tb_core.u_sdram32 : at time 52063.0 ns READ : Bank = 3 Row = 755, Col = 94, Data = 06db6b0d
|
# tb_core.u_sdram32 : at time 53113.0 ns READ : Bank = 3 Row = 755, Col = 94, Data = 06db6b0d
|
# READ STATUS: Burst-No: 6 Addr: 002f3d6b Rxd: 0650df0c
|
# READ STATUS: Burst-No: 6 Addr: 002f3d6b Rxd: 0650df0c
|
# READ STATUS: Burst-No: 7 Addr: 002f3d6d Rxd: 06db6b0d
|
# READ STATUS: Burst-No: 7 Addr: 002f3d6d Rxd: 06db6b0d
|
# Write Address: 000d1315, Burst Size: 1
|
# Write Address: 000d1315, Burst Size: 1
|
# tb_core.u_sdram32 : at time 52257.0 ns ACT : Bank = 0 Row = 209
|
# tb_core.u_sdram32 : at time 53307.0 ns ACT : Bank = 0 Row = 209
|
# tb_core.u_sdram32 : at time 52297.0 ns WRITE: Bank = 0 Row = 209, Col = 197, Data = 4a638d94
|
# tb_core.u_sdram32 : at time 53347.0 ns WRITE: Bank = 0 Row = 209, Col = 197, Data = 4a638d94
|
# Status: Burst-No: 0 Write Address: 000d1315 WriteData: 4a638d94
|
# Status: Burst-No: 0 Write Address: 000d1315 WriteData: 4a638d94
|
# tb_core.u_sdram32 : at time 52307.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 53357.0 ns BST : Burst Terminate
|
# Write Address: 001ba354, Burst Size: 1
|
# Write Address: 001ba354, Burst Size: 1
|
# tb_core.u_sdram32 : at time 52467.0 ns ACT : Bank = 0 Row = 442
|
# tb_core.u_sdram32 : at time 53517.0 ns ACT : Bank = 0 Row = 442
|
# tb_core.u_sdram32 : at time 52507.0 ns WRITE: Bank = 0 Row = 442, Col = 213, Data = 098d1513
|
# tb_core.u_sdram32 : at time 53557.0 ns WRITE: Bank = 0 Row = 442, Col = 213, Data = 098d1513
|
# Status: Burst-No: 0 Write Address: 001ba354 WriteData: 098d1513
|
# Status: Burst-No: 0 Write Address: 001ba354 WriteData: 098d1513
|
# tb_core.u_sdram32 : at time 52517.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 53567.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 52677.0 ns ACT : Bank = 0 Row = 209
|
# tb_core.u_sdram32 : at time 53727.0 ns ACT : Bank = 0 Row = 209
|
# tb_core.u_sdram32 : at time 52727.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 53777.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 52743.0 ns READ : Bank = 0 Row = 209, Col = 197, Data = 4a638d94
|
# tb_core.u_sdram32 : at time 53793.0 ns READ : Bank = 0 Row = 209, Col = 197, Data = 4a638d94
|
# READ STATUS: Burst-No: 0 Addr: 000d1315 Rxd: 4a638d94
|
# READ STATUS: Burst-No: 0 Addr: 000d1315 Rxd: 4a638d94
|
# tb_core.u_sdram32 : at time 52937.0 ns ACT : Bank = 0 Row = 442
|
# tb_core.u_sdram32 : at time 53987.0 ns ACT : Bank = 0 Row = 442
|
# tb_core.u_sdram32 : at time 52987.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 54037.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 53003.0 ns READ : Bank = 0 Row = 442, Col = 213, Data = 098d1513
|
# tb_core.u_sdram32 : at time 54053.0 ns READ : Bank = 0 Row = 442, Col = 213, Data = 098d1513
|
# READ STATUS: Burst-No: 0 Addr: 001ba354 Rxd: 098d1513
|
# READ STATUS: Burst-No: 0 Addr: 001ba354 Rxd: 098d1513
|
# Write Address: 002386c3, Burst Size: 14
|
# Write Address: 002386c3, Burst Size: 14
|
# tb_core.u_sdram32 : at time 53197.0 ns ACT : Bank = 1 Row = 568
|
# tb_core.u_sdram32 : at time 54247.0 ns ACT : Bank = 1 Row = 568
|
# tb_core.u_sdram32 : at time 53237.0 ns WRITE: Bank = 1 Row = 568, Col = 176, Data = ee4ee6dc
|
# tb_core.u_sdram32 : at time 54287.0 ns WRITE: Bank = 1 Row = 568, Col = 176, Data = ee4ee6dc
|
# Status: Burst-No: 0 Write Address: 002386c3 WriteData: ee4ee6dc
|
# Status: Burst-No: 0 Write Address: 002386c3 WriteData: ee4ee6dc
|
# tb_core.u_sdram32 : at time 53247.0 ns WRITE: Bank = 1 Row = 568, Col = 177, Data = bc781078
|
# tb_core.u_sdram32 : at time 54297.0 ns WRITE: Bank = 1 Row = 568, Col = 177, Data = bc781078
|
# Status: Burst-No: 1 Write Address: 002386c3 WriteData: bc781078
|
# Status: Burst-No: 1 Write Address: 002386c3 WriteData: bc781078
|
# tb_core.u_sdram32 : at time 53257.0 ns WRITE: Bank = 1 Row = 568, Col = 178, Data = 13d40d27
|
# tb_core.u_sdram32 : at time 54307.0 ns WRITE: Bank = 1 Row = 568, Col = 178, Data = 13d40d27
|
# Status: Burst-No: 2 Write Address: 002386c3 WriteData: 13d40d27
|
# Status: Burst-No: 2 Write Address: 002386c3 WriteData: 13d40d27
|
# tb_core.u_sdram32 : at time 53267.0 ns WRITE: Bank = 1 Row = 568, Col = 179, Data = afed265f
|
# tb_core.u_sdram32 : at time 54317.0 ns WRITE: Bank = 1 Row = 568, Col = 179, Data = afed265f
|
# Status: Burst-No: 3 Write Address: 002386c3 WriteData: afed265f
|
# Status: Burst-No: 3 Write Address: 002386c3 WriteData: afed265f
|
# tb_core.u_sdram32 : at time 53277.0 ns WRITE: Bank = 1 Row = 568, Col = 180, Data = 11c05b23
|
# tb_core.u_sdram32 : at time 54327.0 ns WRITE: Bank = 1 Row = 568, Col = 180, Data = 11c05b23
|
# Status: Burst-No: 4 Write Address: 002386c3 WriteData: 11c05b23
|
# Status: Burst-No: 4 Write Address: 002386c3 WriteData: 11c05b23
|
# tb_core.u_sdram32 : at time 53287.0 ns WRITE: Bank = 1 Row = 568, Col = 181, Data = 5596ebab
|
# tb_core.u_sdram32 : at time 54337.0 ns WRITE: Bank = 1 Row = 568, Col = 181, Data = 5596ebab
|
# Status: Burst-No: 5 Write Address: 002386c3 WriteData: 5596ebab
|
# Status: Burst-No: 5 Write Address: 002386c3 WriteData: 5596ebab
|
# tb_core.u_sdram32 : at time 53297.0 ns WRITE: Bank = 1 Row = 568, Col = 182, Data = 1c421738
|
# tb_core.u_sdram32 : at time 54347.0 ns WRITE: Bank = 1 Row = 568, Col = 182, Data = 1c421738
|
# Status: Burst-No: 6 Write Address: 002386c3 WriteData: 1c421738
|
# Status: Burst-No: 6 Write Address: 002386c3 WriteData: 1c421738
|
# tb_core.u_sdram32 : at time 53307.0 ns WRITE: Bank = 1 Row = 568, Col = 183, Data = 11534d22
|
# tb_core.u_sdram32 : at time 54357.0 ns WRITE: Bank = 1 Row = 568, Col = 183, Data = 11534d22
|
# Status: Burst-No: 7 Write Address: 002386c3 WriteData: 11534d22
|
# Status: Burst-No: 7 Write Address: 002386c3 WriteData: 11534d22
|
# tb_core.u_sdram32 : at time 53317.0 ns WRITE: Bank = 1 Row = 568, Col = 184, Data = 64f2bdc9
|
# tb_core.u_sdram32 : at time 54367.0 ns WRITE: Bank = 1 Row = 568, Col = 184, Data = 64f2bdc9
|
# Status: Burst-No: 8 Write Address: 002386c3 WriteData: 64f2bdc9
|
# Status: Burst-No: 8 Write Address: 002386c3 WriteData: 64f2bdc9
|
# tb_core.u_sdram32 : at time 53327.0 ns WRITE: Bank = 1 Row = 568, Col = 185, Data = e3eb4cc7
|
# tb_core.u_sdram32 : at time 54377.0 ns WRITE: Bank = 1 Row = 568, Col = 185, Data = e3eb4cc7
|
# Status: Burst-No: 9 Write Address: 002386c3 WriteData: e3eb4cc7
|
# Status: Burst-No: 9 Write Address: 002386c3 WriteData: e3eb4cc7
|
# tb_core.u_sdram32 : at time 53337.0 ns WRITE: Bank = 1 Row = 568, Col = 186, Data = c1406282
|
# tb_core.u_sdram32 : at time 54387.0 ns WRITE: Bank = 1 Row = 568, Col = 186, Data = c1406282
|
# Status: Burst-No: 10 Write Address: 002386c3 WriteData: c1406282
|
# Status: Burst-No: 10 Write Address: 002386c3 WriteData: c1406282
|
# tb_core.u_sdram32 : at time 53347.0 ns WRITE: Bank = 1 Row = 568, Col = 187, Data = 6754d7ce
|
# tb_core.u_sdram32 : at time 54397.0 ns WRITE: Bank = 1 Row = 568, Col = 187, Data = 6754d7ce
|
# Status: Burst-No: 11 Write Address: 002386c3 WriteData: 6754d7ce
|
# Status: Burst-No: 11 Write Address: 002386c3 WriteData: 6754d7ce
|
# tb_core.u_sdram32 : at time 53357.0 ns WRITE: Bank = 1 Row = 568, Col = 188, Data = e38e22c7
|
# tb_core.u_sdram32 : at time 54407.0 ns WRITE: Bank = 1 Row = 568, Col = 188, Data = e38e22c7
|
# Status: Burst-No: 12 Write Address: 002386c3 WriteData: e38e22c7
|
# Status: Burst-No: 12 Write Address: 002386c3 WriteData: e38e22c7
|
# tb_core.u_sdram32 : at time 53367.0 ns WRITE: Bank = 1 Row = 568, Col = 189, Data = 927fa424
|
# tb_core.u_sdram32 : at time 54417.0 ns WRITE: Bank = 1 Row = 568, Col = 189, Data = 927fa424
|
# Status: Burst-No: 13 Write Address: 002386c3 WriteData: 927fa424
|
# Status: Burst-No: 13 Write Address: 002386c3 WriteData: 927fa424
|
# tb_core.u_sdram32 : at time 53377.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 54427.0 ns BST : Burst Terminate
|
# Write Address: 00236fdb, Burst Size: 9
|
# Write Address: 00236fdb, Burst Size: 9
|
# tb_core.u_sdram32 : at time 53537.0 ns ACT : Bank = 3 Row = 566
|
# tb_core.u_sdram32 : at time 54587.0 ns ACT : Bank = 3 Row = 566
|
# tb_core.u_sdram32 : at time 53577.0 ns WRITE: Bank = 3 Row = 566, Col = 246, Data = 3ac26f75
|
# tb_core.u_sdram32 : at time 54627.0 ns WRITE: Bank = 3 Row = 566, Col = 246, Data = 3ac26f75
|
# Status: Burst-No: 0 Write Address: 00236fdb WriteData: 3ac26f75
|
# Status: Burst-No: 0 Write Address: 00236fdb WriteData: 3ac26f75
|
# tb_core.u_sdram32 : at time 53587.0 ns WRITE: Bank = 3 Row = 566, Col = 247, Data = 5ad31db5
|
# tb_core.u_sdram32 : at time 54637.0 ns WRITE: Bank = 3 Row = 566, Col = 247, Data = 5ad31db5
|
# Status: Burst-No: 1 Write Address: 00236fdb WriteData: 5ad31db5
|
# Status: Burst-No: 1 Write Address: 00236fdb WriteData: 5ad31db5
|
# tb_core.u_sdram32 : at time 53597.0 ns WRITE: Bank = 3 Row = 566, Col = 248, Data = 8d7d721a
|
# tb_core.u_sdram32 : at time 54647.0 ns WRITE: Bank = 3 Row = 566, Col = 248, Data = 8d7d721a
|
# Status: Burst-No: 2 Write Address: 00236fdb WriteData: 8d7d721a
|
# Status: Burst-No: 2 Write Address: 00236fdb WriteData: 8d7d721a
|
# tb_core.u_sdram32 : at time 53607.0 ns WRITE: Bank = 3 Row = 566, Col = 249, Data = 1c2a1338
|
# tb_core.u_sdram32 : at time 54657.0 ns WRITE: Bank = 3 Row = 566, Col = 249, Data = 1c2a1338
|
# Status: Burst-No: 3 Write Address: 00236fdb WriteData: 1c2a1338
|
# Status: Burst-No: 3 Write Address: 00236fdb WriteData: 1c2a1338
|
# tb_core.u_sdram32 : at time 53617.0 ns WRITE: Bank = 3 Row = 566, Col = 250, Data = c1233a82
|
# tb_core.u_sdram32 : at time 54667.0 ns WRITE: Bank = 3 Row = 566, Col = 250, Data = c1233a82
|
# Status: Burst-No: 4 Write Address: 00236fdb WriteData: c1233a82
|
# Status: Burst-No: 4 Write Address: 00236fdb WriteData: c1233a82
|
# tb_core.u_sdram32 : at time 53627.0 ns WRITE: Bank = 3 Row = 566, Col = 251, Data = ac05a058
|
# tb_core.u_sdram32 : at time 54677.0 ns WRITE: Bank = 3 Row = 566, Col = 251, Data = ac05a058
|
# Status: Burst-No: 5 Write Address: 00236fdb WriteData: ac05a058
|
# Status: Burst-No: 5 Write Address: 00236fdb WriteData: ac05a058
|
# tb_core.u_sdram32 : at time 53637.0 ns WRITE: Bank = 3 Row = 566, Col = 252, Data = a85a6a50
|
# tb_core.u_sdram32 : at time 54687.0 ns WRITE: Bank = 3 Row = 566, Col = 252, Data = a85a6a50
|
# Status: Burst-No: 6 Write Address: 00236fdb WriteData: a85a6a50
|
# Status: Burst-No: 6 Write Address: 00236fdb WriteData: a85a6a50
|
# tb_core.u_sdram32 : at time 53647.0 ns WRITE: Bank = 3 Row = 566, Col = 253, Data = d1889aa3
|
# tb_core.u_sdram32 : at time 54697.0 ns WRITE: Bank = 3 Row = 566, Col = 253, Data = d1889aa3
|
# Status: Burst-No: 7 Write Address: 00236fdb WriteData: d1889aa3
|
# Status: Burst-No: 7 Write Address: 00236fdb WriteData: d1889aa3
|
# tb_core.u_sdram32 : at time 53657.0 ns WRITE: Bank = 3 Row = 566, Col = 254, Data = 5243e3a4
|
# tb_core.u_sdram32 : at time 54707.0 ns WRITE: Bank = 3 Row = 566, Col = 254, Data = 5243e3a4
|
# Status: Burst-No: 8 Write Address: 00236fdb WriteData: 5243e3a4
|
# Status: Burst-No: 8 Write Address: 00236fdb WriteData: 5243e3a4
|
# tb_core.u_sdram32 : at time 53667.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 54717.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 53823.0 ns READ : Bank = 1 Row = 568, Col = 176, Data = ee4ee6dc
|
# tb_core.u_sdram32 : at time 54873.0 ns READ : Bank = 1 Row = 568, Col = 176, Data = ee4ee6dc
|
# tb_core.u_sdram32 : at time 53833.0 ns READ : Bank = 1 Row = 568, Col = 177, Data = bc781078
|
# tb_core.u_sdram32 : at time 54883.0 ns READ : Bank = 1 Row = 568, Col = 177, Data = bc781078
|
# READ STATUS: Burst-No: 0 Addr: 002386c3 Rxd: ee4ee6dc
|
# READ STATUS: Burst-No: 0 Addr: 002386c3 Rxd: ee4ee6dc
|
# tb_core.u_sdram32 : at time 53843.0 ns READ : Bank = 1 Row = 568, Col = 178, Data = 13d40d27
|
# tb_core.u_sdram32 : at time 54893.0 ns READ : Bank = 1 Row = 568, Col = 178, Data = 13d40d27
|
# READ STATUS: Burst-No: 1 Addr: 002386c5 Rxd: bc781078
|
# READ STATUS: Burst-No: 1 Addr: 002386c5 Rxd: bc781078
|
# tb_core.u_sdram32 : at time 53853.0 ns READ : Bank = 1 Row = 568, Col = 179, Data = afed265f
|
# tb_core.u_sdram32 : at time 54903.0 ns READ : Bank = 1 Row = 568, Col = 179, Data = afed265f
|
# READ STATUS: Burst-No: 2 Addr: 002386c7 Rxd: 13d40d27
|
# READ STATUS: Burst-No: 2 Addr: 002386c7 Rxd: 13d40d27
|
# tb_core.u_sdram32 : at time 53863.0 ns READ : Bank = 1 Row = 568, Col = 180, Data = 11c05b23
|
# tb_core.u_sdram32 : at time 54913.0 ns READ : Bank = 1 Row = 568, Col = 180, Data = 11c05b23
|
# READ STATUS: Burst-No: 3 Addr: 002386c9 Rxd: afed265f
|
# READ STATUS: Burst-No: 3 Addr: 002386c9 Rxd: afed265f
|
# tb_core.u_sdram32 : at time 53873.0 ns READ : Bank = 1 Row = 568, Col = 181, Data = 5596ebab
|
# tb_core.u_sdram32 : at time 54923.0 ns READ : Bank = 1 Row = 568, Col = 181, Data = 5596ebab
|
# READ STATUS: Burst-No: 4 Addr: 002386cb Rxd: 11c05b23
|
# READ STATUS: Burst-No: 4 Addr: 002386cb Rxd: 11c05b23
|
# tb_core.u_sdram32 : at time 53883.0 ns READ : Bank = 1 Row = 568, Col = 182, Data = 1c421738
|
# tb_core.u_sdram32 : at time 54933.0 ns READ : Bank = 1 Row = 568, Col = 182, Data = 1c421738
|
# READ STATUS: Burst-No: 5 Addr: 002386cd Rxd: 5596ebab
|
# READ STATUS: Burst-No: 5 Addr: 002386cd Rxd: 5596ebab
|
# tb_core.u_sdram32 : at time 53893.0 ns READ : Bank = 1 Row = 568, Col = 183, Data = 11534d22
|
# tb_core.u_sdram32 : at time 54943.0 ns READ : Bank = 1 Row = 568, Col = 183, Data = 11534d22
|
# READ STATUS: Burst-No: 6 Addr: 002386cf Rxd: 1c421738
|
# READ STATUS: Burst-No: 6 Addr: 002386cf Rxd: 1c421738
|
# tb_core.u_sdram32 : at time 53903.0 ns READ : Bank = 1 Row = 568, Col = 184, Data = 64f2bdc9
|
# tb_core.u_sdram32 : at time 54953.0 ns READ : Bank = 1 Row = 568, Col = 184, Data = 64f2bdc9
|
# READ STATUS: Burst-No: 7 Addr: 002386d1 Rxd: 11534d22
|
# READ STATUS: Burst-No: 7 Addr: 002386d1 Rxd: 11534d22
|
# tb_core.u_sdram32 : at time 53913.0 ns READ : Bank = 1 Row = 568, Col = 185, Data = e3eb4cc7
|
# tb_core.u_sdram32 : at time 54963.0 ns READ : Bank = 1 Row = 568, Col = 185, Data = e3eb4cc7
|
# READ STATUS: Burst-No: 8 Addr: 002386d3 Rxd: 64f2bdc9
|
# READ STATUS: Burst-No: 8 Addr: 002386d3 Rxd: 64f2bdc9
|
# tb_core.u_sdram32 : at time 53923.0 ns READ : Bank = 1 Row = 568, Col = 186, Data = c1406282
|
# tb_core.u_sdram32 : at time 54973.0 ns READ : Bank = 1 Row = 568, Col = 186, Data = c1406282
|
# READ STATUS: Burst-No: 9 Addr: 002386d5 Rxd: e3eb4cc7
|
# READ STATUS: Burst-No: 9 Addr: 002386d5 Rxd: e3eb4cc7
|
# tb_core.u_sdram32 : at time 53933.0 ns READ : Bank = 1 Row = 568, Col = 187, Data = 6754d7ce
|
# tb_core.u_sdram32 : at time 54983.0 ns READ : Bank = 1 Row = 568, Col = 187, Data = 6754d7ce
|
# tb_core.u_sdram32 : at time 53937.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 54987.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 10 Addr: 002386d7 Rxd: c1406282
|
# READ STATUS: Burst-No: 10 Addr: 002386d7 Rxd: c1406282
|
# tb_core.u_sdram32 : at time 53943.0 ns READ : Bank = 1 Row = 568, Col = 188, Data = e38e22c7
|
# tb_core.u_sdram32 : at time 54993.0 ns READ : Bank = 1 Row = 568, Col = 188, Data = e38e22c7
|
# READ STATUS: Burst-No: 11 Addr: 002386d9 Rxd: 6754d7ce
|
# READ STATUS: Burst-No: 11 Addr: 002386d9 Rxd: 6754d7ce
|
# tb_core.u_sdram32 : at time 53953.0 ns READ : Bank = 1 Row = 568, Col = 189, Data = 927fa424
|
# tb_core.u_sdram32 : at time 55003.0 ns READ : Bank = 1 Row = 568, Col = 189, Data = 927fa424
|
# READ STATUS: Burst-No: 12 Addr: 002386db Rxd: e38e22c7
|
# READ STATUS: Burst-No: 12 Addr: 002386db Rxd: e38e22c7
|
# READ STATUS: Burst-No: 13 Addr: 002386dd Rxd: 927fa424
|
# READ STATUS: Burst-No: 13 Addr: 002386dd Rxd: 927fa424
|
# tb_core.u_sdram32 : at time 54143.0 ns READ : Bank = 3 Row = 566, Col = 246, Data = 3ac26f75
|
# tb_core.u_sdram32 : at time 55193.0 ns READ : Bank = 3 Row = 566, Col = 246, Data = 3ac26f75
|
# tb_core.u_sdram32 : at time 54153.0 ns READ : Bank = 3 Row = 566, Col = 247, Data = 5ad31db5
|
# tb_core.u_sdram32 : at time 55203.0 ns READ : Bank = 3 Row = 566, Col = 247, Data = 5ad31db5
|
# READ STATUS: Burst-No: 0 Addr: 00236fdb Rxd: 3ac26f75
|
# READ STATUS: Burst-No: 0 Addr: 00236fdb Rxd: 3ac26f75
|
# tb_core.u_sdram32 : at time 54163.0 ns READ : Bank = 3 Row = 566, Col = 248, Data = 8d7d721a
|
# tb_core.u_sdram32 : at time 55213.0 ns READ : Bank = 3 Row = 566, Col = 248, Data = 8d7d721a
|
# READ STATUS: Burst-No: 1 Addr: 00236fdd Rxd: 5ad31db5
|
# READ STATUS: Burst-No: 1 Addr: 00236fdd Rxd: 5ad31db5
|
# tb_core.u_sdram32 : at time 54173.0 ns READ : Bank = 3 Row = 566, Col = 249, Data = 1c2a1338
|
# tb_core.u_sdram32 : at time 55223.0 ns READ : Bank = 3 Row = 566, Col = 249, Data = 1c2a1338
|
# READ STATUS: Burst-No: 2 Addr: 00236fdf Rxd: 8d7d721a
|
# READ STATUS: Burst-No: 2 Addr: 00236fdf Rxd: 8d7d721a
|
# tb_core.u_sdram32 : at time 54183.0 ns READ : Bank = 3 Row = 566, Col = 250, Data = c1233a82
|
# tb_core.u_sdram32 : at time 55233.0 ns READ : Bank = 3 Row = 566, Col = 250, Data = c1233a82
|
# READ STATUS: Burst-No: 3 Addr: 00236fe1 Rxd: 1c2a1338
|
# READ STATUS: Burst-No: 3 Addr: 00236fe1 Rxd: 1c2a1338
|
# tb_core.u_sdram32 : at time 54193.0 ns READ : Bank = 3 Row = 566, Col = 251, Data = ac05a058
|
# tb_core.u_sdram32 : at time 55243.0 ns READ : Bank = 3 Row = 566, Col = 251, Data = ac05a058
|
# READ STATUS: Burst-No: 4 Addr: 00236fe3 Rxd: c1233a82
|
# READ STATUS: Burst-No: 4 Addr: 00236fe3 Rxd: c1233a82
|
# tb_core.u_sdram32 : at time 54203.0 ns READ : Bank = 3 Row = 566, Col = 252, Data = a85a6a50
|
# tb_core.u_sdram32 : at time 55253.0 ns READ : Bank = 3 Row = 566, Col = 252, Data = a85a6a50
|
# tb_core.u_sdram32 : at time 54207.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 55257.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 5 Addr: 00236fe5 Rxd: ac05a058
|
# READ STATUS: Burst-No: 5 Addr: 00236fe5 Rxd: ac05a058
|
# tb_core.u_sdram32 : at time 54213.0 ns READ : Bank = 3 Row = 566, Col = 253, Data = d1889aa3
|
# tb_core.u_sdram32 : at time 55263.0 ns READ : Bank = 3 Row = 566, Col = 253, Data = d1889aa3
|
# READ STATUS: Burst-No: 6 Addr: 00236fe7 Rxd: a85a6a50
|
# READ STATUS: Burst-No: 6 Addr: 00236fe7 Rxd: a85a6a50
|
# tb_core.u_sdram32 : at time 54223.0 ns READ : Bank = 3 Row = 566, Col = 254, Data = 5243e3a4
|
# tb_core.u_sdram32 : at time 55273.0 ns READ : Bank = 3 Row = 566, Col = 254, Data = 5243e3a4
|
# READ STATUS: Burst-No: 7 Addr: 00236fe9 Rxd: d1889aa3
|
# READ STATUS: Burst-No: 7 Addr: 00236fe9 Rxd: d1889aa3
|
# READ STATUS: Burst-No: 8 Addr: 00236feb Rxd: 5243e3a4
|
# READ STATUS: Burst-No: 8 Addr: 00236feb Rxd: 5243e3a4
|
# Write Address: 0003df65, Burst Size: 11
|
# Write Address: 0003df65, Burst Size: 11
|
# tb_core.u_sdram32 : at time 54417.0 ns ACT : Bank = 3 Row = 61
|
# tb_core.u_sdram32 : at time 55467.0 ns ACT : Bank = 3 Row = 61
|
# tb_core.u_sdram32 : at time 54457.0 ns WRITE: Bank = 3 Row = 61, Col = 217, Data = 03703906
|
# tb_core.u_sdram32 : at time 55507.0 ns WRITE: Bank = 3 Row = 61, Col = 217, Data = 03703906
|
# Status: Burst-No: 0 Write Address: 0003df65 WriteData: 03703906
|
# Status: Burst-No: 0 Write Address: 0003df65 WriteData: 03703906
|
# tb_core.u_sdram32 : at time 54467.0 ns WRITE: Bank = 3 Row = 61, Col = 218, Data = aa138054
|
# tb_core.u_sdram32 : at time 55517.0 ns WRITE: Bank = 3 Row = 61, Col = 218, Data = aa138054
|
# Status: Burst-No: 1 Write Address: 0003df65 WriteData: aa138054
|
# Status: Burst-No: 1 Write Address: 0003df65 WriteData: aa138054
|
# tb_core.u_sdram32 : at time 54477.0 ns WRITE: Bank = 3 Row = 61, Col = 219, Data = adf3405b
|
# tb_core.u_sdram32 : at time 55527.0 ns WRITE: Bank = 3 Row = 61, Col = 219, Data = adf3405b
|
# Status: Burst-No: 2 Write Address: 0003df65 WriteData: adf3405b
|
# Status: Burst-No: 2 Write Address: 0003df65 WriteData: adf3405b
|
# tb_core.u_sdram32 : at time 54487.0 ns WRITE: Bank = 3 Row = 61, Col = 220, Data = e455f0c8
|
# tb_core.u_sdram32 : at time 55537.0 ns WRITE: Bank = 3 Row = 61, Col = 220, Data = e455f0c8
|
# Status: Burst-No: 3 Write Address: 0003df65 WriteData: e455f0c8
|
# Status: Burst-No: 3 Write Address: 0003df65 WriteData: e455f0c8
|
# tb_core.u_sdram32 : at time 54497.0 ns WRITE: Bank = 3 Row = 61, Col = 221, Data = 24673948
|
# tb_core.u_sdram32 : at time 55547.0 ns WRITE: Bank = 3 Row = 61, Col = 221, Data = 24673948
|
# Status: Burst-No: 4 Write Address: 0003df65 WriteData: 24673948
|
# Status: Burst-No: 4 Write Address: 0003df65 WriteData: 24673948
|
# tb_core.u_sdram32 : at time 54507.0 ns WRITE: Bank = 3 Row = 61, Col = 222, Data = 9bf8f237
|
# tb_core.u_sdram32 : at time 55557.0 ns WRITE: Bank = 3 Row = 61, Col = 222, Data = 9bf8f237
|
# Status: Burst-No: 5 Write Address: 0003df65 WriteData: 9bf8f237
|
# Status: Burst-No: 5 Write Address: 0003df65 WriteData: 9bf8f237
|
# tb_core.u_sdram32 : at time 54517.0 ns WRITE: Bank = 3 Row = 61, Col = 223, Data = 7c1df3f8
|
# tb_core.u_sdram32 : at time 55567.0 ns WRITE: Bank = 3 Row = 61, Col = 223, Data = 7c1df3f8
|
# Status: Burst-No: 6 Write Address: 0003df65 WriteData: 7c1df3f8
|
# Status: Burst-No: 6 Write Address: 0003df65 WriteData: 7c1df3f8
|
# tb_core.u_sdram32 : at time 54527.0 ns WRITE: Bank = 3 Row = 61, Col = 224, Data = da8932b5
|
# tb_core.u_sdram32 : at time 55577.0 ns WRITE: Bank = 3 Row = 61, Col = 224, Data = da8932b5
|
# Status: Burst-No: 7 Write Address: 0003df65 WriteData: da8932b5
|
# Status: Burst-No: 7 Write Address: 0003df65 WriteData: da8932b5
|
# tb_core.u_sdram32 : at time 54537.0 ns WRITE: Bank = 3 Row = 61, Col = 225, Data = 28d6a951
|
# tb_core.u_sdram32 : at time 55587.0 ns WRITE: Bank = 3 Row = 61, Col = 225, Data = 28d6a951
|
# Status: Burst-No: 8 Write Address: 0003df65 WriteData: 28d6a951
|
# Status: Burst-No: 8 Write Address: 0003df65 WriteData: 28d6a951
|
# tb_core.u_sdram32 : at time 54547.0 ns WRITE: Bank = 3 Row = 61, Col = 226, Data = 41aed583
|
# tb_core.u_sdram32 : at time 55597.0 ns WRITE: Bank = 3 Row = 61, Col = 226, Data = 41aed583
|
# Status: Burst-No: 9 Write Address: 0003df65 WriteData: 41aed583
|
# Status: Burst-No: 9 Write Address: 0003df65 WriteData: 41aed583
|
# tb_core.u_sdram32 : at time 54557.0 ns WRITE: Bank = 3 Row = 61, Col = 227, Data = 4d9ee39b
|
# tb_core.u_sdram32 : at time 55607.0 ns WRITE: Bank = 3 Row = 61, Col = 227, Data = 4d9ee39b
|
# Status: Burst-No: 10 Write Address: 0003df65 WriteData: 4d9ee39b
|
# Status: Burst-No: 10 Write Address: 0003df65 WriteData: 4d9ee39b
|
# tb_core.u_sdram32 : at time 54567.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 55617.0 ns BST : Burst Terminate
|
# Write Address: 0020dd35, Burst Size: 1
|
# Write Address: 0020dd35, Burst Size: 1
|
# tb_core.u_sdram32 : at time 54727.0 ns ACT : Bank = 3 Row = 525
|
# tb_core.u_sdram32 : at time 55777.0 ns ACT : Bank = 3 Row = 525
|
# tb_core.u_sdram32 : at time 54767.0 ns WRITE: Bank = 3 Row = 525, Col = 77, Data = fddf82fb
|
# tb_core.u_sdram32 : at time 55817.0 ns WRITE: Bank = 3 Row = 525, Col = 77, Data = fddf82fb
|
# Status: Burst-No: 0 Write Address: 0020dd35 WriteData: fddf82fb
|
# Status: Burst-No: 0 Write Address: 0020dd35 WriteData: fddf82fb
|
# tb_core.u_sdram32 : at time 54777.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 55827.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 54937.0 ns ACT : Bank = 3 Row = 61
|
# tb_core.u_sdram32 : at time 55987.0 ns ACT : Bank = 3 Row = 61
|
# tb_core.u_sdram32 : at time 55003.0 ns READ : Bank = 3 Row = 61, Col = 217, Data = 03703906
|
# tb_core.u_sdram32 : at time 56053.0 ns READ : Bank = 3 Row = 61, Col = 217, Data = 03703906
|
# tb_core.u_sdram32 : at time 55013.0 ns READ : Bank = 3 Row = 61, Col = 218, Data = aa138054
|
# tb_core.u_sdram32 : at time 56063.0 ns READ : Bank = 3 Row = 61, Col = 218, Data = aa138054
|
# READ STATUS: Burst-No: 0 Addr: 0003df65 Rxd: 03703906
|
# READ STATUS: Burst-No: 0 Addr: 0003df65 Rxd: 03703906
|
# tb_core.u_sdram32 : at time 55023.0 ns READ : Bank = 3 Row = 61, Col = 219, Data = adf3405b
|
# tb_core.u_sdram32 : at time 56073.0 ns READ : Bank = 3 Row = 61, Col = 219, Data = adf3405b
|
# READ STATUS: Burst-No: 1 Addr: 0003df67 Rxd: aa138054
|
# READ STATUS: Burst-No: 1 Addr: 0003df67 Rxd: aa138054
|
# tb_core.u_sdram32 : at time 55033.0 ns READ : Bank = 3 Row = 61, Col = 220, Data = e455f0c8
|
# tb_core.u_sdram32 : at time 56083.0 ns READ : Bank = 3 Row = 61, Col = 220, Data = e455f0c8
|
# READ STATUS: Burst-No: 2 Addr: 0003df69 Rxd: adf3405b
|
# READ STATUS: Burst-No: 2 Addr: 0003df69 Rxd: adf3405b
|
# tb_core.u_sdram32 : at time 55043.0 ns READ : Bank = 3 Row = 61, Col = 221, Data = 24673948
|
# tb_core.u_sdram32 : at time 56093.0 ns READ : Bank = 3 Row = 61, Col = 221, Data = 24673948
|
# READ STATUS: Burst-No: 3 Addr: 0003df6b Rxd: e455f0c8
|
# READ STATUS: Burst-No: 3 Addr: 0003df6b Rxd: e455f0c8
|
# tb_core.u_sdram32 : at time 55053.0 ns READ : Bank = 3 Row = 61, Col = 222, Data = 9bf8f237
|
# tb_core.u_sdram32 : at time 56103.0 ns READ : Bank = 3 Row = 61, Col = 222, Data = 9bf8f237
|
# READ STATUS: Burst-No: 4 Addr: 0003df6d Rxd: 24673948
|
# READ STATUS: Burst-No: 4 Addr: 0003df6d Rxd: 24673948
|
# tb_core.u_sdram32 : at time 55063.0 ns READ : Bank = 3 Row = 61, Col = 223, Data = 7c1df3f8
|
# tb_core.u_sdram32 : at time 56113.0 ns READ : Bank = 3 Row = 61, Col = 223, Data = 7c1df3f8
|
# READ STATUS: Burst-No: 5 Addr: 0003df6f Rxd: 9bf8f237
|
# READ STATUS: Burst-No: 5 Addr: 0003df6f Rxd: 9bf8f237
|
# tb_core.u_sdram32 : at time 55073.0 ns READ : Bank = 3 Row = 61, Col = 224, Data = da8932b5
|
# tb_core.u_sdram32 : at time 56123.0 ns READ : Bank = 3 Row = 61, Col = 224, Data = da8932b5
|
# READ STATUS: Burst-No: 6 Addr: 0003df71 Rxd: 7c1df3f8
|
# READ STATUS: Burst-No: 6 Addr: 0003df71 Rxd: 7c1df3f8
|
# tb_core.u_sdram32 : at time 55083.0 ns READ : Bank = 3 Row = 61, Col = 225, Data = 28d6a951
|
# tb_core.u_sdram32 : at time 56133.0 ns READ : Bank = 3 Row = 61, Col = 225, Data = 28d6a951
|
# tb_core.u_sdram32 : at time 55087.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 56137.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 7 Addr: 0003df73 Rxd: da8932b5
|
# READ STATUS: Burst-No: 7 Addr: 0003df73 Rxd: da8932b5
|
# tb_core.u_sdram32 : at time 55093.0 ns READ : Bank = 3 Row = 61, Col = 226, Data = 41aed583
|
# tb_core.u_sdram32 : at time 56143.0 ns READ : Bank = 3 Row = 61, Col = 226, Data = 41aed583
|
# READ STATUS: Burst-No: 8 Addr: 0003df75 Rxd: 28d6a951
|
# READ STATUS: Burst-No: 8 Addr: 0003df75 Rxd: 28d6a951
|
# tb_core.u_sdram32 : at time 55103.0 ns READ : Bank = 3 Row = 61, Col = 227, Data = 4d9ee39b
|
# tb_core.u_sdram32 : at time 56153.0 ns READ : Bank = 3 Row = 61, Col = 227, Data = 4d9ee39b
|
# READ STATUS: Burst-No: 9 Addr: 0003df77 Rxd: 41aed583
|
# READ STATUS: Burst-No: 9 Addr: 0003df77 Rxd: 41aed583
|
# READ STATUS: Burst-No: 10 Addr: 0003df79 Rxd: 4d9ee39b
|
# READ STATUS: Burst-No: 10 Addr: 0003df79 Rxd: 4d9ee39b
|
# tb_core.u_sdram32 : at time 55297.0 ns ACT : Bank = 3 Row = 525
|
# tb_core.u_sdram32 : at time 56347.0 ns ACT : Bank = 3 Row = 525
|
# tb_core.u_sdram32 : at time 55347.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 56447.0 ns AREF : Auto Refresh
|
# tb_core.u_sdram32 : at time 55363.0 ns READ : Bank = 3 Row = 525, Col = 77, Data = fddf82fb
|
# tb_core.u_sdram32 : at time 56537.0 ns AREF : Auto Refresh
|
|
# tb_core.u_sdram32 : at time 56627.0 ns AREF : Auto Refresh
|
|
# tb_core.u_sdram32 : at time 56717.0 ns AREF : Auto Refresh
|
|
# tb_core.u_sdram32 : at time 56807.0 ns AREF : Auto Refresh
|
|
# tb_core.u_sdram32 : at time 56897.0 ns AREF : Auto Refresh
|
|
# tb_core.u_sdram32 : at time 56987.0 ns ACT : Bank = 3 Row = 525
|
|
# tb_core.u_sdram32 : at time 57037.0 ns BST : Burst Terminate
|
|
# tb_core.u_sdram32 : at time 57053.0 ns READ : Bank = 3 Row = 525, Col = 77, Data = fddf82fb
|
# READ STATUS: Burst-No: 0 Addr: 0020dd35 Rxd: fddf82fb
|
# READ STATUS: Burst-No: 0 Addr: 0020dd35 Rxd: fddf82fb
|
# Write Address: 000dbb4f, Burst Size: 1
|
# Write Address: 000dbb4f, Burst Size: 1
|
# tb_core.u_sdram32 : at time 55557.0 ns ACT : Bank = 2 Row = 219
|
# tb_core.u_sdram32 : at time 57247.0 ns ACT : Bank = 2 Row = 219
|
# tb_core.u_sdram32 : at time 55597.0 ns WRITE: Bank = 2 Row = 219, Col = 211, Data = 8c38c418
|
# tb_core.u_sdram32 : at time 57287.0 ns WRITE: Bank = 2 Row = 219, Col = 211, Data = 8c38c418
|
# Status: Burst-No: 0 Write Address: 000dbb4f WriteData: 8c38c418
|
# Status: Burst-No: 0 Write Address: 000dbb4f WriteData: 8c38c418
|
# tb_core.u_sdram32 : at time 55607.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 57297.0 ns BST : Burst Terminate
|
# Write Address: 000118dd, Burst Size: 7
|
# Write Address: 000118dd, Burst Size: 7
|
# tb_core.u_sdram32 : at time 55767.0 ns ACT : Bank = 2 Row = 17
|
# tb_core.u_sdram32 : at time 57457.0 ns ACT : Bank = 2 Row = 17
|
# tb_core.u_sdram32 : at time 55807.0 ns WRITE: Bank = 2 Row = 17, Col = 55, Data = 30e20f61
|
# tb_core.u_sdram32 : at time 57497.0 ns WRITE: Bank = 2 Row = 17, Col = 55, Data = 30e20f61
|
# Status: Burst-No: 0 Write Address: 000118dd WriteData: 30e20f61
|
# Status: Burst-No: 0 Write Address: 000118dd WriteData: 30e20f61
|
# tb_core.u_sdram32 : at time 55817.0 ns WRITE: Bank = 2 Row = 17, Col = 56, Data = ac974859
|
# tb_core.u_sdram32 : at time 57507.0 ns WRITE: Bank = 2 Row = 17, Col = 56, Data = ac974859
|
# Status: Burst-No: 1 Write Address: 000118dd WriteData: ac974859
|
# Status: Burst-No: 1 Write Address: 000118dd WriteData: ac974859
|
# tb_core.u_sdram32 : at time 55827.0 ns WRITE: Bank = 2 Row = 17, Col = 57, Data = 2af17355
|
# tb_core.u_sdram32 : at time 57517.0 ns WRITE: Bank = 2 Row = 17, Col = 57, Data = 2af17355
|
# Status: Burst-No: 2 Write Address: 000118dd WriteData: 2af17355
|
# Status: Burst-No: 2 Write Address: 000118dd WriteData: 2af17355
|
# tb_core.u_sdram32 : at time 55837.0 ns WRITE: Bank = 2 Row = 17, Col = 58, Data = 178b972f
|
# tb_core.u_sdram32 : at time 57527.0 ns WRITE: Bank = 2 Row = 17, Col = 58, Data = 178b972f
|
# Status: Burst-No: 3 Write Address: 000118dd WriteData: 178b972f
|
# Status: Burst-No: 3 Write Address: 000118dd WriteData: 178b972f
|
# tb_core.u_sdram32 : at time 55847.0 ns WRITE: Bank = 2 Row = 17, Col = 59, Data = 85ce500b
|
# tb_core.u_sdram32 : at time 57537.0 ns WRITE: Bank = 2 Row = 17, Col = 59, Data = 85ce500b
|
# Status: Burst-No: 4 Write Address: 000118dd WriteData: 85ce500b
|
# Status: Burst-No: 4 Write Address: 000118dd WriteData: 85ce500b
|
# tb_core.u_sdram32 : at time 55857.0 ns WRITE: Bank = 2 Row = 17, Col = 60, Data = ef1deade
|
# tb_core.u_sdram32 : at time 57547.0 ns WRITE: Bank = 2 Row = 17, Col = 60, Data = ef1deade
|
# Status: Burst-No: 5 Write Address: 000118dd WriteData: ef1deade
|
# Status: Burst-No: 5 Write Address: 000118dd WriteData: ef1deade
|
# tb_core.u_sdram32 : at time 55867.0 ns WRITE: Bank = 2 Row = 17, Col = 61, Data = e9d22cd3
|
# tb_core.u_sdram32 : at time 57557.0 ns WRITE: Bank = 2 Row = 17, Col = 61, Data = e9d22cd3
|
# Status: Burst-No: 6 Write Address: 000118dd WriteData: e9d22cd3
|
# Status: Burst-No: 6 Write Address: 000118dd WriteData: e9d22cd3
|
# tb_core.u_sdram32 : at time 55877.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 57567.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 56037.0 ns ACT : Bank = 2 Row = 219
|
# tb_core.u_sdram32 : at time 57727.0 ns ACT : Bank = 2 Row = 219
|
# tb_core.u_sdram32 : at time 56087.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 57777.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 56103.0 ns READ : Bank = 2 Row = 219, Col = 211, Data = 8c38c418
|
# tb_core.u_sdram32 : at time 57793.0 ns READ : Bank = 2 Row = 219, Col = 211, Data = 8c38c418
|
# READ STATUS: Burst-No: 0 Addr: 000dbb4f Rxd: 8c38c418
|
# READ STATUS: Burst-No: 0 Addr: 000dbb4f Rxd: 8c38c418
|
# tb_core.u_sdram32 : at time 56297.0 ns ACT : Bank = 2 Row = 17
|
# tb_core.u_sdram32 : at time 57987.0 ns ACT : Bank = 2 Row = 17
|
# tb_core.u_sdram32 : at time 56363.0 ns READ : Bank = 2 Row = 17, Col = 55, Data = 30e20f61
|
# tb_core.u_sdram32 : at time 58053.0 ns READ : Bank = 2 Row = 17, Col = 55, Data = 30e20f61
|
# tb_core.u_sdram32 : at time 56373.0 ns READ : Bank = 2 Row = 17, Col = 56, Data = ac974859
|
# tb_core.u_sdram32 : at time 58063.0 ns READ : Bank = 2 Row = 17, Col = 56, Data = ac974859
|
# READ STATUS: Burst-No: 0 Addr: 000118dd Rxd: 30e20f61
|
# READ STATUS: Burst-No: 0 Addr: 000118dd Rxd: 30e20f61
|
# tb_core.u_sdram32 : at time 56383.0 ns READ : Bank = 2 Row = 17, Col = 57, Data = 2af17355
|
# tb_core.u_sdram32 : at time 58073.0 ns READ : Bank = 2 Row = 17, Col = 57, Data = 2af17355
|
# READ STATUS: Burst-No: 1 Addr: 000118df Rxd: ac974859
|
# READ STATUS: Burst-No: 1 Addr: 000118df Rxd: ac974859
|
# tb_core.u_sdram32 : at time 56393.0 ns READ : Bank = 2 Row = 17, Col = 58, Data = 178b972f
|
# tb_core.u_sdram32 : at time 58083.0 ns READ : Bank = 2 Row = 17, Col = 58, Data = 178b972f
|
# READ STATUS: Burst-No: 2 Addr: 000118e1 Rxd: 2af17355
|
# READ STATUS: Burst-No: 2 Addr: 000118e1 Rxd: 2af17355
|
# tb_core.u_sdram32 : at time 56403.0 ns READ : Bank = 2 Row = 17, Col = 59, Data = 85ce500b
|
# tb_core.u_sdram32 : at time 58093.0 ns READ : Bank = 2 Row = 17, Col = 59, Data = 85ce500b
|
# tb_core.u_sdram32 : at time 56407.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 58097.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 3 Addr: 000118e3 Rxd: 178b972f
|
# READ STATUS: Burst-No: 3 Addr: 000118e3 Rxd: 178b972f
|
# tb_core.u_sdram32 : at time 56413.0 ns READ : Bank = 2 Row = 17, Col = 60, Data = ef1deade
|
# tb_core.u_sdram32 : at time 58103.0 ns READ : Bank = 2 Row = 17, Col = 60, Data = ef1deade
|
# READ STATUS: Burst-No: 4 Addr: 000118e5 Rxd: 85ce500b
|
# READ STATUS: Burst-No: 4 Addr: 000118e5 Rxd: 85ce500b
|
# tb_core.u_sdram32 : at time 56423.0 ns READ : Bank = 2 Row = 17, Col = 61, Data = e9d22cd3
|
# tb_core.u_sdram32 : at time 58113.0 ns READ : Bank = 2 Row = 17, Col = 61, Data = e9d22cd3
|
# READ STATUS: Burst-No: 5 Addr: 000118e7 Rxd: ef1deade
|
# READ STATUS: Burst-No: 5 Addr: 000118e7 Rxd: ef1deade
|
# READ STATUS: Burst-No: 6 Addr: 000118e9 Rxd: e9d22cd3
|
# READ STATUS: Burst-No: 6 Addr: 000118e9 Rxd: e9d22cd3
|
# tb_core.u_sdram32 : at time 56457.0 ns AREF : Auto Refresh
|
|
# tb_core.u_sdram32 : at time 56547.0 ns AREF : Auto Refresh
|
|
# Write Address: 0005b128, Burst Size: 10
|
# Write Address: 0005b128, Burst Size: 10
|
# tb_core.u_sdram32 : at time 56637.0 ns AREF : Auto Refresh
|
# tb_core.u_sdram32 : at time 58307.0 ns ACT : Bank = 0 Row = 91
|
# tb_core.u_sdram32 : at time 56727.0 ns AREF : Auto Refresh
|
# tb_core.u_sdram32 : at time 58347.0 ns WRITE: Bank = 0 Row = 91, Col = 74, Data = 2c577958
|
# tb_core.u_sdram32 : at time 56817.0 ns AREF : Auto Refresh
|
|
# tb_core.u_sdram32 : at time 56907.0 ns AREF : Auto Refresh
|
|
# tb_core.u_sdram32 : at time 57037.0 ns ACT : Bank = 0 Row = 91
|
|
# tb_core.u_sdram32 : at time 57077.0 ns WRITE: Bank = 0 Row = 91, Col = 74, Data = 2c577958
|
|
# Status: Burst-No: 0 Write Address: 0005b128 WriteData: 2c577958
|
# Status: Burst-No: 0 Write Address: 0005b128 WriteData: 2c577958
|
# tb_core.u_sdram32 : at time 57087.0 ns WRITE: Bank = 0 Row = 91, Col = 75, Data = 6aa4a1d5
|
# tb_core.u_sdram32 : at time 58357.0 ns WRITE: Bank = 0 Row = 91, Col = 75, Data = 6aa4a1d5
|
# Status: Burst-No: 1 Write Address: 0005b128 WriteData: 6aa4a1d5
|
# Status: Burst-No: 1 Write Address: 0005b128 WriteData: 6aa4a1d5
|
# tb_core.u_sdram32 : at time 57097.0 ns WRITE: Bank = 0 Row = 91, Col = 76, Data = 61dbe5c3
|
# tb_core.u_sdram32 : at time 58367.0 ns WRITE: Bank = 0 Row = 91, Col = 76, Data = 61dbe5c3
|
# Status: Burst-No: 2 Write Address: 0005b128 WriteData: 61dbe5c3
|
# Status: Burst-No: 2 Write Address: 0005b128 WriteData: 61dbe5c3
|
# tb_core.u_sdram32 : at time 57107.0 ns WRITE: Bank = 0 Row = 91, Col = 77, Data = 6a2c13d4
|
# tb_core.u_sdram32 : at time 58377.0 ns WRITE: Bank = 0 Row = 91, Col = 77, Data = 6a2c13d4
|
# Status: Burst-No: 3 Write Address: 0005b128 WriteData: 6a2c13d4
|
# Status: Burst-No: 3 Write Address: 0005b128 WriteData: 6a2c13d4
|
# tb_core.u_sdram32 : at time 57117.0 ns WRITE: Bank = 0 Row = 91, Col = 78, Data = 52397da4
|
# tb_core.u_sdram32 : at time 58387.0 ns WRITE: Bank = 0 Row = 91, Col = 78, Data = 52397da4
|
# Status: Burst-No: 4 Write Address: 0005b128 WriteData: 52397da4
|
# Status: Burst-No: 4 Write Address: 0005b128 WriteData: 52397da4
|
# tb_core.u_sdram32 : at time 57127.0 ns WRITE: Bank = 0 Row = 91, Col = 79, Data = 3f25ef7e
|
# tb_core.u_sdram32 : at time 58397.0 ns WRITE: Bank = 0 Row = 91, Col = 79, Data = 3f25ef7e
|
# Status: Burst-No: 5 Write Address: 0005b128 WriteData: 3f25ef7e
|
# Status: Burst-No: 5 Write Address: 0005b128 WriteData: 3f25ef7e
|
# tb_core.u_sdram32 : at time 57137.0 ns WRITE: Bank = 0 Row = 91, Col = 80, Data = 6b299dd6
|
# tb_core.u_sdram32 : at time 58407.0 ns WRITE: Bank = 0 Row = 91, Col = 80, Data = 6b299dd6
|
# Status: Burst-No: 6 Write Address: 0005b128 WriteData: 6b299dd6
|
# Status: Burst-No: 6 Write Address: 0005b128 WriteData: 6b299dd6
|
# tb_core.u_sdram32 : at time 57147.0 ns WRITE: Bank = 0 Row = 91, Col = 81, Data = 87eec80f
|
# tb_core.u_sdram32 : at time 58417.0 ns WRITE: Bank = 0 Row = 91, Col = 81, Data = 87eec80f
|
# Status: Burst-No: 7 Write Address: 0005b128 WriteData: 87eec80f
|
# Status: Burst-No: 7 Write Address: 0005b128 WriteData: 87eec80f
|
# tb_core.u_sdram32 : at time 57157.0 ns WRITE: Bank = 0 Row = 91, Col = 82, Data = c1b04483
|
# tb_core.u_sdram32 : at time 58427.0 ns WRITE: Bank = 0 Row = 91, Col = 82, Data = c1b04483
|
# Status: Burst-No: 8 Write Address: 0005b128 WriteData: c1b04483
|
# Status: Burst-No: 8 Write Address: 0005b128 WriteData: c1b04483
|
# tb_core.u_sdram32 : at time 57167.0 ns WRITE: Bank = 0 Row = 91, Col = 83, Data = 506aefa0
|
# tb_core.u_sdram32 : at time 58437.0 ns WRITE: Bank = 0 Row = 91, Col = 83, Data = 506aefa0
|
# Status: Burst-No: 9 Write Address: 0005b128 WriteData: 506aefa0
|
# Status: Burst-No: 9 Write Address: 0005b128 WriteData: 506aefa0
|
# tb_core.u_sdram32 : at time 57177.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 58447.0 ns BST : Burst Terminate
|
# Write Address: 000f0482, Burst Size: 16
|
# Write Address: 000f0482, Burst Size: 16
|
# tb_core.u_sdram32 : at time 57337.0 ns ACT : Bank = 1 Row = 240
|
# tb_core.u_sdram32 : at time 58607.0 ns ACT : Bank = 1 Row = 240
|
# tb_core.u_sdram32 : at time 57377.0 ns WRITE: Bank = 1 Row = 240, Col = 32, Data = 22eadb45
|
# tb_core.u_sdram32 : at time 58647.0 ns WRITE: Bank = 1 Row = 240, Col = 32, Data = 22eadb45
|
# Status: Burst-No: 0 Write Address: 000f0482 WriteData: 22eadb45
|
# Status: Burst-No: 0 Write Address: 000f0482 WriteData: 22eadb45
|
# tb_core.u_sdram32 : at time 57387.0 ns WRITE: Bank = 1 Row = 240, Col = 33, Data = bbbc3e77
|
# tb_core.u_sdram32 : at time 58657.0 ns WRITE: Bank = 1 Row = 240, Col = 33, Data = bbbc3e77
|
# Status: Burst-No: 1 Write Address: 000f0482 WriteData: bbbc3e77
|
# Status: Burst-No: 1 Write Address: 000f0482 WriteData: bbbc3e77
|
# tb_core.u_sdram32 : at time 57397.0 ns WRITE: Bank = 1 Row = 240, Col = 34, Data = 229d0b45
|
# tb_core.u_sdram32 : at time 58667.0 ns WRITE: Bank = 1 Row = 240, Col = 34, Data = 229d0b45
|
# Status: Burst-No: 2 Write Address: 000f0482 WriteData: 229d0b45
|
# Status: Burst-No: 2 Write Address: 000f0482 WriteData: 229d0b45
|
# tb_core.u_sdram32 : at time 57407.0 ns WRITE: Bank = 1 Row = 240, Col = 35, Data = ba941075
|
# tb_core.u_sdram32 : at time 58677.0 ns WRITE: Bank = 1 Row = 240, Col = 35, Data = ba941075
|
# Status: Burst-No: 3 Write Address: 000f0482 WriteData: ba941075
|
# Status: Burst-No: 3 Write Address: 000f0482 WriteData: ba941075
|
# tb_core.u_sdram32 : at time 57417.0 ns WRITE: Bank = 1 Row = 240, Col = 36, Data = fc670af8
|
# tb_core.u_sdram32 : at time 58687.0 ns WRITE: Bank = 1 Row = 240, Col = 36, Data = fc670af8
|
# Status: Burst-No: 4 Write Address: 000f0482 WriteData: fc670af8
|
# Status: Burst-No: 4 Write Address: 000f0482 WriteData: fc670af8
|
# tb_core.u_sdram32 : at time 57427.0 ns WRITE: Bank = 1 Row = 240, Col = 37, Data = 63323bc6
|
# tb_core.u_sdram32 : at time 58697.0 ns WRITE: Bank = 1 Row = 240, Col = 37, Data = 63323bc6
|
# Status: Burst-No: 5 Write Address: 000f0482 WriteData: 63323bc6
|
# Status: Burst-No: 5 Write Address: 000f0482 WriteData: 63323bc6
|
# tb_core.u_sdram32 : at time 57437.0 ns WRITE: Bank = 1 Row = 240, Col = 38, Data = 3601596c
|
# tb_core.u_sdram32 : at time 58707.0 ns WRITE: Bank = 1 Row = 240, Col = 38, Data = 3601596c
|
# Status: Burst-No: 6 Write Address: 000f0482 WriteData: 3601596c
|
# Status: Burst-No: 6 Write Address: 000f0482 WriteData: 3601596c
|
# tb_core.u_sdram32 : at time 57447.0 ns WRITE: Bank = 1 Row = 240, Col = 39, Data = a84e5850
|
# tb_core.u_sdram32 : at time 58717.0 ns WRITE: Bank = 1 Row = 240, Col = 39, Data = a84e5850
|
# Status: Burst-No: 7 Write Address: 000f0482 WriteData: a84e5850
|
# Status: Burst-No: 7 Write Address: 000f0482 WriteData: a84e5850
|
# tb_core.u_sdram32 : at time 57457.0 ns WRITE: Bank = 1 Row = 240, Col = 40, Data = 18bd6331
|
# tb_core.u_sdram32 : at time 58727.0 ns WRITE: Bank = 1 Row = 240, Col = 40, Data = 18bd6331
|
# Status: Burst-No: 8 Write Address: 000f0482 WriteData: 18bd6331
|
# Status: Burst-No: 8 Write Address: 000f0482 WriteData: 18bd6331
|
# tb_core.u_sdram32 : at time 57467.0 ns WRITE: Bank = 1 Row = 240, Col = 41, Data = ce10fe9c
|
# tb_core.u_sdram32 : at time 58737.0 ns WRITE: Bank = 1 Row = 240, Col = 41, Data = ce10fe9c
|
# Status: Burst-No: 9 Write Address: 000f0482 WriteData: ce10fe9c
|
# Status: Burst-No: 9 Write Address: 000f0482 WriteData: ce10fe9c
|
# tb_core.u_sdram32 : at time 57477.0 ns WRITE: Bank = 1 Row = 240, Col = 42, Data = de325cbc
|
# tb_core.u_sdram32 : at time 58747.0 ns WRITE: Bank = 1 Row = 240, Col = 42, Data = de325cbc
|
# Status: Burst-No: 10 Write Address: 000f0482 WriteData: de325cbc
|
# Status: Burst-No: 10 Write Address: 000f0482 WriteData: de325cbc
|
# tb_core.u_sdram32 : at time 57487.0 ns WRITE: Bank = 1 Row = 240, Col = 43, Data = d7e31eaf
|
# tb_core.u_sdram32 : at time 58757.0 ns WRITE: Bank = 1 Row = 240, Col = 43, Data = d7e31eaf
|
# Status: Burst-No: 11 Write Address: 000f0482 WriteData: d7e31eaf
|
# Status: Burst-No: 11 Write Address: 000f0482 WriteData: d7e31eaf
|
# tb_core.u_sdram32 : at time 57497.0 ns WRITE: Bank = 1 Row = 240, Col = 44, Data = 872d2c0e
|
# tb_core.u_sdram32 : at time 58767.0 ns WRITE: Bank = 1 Row = 240, Col = 44, Data = 872d2c0e
|
# Status: Burst-No: 12 Write Address: 000f0482 WriteData: 872d2c0e
|
# Status: Burst-No: 12 Write Address: 000f0482 WriteData: 872d2c0e
|
# tb_core.u_sdram32 : at time 57507.0 ns WRITE: Bank = 1 Row = 240, Col = 45, Data = b4e46669
|
# tb_core.u_sdram32 : at time 58777.0 ns WRITE: Bank = 1 Row = 240, Col = 45, Data = b4e46669
|
# Status: Burst-No: 13 Write Address: 000f0482 WriteData: b4e46669
|
# Status: Burst-No: 13 Write Address: 000f0482 WriteData: b4e46669
|
# tb_core.u_sdram32 : at time 57517.0 ns WRITE: Bank = 1 Row = 240, Col = 46, Data = d95b40b2
|
# tb_core.u_sdram32 : at time 58787.0 ns WRITE: Bank = 1 Row = 240, Col = 46, Data = d95b40b2
|
# Status: Burst-No: 14 Write Address: 000f0482 WriteData: d95b40b2
|
# Status: Burst-No: 14 Write Address: 000f0482 WriteData: d95b40b2
|
# tb_core.u_sdram32 : at time 57527.0 ns WRITE: Bank = 1 Row = 240, Col = 47, Data = ef209ede
|
# tb_core.u_sdram32 : at time 58797.0 ns WRITE: Bank = 1 Row = 240, Col = 47, Data = ef209ede
|
# Status: Burst-No: 15 Write Address: 000f0482 WriteData: ef209ede
|
# Status: Burst-No: 15 Write Address: 000f0482 WriteData: ef209ede
|
# tb_core.u_sdram32 : at time 57537.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 58807.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 57683.0 ns READ : Bank = 0 Row = 91, Col = 74, Data = 2c577958
|
# tb_core.u_sdram32 : at time 58953.0 ns READ : Bank = 0 Row = 91, Col = 74, Data = 2c577958
|
# tb_core.u_sdram32 : at time 57693.0 ns READ : Bank = 0 Row = 91, Col = 75, Data = 6aa4a1d5
|
# tb_core.u_sdram32 : at time 58963.0 ns READ : Bank = 0 Row = 91, Col = 75, Data = 6aa4a1d5
|
# READ STATUS: Burst-No: 0 Addr: 0005b128 Rxd: 2c577958
|
# READ STATUS: Burst-No: 0 Addr: 0005b128 Rxd: 2c577958
|
# tb_core.u_sdram32 : at time 57703.0 ns READ : Bank = 0 Row = 91, Col = 76, Data = 61dbe5c3
|
# tb_core.u_sdram32 : at time 58973.0 ns READ : Bank = 0 Row = 91, Col = 76, Data = 61dbe5c3
|
# READ STATUS: Burst-No: 1 Addr: 0005b12a Rxd: 6aa4a1d5
|
# READ STATUS: Burst-No: 1 Addr: 0005b12a Rxd: 6aa4a1d5
|
# tb_core.u_sdram32 : at time 57713.0 ns READ : Bank = 0 Row = 91, Col = 77, Data = 6a2c13d4
|
# tb_core.u_sdram32 : at time 58983.0 ns READ : Bank = 0 Row = 91, Col = 77, Data = 6a2c13d4
|
# READ STATUS: Burst-No: 2 Addr: 0005b12c Rxd: 61dbe5c3
|
# READ STATUS: Burst-No: 2 Addr: 0005b12c Rxd: 61dbe5c3
|
# tb_core.u_sdram32 : at time 57723.0 ns READ : Bank = 0 Row = 91, Col = 78, Data = 52397da4
|
# tb_core.u_sdram32 : at time 58993.0 ns READ : Bank = 0 Row = 91, Col = 78, Data = 52397da4
|
# READ STATUS: Burst-No: 3 Addr: 0005b12e Rxd: 6a2c13d4
|
# READ STATUS: Burst-No: 3 Addr: 0005b12e Rxd: 6a2c13d4
|
# tb_core.u_sdram32 : at time 57733.0 ns READ : Bank = 0 Row = 91, Col = 79, Data = 3f25ef7e
|
# tb_core.u_sdram32 : at time 59003.0 ns READ : Bank = 0 Row = 91, Col = 79, Data = 3f25ef7e
|
# READ STATUS: Burst-No: 4 Addr: 0005b130 Rxd: 52397da4
|
# READ STATUS: Burst-No: 4 Addr: 0005b130 Rxd: 52397da4
|
# tb_core.u_sdram32 : at time 57743.0 ns READ : Bank = 0 Row = 91, Col = 80, Data = 6b299dd6
|
# tb_core.u_sdram32 : at time 59013.0 ns READ : Bank = 0 Row = 91, Col = 80, Data = 6b299dd6
|
# READ STATUS: Burst-No: 5 Addr: 0005b132 Rxd: 3f25ef7e
|
# READ STATUS: Burst-No: 5 Addr: 0005b132 Rxd: 3f25ef7e
|
# tb_core.u_sdram32 : at time 57753.0 ns READ : Bank = 0 Row = 91, Col = 81, Data = 87eec80f
|
# tb_core.u_sdram32 : at time 59023.0 ns READ : Bank = 0 Row = 91, Col = 81, Data = 87eec80f
|
# tb_core.u_sdram32 : at time 57757.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 59027.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 6 Addr: 0005b134 Rxd: 6b299dd6
|
# READ STATUS: Burst-No: 6 Addr: 0005b134 Rxd: 6b299dd6
|
# tb_core.u_sdram32 : at time 57763.0 ns READ : Bank = 0 Row = 91, Col = 82, Data = c1b04483
|
# tb_core.u_sdram32 : at time 59033.0 ns READ : Bank = 0 Row = 91, Col = 82, Data = c1b04483
|
# READ STATUS: Burst-No: 7 Addr: 0005b136 Rxd: 87eec80f
|
# READ STATUS: Burst-No: 7 Addr: 0005b136 Rxd: 87eec80f
|
# tb_core.u_sdram32 : at time 57773.0 ns READ : Bank = 0 Row = 91, Col = 83, Data = 506aefa0
|
# tb_core.u_sdram32 : at time 59043.0 ns READ : Bank = 0 Row = 91, Col = 83, Data = 506aefa0
|
# READ STATUS: Burst-No: 8 Addr: 0005b138 Rxd: c1b04483
|
# READ STATUS: Burst-No: 8 Addr: 0005b138 Rxd: c1b04483
|
# READ STATUS: Burst-No: 9 Addr: 0005b13a Rxd: 506aefa0
|
# READ STATUS: Burst-No: 9 Addr: 0005b13a Rxd: 506aefa0
|
# tb_core.u_sdram32 : at time 57963.0 ns READ : Bank = 1 Row = 240, Col = 32, Data = 22eadb45
|
# tb_core.u_sdram32 : at time 59233.0 ns READ : Bank = 1 Row = 240, Col = 32, Data = 22eadb45
|
# tb_core.u_sdram32 : at time 57973.0 ns READ : Bank = 1 Row = 240, Col = 33, Data = bbbc3e77
|
# tb_core.u_sdram32 : at time 59243.0 ns READ : Bank = 1 Row = 240, Col = 33, Data = bbbc3e77
|
# READ STATUS: Burst-No: 0 Addr: 000f0482 Rxd: 22eadb45
|
# READ STATUS: Burst-No: 0 Addr: 000f0482 Rxd: 22eadb45
|
# tb_core.u_sdram32 : at time 57983.0 ns READ : Bank = 1 Row = 240, Col = 34, Data = 229d0b45
|
# tb_core.u_sdram32 : at time 59253.0 ns READ : Bank = 1 Row = 240, Col = 34, Data = 229d0b45
|
# READ STATUS: Burst-No: 1 Addr: 000f0484 Rxd: bbbc3e77
|
# READ STATUS: Burst-No: 1 Addr: 000f0484 Rxd: bbbc3e77
|
# tb_core.u_sdram32 : at time 57993.0 ns READ : Bank = 1 Row = 240, Col = 35, Data = ba941075
|
# tb_core.u_sdram32 : at time 59263.0 ns READ : Bank = 1 Row = 240, Col = 35, Data = ba941075
|
# READ STATUS: Burst-No: 2 Addr: 000f0486 Rxd: 229d0b45
|
# READ STATUS: Burst-No: 2 Addr: 000f0486 Rxd: 229d0b45
|
# tb_core.u_sdram32 : at time 58003.0 ns READ : Bank = 1 Row = 240, Col = 36, Data = fc670af8
|
# tb_core.u_sdram32 : at time 59273.0 ns READ : Bank = 1 Row = 240, Col = 36, Data = fc670af8
|
# READ STATUS: Burst-No: 3 Addr: 000f0488 Rxd: ba941075
|
# READ STATUS: Burst-No: 3 Addr: 000f0488 Rxd: ba941075
|
# tb_core.u_sdram32 : at time 58013.0 ns READ : Bank = 1 Row = 240, Col = 37, Data = 63323bc6
|
# tb_core.u_sdram32 : at time 59283.0 ns READ : Bank = 1 Row = 240, Col = 37, Data = 63323bc6
|
# READ STATUS: Burst-No: 4 Addr: 000f048a Rxd: fc670af8
|
# READ STATUS: Burst-No: 4 Addr: 000f048a Rxd: fc670af8
|
# tb_core.u_sdram32 : at time 58023.0 ns READ : Bank = 1 Row = 240, Col = 38, Data = 3601596c
|
# tb_core.u_sdram32 : at time 59293.0 ns READ : Bank = 1 Row = 240, Col = 38, Data = 3601596c
|
# READ STATUS: Burst-No: 5 Addr: 000f048c Rxd: 63323bc6
|
# READ STATUS: Burst-No: 5 Addr: 000f048c Rxd: 63323bc6
|
# tb_core.u_sdram32 : at time 58033.0 ns READ : Bank = 1 Row = 240, Col = 39, Data = a84e5850
|
# tb_core.u_sdram32 : at time 59303.0 ns READ : Bank = 1 Row = 240, Col = 39, Data = a84e5850
|
# READ STATUS: Burst-No: 6 Addr: 000f048e Rxd: 3601596c
|
# READ STATUS: Burst-No: 6 Addr: 000f048e Rxd: 3601596c
|
# tb_core.u_sdram32 : at time 58043.0 ns READ : Bank = 1 Row = 240, Col = 40, Data = 18bd6331
|
# tb_core.u_sdram32 : at time 59313.0 ns READ : Bank = 1 Row = 240, Col = 40, Data = 18bd6331
|
# READ STATUS: Burst-No: 7 Addr: 000f0490 Rxd: a84e5850
|
# READ STATUS: Burst-No: 7 Addr: 000f0490 Rxd: a84e5850
|
# tb_core.u_sdram32 : at time 58053.0 ns READ : Bank = 1 Row = 240, Col = 41, Data = ce10fe9c
|
# tb_core.u_sdram32 : at time 59323.0 ns READ : Bank = 1 Row = 240, Col = 41, Data = ce10fe9c
|
# READ STATUS: Burst-No: 8 Addr: 000f0492 Rxd: 18bd6331
|
# READ STATUS: Burst-No: 8 Addr: 000f0492 Rxd: 18bd6331
|
# tb_core.u_sdram32 : at time 58063.0 ns READ : Bank = 1 Row = 240, Col = 42, Data = de325cbc
|
# tb_core.u_sdram32 : at time 59333.0 ns READ : Bank = 1 Row = 240, Col = 42, Data = de325cbc
|
# READ STATUS: Burst-No: 9 Addr: 000f0494 Rxd: ce10fe9c
|
# READ STATUS: Burst-No: 9 Addr: 000f0494 Rxd: ce10fe9c
|
# tb_core.u_sdram32 : at time 58073.0 ns READ : Bank = 1 Row = 240, Col = 43, Data = d7e31eaf
|
# tb_core.u_sdram32 : at time 59343.0 ns READ : Bank = 1 Row = 240, Col = 43, Data = d7e31eaf
|
# READ STATUS: Burst-No: 10 Addr: 000f0496 Rxd: de325cbc
|
# READ STATUS: Burst-No: 10 Addr: 000f0496 Rxd: de325cbc
|
# tb_core.u_sdram32 : at time 58083.0 ns READ : Bank = 1 Row = 240, Col = 44, Data = 872d2c0e
|
# tb_core.u_sdram32 : at time 59353.0 ns READ : Bank = 1 Row = 240, Col = 44, Data = 872d2c0e
|
# READ STATUS: Burst-No: 11 Addr: 000f0498 Rxd: d7e31eaf
|
# READ STATUS: Burst-No: 11 Addr: 000f0498 Rxd: d7e31eaf
|
# tb_core.u_sdram32 : at time 58093.0 ns READ : Bank = 1 Row = 240, Col = 45, Data = b4e46669
|
# tb_core.u_sdram32 : at time 59363.0 ns READ : Bank = 1 Row = 240, Col = 45, Data = b4e46669
|
# tb_core.u_sdram32 : at time 58097.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 59367.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 12 Addr: 000f049a Rxd: 872d2c0e
|
# READ STATUS: Burst-No: 12 Addr: 000f049a Rxd: 872d2c0e
|
# tb_core.u_sdram32 : at time 58103.0 ns READ : Bank = 1 Row = 240, Col = 46, Data = d95b40b2
|
# tb_core.u_sdram32 : at time 59373.0 ns READ : Bank = 1 Row = 240, Col = 46, Data = d95b40b2
|
# READ STATUS: Burst-No: 13 Addr: 000f049c Rxd: b4e46669
|
# READ STATUS: Burst-No: 13 Addr: 000f049c Rxd: b4e46669
|
# tb_core.u_sdram32 : at time 58113.0 ns READ : Bank = 1 Row = 240, Col = 47, Data = ef209ede
|
# tb_core.u_sdram32 : at time 59383.0 ns READ : Bank = 1 Row = 240, Col = 47, Data = ef209ede
|
# READ STATUS: Burst-No: 14 Addr: 000f049e Rxd: d95b40b2
|
# READ STATUS: Burst-No: 14 Addr: 000f049e Rxd: d95b40b2
|
# READ STATUS: Burst-No: 15 Addr: 000f04a0 Rxd: ef209ede
|
# READ STATUS: Burst-No: 15 Addr: 000f04a0 Rxd: ef209ede
|
# Write Address: 00287485, Burst Size: 11
|
# Write Address: 00287485, Burst Size: 11
|
# tb_core.u_sdram32 : at time 58307.0 ns ACT : Bank = 1 Row = 647
|
# tb_core.u_sdram32 : at time 59577.0 ns ACT : Bank = 1 Row = 647
|
# tb_core.u_sdram32 : at time 58347.0 ns WRITE: Bank = 1 Row = 647, Col = 33, Data = 1407f128
|
# tb_core.u_sdram32 : at time 59617.0 ns WRITE: Bank = 1 Row = 647, Col = 33, Data = 1407f128
|
# Status: Burst-No: 0 Write Address: 00287485 WriteData: 1407f128
|
# Status: Burst-No: 0 Write Address: 00287485 WriteData: 1407f128
|
# tb_core.u_sdram32 : at time 58357.0 ns WRITE: Bank = 1 Row = 647, Col = 34, Data = 610ed5c2
|
# tb_core.u_sdram32 : at time 59627.0 ns WRITE: Bank = 1 Row = 647, Col = 34, Data = 610ed5c2
|
# Status: Burst-No: 1 Write Address: 00287485 WriteData: 610ed5c2
|
# Status: Burst-No: 1 Write Address: 00287485 WriteData: 610ed5c2
|
# tb_core.u_sdram32 : at time 58367.0 ns WRITE: Bank = 1 Row = 647, Col = 35, Data = 4d20099a
|
# tb_core.u_sdram32 : at time 59637.0 ns WRITE: Bank = 1 Row = 647, Col = 35, Data = 4d20099a
|
# Status: Burst-No: 2 Write Address: 00287485 WriteData: 4d20099a
|
# Status: Burst-No: 2 Write Address: 00287485 WriteData: 4d20099a
|
# tb_core.u_sdram32 : at time 58377.0 ns WRITE: Bank = 1 Row = 647, Col = 36, Data = 69e751d3
|
# tb_core.u_sdram32 : at time 59647.0 ns WRITE: Bank = 1 Row = 647, Col = 36, Data = 69e751d3
|
# Status: Burst-No: 3 Write Address: 00287485 WriteData: 69e751d3
|
# Status: Burst-No: 3 Write Address: 00287485 WriteData: 69e751d3
|
# tb_core.u_sdram32 : at time 58387.0 ns WRITE: Bank = 1 Row = 647, Col = 37, Data = dd111aba
|
# tb_core.u_sdram32 : at time 59657.0 ns WRITE: Bank = 1 Row = 647, Col = 37, Data = dd111aba
|
# Status: Burst-No: 4 Write Address: 00287485 WriteData: dd111aba
|
# Status: Burst-No: 4 Write Address: 00287485 WriteData: dd111aba
|
# tb_core.u_sdram32 : at time 58397.0 ns WRITE: Bank = 1 Row = 647, Col = 38, Data = fdeb7cfb
|
# tb_core.u_sdram32 : at time 59667.0 ns WRITE: Bank = 1 Row = 647, Col = 38, Data = fdeb7cfb
|
# Status: Burst-No: 5 Write Address: 00287485 WriteData: fdeb7cfb
|
# Status: Burst-No: 5 Write Address: 00287485 WriteData: fdeb7cfb
|
# tb_core.u_sdram32 : at time 58407.0 ns WRITE: Bank = 1 Row = 647, Col = 39, Data = c5cf728b
|
# tb_core.u_sdram32 : at time 59677.0 ns WRITE: Bank = 1 Row = 647, Col = 39, Data = c5cf728b
|
# Status: Burst-No: 6 Write Address: 00287485 WriteData: c5cf728b
|
# Status: Burst-No: 6 Write Address: 00287485 WriteData: c5cf728b
|
# tb_core.u_sdram32 : at time 58417.0 ns WRITE: Bank = 1 Row = 647, Col = 40, Data = 61114dc2
|
# tb_core.u_sdram32 : at time 59687.0 ns WRITE: Bank = 1 Row = 647, Col = 40, Data = 61114dc2
|
# Status: Burst-No: 7 Write Address: 00287485 WriteData: 61114dc2
|
# Status: Burst-No: 7 Write Address: 00287485 WriteData: 61114dc2
|
# tb_core.u_sdram32 : at time 58427.0 ns WRITE: Bank = 1 Row = 647, Col = 41, Data = e64828cc
|
# tb_core.u_sdram32 : at time 59697.0 ns WRITE: Bank = 1 Row = 647, Col = 41, Data = e64828cc
|
# Status: Burst-No: 8 Write Address: 00287485 WriteData: e64828cc
|
# Status: Burst-No: 8 Write Address: 00287485 WriteData: e64828cc
|
# tb_core.u_sdram32 : at time 58437.0 ns WRITE: Bank = 1 Row = 647, Col = 42, Data = 38e61371
|
# tb_core.u_sdram32 : at time 59707.0 ns WRITE: Bank = 1 Row = 647, Col = 42, Data = 38e61371
|
# Status: Burst-No: 9 Write Address: 00287485 WriteData: 38e61371
|
# Status: Burst-No: 9 Write Address: 00287485 WriteData: 38e61371
|
# tb_core.u_sdram32 : at time 58447.0 ns WRITE: Bank = 1 Row = 647, Col = 43, Data = 4f49019e
|
# tb_core.u_sdram32 : at time 59717.0 ns WRITE: Bank = 1 Row = 647, Col = 43, Data = 4f49019e
|
# Status: Burst-No: 10 Write Address: 00287485 WriteData: 4f49019e
|
# Status: Burst-No: 10 Write Address: 00287485 WriteData: 4f49019e
|
# tb_core.u_sdram32 : at time 58457.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 59727.0 ns BST : Burst Terminate
|
# Write Address: 001cdb61, Burst Size: 12
|
# Write Address: 001cdb61, Burst Size: 12
|
# tb_core.u_sdram32 : at time 58617.0 ns ACT : Bank = 2 Row = 461
|
# tb_core.u_sdram32 : at time 59887.0 ns ACT : Bank = 2 Row = 461
|
# tb_core.u_sdram32 : at time 58657.0 ns WRITE: Bank = 2 Row = 461, Col = 216, Data = df9bd0bf
|
# tb_core.u_sdram32 : at time 59927.0 ns WRITE: Bank = 2 Row = 461, Col = 216, Data = df9bd0bf
|
# Status: Burst-No: 0 Write Address: 001cdb61 WriteData: df9bd0bf
|
# Status: Burst-No: 0 Write Address: 001cdb61 WriteData: df9bd0bf
|
# tb_core.u_sdram32 : at time 58667.0 ns WRITE: Bank = 2 Row = 461, Col = 217, Data = c881bc91
|
# tb_core.u_sdram32 : at time 59937.0 ns WRITE: Bank = 2 Row = 461, Col = 217, Data = c881bc91
|
# Status: Burst-No: 1 Write Address: 001cdb61 WriteData: c881bc91
|
# Status: Burst-No: 1 Write Address: 001cdb61 WriteData: c881bc91
|
# tb_core.u_sdram32 : at time 58677.0 ns WRITE: Bank = 2 Row = 461, Col = 218, Data = e06098c0
|
# tb_core.u_sdram32 : at time 59947.0 ns WRITE: Bank = 2 Row = 461, Col = 218, Data = e06098c0
|
# Status: Burst-No: 2 Write Address: 001cdb61 WriteData: e06098c0
|
# Status: Burst-No: 2 Write Address: 001cdb61 WriteData: e06098c0
|
# tb_core.u_sdram32 : at time 58687.0 ns WRITE: Bank = 2 Row = 461, Col = 219, Data = 2ca96359
|
# tb_core.u_sdram32 : at time 59957.0 ns WRITE: Bank = 2 Row = 461, Col = 219, Data = 2ca96359
|
# Status: Burst-No: 3 Write Address: 001cdb61 WriteData: 2ca96359
|
# Status: Burst-No: 3 Write Address: 001cdb61 WriteData: 2ca96359
|
# tb_core.u_sdram32 : at time 58697.0 ns WRITE: Bank = 2 Row = 461, Col = 220, Data = bf53b47e
|
# tb_core.u_sdram32 : at time 59967.0 ns WRITE: Bank = 2 Row = 461, Col = 220, Data = bf53b47e
|
# Status: Burst-No: 4 Write Address: 001cdb61 WriteData: bf53b47e
|
# Status: Burst-No: 4 Write Address: 001cdb61 WriteData: bf53b47e
|
# tb_core.u_sdram32 : at time 58707.0 ns WRITE: Bank = 2 Row = 461, Col = 221, Data = 2a1d7354
|
# tb_core.u_sdram32 : at time 59977.0 ns WRITE: Bank = 2 Row = 461, Col = 221, Data = 2a1d7354
|
# Status: Burst-No: 5 Write Address: 001cdb61 WriteData: 2a1d7354
|
# Status: Burst-No: 5 Write Address: 001cdb61 WriteData: 2a1d7354
|
# tb_core.u_sdram32 : at time 58717.0 ns WRITE: Bank = 2 Row = 461, Col = 222, Data = a8e2e251
|
# tb_core.u_sdram32 : at time 59987.0 ns WRITE: Bank = 2 Row = 461, Col = 222, Data = a8e2e251
|
# Status: Burst-No: 6 Write Address: 001cdb61 WriteData: a8e2e251
|
# Status: Burst-No: 6 Write Address: 001cdb61 WriteData: a8e2e251
|
# tb_core.u_sdram32 : at time 58727.0 ns WRITE: Bank = 2 Row = 461, Col = 223, Data = a4de2849
|
# tb_core.u_sdram32 : at time 59997.0 ns WRITE: Bank = 2 Row = 461, Col = 223, Data = a4de2849
|
# Status: Burst-No: 7 Write Address: 001cdb61 WriteData: a4de2849
|
# Status: Burst-No: 7 Write Address: 001cdb61 WriteData: a4de2849
|
# tb_core.u_sdram32 : at time 58737.0 ns WRITE: Bank = 2 Row = 461, Col = 224, Data = 73fa7de7
|
# tb_core.u_sdram32 : at time 60007.0 ns WRITE: Bank = 2 Row = 461, Col = 224, Data = 73fa7de7
|
# Status: Burst-No: 8 Write Address: 001cdb61 WriteData: 73fa7de7
|
# Status: Burst-No: 8 Write Address: 001cdb61 WriteData: 73fa7de7
|
# tb_core.u_sdram32 : at time 58747.0 ns WRITE: Bank = 2 Row = 461, Col = 225, Data = 123aaf24
|
# tb_core.u_sdram32 : at time 60017.0 ns WRITE: Bank = 2 Row = 461, Col = 225, Data = 123aaf24
|
# Status: Burst-No: 9 Write Address: 001cdb61 WriteData: 123aaf24
|
# Status: Burst-No: 9 Write Address: 001cdb61 WriteData: 123aaf24
|
# tb_core.u_sdram32 : at time 58757.0 ns WRITE: Bank = 2 Row = 461, Col = 226, Data = 41b5d583
|
# tb_core.u_sdram32 : at time 60027.0 ns WRITE: Bank = 2 Row = 461, Col = 226, Data = 41b5d583
|
# Status: Burst-No: 10 Write Address: 001cdb61 WriteData: 41b5d583
|
# Status: Burst-No: 10 Write Address: 001cdb61 WriteData: 41b5d583
|
# tb_core.u_sdram32 : at time 58767.0 ns WRITE: Bank = 2 Row = 461, Col = 227, Data = adee005b
|
# tb_core.u_sdram32 : at time 60037.0 ns WRITE: Bank = 2 Row = 461, Col = 227, Data = adee005b
|
# Status: Burst-No: 11 Write Address: 001cdb61 WriteData: adee005b
|
# Status: Burst-No: 11 Write Address: 001cdb61 WriteData: adee005b
|
# tb_core.u_sdram32 : at time 58777.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 60047.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 58933.0 ns READ : Bank = 1 Row = 647, Col = 33, Data = 1407f128
|
# tb_core.u_sdram32 : at time 60203.0 ns READ : Bank = 1 Row = 647, Col = 33, Data = 1407f128
|
# tb_core.u_sdram32 : at time 58943.0 ns READ : Bank = 1 Row = 647, Col = 34, Data = 610ed5c2
|
# tb_core.u_sdram32 : at time 60213.0 ns READ : Bank = 1 Row = 647, Col = 34, Data = 610ed5c2
|
# READ STATUS: Burst-No: 0 Addr: 00287485 Rxd: 1407f128
|
# READ STATUS: Burst-No: 0 Addr: 00287485 Rxd: 1407f128
|
# tb_core.u_sdram32 : at time 58953.0 ns READ : Bank = 1 Row = 647, Col = 35, Data = 4d20099a
|
# tb_core.u_sdram32 : at time 60223.0 ns READ : Bank = 1 Row = 647, Col = 35, Data = 4d20099a
|
# READ STATUS: Burst-No: 1 Addr: 00287487 Rxd: 610ed5c2
|
# READ STATUS: Burst-No: 1 Addr: 00287487 Rxd: 610ed5c2
|
# tb_core.u_sdram32 : at time 58963.0 ns READ : Bank = 1 Row = 647, Col = 36, Data = 69e751d3
|
# tb_core.u_sdram32 : at time 60233.0 ns READ : Bank = 1 Row = 647, Col = 36, Data = 69e751d3
|
# READ STATUS: Burst-No: 2 Addr: 00287489 Rxd: 4d20099a
|
# READ STATUS: Burst-No: 2 Addr: 00287489 Rxd: 4d20099a
|
# tb_core.u_sdram32 : at time 58973.0 ns READ : Bank = 1 Row = 647, Col = 37, Data = dd111aba
|
# tb_core.u_sdram32 : at time 60243.0 ns READ : Bank = 1 Row = 647, Col = 37, Data = dd111aba
|
# READ STATUS: Burst-No: 3 Addr: 0028748b Rxd: 69e751d3
|
# READ STATUS: Burst-No: 3 Addr: 0028748b Rxd: 69e751d3
|
# tb_core.u_sdram32 : at time 58983.0 ns READ : Bank = 1 Row = 647, Col = 38, Data = fdeb7cfb
|
# tb_core.u_sdram32 : at time 60253.0 ns READ : Bank = 1 Row = 647, Col = 38, Data = fdeb7cfb
|
# READ STATUS: Burst-No: 4 Addr: 0028748d Rxd: dd111aba
|
# READ STATUS: Burst-No: 4 Addr: 0028748d Rxd: dd111aba
|
# tb_core.u_sdram32 : at time 58993.0 ns READ : Bank = 1 Row = 647, Col = 39, Data = c5cf728b
|
# tb_core.u_sdram32 : at time 60263.0 ns READ : Bank = 1 Row = 647, Col = 39, Data = c5cf728b
|
# READ STATUS: Burst-No: 5 Addr: 0028748f Rxd: fdeb7cfb
|
# READ STATUS: Burst-No: 5 Addr: 0028748f Rxd: fdeb7cfb
|
# tb_core.u_sdram32 : at time 59003.0 ns READ : Bank = 1 Row = 647, Col = 40, Data = 61114dc2
|
# tb_core.u_sdram32 : at time 60273.0 ns READ : Bank = 1 Row = 647, Col = 40, Data = 61114dc2
|
# READ STATUS: Burst-No: 6 Addr: 00287491 Rxd: c5cf728b
|
# READ STATUS: Burst-No: 6 Addr: 00287491 Rxd: c5cf728b
|
# tb_core.u_sdram32 : at time 59013.0 ns READ : Bank = 1 Row = 647, Col = 41, Data = e64828cc
|
# tb_core.u_sdram32 : at time 60283.0 ns READ : Bank = 1 Row = 647, Col = 41, Data = e64828cc
|
# tb_core.u_sdram32 : at time 59017.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 60287.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 7 Addr: 00287493 Rxd: 61114dc2
|
# READ STATUS: Burst-No: 7 Addr: 00287493 Rxd: 61114dc2
|
# tb_core.u_sdram32 : at time 59023.0 ns READ : Bank = 1 Row = 647, Col = 42, Data = 38e61371
|
# tb_core.u_sdram32 : at time 60293.0 ns READ : Bank = 1 Row = 647, Col = 42, Data = 38e61371
|
# READ STATUS: Burst-No: 8 Addr: 00287495 Rxd: e64828cc
|
# READ STATUS: Burst-No: 8 Addr: 00287495 Rxd: e64828cc
|
# tb_core.u_sdram32 : at time 59033.0 ns READ : Bank = 1 Row = 647, Col = 43, Data = 4f49019e
|
# tb_core.u_sdram32 : at time 60303.0 ns READ : Bank = 1 Row = 647, Col = 43, Data = 4f49019e
|
# READ STATUS: Burst-No: 9 Addr: 00287497 Rxd: 38e61371
|
# READ STATUS: Burst-No: 9 Addr: 00287497 Rxd: 38e61371
|
# READ STATUS: Burst-No: 10 Addr: 00287499 Rxd: 4f49019e
|
# READ STATUS: Burst-No: 10 Addr: 00287499 Rxd: 4f49019e
|
# tb_core.u_sdram32 : at time 59223.0 ns READ : Bank = 2 Row = 461, Col = 216, Data = df9bd0bf
|
# tb_core.u_sdram32 : at time 60493.0 ns READ : Bank = 2 Row = 461, Col = 216, Data = df9bd0bf
|
# tb_core.u_sdram32 : at time 59233.0 ns READ : Bank = 2 Row = 461, Col = 217, Data = c881bc91
|
# tb_core.u_sdram32 : at time 60503.0 ns READ : Bank = 2 Row = 461, Col = 217, Data = c881bc91
|
# READ STATUS: Burst-No: 0 Addr: 001cdb61 Rxd: df9bd0bf
|
# READ STATUS: Burst-No: 0 Addr: 001cdb61 Rxd: df9bd0bf
|
# tb_core.u_sdram32 : at time 59243.0 ns READ : Bank = 2 Row = 461, Col = 218, Data = e06098c0
|
# tb_core.u_sdram32 : at time 60513.0 ns READ : Bank = 2 Row = 461, Col = 218, Data = e06098c0
|
# READ STATUS: Burst-No: 1 Addr: 001cdb63 Rxd: c881bc91
|
# READ STATUS: Burst-No: 1 Addr: 001cdb63 Rxd: c881bc91
|
# tb_core.u_sdram32 : at time 59253.0 ns READ : Bank = 2 Row = 461, Col = 219, Data = 2ca96359
|
# tb_core.u_sdram32 : at time 60523.0 ns READ : Bank = 2 Row = 461, Col = 219, Data = 2ca96359
|
# READ STATUS: Burst-No: 2 Addr: 001cdb65 Rxd: e06098c0
|
# READ STATUS: Burst-No: 2 Addr: 001cdb65 Rxd: e06098c0
|
# tb_core.u_sdram32 : at time 59263.0 ns READ : Bank = 2 Row = 461, Col = 220, Data = bf53b47e
|
# tb_core.u_sdram32 : at time 60533.0 ns READ : Bank = 2 Row = 461, Col = 220, Data = bf53b47e
|
# READ STATUS: Burst-No: 3 Addr: 001cdb67 Rxd: 2ca96359
|
# READ STATUS: Burst-No: 3 Addr: 001cdb67 Rxd: 2ca96359
|
# tb_core.u_sdram32 : at time 59273.0 ns READ : Bank = 2 Row = 461, Col = 221, Data = 2a1d7354
|
# tb_core.u_sdram32 : at time 60543.0 ns READ : Bank = 2 Row = 461, Col = 221, Data = 2a1d7354
|
# READ STATUS: Burst-No: 4 Addr: 001cdb69 Rxd: bf53b47e
|
# READ STATUS: Burst-No: 4 Addr: 001cdb69 Rxd: bf53b47e
|
# tb_core.u_sdram32 : at time 59283.0 ns READ : Bank = 2 Row = 461, Col = 222, Data = a8e2e251
|
# tb_core.u_sdram32 : at time 60553.0 ns READ : Bank = 2 Row = 461, Col = 222, Data = a8e2e251
|
# READ STATUS: Burst-No: 5 Addr: 001cdb6b Rxd: 2a1d7354
|
# READ STATUS: Burst-No: 5 Addr: 001cdb6b Rxd: 2a1d7354
|
# tb_core.u_sdram32 : at time 59293.0 ns READ : Bank = 2 Row = 461, Col = 223, Data = a4de2849
|
# tb_core.u_sdram32 : at time 60563.0 ns READ : Bank = 2 Row = 461, Col = 223, Data = a4de2849
|
# READ STATUS: Burst-No: 6 Addr: 001cdb6d Rxd: a8e2e251
|
# READ STATUS: Burst-No: 6 Addr: 001cdb6d Rxd: a8e2e251
|
# tb_core.u_sdram32 : at time 59303.0 ns READ : Bank = 2 Row = 461, Col = 224, Data = 73fa7de7
|
# tb_core.u_sdram32 : at time 60573.0 ns READ : Bank = 2 Row = 461, Col = 224, Data = 73fa7de7
|
# READ STATUS: Burst-No: 7 Addr: 001cdb6f Rxd: a4de2849
|
# READ STATUS: Burst-No: 7 Addr: 001cdb6f Rxd: a4de2849
|
# tb_core.u_sdram32 : at time 59313.0 ns READ : Bank = 2 Row = 461, Col = 225, Data = 123aaf24
|
# tb_core.u_sdram32 : at time 60583.0 ns READ : Bank = 2 Row = 461, Col = 225, Data = 123aaf24
|
# tb_core.u_sdram32 : at time 59317.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 60587.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 8 Addr: 001cdb71 Rxd: 73fa7de7
|
# READ STATUS: Burst-No: 8 Addr: 001cdb71 Rxd: 73fa7de7
|
# tb_core.u_sdram32 : at time 59323.0 ns READ : Bank = 2 Row = 461, Col = 226, Data = 41b5d583
|
# tb_core.u_sdram32 : at time 60593.0 ns READ : Bank = 2 Row = 461, Col = 226, Data = 41b5d583
|
# READ STATUS: Burst-No: 9 Addr: 001cdb73 Rxd: 123aaf24
|
# READ STATUS: Burst-No: 9 Addr: 001cdb73 Rxd: 123aaf24
|
# tb_core.u_sdram32 : at time 59333.0 ns READ : Bank = 2 Row = 461, Col = 227, Data = adee005b
|
# tb_core.u_sdram32 : at time 60603.0 ns READ : Bank = 2 Row = 461, Col = 227, Data = adee005b
|
# READ STATUS: Burst-No: 10 Addr: 001cdb75 Rxd: 41b5d583
|
# READ STATUS: Burst-No: 10 Addr: 001cdb75 Rxd: 41b5d583
|
# READ STATUS: Burst-No: 11 Addr: 001cdb77 Rxd: adee005b
|
# READ STATUS: Burst-No: 11 Addr: 001cdb77 Rxd: adee005b
|
# Write Address: 001ea1b9, Burst Size: 6
|
# Write Address: 001ea1b9, Burst Size: 6
|
# tb_core.u_sdram32 : at time 59527.0 ns ACT : Bank = 0 Row = 490
|
# tb_core.u_sdram32 : at time 60797.0 ns ACT : Bank = 0 Row = 490
|
# tb_core.u_sdram32 : at time 59567.0 ns WRITE: Bank = 0 Row = 490, Col = 110, Data = bb934a77
|
# tb_core.u_sdram32 : at time 60837.0 ns WRITE: Bank = 0 Row = 490, Col = 110, Data = bb934a77
|
# Status: Burst-No: 0 Write Address: 001ea1b9 WriteData: bb934a77
|
# Status: Burst-No: 0 Write Address: 001ea1b9 WriteData: bb934a77
|
# tb_core.u_sdram32 : at time 59577.0 ns WRITE: Bank = 0 Row = 490, Col = 111, Data = f8da1af1
|
# tb_core.u_sdram32 : at time 60847.0 ns WRITE: Bank = 0 Row = 490, Col = 111, Data = f8da1af1
|
# Status: Burst-No: 1 Write Address: 001ea1b9 WriteData: f8da1af1
|
# Status: Burst-No: 1 Write Address: 001ea1b9 WriteData: f8da1af1
|
# tb_core.u_sdram32 : at time 59587.0 ns WRITE: Bank = 0 Row = 490, Col = 112, Data = 732c5fe6
|
# tb_core.u_sdram32 : at time 60857.0 ns WRITE: Bank = 0 Row = 490, Col = 112, Data = 732c5fe6
|
# Status: Burst-No: 2 Write Address: 001ea1b9 WriteData: 732c5fe6
|
# Status: Burst-No: 2 Write Address: 001ea1b9 WriteData: 732c5fe6
|
# tb_core.u_sdram32 : at time 59597.0 ns WRITE: Bank = 0 Row = 490, Col = 113, Data = d7e1aeaf
|
# tb_core.u_sdram32 : at time 60867.0 ns WRITE: Bank = 0 Row = 490, Col = 113, Data = d7e1aeaf
|
# Status: Burst-No: 3 Write Address: 001ea1b9 WriteData: d7e1aeaf
|
# Status: Burst-No: 3 Write Address: 001ea1b9 WriteData: d7e1aeaf
|
# tb_core.u_sdram32 : at time 59607.0 ns WRITE: Bank = 0 Row = 490, Col = 114, Data = 0238e104
|
# tb_core.u_sdram32 : at time 60877.0 ns WRITE: Bank = 0 Row = 490, Col = 114, Data = 0238e104
|
# Status: Burst-No: 4 Write Address: 001ea1b9 WriteData: 0238e104
|
# Status: Burst-No: 4 Write Address: 001ea1b9 WriteData: 0238e104
|
# tb_core.u_sdram32 : at time 59617.0 ns WRITE: Bank = 0 Row = 490, Col = 115, Data = 89646012
|
# tb_core.u_sdram32 : at time 60887.0 ns WRITE: Bank = 0 Row = 490, Col = 115, Data = 89646012
|
# Status: Burst-No: 5 Write Address: 001ea1b9 WriteData: 89646012
|
# Status: Burst-No: 5 Write Address: 001ea1b9 WriteData: 89646012
|
# tb_core.u_sdram32 : at time 59627.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 60897.0 ns BST : Burst Terminate
|
# Write Address: 0029b3fc, Burst Size: 12
|
# Write Address: 0029b3fc, Burst Size: 12
|
# tb_core.u_sdram32 : at time 59787.0 ns ACT : Bank = 0 Row = 667
|
# tb_core.u_sdram32 : at time 61057.0 ns ACT : Bank = 0 Row = 667
|
# tb_core.u_sdram32 : at time 59797.0 ns ACT : Bank = 1 Row = 667
|
# tb_core.u_sdram32 : at time 61097.0 ns WRITE: Bank = 0 Row = 667, Col = 255, Data = e203f0c4
|
# tb_core.u_sdram32 : at time 59797.0 ns ERROR: tRRD violation during Activate bank = 1
|
|
# tb_core.u_sdram32 : at time 59827.0 ns WRITE: Bank = 0 Row = 667, Col = 255, Data = e203f0c4
|
|
# Status: Burst-No: 0 Write Address: 0029b3fc WriteData: e203f0c4
|
# Status: Burst-No: 0 Write Address: 0029b3fc WriteData: e203f0c4
|
# tb_core.u_sdram32 : at time 59837.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 61107.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 59847.0 ns WRITE: Bank = 1 Row = 667, Col = 0, Data = 1ffb813f
|
# tb_core.u_sdram32 : at time 61167.0 ns ACT : Bank = 1 Row = 667
|
|
# tb_core.u_sdram32 : at time 61207.0 ns WRITE: Bank = 1 Row = 667, Col = 0, Data = 1ffb813f
|
# Status: Burst-No: 1 Write Address: 0029b3fc WriteData: 1ffb813f
|
# Status: Burst-No: 1 Write Address: 0029b3fc WriteData: 1ffb813f
|
# tb_core.u_sdram32 : at time 59857.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 61217.0 ns WRITE: Bank = 1 Row = 667, Col = 1, Data = e13256c2
|
# tb_core.u_sdram32 : at time 59877.0 ns WRITE: Bank = 1 Row = 667, Col = 1, Data = e13256c2
|
|
# Status: Burst-No: 2 Write Address: 0029b3fc WriteData: e13256c2
|
# Status: Burst-No: 2 Write Address: 0029b3fc WriteData: e13256c2
|
# tb_core.u_sdram32 : at time 59887.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 61227.0 ns WRITE: Bank = 1 Row = 667, Col = 2, Data = 398a1973
|
# tb_core.u_sdram32 : at time 59907.0 ns WRITE: Bank = 1 Row = 667, Col = 2, Data = 398a1973
|
|
# Status: Burst-No: 3 Write Address: 0029b3fc WriteData: 398a1973
|
# Status: Burst-No: 3 Write Address: 0029b3fc WriteData: 398a1973
|
# tb_core.u_sdram32 : at time 59917.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 61237.0 ns WRITE: Bank = 1 Row = 667, Col = 3, Data = 2d4d9b5a
|
# tb_core.u_sdram32 : at time 59937.0 ns WRITE: Bank = 1 Row = 667, Col = 3, Data = 2d4d9b5a
|
|
# Status: Burst-No: 4 Write Address: 0029b3fc WriteData: 2d4d9b5a
|
# Status: Burst-No: 4 Write Address: 0029b3fc WriteData: 2d4d9b5a
|
# tb_core.u_sdram32 : at time 59947.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 61247.0 ns WRITE: Bank = 1 Row = 667, Col = 4, Data = d066e4a0
|
# tb_core.u_sdram32 : at time 59967.0 ns WRITE: Bank = 1 Row = 667, Col = 4, Data = d066e4a0
|
|
# Status: Burst-No: 5 Write Address: 0029b3fc WriteData: d066e4a0
|
# Status: Burst-No: 5 Write Address: 0029b3fc WriteData: d066e4a0
|
# tb_core.u_sdram32 : at time 59977.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 61257.0 ns WRITE: Bank = 1 Row = 667, Col = 5, Data = ff73cafe
|
# tb_core.u_sdram32 : at time 59997.0 ns WRITE: Bank = 1 Row = 667, Col = 5, Data = ff73cafe
|
|
# Status: Burst-No: 6 Write Address: 0029b3fc WriteData: ff73cafe
|
# Status: Burst-No: 6 Write Address: 0029b3fc WriteData: ff73cafe
|
# tb_core.u_sdram32 : at time 60007.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 61267.0 ns WRITE: Bank = 1 Row = 667, Col = 6, Data = 3a096b74
|
# tb_core.u_sdram32 : at time 60027.0 ns WRITE: Bank = 1 Row = 667, Col = 6, Data = 3a096b74
|
|
# Status: Burst-No: 7 Write Address: 0029b3fc WriteData: 3a096b74
|
# Status: Burst-No: 7 Write Address: 0029b3fc WriteData: 3a096b74
|
# tb_core.u_sdram32 : at time 60037.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 61277.0 ns WRITE: Bank = 1 Row = 667, Col = 7, Data = 5d86b7bb
|
# tb_core.u_sdram32 : at time 60057.0 ns WRITE: Bank = 1 Row = 667, Col = 7, Data = 5d86b7bb
|
|
# Status: Burst-No: 8 Write Address: 0029b3fc WriteData: 5d86b7bb
|
# Status: Burst-No: 8 Write Address: 0029b3fc WriteData: 5d86b7bb
|
# tb_core.u_sdram32 : at time 60067.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 61287.0 ns WRITE: Bank = 1 Row = 667, Col = 8, Data = 7132bbe2
|
# tb_core.u_sdram32 : at time 60087.0 ns WRITE: Bank = 1 Row = 667, Col = 8, Data = 7132bbe2
|
|
# Status: Burst-No: 9 Write Address: 0029b3fc WriteData: 7132bbe2
|
# Status: Burst-No: 9 Write Address: 0029b3fc WriteData: 7132bbe2
|
# tb_core.u_sdram32 : at time 60097.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 61297.0 ns WRITE: Bank = 1 Row = 667, Col = 9, Data = f16948e2
|
# tb_core.u_sdram32 : at time 60117.0 ns WRITE: Bank = 1 Row = 667, Col = 9, Data = f16948e2
|
|
# Status: Burst-No: 10 Write Address: 0029b3fc WriteData: f16948e2
|
# Status: Burst-No: 10 Write Address: 0029b3fc WriteData: f16948e2
|
# tb_core.u_sdram32 : at time 60127.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 61307.0 ns WRITE: Bank = 1 Row = 667, Col = 10, Data = eff34cdf
|
# tb_core.u_sdram32 : at time 60147.0 ns WRITE: Bank = 1 Row = 667, Col = 10, Data = eff34cdf
|
|
# Status: Burst-No: 11 Write Address: 0029b3fc WriteData: eff34cdf
|
# Status: Burst-No: 11 Write Address: 0029b3fc WriteData: eff34cdf
|
# tb_core.u_sdram32 : at time 60157.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 61317.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 60317.0 ns ACT : Bank = 0 Row = 490
|
# tb_core.u_sdram32 : at time 61477.0 ns ACT : Bank = 0 Row = 490
|
# tb_core.u_sdram32 : at time 60383.0 ns READ : Bank = 0 Row = 490, Col = 110, Data = bb934a77
|
# tb_core.u_sdram32 : at time 61543.0 ns READ : Bank = 0 Row = 490, Col = 110, Data = bb934a77
|
# tb_core.u_sdram32 : at time 60393.0 ns READ : Bank = 0 Row = 490, Col = 111, Data = f8da1af1
|
# tb_core.u_sdram32 : at time 61553.0 ns READ : Bank = 0 Row = 490, Col = 111, Data = f8da1af1
|
# READ STATUS: Burst-No: 0 Addr: 001ea1b9 Rxd: bb934a77
|
# READ STATUS: Burst-No: 0 Addr: 001ea1b9 Rxd: bb934a77
|
# tb_core.u_sdram32 : at time 60403.0 ns READ : Bank = 0 Row = 490, Col = 112, Data = 732c5fe6
|
# tb_core.u_sdram32 : at time 61563.0 ns READ : Bank = 0 Row = 490, Col = 112, Data = 732c5fe6
|
# READ STATUS: Burst-No: 1 Addr: 001ea1bb Rxd: f8da1af1
|
# READ STATUS: Burst-No: 1 Addr: 001ea1bb Rxd: f8da1af1
|
# tb_core.u_sdram32 : at time 60413.0 ns READ : Bank = 0 Row = 490, Col = 113, Data = d7e1aeaf
|
# tb_core.u_sdram32 : at time 61573.0 ns READ : Bank = 0 Row = 490, Col = 113, Data = d7e1aeaf
|
# tb_core.u_sdram32 : at time 60417.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 61577.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 2 Addr: 001ea1bd Rxd: 732c5fe6
|
# READ STATUS: Burst-No: 2 Addr: 001ea1bd Rxd: 732c5fe6
|
# tb_core.u_sdram32 : at time 60423.0 ns READ : Bank = 0 Row = 490, Col = 114, Data = 0238e104
|
# tb_core.u_sdram32 : at time 61583.0 ns READ : Bank = 0 Row = 490, Col = 114, Data = 0238e104
|
# READ STATUS: Burst-No: 3 Addr: 001ea1bf Rxd: d7e1aeaf
|
# READ STATUS: Burst-No: 3 Addr: 001ea1bf Rxd: d7e1aeaf
|
# tb_core.u_sdram32 : at time 60433.0 ns READ : Bank = 0 Row = 490, Col = 115, Data = 89646012
|
# tb_core.u_sdram32 : at time 61593.0 ns READ : Bank = 0 Row = 490, Col = 115, Data = 89646012
|
# READ STATUS: Burst-No: 4 Addr: 001ea1c1 Rxd: 0238e104
|
# READ STATUS: Burst-No: 4 Addr: 001ea1c1 Rxd: 0238e104
|
# READ STATUS: Burst-No: 5 Addr: 001ea1c3 Rxd: 89646012
|
# READ STATUS: Burst-No: 5 Addr: 001ea1c3 Rxd: 89646012
|
# tb_core.u_sdram32 : at time 60627.0 ns ACT : Bank = 0 Row = 667
|
# tb_core.u_sdram32 : at time 61787.0 ns ACT : Bank = 0 Row = 667
|
# tb_core.u_sdram32 : at time 60677.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 61837.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 60693.0 ns READ : Bank = 0 Row = 667, Col = 255, Data = e203f0c4
|
# tb_core.u_sdram32 : at time 61853.0 ns READ : Bank = 0 Row = 667, Col = 255, Data = e203f0c4
|
# tb_core.u_sdram32 : at time 60697.0 ns BST : Burst Terminate
|
|
# READ STATUS: Burst-No: 0 Addr: 0029b3fc Rxd: e203f0c4
|
# READ STATUS: Burst-No: 0 Addr: 0029b3fc Rxd: e203f0c4
|
# tb_core.u_sdram32 : at time 60713.0 ns READ : Bank = 1 Row = 667, Col = 0, Data = 1ffb813f
|
# tb_core.u_sdram32 : at time 61873.0 ns READ : Bank = 1 Row = 667, Col = 0, Data = 1ffb813f
|
|
# tb_core.u_sdram32 : at time 61883.0 ns READ : Bank = 1 Row = 667, Col = 1, Data = e13256c2
|
# READ STATUS: Burst-No: 1 Addr: 0029b3fe Rxd: 1ffb813f
|
# READ STATUS: Burst-No: 1 Addr: 0029b3fe Rxd: 1ffb813f
|
# tb_core.u_sdram32 : at time 60727.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 61893.0 ns READ : Bank = 1 Row = 667, Col = 2, Data = 398a1973
|
# tb_core.u_sdram32 : at time 60743.0 ns READ : Bank = 1 Row = 667, Col = 1, Data = e13256c2
|
|
# READ STATUS: Burst-No: 2 Addr: 0029b400 Rxd: e13256c2
|
# READ STATUS: Burst-No: 2 Addr: 0029b400 Rxd: e13256c2
|
# tb_core.u_sdram32 : at time 60757.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 61903.0 ns READ : Bank = 1 Row = 667, Col = 3, Data = 2d4d9b5a
|
# tb_core.u_sdram32 : at time 60773.0 ns READ : Bank = 1 Row = 667, Col = 2, Data = 398a1973
|
|
# READ STATUS: Burst-No: 3 Addr: 0029b402 Rxd: 398a1973
|
# READ STATUS: Burst-No: 3 Addr: 0029b402 Rxd: 398a1973
|
# tb_core.u_sdram32 : at time 60787.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 61913.0 ns READ : Bank = 1 Row = 667, Col = 4, Data = d066e4a0
|
# tb_core.u_sdram32 : at time 60803.0 ns READ : Bank = 1 Row = 667, Col = 3, Data = 2d4d9b5a
|
|
# READ STATUS: Burst-No: 4 Addr: 0029b404 Rxd: 2d4d9b5a
|
# READ STATUS: Burst-No: 4 Addr: 0029b404 Rxd: 2d4d9b5a
|
# tb_core.u_sdram32 : at time 60817.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 61923.0 ns READ : Bank = 1 Row = 667, Col = 5, Data = ff73cafe
|
# tb_core.u_sdram32 : at time 60833.0 ns READ : Bank = 1 Row = 667, Col = 4, Data = d066e4a0
|
|
# READ STATUS: Burst-No: 5 Addr: 0029b406 Rxd: d066e4a0
|
# READ STATUS: Burst-No: 5 Addr: 0029b406 Rxd: d066e4a0
|
# tb_core.u_sdram32 : at time 60847.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 61933.0 ns READ : Bank = 1 Row = 667, Col = 6, Data = 3a096b74
|
# tb_core.u_sdram32 : at time 60863.0 ns READ : Bank = 1 Row = 667, Col = 5, Data = ff73cafe
|
|
# READ STATUS: Burst-No: 6 Addr: 0029b408 Rxd: ff73cafe
|
# READ STATUS: Burst-No: 6 Addr: 0029b408 Rxd: ff73cafe
|
# tb_core.u_sdram32 : at time 60877.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 61943.0 ns READ : Bank = 1 Row = 667, Col = 7, Data = 5d86b7bb
|
# tb_core.u_sdram32 : at time 60893.0 ns READ : Bank = 1 Row = 667, Col = 6, Data = 3a096b74
|
|
# READ STATUS: Burst-No: 7 Addr: 0029b40a Rxd: 3a096b74
|
# READ STATUS: Burst-No: 7 Addr: 0029b40a Rxd: 3a096b74
|
# tb_core.u_sdram32 : at time 60907.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 61953.0 ns READ : Bank = 1 Row = 667, Col = 8, Data = 7132bbe2
|
# tb_core.u_sdram32 : at time 60923.0 ns READ : Bank = 1 Row = 667, Col = 7, Data = 5d86b7bb
|
# tb_core.u_sdram32 : at time 61957.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 8 Addr: 0029b40c Rxd: 5d86b7bb
|
# READ STATUS: Burst-No: 8 Addr: 0029b40c Rxd: 5d86b7bb
|
# tb_core.u_sdram32 : at time 60937.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 61963.0 ns READ : Bank = 1 Row = 667, Col = 9, Data = f16948e2
|
# tb_core.u_sdram32 : at time 60953.0 ns READ : Bank = 1 Row = 667, Col = 8, Data = 7132bbe2
|
|
# READ STATUS: Burst-No: 9 Addr: 0029b40e Rxd: 7132bbe2
|
# READ STATUS: Burst-No: 9 Addr: 0029b40e Rxd: 7132bbe2
|
# tb_core.u_sdram32 : at time 60967.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 61973.0 ns READ : Bank = 1 Row = 667, Col = 10, Data = eff34cdf
|
# tb_core.u_sdram32 : at time 60983.0 ns READ : Bank = 1 Row = 667, Col = 9, Data = f16948e2
|
|
# READ STATUS: Burst-No: 10 Addr: 0029b410 Rxd: f16948e2
|
# READ STATUS: Burst-No: 10 Addr: 0029b410 Rxd: f16948e2
|
# tb_core.u_sdram32 : at time 60997.0 ns BST : Burst Terminate
|
|
# tb_core.u_sdram32 : at time 61013.0 ns READ : Bank = 1 Row = 667, Col = 10, Data = eff34cdf
|
|
# READ STATUS: Burst-No: 11 Addr: 0029b412 Rxd: eff34cdf
|
# READ STATUS: Burst-No: 11 Addr: 0029b412 Rxd: eff34cdf
|
# Write Address: 0013e298, Burst Size: 16
|
# Write Address: 0013e298, Burst Size: 16
|
# tb_core.u_sdram32 : at time 61207.0 ns ACT : Bank = 0 Row = 318
|
# tb_core.u_sdram32 : at time 62167.0 ns ACT : Bank = 0 Row = 318
|
# tb_core.u_sdram32 : at time 61247.0 ns WRITE: Bank = 0 Row = 318, Col = 166, Data = 0817cb10
|
# tb_core.u_sdram32 : at time 62207.0 ns WRITE: Bank = 0 Row = 318, Col = 166, Data = 0817cb10
|
# Status: Burst-No: 0 Write Address: 0013e298 WriteData: 0817cb10
|
# Status: Burst-No: 0 Write Address: 0013e298 WriteData: 0817cb10
|
# tb_core.u_sdram32 : at time 61257.0 ns WRITE: Bank = 0 Row = 318, Col = 167, Data = 791189f2
|
# tb_core.u_sdram32 : at time 62217.0 ns WRITE: Bank = 0 Row = 318, Col = 167, Data = 791189f2
|
# Status: Burst-No: 1 Write Address: 0013e298 WriteData: 791189f2
|
# Status: Burst-No: 1 Write Address: 0013e298 WriteData: 791189f2
|
# tb_core.u_sdram32 : at time 61267.0 ns WRITE: Bank = 0 Row = 318, Col = 168, Data = 5ee97bbd
|
# tb_core.u_sdram32 : at time 62227.0 ns WRITE: Bank = 0 Row = 318, Col = 168, Data = 5ee97bbd
|
# Status: Burst-No: 2 Write Address: 0013e298 WriteData: 5ee97bbd
|
# Status: Burst-No: 2 Write Address: 0013e298 WriteData: 5ee97bbd
|
# tb_core.u_sdram32 : at time 61277.0 ns WRITE: Bank = 0 Row = 318, Col = 169, Data = 55bc27ab
|
# tb_core.u_sdram32 : at time 62237.0 ns WRITE: Bank = 0 Row = 318, Col = 169, Data = 55bc27ab
|
# Status: Burst-No: 3 Write Address: 0013e298 WriteData: 55bc27ab
|
# Status: Burst-No: 3 Write Address: 0013e298 WriteData: 55bc27ab
|
# tb_core.u_sdram32 : at time 61287.0 ns WRITE: Bank = 0 Row = 318, Col = 170, Data = 5a0a0fb4
|
# tb_core.u_sdram32 : at time 62247.0 ns WRITE: Bank = 0 Row = 318, Col = 170, Data = 5a0a0fb4
|
# Status: Burst-No: 4 Write Address: 0013e298 WriteData: 5a0a0fb4
|
# Status: Burst-No: 4 Write Address: 0013e298 WriteData: 5a0a0fb4
|
# tb_core.u_sdram32 : at time 61297.0 ns WRITE: Bank = 0 Row = 318, Col = 171, Data = aa08ac54
|
# tb_core.u_sdram32 : at time 62257.0 ns WRITE: Bank = 0 Row = 318, Col = 171, Data = aa08ac54
|
# Status: Burst-No: 5 Write Address: 0013e298 WriteData: aa08ac54
|
# Status: Burst-No: 5 Write Address: 0013e298 WriteData: aa08ac54
|
# tb_core.u_sdram32 : at time 61307.0 ns WRITE: Bank = 0 Row = 318, Col = 172, Data = 44e79b89
|
# tb_core.u_sdram32 : at time 62267.0 ns WRITE: Bank = 0 Row = 318, Col = 172, Data = 44e79b89
|
# Status: Burst-No: 6 Write Address: 0013e298 WriteData: 44e79b89
|
# Status: Burst-No: 6 Write Address: 0013e298 WriteData: 44e79b89
|
# tb_core.u_sdram32 : at time 61317.0 ns WRITE: Bank = 0 Row = 318, Col = 173, Data = 89b5d413
|
# tb_core.u_sdram32 : at time 62277.0 ns WRITE: Bank = 0 Row = 318, Col = 173, Data = 89b5d413
|
# Status: Burst-No: 7 Write Address: 0013e298 WriteData: 89b5d413
|
# Status: Burst-No: 7 Write Address: 0013e298 WriteData: 89b5d413
|
# tb_core.u_sdram32 : at time 61327.0 ns WRITE: Bank = 0 Row = 318, Col = 174, Data = 560c91ac
|
# tb_core.u_sdram32 : at time 62287.0 ns WRITE: Bank = 0 Row = 318, Col = 174, Data = 560c91ac
|
# Status: Burst-No: 8 Write Address: 0013e298 WriteData: 560c91ac
|
# Status: Burst-No: 8 Write Address: 0013e298 WriteData: 560c91ac
|
# tb_core.u_sdram32 : at time 61337.0 ns WRITE: Bank = 0 Row = 318, Col = 175, Data = 1ae40335
|
# tb_core.u_sdram32 : at time 62297.0 ns WRITE: Bank = 0 Row = 318, Col = 175, Data = 1ae40335
|
# Status: Burst-No: 9 Write Address: 0013e298 WriteData: 1ae40335
|
# Status: Burst-No: 9 Write Address: 0013e298 WriteData: 1ae40335
|
# tb_core.u_sdram32 : at time 61347.0 ns WRITE: Bank = 0 Row = 318, Col = 176, Data = 1df61f3b
|
# tb_core.u_sdram32 : at time 62307.0 ns WRITE: Bank = 0 Row = 318, Col = 176, Data = 1df61f3b
|
# Status: Burst-No: 10 Write Address: 0013e298 WriteData: 1df61f3b
|
# Status: Burst-No: 10 Write Address: 0013e298 WriteData: 1df61f3b
|
# tb_core.u_sdram32 : at time 61357.0 ns WRITE: Bank = 0 Row = 318, Col = 177, Data = 9aa02435
|
# tb_core.u_sdram32 : at time 62317.0 ns WRITE: Bank = 0 Row = 318, Col = 177, Data = 9aa02435
|
# Status: Burst-No: 11 Write Address: 0013e298 WriteData: 9aa02435
|
# Status: Burst-No: 11 Write Address: 0013e298 WriteData: 9aa02435
|
# tb_core.u_sdram32 : at time 61367.0 ns WRITE: Bank = 0 Row = 318, Col = 178, Data = 17a98d2f
|
# tb_core.u_sdram32 : at time 62327.0 ns WRITE: Bank = 0 Row = 318, Col = 178, Data = 17a98d2f
|
# Status: Burst-No: 12 Write Address: 0013e298 WriteData: 17a98d2f
|
# Status: Burst-No: 12 Write Address: 0013e298 WriteData: 17a98d2f
|
# tb_core.u_sdram32 : at time 61377.0 ns WRITE: Bank = 0 Row = 318, Col = 179, Data = 1a619934
|
# tb_core.u_sdram32 : at time 62337.0 ns WRITE: Bank = 0 Row = 318, Col = 179, Data = 1a619934
|
# Status: Burst-No: 13 Write Address: 0013e298 WriteData: 1a619934
|
# Status: Burst-No: 13 Write Address: 0013e298 WriteData: 1a619934
|
# tb_core.u_sdram32 : at time 61387.0 ns WRITE: Bank = 0 Row = 318, Col = 180, Data = aae0a255
|
# tb_core.u_sdram32 : at time 62347.0 ns WRITE: Bank = 0 Row = 318, Col = 180, Data = aae0a255
|
# Status: Burst-No: 14 Write Address: 0013e298 WriteData: aae0a255
|
# Status: Burst-No: 14 Write Address: 0013e298 WriteData: aae0a255
|
# tb_core.u_sdram32 : at time 61397.0 ns WRITE: Bank = 0 Row = 318, Col = 181, Data = de7302bc
|
# tb_core.u_sdram32 : at time 62357.0 ns WRITE: Bank = 0 Row = 318, Col = 181, Data = de7302bc
|
# Status: Burst-No: 15 Write Address: 0013e298 WriteData: de7302bc
|
# Status: Burst-No: 15 Write Address: 0013e298 WriteData: de7302bc
|
# tb_core.u_sdram32 : at time 61407.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 62367.0 ns BST : Burst Terminate
|
# Write Address: 0024fef2, Burst Size: 8
|
# Write Address: 0024fef2, Burst Size: 8
|
# tb_core.u_sdram32 : at time 61567.0 ns ACT : Bank = 3 Row = 591
|
# tb_core.u_sdram32 : at time 62527.0 ns ACT : Bank = 3 Row = 591
|
# tb_core.u_sdram32 : at time 61607.0 ns WRITE: Bank = 3 Row = 591, Col = 188, Data = e0f280c1
|
# tb_core.u_sdram32 : at time 62567.0 ns WRITE: Bank = 3 Row = 591, Col = 188, Data = e0f280c1
|
# Status: Burst-No: 0 Write Address: 0024fef2 WriteData: e0f280c1
|
# Status: Burst-No: 0 Write Address: 0024fef2 WriteData: e0f280c1
|
# tb_core.u_sdram32 : at time 61617.0 ns WRITE: Bank = 3 Row = 591, Col = 189, Data = f23316e4
|
# tb_core.u_sdram32 : at time 62577.0 ns WRITE: Bank = 3 Row = 591, Col = 189, Data = f23316e4
|
# Status: Burst-No: 1 Write Address: 0024fef2 WriteData: f23316e4
|
# Status: Burst-No: 1 Write Address: 0024fef2 WriteData: f23316e4
|
# tb_core.u_sdram32 : at time 61627.0 ns WRITE: Bank = 3 Row = 591, Col = 190, Data = a0b8a241
|
# tb_core.u_sdram32 : at time 62587.0 ns WRITE: Bank = 3 Row = 591, Col = 190, Data = a0b8a241
|
# Status: Burst-No: 2 Write Address: 0024fef2 WriteData: a0b8a241
|
# Status: Burst-No: 2 Write Address: 0024fef2 WriteData: a0b8a241
|
# tb_core.u_sdram32 : at time 61637.0 ns WRITE: Bank = 3 Row = 591, Col = 191, Data = b4c16c69
|
# tb_core.u_sdram32 : at time 62597.0 ns WRITE: Bank = 3 Row = 591, Col = 191, Data = b4c16c69
|
# Status: Burst-No: 3 Write Address: 0024fef2 WriteData: b4c16c69
|
# Status: Burst-No: 3 Write Address: 0024fef2 WriteData: b4c16c69
|
# tb_core.u_sdram32 : at time 61647.0 ns WRITE: Bank = 3 Row = 591, Col = 192, Data = fd52d8fa
|
# tb_core.u_sdram32 : at time 62607.0 ns WRITE: Bank = 3 Row = 591, Col = 192, Data = fd52d8fa
|
# Status: Burst-No: 4 Write Address: 0024fef2 WriteData: fd52d8fa
|
# Status: Burst-No: 4 Write Address: 0024fef2 WriteData: fd52d8fa
|
# tb_core.u_sdram32 : at time 61657.0 ns WRITE: Bank = 3 Row = 591, Col = 193, Data = e69dd0cd
|
# tb_core.u_sdram32 : at time 62617.0 ns WRITE: Bank = 3 Row = 591, Col = 193, Data = e69dd0cd
|
# Status: Burst-No: 5 Write Address: 0024fef2 WriteData: e69dd0cd
|
# Status: Burst-No: 5 Write Address: 0024fef2 WriteData: e69dd0cd
|
# tb_core.u_sdram32 : at time 61667.0 ns WRITE: Bank = 3 Row = 591, Col = 194, Data = 7fcff3ff
|
# tb_core.u_sdram32 : at time 62627.0 ns WRITE: Bank = 3 Row = 591, Col = 194, Data = 7fcff3ff
|
# Status: Burst-No: 6 Write Address: 0024fef2 WriteData: 7fcff3ff
|
# Status: Burst-No: 6 Write Address: 0024fef2 WriteData: 7fcff3ff
|
# tb_core.u_sdram32 : at time 61677.0 ns WRITE: Bank = 3 Row = 591, Col = 195, Data = dac986b5
|
# tb_core.u_sdram32 : at time 62637.0 ns WRITE: Bank = 3 Row = 591, Col = 195, Data = dac986b5
|
# Status: Burst-No: 7 Write Address: 0024fef2 WriteData: dac986b5
|
# Status: Burst-No: 7 Write Address: 0024fef2 WriteData: dac986b5
|
# tb_core.u_sdram32 : at time 61687.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 62647.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 61833.0 ns READ : Bank = 0 Row = 318, Col = 166, Data = 0817cb10
|
# tb_core.u_sdram32 : at time 62793.0 ns READ : Bank = 0 Row = 318, Col = 166, Data = 0817cb10
|
# tb_core.u_sdram32 : at time 61843.0 ns READ : Bank = 0 Row = 318, Col = 167, Data = 791189f2
|
# tb_core.u_sdram32 : at time 62803.0 ns READ : Bank = 0 Row = 318, Col = 167, Data = 791189f2
|
# READ STATUS: Burst-No: 0 Addr: 0013e298 Rxd: 0817cb10
|
# READ STATUS: Burst-No: 0 Addr: 0013e298 Rxd: 0817cb10
|
# tb_core.u_sdram32 : at time 61853.0 ns READ : Bank = 0 Row = 318, Col = 168, Data = 5ee97bbd
|
# tb_core.u_sdram32 : at time 62813.0 ns READ : Bank = 0 Row = 318, Col = 168, Data = 5ee97bbd
|
# READ STATUS: Burst-No: 1 Addr: 0013e29a Rxd: 791189f2
|
# READ STATUS: Burst-No: 1 Addr: 0013e29a Rxd: 791189f2
|
# tb_core.u_sdram32 : at time 61863.0 ns READ : Bank = 0 Row = 318, Col = 169, Data = 55bc27ab
|
# tb_core.u_sdram32 : at time 62823.0 ns READ : Bank = 0 Row = 318, Col = 169, Data = 55bc27ab
|
# READ STATUS: Burst-No: 2 Addr: 0013e29c Rxd: 5ee97bbd
|
# READ STATUS: Burst-No: 2 Addr: 0013e29c Rxd: 5ee97bbd
|
# tb_core.u_sdram32 : at time 61873.0 ns READ : Bank = 0 Row = 318, Col = 170, Data = 5a0a0fb4
|
# tb_core.u_sdram32 : at time 62833.0 ns READ : Bank = 0 Row = 318, Col = 170, Data = 5a0a0fb4
|
# READ STATUS: Burst-No: 3 Addr: 0013e29e Rxd: 55bc27ab
|
# READ STATUS: Burst-No: 3 Addr: 0013e29e Rxd: 55bc27ab
|
# tb_core.u_sdram32 : at time 61883.0 ns READ : Bank = 0 Row = 318, Col = 171, Data = aa08ac54
|
# tb_core.u_sdram32 : at time 62843.0 ns READ : Bank = 0 Row = 318, Col = 171, Data = aa08ac54
|
# READ STATUS: Burst-No: 4 Addr: 0013e2a0 Rxd: 5a0a0fb4
|
# READ STATUS: Burst-No: 4 Addr: 0013e2a0 Rxd: 5a0a0fb4
|
# tb_core.u_sdram32 : at time 61893.0 ns READ : Bank = 0 Row = 318, Col = 172, Data = 44e79b89
|
# tb_core.u_sdram32 : at time 62853.0 ns READ : Bank = 0 Row = 318, Col = 172, Data = 44e79b89
|
# READ STATUS: Burst-No: 5 Addr: 0013e2a2 Rxd: aa08ac54
|
# READ STATUS: Burst-No: 5 Addr: 0013e2a2 Rxd: aa08ac54
|
# tb_core.u_sdram32 : at time 61903.0 ns READ : Bank = 0 Row = 318, Col = 173, Data = 89b5d413
|
# tb_core.u_sdram32 : at time 62863.0 ns READ : Bank = 0 Row = 318, Col = 173, Data = 89b5d413
|
# READ STATUS: Burst-No: 6 Addr: 0013e2a4 Rxd: 44e79b89
|
# READ STATUS: Burst-No: 6 Addr: 0013e2a4 Rxd: 44e79b89
|
# tb_core.u_sdram32 : at time 61913.0 ns READ : Bank = 0 Row = 318, Col = 174, Data = 560c91ac
|
# tb_core.u_sdram32 : at time 62873.0 ns READ : Bank = 0 Row = 318, Col = 174, Data = 560c91ac
|
# READ STATUS: Burst-No: 7 Addr: 0013e2a6 Rxd: 89b5d413
|
# READ STATUS: Burst-No: 7 Addr: 0013e2a6 Rxd: 89b5d413
|
# tb_core.u_sdram32 : at time 61923.0 ns READ : Bank = 0 Row = 318, Col = 175, Data = 1ae40335
|
# tb_core.u_sdram32 : at time 62883.0 ns READ : Bank = 0 Row = 318, Col = 175, Data = 1ae40335
|
# READ STATUS: Burst-No: 8 Addr: 0013e2a8 Rxd: 560c91ac
|
# READ STATUS: Burst-No: 8 Addr: 0013e2a8 Rxd: 560c91ac
|
# tb_core.u_sdram32 : at time 61933.0 ns READ : Bank = 0 Row = 318, Col = 176, Data = 1df61f3b
|
# tb_core.u_sdram32 : at time 62893.0 ns READ : Bank = 0 Row = 318, Col = 176, Data = 1df61f3b
|
# READ STATUS: Burst-No: 9 Addr: 0013e2aa Rxd: 1ae40335
|
# READ STATUS: Burst-No: 9 Addr: 0013e2aa Rxd: 1ae40335
|
# tb_core.u_sdram32 : at time 61943.0 ns READ : Bank = 0 Row = 318, Col = 177, Data = 9aa02435
|
# tb_core.u_sdram32 : at time 62903.0 ns READ : Bank = 0 Row = 318, Col = 177, Data = 9aa02435
|
# READ STATUS: Burst-No: 10 Addr: 0013e2ac Rxd: 1df61f3b
|
# READ STATUS: Burst-No: 10 Addr: 0013e2ac Rxd: 1df61f3b
|
# tb_core.u_sdram32 : at time 61953.0 ns READ : Bank = 0 Row = 318, Col = 178, Data = 17a98d2f
|
# tb_core.u_sdram32 : at time 62913.0 ns READ : Bank = 0 Row = 318, Col = 178, Data = 17a98d2f
|
# READ STATUS: Burst-No: 11 Addr: 0013e2ae Rxd: 9aa02435
|
# READ STATUS: Burst-No: 11 Addr: 0013e2ae Rxd: 9aa02435
|
# tb_core.u_sdram32 : at time 61963.0 ns READ : Bank = 0 Row = 318, Col = 179, Data = 1a619934
|
# tb_core.u_sdram32 : at time 62923.0 ns READ : Bank = 0 Row = 318, Col = 179, Data = 1a619934
|
# tb_core.u_sdram32 : at time 61967.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 62927.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 12 Addr: 0013e2b0 Rxd: 17a98d2f
|
# READ STATUS: Burst-No: 12 Addr: 0013e2b0 Rxd: 17a98d2f
|
# tb_core.u_sdram32 : at time 61973.0 ns READ : Bank = 0 Row = 318, Col = 180, Data = aae0a255
|
# tb_core.u_sdram32 : at time 62933.0 ns READ : Bank = 0 Row = 318, Col = 180, Data = aae0a255
|
# READ STATUS: Burst-No: 13 Addr: 0013e2b2 Rxd: 1a619934
|
# READ STATUS: Burst-No: 13 Addr: 0013e2b2 Rxd: 1a619934
|
# tb_core.u_sdram32 : at time 61983.0 ns READ : Bank = 0 Row = 318, Col = 181, Data = de7302bc
|
# tb_core.u_sdram32 : at time 62943.0 ns READ : Bank = 0 Row = 318, Col = 181, Data = de7302bc
|
# READ STATUS: Burst-No: 14 Addr: 0013e2b4 Rxd: aae0a255
|
# READ STATUS: Burst-No: 14 Addr: 0013e2b4 Rxd: aae0a255
|
# READ STATUS: Burst-No: 15 Addr: 0013e2b6 Rxd: de7302bc
|
# READ STATUS: Burst-No: 15 Addr: 0013e2b6 Rxd: de7302bc
|
# tb_core.u_sdram32 : at time 62173.0 ns READ : Bank = 3 Row = 591, Col = 188, Data = e0f280c1
|
# tb_core.u_sdram32 : at time 63133.0 ns READ : Bank = 3 Row = 591, Col = 188, Data = e0f280c1
|
# tb_core.u_sdram32 : at time 62183.0 ns READ : Bank = 3 Row = 591, Col = 189, Data = f23316e4
|
# tb_core.u_sdram32 : at time 63143.0 ns READ : Bank = 3 Row = 591, Col = 189, Data = f23316e4
|
# READ STATUS: Burst-No: 0 Addr: 0024fef2 Rxd: e0f280c1
|
# READ STATUS: Burst-No: 0 Addr: 0024fef2 Rxd: e0f280c1
|
# tb_core.u_sdram32 : at time 62193.0 ns READ : Bank = 3 Row = 591, Col = 190, Data = a0b8a241
|
# tb_core.u_sdram32 : at time 63153.0 ns READ : Bank = 3 Row = 591, Col = 190, Data = a0b8a241
|
# READ STATUS: Burst-No: 1 Addr: 0024fef4 Rxd: f23316e4
|
# READ STATUS: Burst-No: 1 Addr: 0024fef4 Rxd: f23316e4
|
# tb_core.u_sdram32 : at time 62203.0 ns READ : Bank = 3 Row = 591, Col = 191, Data = b4c16c69
|
# tb_core.u_sdram32 : at time 63163.0 ns READ : Bank = 3 Row = 591, Col = 191, Data = b4c16c69
|
# READ STATUS: Burst-No: 2 Addr: 0024fef6 Rxd: a0b8a241
|
# READ STATUS: Burst-No: 2 Addr: 0024fef6 Rxd: a0b8a241
|
# tb_core.u_sdram32 : at time 62213.0 ns READ : Bank = 3 Row = 591, Col = 192, Data = fd52d8fa
|
# tb_core.u_sdram32 : at time 63173.0 ns READ : Bank = 3 Row = 591, Col = 192, Data = fd52d8fa
|
# READ STATUS: Burst-No: 3 Addr: 0024fef8 Rxd: b4c16c69
|
# READ STATUS: Burst-No: 3 Addr: 0024fef8 Rxd: b4c16c69
|
# tb_core.u_sdram32 : at time 62223.0 ns READ : Bank = 3 Row = 591, Col = 193, Data = e69dd0cd
|
# tb_core.u_sdram32 : at time 63183.0 ns READ : Bank = 3 Row = 591, Col = 193, Data = e69dd0cd
|
# tb_core.u_sdram32 : at time 62227.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 63187.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 4 Addr: 0024fefa Rxd: fd52d8fa
|
# READ STATUS: Burst-No: 4 Addr: 0024fefa Rxd: fd52d8fa
|
# tb_core.u_sdram32 : at time 62233.0 ns READ : Bank = 3 Row = 591, Col = 194, Data = 7fcff3ff
|
# tb_core.u_sdram32 : at time 63193.0 ns READ : Bank = 3 Row = 591, Col = 194, Data = 7fcff3ff
|
# READ STATUS: Burst-No: 5 Addr: 0024fefc Rxd: e69dd0cd
|
# READ STATUS: Burst-No: 5 Addr: 0024fefc Rxd: e69dd0cd
|
# tb_core.u_sdram32 : at time 62243.0 ns READ : Bank = 3 Row = 591, Col = 195, Data = dac986b5
|
# tb_core.u_sdram32 : at time 63203.0 ns READ : Bank = 3 Row = 591, Col = 195, Data = dac986b5
|
# READ STATUS: Burst-No: 6 Addr: 0024fefe Rxd: 7fcff3ff
|
# READ STATUS: Burst-No: 6 Addr: 0024fefe Rxd: 7fcff3ff
|
# READ STATUS: Burst-No: 7 Addr: 0024ff00 Rxd: dac986b5
|
# READ STATUS: Burst-No: 7 Addr: 0024ff00 Rxd: dac986b5
|
# Write Address: 002082e8, Burst Size: 12
|
# Write Address: 002082e8, Burst Size: 12
|
# tb_core.u_sdram32 : at time 62437.0 ns ACT : Bank = 0 Row = 520
|
# tb_core.u_sdram32 : at time 63397.0 ns ACT : Bank = 0 Row = 520
|
# tb_core.u_sdram32 : at time 62477.0 ns WRITE: Bank = 0 Row = 520, Col = 186, Data = 89042e12
|
# tb_core.u_sdram32 : at time 63437.0 ns WRITE: Bank = 0 Row = 520, Col = 186, Data = 89042e12
|
# Status: Burst-No: 0 Write Address: 002082e8 WriteData: 89042e12
|
# Status: Burst-No: 0 Write Address: 002082e8 WriteData: 89042e12
|
# tb_core.u_sdram32 : at time 62487.0 ns WRITE: Bank = 0 Row = 520, Col = 187, Data = 1b978f37
|
# tb_core.u_sdram32 : at time 63447.0 ns WRITE: Bank = 0 Row = 520, Col = 187, Data = 1b978f37
|
# Status: Burst-No: 1 Write Address: 002082e8 WriteData: 1b978f37
|
# Status: Burst-No: 1 Write Address: 002082e8 WriteData: 1b978f37
|
# tb_core.u_sdram32 : at time 62497.0 ns WRITE: Bank = 0 Row = 520, Col = 188, Data = 574e1dae
|
# tb_core.u_sdram32 : at time 63457.0 ns WRITE: Bank = 0 Row = 520, Col = 188, Data = 574e1dae
|
# Status: Burst-No: 2 Write Address: 002082e8 WriteData: 574e1dae
|
# Status: Burst-No: 2 Write Address: 002082e8 WriteData: 574e1dae
|
# tb_core.u_sdram32 : at time 62507.0 ns WRITE: Bank = 0 Row = 520, Col = 189, Data = fc4ca4f8
|
# tb_core.u_sdram32 : at time 63467.0 ns WRITE: Bank = 0 Row = 520, Col = 189, Data = fc4ca4f8
|
# Status: Burst-No: 3 Write Address: 002082e8 WriteData: fc4ca4f8
|
# Status: Burst-No: 3 Write Address: 002082e8 WriteData: fc4ca4f8
|
# tb_core.u_sdram32 : at time 62517.0 ns WRITE: Bank = 0 Row = 520, Col = 190, Data = 90184e20
|
# tb_core.u_sdram32 : at time 63477.0 ns WRITE: Bank = 0 Row = 520, Col = 190, Data = 90184e20
|
# Status: Burst-No: 4 Write Address: 002082e8 WriteData: 90184e20
|
# Status: Burst-No: 4 Write Address: 002082e8 WriteData: 90184e20
|
# tb_core.u_sdram32 : at time 62527.0 ns WRITE: Bank = 0 Row = 520, Col = 191, Data = ed1b50da
|
# tb_core.u_sdram32 : at time 63487.0 ns WRITE: Bank = 0 Row = 520, Col = 191, Data = ed1b50da
|
# Status: Burst-No: 5 Write Address: 002082e8 WriteData: ed1b50da
|
# Status: Burst-No: 5 Write Address: 002082e8 WriteData: ed1b50da
|
# tb_core.u_sdram32 : at time 62537.0 ns WRITE: Bank = 0 Row = 520, Col = 192, Data = 913e0222
|
# tb_core.u_sdram32 : at time 63497.0 ns WRITE: Bank = 0 Row = 520, Col = 192, Data = 913e0222
|
# Status: Burst-No: 6 Write Address: 002082e8 WriteData: 913e0222
|
# Status: Burst-No: 6 Write Address: 002082e8 WriteData: 913e0222
|
# tb_core.u_sdram32 : at time 62547.0 ns WRITE: Bank = 0 Row = 520, Col = 193, Data = 763355ec
|
# tb_core.u_sdram32 : at time 63507.0 ns WRITE: Bank = 0 Row = 520, Col = 193, Data = 763355ec
|
# Status: Burst-No: 7 Write Address: 002082e8 WriteData: 763355ec
|
# Status: Burst-No: 7 Write Address: 002082e8 WriteData: 763355ec
|
# tb_core.u_sdram32 : at time 62557.0 ns WRITE: Bank = 0 Row = 520, Col = 194, Data = 9535122a
|
# tb_core.u_sdram32 : at time 63517.0 ns WRITE: Bank = 0 Row = 520, Col = 194, Data = 9535122a
|
# Status: Burst-No: 8 Write Address: 002082e8 WriteData: 9535122a
|
# Status: Burst-No: 8 Write Address: 002082e8 WriteData: 9535122a
|
# tb_core.u_sdram32 : at time 62567.0 ns WRITE: Bank = 0 Row = 520, Col = 195, Data = 3d7f5b7a
|
# tb_core.u_sdram32 : at time 63527.0 ns WRITE: Bank = 0 Row = 520, Col = 195, Data = 3d7f5b7a
|
# Status: Burst-No: 9 Write Address: 002082e8 WriteData: 3d7f5b7a
|
# Status: Burst-No: 9 Write Address: 002082e8 WriteData: 3d7f5b7a
|
# tb_core.u_sdram32 : at time 62577.0 ns WRITE: Bank = 0 Row = 520, Col = 196, Data = 0f1e511e
|
# tb_core.u_sdram32 : at time 63537.0 ns WRITE: Bank = 0 Row = 520, Col = 196, Data = 0f1e511e
|
# Status: Burst-No: 10 Write Address: 002082e8 WriteData: 0f1e511e
|
# Status: Burst-No: 10 Write Address: 002082e8 WriteData: 0f1e511e
|
# tb_core.u_sdram32 : at time 62587.0 ns WRITE: Bank = 0 Row = 520, Col = 197, Data = f4a1dae9
|
# tb_core.u_sdram32 : at time 63547.0 ns WRITE: Bank = 0 Row = 520, Col = 197, Data = f4a1dae9
|
# Status: Burst-No: 11 Write Address: 002082e8 WriteData: f4a1dae9
|
# Status: Burst-No: 11 Write Address: 002082e8 WriteData: f4a1dae9
|
# tb_core.u_sdram32 : at time 62597.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 63557.0 ns BST : Burst Terminate
|
# Write Address: 0024f2eb, Burst Size: 12
|
# Write Address: 0024f2eb, Burst Size: 12
|
# tb_core.u_sdram32 : at time 62757.0 ns ACT : Bank = 0 Row = 591
|
# tb_core.u_sdram32 : at time 63717.0 ns ACT : Bank = 0 Row = 591
|
# tb_core.u_sdram32 : at time 62797.0 ns WRITE: Bank = 0 Row = 591, Col = 186, Data = b704e26e
|
# tb_core.u_sdram32 : at time 63757.0 ns WRITE: Bank = 0 Row = 591, Col = 186, Data = b704e26e
|
# Status: Burst-No: 0 Write Address: 0024f2eb WriteData: b704e26e
|
# Status: Burst-No: 0 Write Address: 0024f2eb WriteData: b704e26e
|
# tb_core.u_sdram32 : at time 62807.0 ns WRITE: Bank = 0 Row = 591, Col = 187, Data = af455e5e
|
# tb_core.u_sdram32 : at time 63767.0 ns WRITE: Bank = 0 Row = 591, Col = 187, Data = af455e5e
|
# Status: Burst-No: 1 Write Address: 0024f2eb WriteData: af455e5e
|
# Status: Burst-No: 1 Write Address: 0024f2eb WriteData: af455e5e
|
# tb_core.u_sdram32 : at time 62817.0 ns WRITE: Bank = 0 Row = 591, Col = 188, Data = 3e502d7c
|
# tb_core.u_sdram32 : at time 63777.0 ns WRITE: Bank = 0 Row = 591, Col = 188, Data = 3e502d7c
|
# Status: Burst-No: 2 Write Address: 0024f2eb WriteData: 3e502d7c
|
# Status: Burst-No: 2 Write Address: 0024f2eb WriteData: 3e502d7c
|
# tb_core.u_sdram32 : at time 62827.0 ns WRITE: Bank = 0 Row = 591, Col = 189, Data = 22c03145
|
# tb_core.u_sdram32 : at time 63787.0 ns WRITE: Bank = 0 Row = 591, Col = 189, Data = 22c03145
|
# Status: Burst-No: 3 Write Address: 0024f2eb WriteData: 22c03145
|
# Status: Burst-No: 3 Write Address: 0024f2eb WriteData: 22c03145
|
# tb_core.u_sdram32 : at time 62837.0 ns WRITE: Bank = 0 Row = 591, Col = 190, Data = c5cb548b
|
# tb_core.u_sdram32 : at time 63797.0 ns WRITE: Bank = 0 Row = 591, Col = 190, Data = c5cb548b
|
# Status: Burst-No: 4 Write Address: 0024f2eb WriteData: c5cb548b
|
# Status: Burst-No: 4 Write Address: 0024f2eb WriteData: c5cb548b
|
# tb_core.u_sdram32 : at time 62847.0 ns WRITE: Bank = 0 Row = 591, Col = 191, Data = 094bd312
|
# tb_core.u_sdram32 : at time 63807.0 ns WRITE: Bank = 0 Row = 591, Col = 191, Data = 094bd312
|
# Status: Burst-No: 5 Write Address: 0024f2eb WriteData: 094bd312
|
# Status: Burst-No: 5 Write Address: 0024f2eb WriteData: 094bd312
|
# tb_core.u_sdram32 : at time 62857.0 ns WRITE: Bank = 0 Row = 591, Col = 192, Data = 1bf8bd37
|
# tb_core.u_sdram32 : at time 63817.0 ns WRITE: Bank = 0 Row = 591, Col = 192, Data = 1bf8bd37
|
# Status: Burst-No: 6 Write Address: 0024f2eb WriteData: 1bf8bd37
|
# Status: Burst-No: 6 Write Address: 0024f2eb WriteData: 1bf8bd37
|
# tb_core.u_sdram32 : at time 62867.0 ns WRITE: Bank = 0 Row = 591, Col = 193, Data = c1c3d683
|
# tb_core.u_sdram32 : at time 63827.0 ns WRITE: Bank = 0 Row = 591, Col = 193, Data = c1c3d683
|
# Status: Burst-No: 7 Write Address: 0024f2eb WriteData: c1c3d683
|
# Status: Burst-No: 7 Write Address: 0024f2eb WriteData: c1c3d683
|
# tb_core.u_sdram32 : at time 62877.0 ns WRITE: Bank = 0 Row = 591, Col = 194, Data = f0ab00e1
|
# tb_core.u_sdram32 : at time 63837.0 ns WRITE: Bank = 0 Row = 591, Col = 194, Data = f0ab00e1
|
# Status: Burst-No: 8 Write Address: 0024f2eb WriteData: f0ab00e1
|
# Status: Burst-No: 8 Write Address: 0024f2eb WriteData: f0ab00e1
|
# tb_core.u_sdram32 : at time 62887.0 ns WRITE: Bank = 0 Row = 591, Col = 195, Data = 674fdfce
|
# tb_core.u_sdram32 : at time 63847.0 ns WRITE: Bank = 0 Row = 591, Col = 195, Data = 674fdfce
|
# Status: Burst-No: 9 Write Address: 0024f2eb WriteData: 674fdfce
|
# Status: Burst-No: 9 Write Address: 0024f2eb WriteData: 674fdfce
|
# tb_core.u_sdram32 : at time 62897.0 ns WRITE: Bank = 0 Row = 591, Col = 196, Data = a5365c4a
|
# tb_core.u_sdram32 : at time 63857.0 ns WRITE: Bank = 0 Row = 591, Col = 196, Data = a5365c4a
|
# Status: Burst-No: 10 Write Address: 0024f2eb WriteData: a5365c4a
|
# Status: Burst-No: 10 Write Address: 0024f2eb WriteData: a5365c4a
|
# tb_core.u_sdram32 : at time 62907.0 ns WRITE: Bank = 0 Row = 591, Col = 197, Data = 6acd73d5
|
# tb_core.u_sdram32 : at time 63867.0 ns WRITE: Bank = 0 Row = 591, Col = 197, Data = 6acd73d5
|
# Status: Burst-No: 11 Write Address: 0024f2eb WriteData: 6acd73d5
|
# Status: Burst-No: 11 Write Address: 0024f2eb WriteData: 6acd73d5
|
# tb_core.u_sdram32 : at time 62917.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 63877.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 63077.0 ns ACT : Bank = 0 Row = 520
|
# tb_core.u_sdram32 : at time 64037.0 ns ACT : Bank = 0 Row = 520
|
# tb_core.u_sdram32 : at time 63143.0 ns READ : Bank = 0 Row = 520, Col = 186, Data = 89042e12
|
# tb_core.u_sdram32 : at time 64103.0 ns READ : Bank = 0 Row = 520, Col = 186, Data = 89042e12
|
# tb_core.u_sdram32 : at time 63153.0 ns READ : Bank = 0 Row = 520, Col = 187, Data = 1b978f37
|
# tb_core.u_sdram32 : at time 64113.0 ns READ : Bank = 0 Row = 520, Col = 187, Data = 1b978f37
|
# READ STATUS: Burst-No: 0 Addr: 002082e8 Rxd: 89042e12
|
# READ STATUS: Burst-No: 0 Addr: 002082e8 Rxd: 89042e12
|
# tb_core.u_sdram32 : at time 63163.0 ns READ : Bank = 0 Row = 520, Col = 188, Data = 574e1dae
|
# tb_core.u_sdram32 : at time 64123.0 ns READ : Bank = 0 Row = 520, Col = 188, Data = 574e1dae
|
# READ STATUS: Burst-No: 1 Addr: 002082ea Rxd: 1b978f37
|
# READ STATUS: Burst-No: 1 Addr: 002082ea Rxd: 1b978f37
|
# tb_core.u_sdram32 : at time 63173.0 ns READ : Bank = 0 Row = 520, Col = 189, Data = fc4ca4f8
|
# tb_core.u_sdram32 : at time 64133.0 ns READ : Bank = 0 Row = 520, Col = 189, Data = fc4ca4f8
|
# READ STATUS: Burst-No: 2 Addr: 002082ec Rxd: 574e1dae
|
# READ STATUS: Burst-No: 2 Addr: 002082ec Rxd: 574e1dae
|
# tb_core.u_sdram32 : at time 63183.0 ns READ : Bank = 0 Row = 520, Col = 190, Data = 90184e20
|
# tb_core.u_sdram32 : at time 64143.0 ns READ : Bank = 0 Row = 520, Col = 190, Data = 90184e20
|
# READ STATUS: Burst-No: 3 Addr: 002082ee Rxd: fc4ca4f8
|
# READ STATUS: Burst-No: 3 Addr: 002082ee Rxd: fc4ca4f8
|
# tb_core.u_sdram32 : at time 63193.0 ns READ : Bank = 0 Row = 520, Col = 191, Data = ed1b50da
|
# tb_core.u_sdram32 : at time 64153.0 ns READ : Bank = 0 Row = 520, Col = 191, Data = ed1b50da
|
# READ STATUS: Burst-No: 4 Addr: 002082f0 Rxd: 90184e20
|
# READ STATUS: Burst-No: 4 Addr: 002082f0 Rxd: 90184e20
|
# tb_core.u_sdram32 : at time 63203.0 ns READ : Bank = 0 Row = 520, Col = 192, Data = 913e0222
|
# tb_core.u_sdram32 : at time 64163.0 ns READ : Bank = 0 Row = 520, Col = 192, Data = 913e0222
|
# READ STATUS: Burst-No: 5 Addr: 002082f2 Rxd: ed1b50da
|
# READ STATUS: Burst-No: 5 Addr: 002082f2 Rxd: ed1b50da
|
# tb_core.u_sdram32 : at time 63213.0 ns READ : Bank = 0 Row = 520, Col = 193, Data = 763355ec
|
# tb_core.u_sdram32 : at time 64173.0 ns READ : Bank = 0 Row = 520, Col = 193, Data = 763355ec
|
# READ STATUS: Burst-No: 6 Addr: 002082f4 Rxd: 913e0222
|
# READ STATUS: Burst-No: 6 Addr: 002082f4 Rxd: 913e0222
|
# tb_core.u_sdram32 : at time 63223.0 ns READ : Bank = 0 Row = 520, Col = 194, Data = 9535122a
|
# tb_core.u_sdram32 : at time 64183.0 ns READ : Bank = 0 Row = 520, Col = 194, Data = 9535122a
|
# READ STATUS: Burst-No: 7 Addr: 002082f6 Rxd: 763355ec
|
# READ STATUS: Burst-No: 7 Addr: 002082f6 Rxd: 763355ec
|
# tb_core.u_sdram32 : at time 63233.0 ns READ : Bank = 0 Row = 520, Col = 195, Data = 3d7f5b7a
|
# tb_core.u_sdram32 : at time 64193.0 ns READ : Bank = 0 Row = 520, Col = 195, Data = 3d7f5b7a
|
# tb_core.u_sdram32 : at time 63237.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 64197.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 8 Addr: 002082f8 Rxd: 9535122a
|
# READ STATUS: Burst-No: 8 Addr: 002082f8 Rxd: 9535122a
|
# tb_core.u_sdram32 : at time 63243.0 ns READ : Bank = 0 Row = 520, Col = 196, Data = 0f1e511e
|
# tb_core.u_sdram32 : at time 64203.0 ns READ : Bank = 0 Row = 520, Col = 196, Data = 0f1e511e
|
# READ STATUS: Burst-No: 9 Addr: 002082fa Rxd: 3d7f5b7a
|
# READ STATUS: Burst-No: 9 Addr: 002082fa Rxd: 3d7f5b7a
|
# tb_core.u_sdram32 : at time 63253.0 ns READ : Bank = 0 Row = 520, Col = 197, Data = f4a1dae9
|
# tb_core.u_sdram32 : at time 64213.0 ns READ : Bank = 0 Row = 520, Col = 197, Data = f4a1dae9
|
# READ STATUS: Burst-No: 10 Addr: 002082fc Rxd: 0f1e511e
|
# READ STATUS: Burst-No: 10 Addr: 002082fc Rxd: 0f1e511e
|
# READ STATUS: Burst-No: 11 Addr: 002082fe Rxd: f4a1dae9
|
# READ STATUS: Burst-No: 11 Addr: 002082fe Rxd: f4a1dae9
|
# tb_core.u_sdram32 : at time 63447.0 ns ACT : Bank = 0 Row = 591
|
# tb_core.u_sdram32 : at time 64407.0 ns ACT : Bank = 0 Row = 591
|
# tb_core.u_sdram32 : at time 63513.0 ns READ : Bank = 0 Row = 591, Col = 186, Data = b704e26e
|
# tb_core.u_sdram32 : at time 64473.0 ns READ : Bank = 0 Row = 591, Col = 186, Data = b704e26e
|
# tb_core.u_sdram32 : at time 63523.0 ns READ : Bank = 0 Row = 591, Col = 187, Data = af455e5e
|
# tb_core.u_sdram32 : at time 64483.0 ns READ : Bank = 0 Row = 591, Col = 187, Data = af455e5e
|
# READ STATUS: Burst-No: 0 Addr: 0024f2eb Rxd: b704e26e
|
# READ STATUS: Burst-No: 0 Addr: 0024f2eb Rxd: b704e26e
|
# tb_core.u_sdram32 : at time 63533.0 ns READ : Bank = 0 Row = 591, Col = 188, Data = 3e502d7c
|
# tb_core.u_sdram32 : at time 64493.0 ns READ : Bank = 0 Row = 591, Col = 188, Data = 3e502d7c
|
# READ STATUS: Burst-No: 1 Addr: 0024f2ed Rxd: af455e5e
|
# READ STATUS: Burst-No: 1 Addr: 0024f2ed Rxd: af455e5e
|
# tb_core.u_sdram32 : at time 63543.0 ns READ : Bank = 0 Row = 591, Col = 189, Data = 22c03145
|
# tb_core.u_sdram32 : at time 64503.0 ns READ : Bank = 0 Row = 591, Col = 189, Data = 22c03145
|
# READ STATUS: Burst-No: 2 Addr: 0024f2ef Rxd: 3e502d7c
|
# READ STATUS: Burst-No: 2 Addr: 0024f2ef Rxd: 3e502d7c
|
# tb_core.u_sdram32 : at time 63553.0 ns READ : Bank = 0 Row = 591, Col = 190, Data = c5cb548b
|
# tb_core.u_sdram32 : at time 64513.0 ns READ : Bank = 0 Row = 591, Col = 190, Data = c5cb548b
|
# READ STATUS: Burst-No: 3 Addr: 0024f2f1 Rxd: 22c03145
|
# READ STATUS: Burst-No: 3 Addr: 0024f2f1 Rxd: 22c03145
|
# tb_core.u_sdram32 : at time 63563.0 ns READ : Bank = 0 Row = 591, Col = 191, Data = 094bd312
|
# tb_core.u_sdram32 : at time 64523.0 ns READ : Bank = 0 Row = 591, Col = 191, Data = 094bd312
|
# READ STATUS: Burst-No: 4 Addr: 0024f2f3 Rxd: c5cb548b
|
# READ STATUS: Burst-No: 4 Addr: 0024f2f3 Rxd: c5cb548b
|
# tb_core.u_sdram32 : at time 63573.0 ns READ : Bank = 0 Row = 591, Col = 192, Data = 1bf8bd37
|
# tb_core.u_sdram32 : at time 64533.0 ns READ : Bank = 0 Row = 591, Col = 192, Data = 1bf8bd37
|
# READ STATUS: Burst-No: 5 Addr: 0024f2f5 Rxd: 094bd312
|
# READ STATUS: Burst-No: 5 Addr: 0024f2f5 Rxd: 094bd312
|
# tb_core.u_sdram32 : at time 63583.0 ns READ : Bank = 0 Row = 591, Col = 193, Data = c1c3d683
|
# tb_core.u_sdram32 : at time 64543.0 ns READ : Bank = 0 Row = 591, Col = 193, Data = c1c3d683
|
# READ STATUS: Burst-No: 6 Addr: 0024f2f7 Rxd: 1bf8bd37
|
# READ STATUS: Burst-No: 6 Addr: 0024f2f7 Rxd: 1bf8bd37
|
# tb_core.u_sdram32 : at time 63593.0 ns READ : Bank = 0 Row = 591, Col = 194, Data = f0ab00e1
|
# tb_core.u_sdram32 : at time 64553.0 ns READ : Bank = 0 Row = 591, Col = 194, Data = f0ab00e1
|
# READ STATUS: Burst-No: 7 Addr: 0024f2f9 Rxd: c1c3d683
|
# READ STATUS: Burst-No: 7 Addr: 0024f2f9 Rxd: c1c3d683
|
# tb_core.u_sdram32 : at time 63603.0 ns READ : Bank = 0 Row = 591, Col = 195, Data = 674fdfce
|
# tb_core.u_sdram32 : at time 64563.0 ns READ : Bank = 0 Row = 591, Col = 195, Data = 674fdfce
|
# tb_core.u_sdram32 : at time 63607.0 ns BST : Burst Terminate
|
# tb_core.u_sdram32 : at time 64567.0 ns BST : Burst Terminate
|
# READ STATUS: Burst-No: 8 Addr: 0024f2fb Rxd: f0ab00e1
|
# READ STATUS: Burst-No: 8 Addr: 0024f2fb Rxd: f0ab00e1
|
# tb_core.u_sdram32 : at time 63613.0 ns READ : Bank = 0 Row = 591, Col = 196, Data = a5365c4a
|
# tb_core.u_sdram32 : at time 64573.0 ns READ : Bank = 0 Row = 591, Col = 196, Data = a5365c4a
|
# READ STATUS: Burst-No: 9 Addr: 0024f2fd Rxd: 674fdfce
|
# READ STATUS: Burst-No: 9 Addr: 0024f2fd Rxd: 674fdfce
|
# tb_core.u_sdram32 : at time 63623.0 ns READ : Bank = 0 Row = 591, Col = 197, Data = 6acd73d5
|
# tb_core.u_sdram32 : at time 64583.0 ns READ : Bank = 0 Row = 591, Col = 197, Data = 6acd73d5
|
# READ STATUS: Burst-No: 10 Addr: 0024f2ff Rxd: a5365c4a
|
# READ STATUS: Burst-No: 10 Addr: 0024f2ff Rxd: a5365c4a
|
# READ STATUS: Burst-No: 11 Addr: 0024f301 Rxd: 6acd73d5
|
# READ STATUS: Burst-No: 11 Addr: 0024f301 Rxd: 6acd73d5
|
# tb_core.u_sdram32 : at time 71837.0 ns AREF : Auto Refresh
|
# tb_core.u_sdram32 : at time 71837.0 ns AREF : Auto Refresh
|
# tb_core.u_sdram32 : at time 71927.0 ns AREF : Auto Refresh
|
# tb_core.u_sdram32 : at time 71927.0 ns AREF : Auto Refresh
|
# tb_core.u_sdram32 : at time 72017.0 ns AREF : Auto Refresh
|
# tb_core.u_sdram32 : at time 72017.0 ns AREF : Auto Refresh
|
| Line 4185... |
Line 4086... |
# tb_core.u_sdram32 : at time 72287.0 ns AREF : Auto Refresh
|
# tb_core.u_sdram32 : at time 72287.0 ns AREF : Auto Refresh
|
###############################
|
###############################
|
# STATUS: SDRAM Write/Read TEST PASSED
|
# STATUS: SDRAM Write/Read TEST PASSED
|
###############################
|
###############################
|
# ** Note: $finish : ../tb/tb_core.sv(442)
|
# ** Note: $finish : ../tb/tb_core.sv(442)
|
# Time: 73750 ns Iteration: 0 Instance: /tb_core
|
# Time: 74710 ns Iteration: 0 Instance: /tb_core
|
### test 1: basic_test1 --> PASSED
|
### test 1: basic_test1 --> PASSED
|
###########################################
|
###########################################
|
|
|
###########################################
|
###########################################
|
### Test Logs
|
### Test Logs
|
