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[/] [sdr_ctrl/] [trunk/] [verif/] [log/] [top_SDR_32BIT_basic_test1.log] - Diff between revs 46 and 48

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Rev 46 Rev 48
Line 9186... Line 9186...
# tb_top.u_sdram32 : at time  411852.0 ns AREF : Auto Refresh
# tb_top.u_sdram32 : at time  411852.0 ns AREF : Auto Refresh
# tb_top.u_sdram32 : at time  412032.0 ns AREF : Auto Refresh
# tb_top.u_sdram32 : at time  412032.0 ns AREF : Auto Refresh
###############################
###############################
# STATUS: SDRAM Write/Read TEST PASSED
# STATUS: SDRAM Write/Read TEST PASSED
###############################
###############################
# ** Note: $finish    : ../tb/tb_top.sv(365)
# ** Note: $finish    : ../tb/tb_top.sv(362)
#    Time: 413400 ns  Iteration: 0  Instance: /tb_top
#    Time: 413400 ns  Iteration: 0  Instance: /tb_top

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