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[/] [sdr_ctrl/] [trunk/] [verif/] [log/] [top_sdr32_sim.log] - Diff between revs 46 and 48
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Rev 48 |
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Line 9213... |
# tb_top.u_sdram32 : at time 411852.0 ns AREF : Auto Refresh
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# tb_top.u_sdram32 : at time 411852.0 ns AREF : Auto Refresh
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# tb_top.u_sdram32 : at time 412032.0 ns AREF : Auto Refresh
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# tb_top.u_sdram32 : at time 412032.0 ns AREF : Auto Refresh
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###############################
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###############################
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# STATUS: SDRAM Write/Read TEST PASSED
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# STATUS: SDRAM Write/Read TEST PASSED
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###############################
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###############################
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# ** Note: $finish : ../tb/tb_top.sv(365)
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# ** Note: $finish : ../tb/tb_top.sv(362)
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# Time: 413400 ns Iteration: 0 Instance: /tb_top
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# Time: 413400 ns Iteration: 0 Instance: /tb_top
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### test 1: basic_test1 --> PASSED
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### test 1: basic_test1 --> PASSED
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###########################################
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###########################################
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###########################################
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###########################################
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