| Line 113... |
Line 113... |
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// CAS Latency Decode
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// CAS Latency Decode
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wire Cas_latency_2 = ~Mode_reg[6] & Mode_reg[5] & ~Mode_reg[4];
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wire Cas_latency_2 = ~Mode_reg[6] & Mode_reg[5] & ~Mode_reg[4];
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wire Cas_latency_3 = ~Mode_reg[6] & Mode_reg[5] & Mode_reg[4];
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wire Cas_latency_3 = ~Mode_reg[6] & Mode_reg[5] & Mode_reg[4];
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`ifdef VERBOSE
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wire Debug = 1'b1; // Debug messages : 1 = On
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`else
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wire Debug = 1'b0; // Debug messages : 1 = On
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`endif
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// Write Burst Mode
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// Write Burst Mode
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wire Write_burst_mode = Mode_reg[9];
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wire Write_burst_mode = Mode_reg[9];
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reg Debug; // Debug messages : 1 = On
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wire Dq_chk = Sys_clk & Data_in_enable; // Check setup/hold time for DQ
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wire Dq_chk = Sys_clk & Data_in_enable; // Check setup/hold time for DQ
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assign Dq = Dq_reg; // DQ buffer
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assign Dq = Dq_reg; // DQ buffer
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// Commands Operation
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// Commands Operation
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| Line 156... |
Line 160... |
time RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3;
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time RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3;
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time RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3;
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time RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3;
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time RP_chk0, RP_chk1, RP_chk2, RP_chk3;
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time RP_chk0, RP_chk1, RP_chk2, RP_chk3;
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initial begin
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initial begin
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Debug = 1'b0;
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Dq_reg = {data_bits{1'bz}};
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Dq_reg = {data_bits{1'bz}};
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{Data_in_enable, Data_out_enable} = 0;
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{Data_in_enable, Data_out_enable} = 0;
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{Act_b0, Act_b1, Act_b2, Act_b3} = 4'b0000;
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{Act_b0, Act_b1, Act_b2, Act_b3} = 4'b0000;
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{Pc_b0, Pc_b1, Pc_b2, Pc_b3} = 4'b0000;
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{Pc_b0, Pc_b1, Pc_b2, Pc_b3} = 4'b0000;
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