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https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk
[/] [sdr_ctrl/] [trunk/] [verif/] [run/] [compile.modelsim] - Diff between revs 5 and 29
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Rev 5 |
Rev 29 |
Line 4... |
Line 4... |
vlib work
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vlib work
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else
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else
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\rm -rf work
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\rm -rf work
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vlib work
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vlib work
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endif
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endif
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if($1 == "core") then # run SDRAM Core level test case
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vlog -work work +define+$1 -f filelist.f
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vlog -work work +define+$2 -f filelist_core.f
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else # Run SDRAM Top Level test cases
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vlog -work work +define+$2 -f filelist_top.f
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endif
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