URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [verif/] [run/] [read.me] - Diff between revs 5 and 45

Rev 5	Rev 45
Line 1...	Line 1...
`1. To run SDRM 16 Bit Test`	`1. To run SDRM 16 Bit Test`
`run_modelsim SDR_16BITa`	`run_modelsim top SDR_16BITa`
`Note: All the logs will be prefixed with SDR_16BBIT`	`Note: All the logs will be prefixed with SDR_16BBIT`
`2. To run SDRAM 32 Bit Test`
`run_modelsim SDR_32BIT`	`2. To run SDRAM top 32 Bit Test`
	`run_modelsim top SDR_32BIT`
`Note: All the logs will be prefixed with SDR_32BBIT`	`Note: All the logs will be prefixed with SDR_32BBIT`
`3. to debug the test in modelsim`
`./compile_modelsim`	`3. To run SDRM 8 Bit Test`
	`run_modelsim top SDR_8BIT`

	`4. to debug the test in modelsim`
	`./compile_modelsim`
`vsim tb_top &`	`vsim tb_top &`

	`5. to complile indipendently`
	`./compile_modelsim`

	`6. To run SDRM 16 Bit Test at SDRAM Core level`
	`run_modelsim core SDR_16BITa`
	`Note: All the logs will be prefixed with SDR_16BBIT`

	`7. To run SDRAM top 32 Bit Test at SDRAM Core level`
	`run_modelsim core SDR_32BIT`
	`Note: All the logs will be prefixed with SDR_32BBIT`

	`8. To run SDRM 8 Bit Test at SDRAM Core level`
	`run_modelsim core SDR_8BIT`