| Line 7... |
Line 7... |
//// Description ////
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//// Description ////
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//// SDRAM CTRL definitions. ////
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//// SDRAM CTRL definitions. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// nothing ////
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//// nothing ////
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// Version :0.1 - Test Bench automation is improvised with ////
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// seperate data,address,burst length fifo. ////
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// Now user can create different write and ////
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// read sequence ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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| Line 228... |
Line 232... |
.Dqm (sdr_dqm )
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.Dqm (sdr_dqm )
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);
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);
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`endif
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`endif
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//--------------------
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//--------------------
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// Write/Read Burst FIFO
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// data/address/burst length FIFO
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//--------------------
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//--------------------
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int wrdfifo[$]; // write data fifo
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int dfifo[$]; // data fifo
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int rddfifo[$]; // read data fifo
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int afifo[$]; // address fifo
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int bfifo[$]; // Burst Length fifo
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reg [31:0] read_data;
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reg [31:0] read_data;
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reg [31:0] ErrCnt;
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reg [31:0] ErrCnt;
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int k;
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int k;
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reg [31:0] StartAddr;
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reg [31:0] StartAddr;
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| Line 263... |
Line 268... |
#1000;
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#1000;
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wait(u_dut.sdr_init_done == 1);
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wait(u_dut.sdr_init_done == 1);
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#1000;
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#1000;
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wrdfifo.push_back(32'h11223344);
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burst_write(32'h4_0000,6'h4);
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wrdfifo.push_back(32'h22334455);
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wrdfifo.push_back(32'h33445566);
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wrdfifo.push_back(32'h44556677);
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wrdfifo.push_back(32'h55667788);
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burst_write(32'h40000);
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#1000;
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#1000;
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burst_read(32'h40000);
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burst_read();
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#1000;
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#1000;
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burst_write(32'h7000_0000);
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burst_write(32'h0040_0000,6'h5);
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#1000;
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#1000;
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burst_read(32'h7000_0000);
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burst_read();
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// 4 Write & 4 Read
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burst_write(32'h4_0000,6'h4);
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burst_write(32'h5_0000,6'h5);
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burst_write(32'h6_0000,6'h6);
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burst_write(32'h7_0000,6'h7);
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burst_read();
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burst_read();
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burst_read();
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burst_read();
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// 2 write and 2 read random
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for(k=0; k < 20; k++) begin
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for(k=0; k < 20; k++) begin
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StartAddr = $random & 32'h07FFFFFF;
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StartAddr = $random & 32'h003FFFFF;
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burst_write(StartAddr);
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burst_write(StartAddr,($random & 8'h3f)+1);
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#1000;
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#100;
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burst_read(StartAddr);
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StartAddr = $random & 32'h003FFFFF;
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burst_write(StartAddr,($random & 8'h3f)+1);
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#100;
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burst_read();
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#100;
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burst_read();
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#100;
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end
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end
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#10000;
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#10000;
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$display("###############################");
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$display("###############################");
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if(ErrCnt == 0)
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if(ErrCnt == 0)
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$display("STATUS: SDRAM Write/Read TEST PASSED");
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$display("STATUS: SDRAM Write/Read TEST PASSED");
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| Line 298... |
Line 318... |
$display("###############################");
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$display("###############################");
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$finish;
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$finish;
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end
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end
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task burst_write;
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task burst_write;
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input [31:0] Address;
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input [31:0] Address;
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input [7:0] bl;
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int i;
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int i;
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begin
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begin
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afifo.push_back(Address);
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bfifo.push_back(bl);
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@ (negedge sdram_clk);
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@ (negedge sdram_clk);
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app_req = 1;
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app_req = 1;
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app_wr_en_n = 0;
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app_wr_en_n = 0;
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app_req_wr_n = 1'b0;
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app_req_wr_n = 1'b0;
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$display("Write Address: %x, Burst Size: %d",Address,wrdfifo.size);
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app_req_addr = Address[31:2];
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app_req_addr = Address[31:2];
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app_req_len = wrdfifo.size;
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app_req_len = bl;
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$display("Write Address: %x, Burst Size: %d",Address,bl);
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// wait for app_req_ack == 1
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// wait for app_req_ack == 1
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do begin
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do begin
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@ (posedge sdram_clk);
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@ (posedge sdram_clk);
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end while(app_req_ack == 1'b0);
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end while(app_req_ack == 1'b0);
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@ (negedge sdram_clk);
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@ (negedge sdram_clk);
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app_req = 0;
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app_req = 0;
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for(i=0; i < wrdfifo.size; i++) begin
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for(i=0; i < bl; i++) begin
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app_wr_data = wrdfifo[i];
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app_wr_data = $random & 32'hFFFFFFFF;
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dfifo.push_back(app_wr_data);
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do begin
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do begin
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@ (posedge sdram_clk);
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@ (posedge sdram_clk);
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end while(app_wr_next_req == 1'b0);
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end while(app_wr_next_req == 1'b0);
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@ (negedge sdram_clk);
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@ (negedge sdram_clk);
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$display("Status: Burst-No: %d Write Address: %x WriteData: %x ",i,Address,app_wr_data);
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$display("Status: Burst-No: %d Write Address: %x WriteData: %x ",i,Address,app_wr_data);
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end
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end
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app_req = 0;
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app_req = 0;
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app_wr_en_n = 4'hF;
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app_wr_en_n = 4'hF;
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end
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end
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endtask
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endtask
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task burst_read;
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task burst_read;
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input [31:0] Address;
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reg [31:0] Address;
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reg [7:0] bl;
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int i,j;
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int i,j;
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reg [31:0] rd_data;
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reg [31:0] exp_data;
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begin
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begin
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@ (negedge sdram_clk);
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Address = afifo.pop_front();
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bl = bfifo.pop_front();
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app_req = 1;
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app_req = 1;
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app_wr_en_n = 0;
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app_wr_en_n = 0;
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app_req_wr_n = 1;
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app_req_wr_n = 1;
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app_req_addr = Address[29:2];
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app_req_addr = Address[29:2];
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app_req_len = wrdfifo.size;
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app_req_len = bl;
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// wait for app_req_ack == 1
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// wait for app_req_ack == 1
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do begin
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do begin
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@ (posedge sdram_clk);
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@ (posedge sdram_clk);
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end while(app_req_ack == 1'b0);
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end while(app_req_ack == 1'b0);
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@ (negedge sdram_clk);
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@ (negedge sdram_clk);
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app_req = 0;
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app_req = 0;
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for(j=0; j < wrdfifo.size; j++) begin
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for(j=0; j < bl; j++) begin
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wait(app_rd_valid == 1);
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wait(app_rd_valid == 1);
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if(app_rd_data !== wrdfifo[j]) begin
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exp_data = dfifo.pop_front(); // Exptected Read Data
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$display("READ ERROR: Burst-No: %d Addr: %x Rxp: %x Exd: %x",j,Address+(j*2),app_rd_data,wrdfifo[j]);
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if(app_rd_data !== exp_data) begin
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$display("READ ERROR: Burst-No: %d Addr: %x Rxp: %x Exd: %x",j,Address+(j*2),app_rd_data,exp_data);
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ErrCnt = ErrCnt+1;
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ErrCnt = ErrCnt+1;
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end else begin
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end else begin
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$display("READ STATUS: Burst-No: %d Addr: %x Rxd: %x",j,Address+(j*2),app_rd_data);
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$display("READ STATUS: Burst-No: %d Addr: %x Rxd: %x",j,Address+(j*2),app_rd_data);
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end
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end
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@ (posedge sdram_clk);
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@ (posedge sdram_clk);
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