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[/] [sdr_ctrl/] [trunk/] [verif/] [tb/] [tb_top.sv] - Diff between revs 22 and 24

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//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
 
 
`timescale 1ns/1ps
`timescale 1ns/1ps
 
 
 
// This testbench verify with SDRAM TOP
 
 
module tb_top;
module tb_top;
 
 
parameter P_SYS  = 10;     //    100MHz
parameter P_SYS  = 10;     //    100MHz
 
 
// General
// General

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