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[/] [sdr_ctrl/] [trunk/] [verif/] [tb/] [tb_top.sv] - Diff between revs 22 and 24
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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`timescale 1ns/1ps
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`timescale 1ns/1ps
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// This testbench verify with SDRAM TOP
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module tb_top;
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module tb_top;
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parameter P_SYS = 10; // 100MHz
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parameter P_SYS = 10; // 100MHz
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// General
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// General
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