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[/] [sdr_ctrl/] [trunk/] [verif/] [tb/] [tb_top.sv] - Diff between revs 37 and 38
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Rev 37 |
Rev 38 |
Line 113... |
Line 113... |
`else // 8 BIT SDRAM
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`else // 8 BIT SDRAM
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sdrc_top #(.SDR_DW(8),.SDR_BW(1)) u_dut(
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sdrc_top #(.SDR_DW(8),.SDR_BW(1)) u_dut(
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`endif
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`endif
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// System
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// System
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`ifdef SDR_32BIT
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`ifdef SDR_32BIT
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.sdr_width (2'b00 ), // 32 BIT SDRAM
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.cfg_sdr_width (2'b00 ), // 32 BIT SDRAM
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`elsif SDR_16BIT
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`elsif SDR_16BIT
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.sdr_width (2'b01 ), // 16 BIT SDRAM
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.cfg_sdr_width (2'b01 ), // 16 BIT SDRAM
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`else
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`else
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.sdr_width (2'b10 ), // 8 BIT SDRAM
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.cfg_sdr_width (2'b10 ), // 8 BIT SDRAM
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`endif
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`endif
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.cfg_colbits (2'b00 ), // 8 Bit Column Address
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.cfg_colbits (2'b00 ), // 8 Bit Column Address
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/* WISH BONE */
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/* WISH BONE */
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.wb_rst_i (!RESETN ),
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.wb_rst_i (!RESETN ),
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