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https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk
[/] [sdr_ctrl/] [trunk/] [verif/] [tb/] [tb_top.sv] - Diff between revs 53 and 56
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| Rev 53 |
Rev 56 |
| Line 76... |
Line 76... |
//--------------------------------------
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//--------------------------------------
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// Wish Bone Interface
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// Wish Bone Interface
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// -------------------------------------
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// -------------------------------------
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reg wb_stb_i ;
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reg wb_stb_i ;
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wire wb_ack_o ;
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wire wb_ack_o ;
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reg [29:0] wb_addr_i ;
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reg [24:0] wb_addr_i ;
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reg wb_we_i ; // 1 - Write, 0 - Read
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reg wb_we_i ; // 1 - Write, 0 - Read
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reg [dw-1:0] wb_dat_i ;
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reg [dw-1:0] wb_dat_i ;
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reg [dw/8-1:0] wb_sel_i ; // Byte enable
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reg [dw/8-1:0] wb_sel_i ; // Byte enable
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wire [dw-1:0] wb_dat_o ;
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wire [dw-1:0] wb_dat_o ;
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reg wb_cyc_i ;
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reg wb_cyc_i ;
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| Line 450... |
Line 450... |
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$display("Status: Burst-No: %d Write Address: %x WriteData: %x ",i,wb_addr_i,wb_dat_i);
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$display("Status: Burst-No: %d Write Address: %x WriteData: %x ",i,wb_addr_i,wb_dat_i);
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end
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end
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wb_stb_i = 0;
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wb_stb_i = 0;
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wb_cyc_i = 0;
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wb_cyc_i = 0;
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wb_we_i = 'hx;
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wb_sel_i = 'hx;
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wb_addr_i = 'hx;
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wb_dat_i = 'hx;
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end
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end
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endtask
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endtask
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task burst_read;
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task burst_read;
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reg [31:0] Address;
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reg [31:0] Address;
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| Line 485... |
Line 489... |
end
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end
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@ (negedge sdram_clk);
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@ (negedge sdram_clk);
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end
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end
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wb_stb_i = 0;
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wb_stb_i = 0;
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wb_cyc_i = 0;
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wb_cyc_i = 0;
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wb_we_i = 'hx;
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wb_addr_i = 'hx;
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end
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end
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endtask
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endtask
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endmodule
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endmodule
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