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https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk
[/] [sdr_ctrl/] [trunk/] [verif/] [tb/] [tb_top.sv] - Diff between revs 56 and 68
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| Rev 56 |
Rev 68 |
| Line 76... |
Line 76... |
//--------------------------------------
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//--------------------------------------
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// Wish Bone Interface
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// Wish Bone Interface
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// -------------------------------------
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// -------------------------------------
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reg wb_stb_i ;
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reg wb_stb_i ;
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wire wb_ack_o ;
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wire wb_ack_o ;
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reg [24:0] wb_addr_i ;
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reg [25:0] wb_addr_i ;
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reg wb_we_i ; // 1 - Write, 0 - Read
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reg wb_we_i ; // 1 - Write, 0 - Read
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reg [dw-1:0] wb_dat_i ;
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reg [dw-1:0] wb_dat_i ;
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reg [dw/8-1:0] wb_sel_i ; // Byte enable
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reg [dw/8-1:0] wb_sel_i ; // Byte enable
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wire [dw-1:0] wb_dat_o ;
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wire [dw-1:0] wb_dat_o ;
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reg wb_cyc_i ;
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reg wb_cyc_i ;
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| Line 102... |
Line 102... |
wire [7:0] Dq ; // SDRAM Read/Write Data Bus
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wire [7:0] Dq ; // SDRAM Read/Write Data Bus
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wire [0:0] sdr_dqm ; // SDRAM DATA Mask
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wire [0:0] sdr_dqm ; // SDRAM DATA Mask
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`endif
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`endif
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wire [1:0] sdr_ba ; // SDRAM Bank Select
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wire [1:0] sdr_ba ; // SDRAM Bank Select
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wire [11:0] sdr_addr ; // SDRAM ADRESS
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wire [12:0] sdr_addr ; // SDRAM ADRESS
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wire sdr_init_done ; // SDRAM Init Done
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wire sdr_init_done ; // SDRAM Init Done
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// to fix the sdram interface timing issue
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// to fix the sdram interface timing issue
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wire #(2.0) sdram_clk_d = sdram_clk;
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wire #(2.0) sdram_clk_d = sdram_clk;
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| Line 173... |
Line 173... |
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`ifdef SDR_32BIT
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`ifdef SDR_32BIT
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mt48lc2m32b2 #(.data_bits(32)) u_sdram32 (
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mt48lc2m32b2 #(.data_bits(32)) u_sdram32 (
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.Dq (Dq ) ,
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.Dq (Dq ) ,
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.Addr (sdr_addr ),
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.Addr (sdr_addr[11:0] ),
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.Ba (sdr_ba ),
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.Ba (sdr_ba ),
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.Clk (sdram_clk_d ),
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.Clk (sdram_clk_d ),
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.Cke (sdr_cke ),
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.Cke (sdr_cke ),
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.Cs_n (sdr_cs_n ),
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.Cs_n (sdr_cs_n ),
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.Ras_n (sdr_ras_n ),
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.Ras_n (sdr_ras_n ),
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| Line 188... |
Line 188... |
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`elsif SDR_16BIT
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`elsif SDR_16BIT
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IS42VM16400K u_sdram16 (
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IS42VM16400K u_sdram16 (
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.dq (Dq ),
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.dq (Dq ),
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.addr (sdr_addr ),
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.addr (sdr_addr[11:0] ),
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.ba (sdr_ba ),
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.ba (sdr_ba ),
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.clk (sdram_clk_d ),
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.clk (sdram_clk_d ),
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.cke (sdr_cke ),
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.cke (sdr_cke ),
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.csb (sdr_cs_n ),
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.csb (sdr_cs_n ),
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.rasb (sdr_ras_n ),
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.rasb (sdr_ras_n ),
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| Line 203... |
Line 203... |
`else
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`else
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mt48lc8m8a2 #(.data_bits(8)) u_sdram8 (
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mt48lc8m8a2 #(.data_bits(8)) u_sdram8 (
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.Dq (Dq ) ,
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.Dq (Dq ) ,
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.Addr (sdr_addr ),
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.Addr (sdr_addr[11:0] ),
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.Ba (sdr_ba ),
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.Ba (sdr_ba ),
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.Clk (sdram_clk_d ),
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.Clk (sdram_clk_d ),
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.Cke (sdr_cke ),
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.Cke (sdr_cke ),
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.Cs_n (sdr_cs_n ),
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.Cs_n (sdr_cs_n ),
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.Ras_n (sdr_ras_n ),
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.Ras_n (sdr_ras_n ),
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