URL
https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk
[/] [sdr_ctrl/] [trunk/] [verif/] [tb/] [tb_top.sv] - Diff between revs 70 and 73
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| Rev 70 |
Rev 73 |
| Line 437... |
Line 437... |
for(i=0; i < bl; i++) begin
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for(i=0; i < bl; i++) begin
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wb_stb_i = 1;
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wb_stb_i = 1;
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wb_cyc_i = 1;
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wb_cyc_i = 1;
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wb_we_i = 1;
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wb_we_i = 1;
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wb_sel_i = 4'b1111;
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wb_sel_i = 4'b1111;
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wb_addr_i = Address[31:2]+i;
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wb_addr_i = {Address[31:2]+i,2'b00};
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wb_dat_i = $random & 32'hFFFFFFFF;
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wb_dat_i = $random & 32'hFFFFFFFF;
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dfifo.push_back(wb_dat_i);
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dfifo.push_back(wb_dat_i);
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do begin
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do begin
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@ (posedge sys_clk);
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@ (posedge sys_clk);
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| Line 473... |
Line 473... |
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for(j=0; j < bl; j++) begin
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for(j=0; j < bl; j++) begin
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wb_stb_i = 1;
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wb_stb_i = 1;
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wb_cyc_i = 1;
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wb_cyc_i = 1;
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wb_we_i = 0;
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wb_we_i = 0;
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wb_addr_i = Address[31:2]+j;
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wb_addr_i = {Address[31:2]+j,2'b00};
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exp_data = dfifo.pop_front(); // Exptected Read Data
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exp_data = dfifo.pop_front(); // Exptected Read Data
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do begin
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do begin
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@ (posedge sys_clk);
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@ (posedge sys_clk);
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end while(wb_ack_o == 1'b0);
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end while(wb_ack_o == 1'b0);
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