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`include "inc.h"
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//*******************************************************************************
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// S Y N T H E S I Z A B L E S D R A M C O N T R O L L E R C O R E
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//
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// This core adheres to the GNU Public License
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//
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// This is a synthesizable Synchronous DRAM controller Core. As it stands,
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// it is ready to work with 8Mbyte SDRAMs, organized as 2M x 32 at 100MHz
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// and 125MHz. For example: Samsung KM432S2030CT, Fujitsu MB81F643242B.
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//
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// The core has been carefully coded so as to be "platform-independent".
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// It has been successfully compiled and simulated under three separate
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// FPGA/CPLD platforms:
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// Xilinx Foundation Base Express V2.1i
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// Altera Max+PlusII V9.21
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// Lattice ispExpert V7.0
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//
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// The interface to the host (i.e. microprocessor, DSP, etc) is synchronous
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// and supports ony one transfer at a time. That is, burst-mode transfers
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// are not yet supported. In may ways, the interface to this core is much
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// like that of a typical SRAM. The hand-shaking between the host and the
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// SDRAM core is done through the "sdram_busy_l" signal generated by the
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// core. Whenever this signal is active low, the host must hold the address,
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// data (if doing a write), size and the controls (cs, rd/wr).
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//
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// Connection Diagram:
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// SDRAM side:
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// sd_wr_l connect to -WR pin of SDRAM
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// sd_cs_l connect to -CS pin of SDRAM
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// sd_ras_l connect to -RAS pin of SDRAM
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// sd_cas_l connect to -CAS pin of SDRAM
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// sd_dqm[3:0] connect to the DQM3,DQM2,DQM1,DQM0 pins
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// sd_addx[10:0] connect to the Address bus [10:0]
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// sd_data[31:0] connect to the data bus [31:0]
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// sd_ba[1:0] connect to BA1, BA0 pins of SDRAM
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//
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// HOST side:
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// mp_addx[22:0] connect to the address bus of the host.
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// 23 bit address bus give access to 8Mbyte
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// of the SDRAM, as byte, half-word (16bit)
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// or word (32bit)
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// mp_data_in[31:0] Unidirectional bus connected to the data out
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// of the host. To use this, enable
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// "databus_is_unidirectional" in INC.H
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// mp_data_out[31:0] Unidirectional bus connected to the data in
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// of the host. To use this, enable
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// "databus_is_unidirectional" in INC.H
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// mp_data[31:0] Bi-directional bus connected to the host's
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// data bus. To use the bi-directionla bus,
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// disable "databus_is_unidirectional" in INC.H
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// mp_rd_l Connect to the -RD output of the host
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// mp_wr_l Connect to the -WR output of the host
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// mp_cs_l Connect to the -CS of the host
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// mp_size[1:0] Connect to the size output of the host
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// if there is one. When set to 0
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// all trasnfers are 32 bits, when set to 1
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// all transfers are 8 bits, and when set to
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// 2 all xfers are 16 bits. If you want the
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// data to be lower order aligned, turn on
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// "align_data_bus" option in INC.H
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// sdram_busy_l Connect this to the wait or hold equivalent
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// input of the host. The host, must hold the
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// bus if it samples this signal as low.
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// sdram_mode_set_l When a write occurs with this set low,
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// the SDRAM's mode set register will be programmed
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// with the data supplied on the data_bus[10:0].
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//
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//
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// Author: Jeung Joon Lee joon.lee@quantum.com, cmosexod@ix.netcom.com
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//
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//*******************************************************************************
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//
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// Hierarchy:
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//
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// SDRAM.V Top Level Module
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// HOSTCONT.V Controls the interfacing between the micro and the SDRAM
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// SDRAMCNT.V This is the SDRAM controller. All data passed to and from
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// is with the HOSTCONT.
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// optional
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// MICRO.V This is the built in SDRAM tester. This module generates
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// a number of test logics which is used to test the SDRAM
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// It is basically a Micro bus generator.
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//
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/*
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*/
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module hostcont (
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// system connections
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sys_rst_l,
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sys_clk,
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// microprocessor side connections
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mp_addx,
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mp_data_in,
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mp_data_out,
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mp_rd_l,
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mp_wr_l,
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mp_cs_l,
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sdram_mode_set_l,
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sdram_busy_l,
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mp_size,
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// SDRAM side connections
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sd_addx,
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sd_data_out,
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sd_data_in,
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sd_ba,
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// SDRAMCNT side
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sd_addx10_mux,
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sd_addx_mux,
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sd_rd_ena,
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do_read,
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do_write,
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doing_refresh,
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do_modeset,
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modereg_cas_latency,
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modereg_burst_length,
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mp_data_mux,
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decoded_dqm,
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do_write_ack,
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do_read_ack,
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do_modeset_ack,
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pwrup,
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// debug
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// rd_wr_clk
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reg_mp_data_mux,
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reg_mp_addx,
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reg_sd_data,
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reg_modeset
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);
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// ****************************************
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//
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// I/O DEFINITION
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//
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// ****************************************
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// system connections
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input sys_rst_l; // asynch active low reset
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input sys_clk; // clock source to the SDRAM
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// microprocessor side connections
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input [22:0] mp_addx; // ABW bits for the addx
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input [31:0] mp_data_in; // DBW bits of data bus input (see INC.H)
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output [31:0] mp_data_out; // DBW bits of data bus output (see INC.H)
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input mp_rd_l; // micro bus read , active low
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input mp_wr_l; // micro bus write, active low
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input mp_cs_l;
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input sdram_mode_set_l; // acive low request for SDRAM mode set
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output sdram_busy_l; // active low busy output
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input [1:0] mp_size;
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// SDRAM side connections
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output [10:0] sd_addx; // 11 bits of muxed SDRAM addx
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input [31:0] sd_data_in;
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output [31:0] sd_data_out;
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output [1:0] sd_ba; // bank select output to the SDRAM
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input pwrup;
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// SDRAMCNT side
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input [1:0] sd_addx10_mux;
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input [1:0] sd_addx_mux;
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input sd_rd_ena;
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output do_write;
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output do_read;
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input doing_refresh;
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output do_modeset;
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output [2:0] modereg_cas_latency;
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output [2:0] modereg_burst_length;
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input mp_data_mux;
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output [3:0] decoded_dqm; // this is the decoded DQM according to the size. Used during writes
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input do_write_ack; // acknowledge signal from sdramcont state machine
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// saying that it is now ok to clear 'do_write' signal
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input do_read_ack; // acknowledge signal from sdramcont state machine
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// saying that is is now ok to clear 'do_read' signal
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input do_modeset_ack;
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//debug
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//output rd_wr_clk;
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output [31:0] reg_mp_data_mux;
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output [22:0] reg_mp_addx;
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output [31:0] reg_sd_data;
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output [10:0] reg_modeset;
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// ****************************************
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//
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// Memory Elements
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//
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// ****************************************
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//
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wire [22:0] reg_mp_addx;
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reg [31:0] reg_mp_data;
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reg [31:0] reg_sd_data;
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reg [3:0] decoded_dqm;
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reg [10:0] reg_modeset;
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reg [10:0] sd_addx;
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reg do_read;
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reg do_write;
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reg [2:0] do_state;
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reg do_modeset;
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reg [1:0] sd_ba;
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reg busy_a_ena;
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//wire [31:0] sd_data;
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wire [31:0] sd_data_buff;
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wire [31:0] reg_mp_data_mux;
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reg [31:0] mp_data_out;
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wire busy_a;
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wire mp_data_ena;
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wire do_read_clk;
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wire do_read_rst_clk;
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wire do_write_clk;
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wire do_modeset_clk;
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wire do_modeset_rst_clk;
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wire clock_xx;
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wire modereg_ena;
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wire read_busy;
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wire write_busy;
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wire refresh_busy;
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wire modeset_busy;
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wire do_write_rst;
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wire do_read_rst;
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wire do_modeset_rst;
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assign mp_data_ena = ~mp_rd_l;
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assign modereg_cas_latency = reg_modeset[6:4];
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assign modereg_burst_length = reg_modeset[2:0];
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assign read_busy = do_read | (~mp_rd_l & busy_a_ena);
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assign write_busy = do_write | (~mp_wr_l & busy_a_ena);
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assign modeset_busy = do_modeset;
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assign refresh_busy = `LO;
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// SDRAM BUSY SIGNAL GENERATION
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//
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// The BUSY signal is NOR'd of READ_BUSY, WRITE_BUSY and DUMB_BUSY.
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// READ_BUSY is generated while the SDRAM is performing a read. This
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// does not necessarily have to he synchronous to the micro's read.
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// The WRITE_BUSY is generated while the SDRAM is performing WRITE.
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// Again, due to the "dump-n-run" mode (only in SMART_H=1) the micro's
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// write bus cycle does not necessarily align with SDRAM's write cycle.
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// DUMB_BUSY is a signal which generates the BUSY at the falling edge of
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// micro's SDRAM_CS. This is used for those microprocessors which
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// require a device BUSY as soon as the address is placed on its bus. For
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// example, most Intel microcontrollers and small processors do have this
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// requirement. This means that one will fofeit on the dump-n-go feature.
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//
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assign sdram_busy_l = ~( read_busy |
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write_busy |
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(doing_refresh & ~mp_cs_l)|
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(modeset_busy & ~mp_cs_l)
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);
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// MP ADDRESS LATCH
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// Transparent latch
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// Used to hold the addx from the micro. Latch on the falling edge of
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// do_write.
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// BAsed on the way "do_write" is generated, we only need to latch on the writes
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// since the write can be queued, but since all reads are blocked, the latch
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// will not latch the addx on reads.
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assign reg_mp_addx = mp_addx;
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//
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// DECODED DQM LATCH
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// generate the proper DQM[3:0] masks based on the address and on the mp_size
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//
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always @(do_write or sys_rst_l or mp_addx or mp_size)
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// 32 bit masks
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// all masks are enabled (LOW)
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if (mp_size==2'b00)
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decoded_dqm <= 4'h0;
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// 16 bit masks
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// enable the masks accorsing to the half-word selected
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else if (mp_size==2'b10)
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case (mp_addx[1])
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`LO: decoded_dqm <= 4'b1100; // lower half-word enabled
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default: decoded_dqm <= 4'b0011; // upper half-word enabled
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endcase
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// 8 bit masks
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// enablethe masks according to the byte specified.
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else if (mp_size==2'b01)
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case (mp_addx[1:0])
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2'b00: decoded_dqm <= 4'b1110;
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2'b01: decoded_dqm <= 4'b1101;
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2'b10: decoded_dqm <= 4'b1011;
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default: decoded_dqm <= 4'b0111;
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endcase
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else
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decoded_dqm <= 4'bxxxx;
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// MP DATA LATCH
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// Used to hold the data from the micro. Latch on the rising edge
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// of mp_wr_l
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//
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`ifdef align_data_bus
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always @(mp_data_in or reg_mp_addx)
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// 32 bit writes
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if (mp_size==2'b00)
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reg_mp_data <= mp_data_in;
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// 16 bit writes
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else if (mp_size==2'b10)
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case(reg_mp_addx[1])
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`LO: reg_mp_data[15:0] <= mp_data_in[15:0];
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default: reg_mp_data[31:16] <= mp_data_in[15:0];
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endcase
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// 8 bit writes
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else if (mp_size==2'b01)
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case(reg_mp_addx[1:0])
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2'b00: reg_mp_data[7:0] <= mp_data_in[7:0];
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2'b01: reg_mp_data[15:8] <= mp_data_in[7:0];
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2'b10: reg_mp_data[23:16] <= mp_data_in[7:0];
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default: reg_mp_data[31:24] <= mp_data_in[7:0];
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endcase
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//---------------------------------- if data aligning is not desired -------------------
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`else
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always @(mp_data_in)
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reg_mp_data <= mp_data_in;
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`endif
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//
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// MODE REG REG
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//
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`define default_mode_reg {4'b0000,`default_mode_reg_CAS_LATENCY,`defulat_mode_reg_BURST_TYPE,`default_mode_reg_BURST_LENGHT}
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always @(posedge sys_clk or negedge sys_rst_l)
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if (~sys_rst_l)
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reg_modeset <= 10'h000;
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else
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if (pwrup)
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reg_modeset <= `default_mode_reg;
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else
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if (~sdram_mode_set_l & ~mp_cs_l & ~mp_wr_l)
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reg_modeset <= mp_data_in[10:0];
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// SD DATA REGISTER
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// This register holds in the data from the SDRAM
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//
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always @(posedge sys_clk or negedge sys_rst_l)
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if (~sys_rst_l)
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reg_sd_data <= 32'h00000000;
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else if (sd_rd_ena)
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reg_sd_data <= sd_data_buff;
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//
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// SD DATA BUS BUFFERS
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//
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assign sd_data_out = reg_mp_data;
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assign sd_data_buff = sd_data_in;
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// SDRAM SIDE ADDX
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always @(sd_addx10_mux or reg_mp_data or reg_mp_addx or reg_modeset)
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case (sd_addx10_mux)
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2'b00: sd_addx[10] <= reg_mp_addx[20];
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2'b01: sd_addx[10] <= 1'b0;
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2'b10: sd_addx[10] <= reg_modeset[10];
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default: sd_addx[10] <= 1'b1;
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endcase
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always @(sd_addx_mux or reg_modeset or reg_mp_addx)
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case (sd_addx_mux)
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2'b00: sd_addx[9:0] <= reg_mp_addx[19:10]; // ROW
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2'b01: sd_addx[9:0] <= {2'b00, reg_mp_addx[9:2]}; // COLUMN
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2'b10: sd_addx[9:0] <= reg_modeset[9:0];
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default: sd_addx[9:0] <= 10'h000;
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endcase
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// SD_BA
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always @(sd_addx_mux or reg_mp_addx)
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case (sd_addx_mux)
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2'b00: sd_ba <= reg_mp_addx[22:21];
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2'b01: sd_ba <= reg_mp_addx[22:21];
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default: sd_ba <= 2'b00;
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endcase
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// Micro data mux
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assign reg_mp_data_mux = mp_data_mux ? 32'h00000000 : reg_mp_data;
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// MP_DATA_OUT mux
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// ------------------------------- do this only if the DATA aligning is desired -------
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`ifdef align_data_bus
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always @(mp_size or reg_sd_data or mp_addx)
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case (mp_size)
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// 32 bit reads
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2'b00:
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mp_data_out <= reg_sd_data;
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// 16 bit reads
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2'b10:
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if (mp_addx[1])
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mp_data_out[15:0] <= reg_sd_data[31:16];
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else
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mp_data_out[15:0] <= reg_sd_data[15:0];
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// 8 bit reads
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default:
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case (mp_addx[1:0])
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2'b00: mp_data_out[7:0] <= reg_sd_data[7:0];
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2'b01: mp_data_out[7:0] <= reg_sd_data[15:0];
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2'b10: mp_data_out[7:0] <= reg_sd_data[23:16];
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default: mp_data_out[7:0] <= reg_sd_data[31:24];
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endcase
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endcase
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`else
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//---------------------------------- if data aligning is not desired -------------------
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always @(reg_sd_data)
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mp_data_out <= reg_sd_data;
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`endif
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//
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// DO_READ DO_WRITE DO_MODESET
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// signal generation
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//
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always @(posedge sys_clk or negedge sys_rst_l)
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if (~sys_rst_l) begin
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do_read <= `LO;
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do_write <= `LO;
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do_modeset <= `LO;
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do_state <= 3'b000;
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busy_a_ena <= `HI;
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end
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else
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case (do_state)
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// hang in here until a read or write is requested
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// (mp_rd_l = 1'b0) or (mp_wr_l = 1'b0)
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3'b000: begin
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// a read request
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if (~mp_rd_l & ~mp_cs_l) begin
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do_read <= `HI;
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do_state <= 3'b001;
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end
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// a write request
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else if (~mp_wr_l & ~mp_cs_l & sdram_mode_set_l) begin
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do_write <= `HI;
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do_state <= 3'b001;
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end
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// a mode set request
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else if (~mp_wr_l & ~mp_cs_l & ~sdram_mode_set_l) begin
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do_modeset <= `HI;
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do_state <= 3'b001;
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end
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else
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do_state <= 3'b000;
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end
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// This cycle is dummy cycle. Just to extend 'busy_ena_a'
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// to a total of 2 cycles
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3'b001:
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begin
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busy_a_ena <= `LO; // disable busy_a generation
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if (do_write)
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do_state <= 3'b011;
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else if (do_read)
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do_state <= 3'b010;
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else if (do_modeset)
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do_state <= 3'b110;
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else
|
|
do_state <= 3'b001;
|
|
end
|
|
|
|
// hang in here until the sdramcnt has acknowledged the
|
|
// read
|
|
3'b010:
|
|
if (do_read_ack) begin
|
|
do_read <= `LO;
|
|
do_state <= 3'b100;
|
|
end
|
|
else
|
|
do_state <= 3'b010;
|
|
|
|
// hang in here until the sdramcnt has acknowledged the
|
|
// write
|
|
3'b011:
|
|
if (do_write_ack) begin
|
|
do_write <= `LO;
|
|
do_state <= 3'b101;
|
|
end
|
|
else
|
|
do_state <= 3'b011;
|
|
|
|
// wait in here until the host has read the data
|
|
// (i.e. has raised its mp_rd_l high)
|
|
3'b100:
|
|
if (mp_rd_l) begin
|
|
busy_a_ena <= `HI; // re-enable busy_a generation
|
|
do_state <= 3'b000;
|
|
end
|
|
else
|
|
do_state <= 3'b100;
|
|
|
|
// wait in here until the host has relinquieshed the write bus
|
|
// (i.e. has raised its mp_wr_l high)
|
|
3'b101:
|
|
if (mp_wr_l) begin
|
|
busy_a_ena <= `HI; // re-enable busy_a generation
|
|
do_state <= 3'b000;
|
|
end
|
|
else
|
|
do_state <= 3'b101;
|
|
|
|
// hang in here until the sdramcnt has acknowledged the
|
|
// mode set
|
|
3'b110:
|
|
if (do_modeset_ack) begin
|
|
do_modeset <= `LO;
|
|
do_state <= 3'b101;
|
|
end else
|
|
do_state <= 3'b110;
|
|
|
|
|
|
endcase
|
|
|
|
|
|
|
|
|
|
endmodule
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
