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`include "inc.h"
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//*******************************************************************************
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// S Y N T H E S I Z A B L E S D R A M C O N T R O L L E R C O R E
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//
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// This core adheres to the GNU Public License
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//
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// This is a synthesizable Synchronous DRAM controller Core. As it stands,
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// it is ready to work with 8Mbyte SDRAMs, organized as 2M x 32 at 100MHz
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// and 125MHz. For example: Samsung KM432S2030CT, Fujitsu MB81F643242B.
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//
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// The core has been carefully coded so as to be "platform-independent".
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// It has been successfully compiled and simulated under three separate
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// FPGA/CPLD platforms:
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// Xilinx Foundation Base Express V2.1i
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// Altera Max+PlusII V9.21
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// Lattice ispExpert V7.0
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//
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// The interface to the host (i.e. microprocessor, DSP, etc) is synchronous
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// and supports ony one transfer at a time. That is, burst-mode transfers
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// are not yet supported. In may ways, the interface to this core is much
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// like that of a typical SRAM. The hand-shaking between the host and the
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// SDRAM core is done through the "sdram_busy_l" signal generated by the
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// core. Whenever this signal is active low, the host must hold the address,
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// data (if doing a write), size and the controls (cs, rd/wr).
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//
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// Connection Diagram:
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// SDRAM side:
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// sd_wr_l connect to -WR pin of SDRAM
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// sd_cs_l connect to -CS pin of SDRAM
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// sd_ras_l connect to -RAS pin of SDRAM
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// sd_cas_l connect to -CAS pin of SDRAM
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// sd_dqm[3:0] connect to the DQM3,DQM2,DQM1,DQM0 pins
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// sd_addx[10:0] connect to the Address bus [10:0]
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// sd_data[31:0] connect to the data bus [31:0]
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// sd_ba[1:0] connect to BA1, BA0 pins of SDRAM
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//
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// HOST side:
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// mp_addx[22:0] connect to the address bus of the host.
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// 23 bit address bus give access to 8Mbyte
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// of the SDRAM, as byte, half-word (16bit)
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// or word (32bit)
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// mp_data_in[31:0] Unidirectional bus connected to the data out
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// of the host. To use this, enable
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// "databus_is_unidirectional" in INC.H
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// mp_data_out[31:0] Unidirectional bus connected to the data in
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// of the host. To use this, enable
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// "databus_is_unidirectional" in INC.H
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// mp_data[31:0] Bi-directional bus connected to the host's
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// data bus. To use the bi-directionla bus,
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// disable "databus_is_unidirectional" in INC.H
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// mp_rd_l Connect to the -RD output of the host
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// mp_wr_l Connect to the -WR output of the host
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// mp_cs_l Connect to the -CS of the host
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// mp_size[1:0] Connect to the size output of the host
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// if there is one. When set to 0
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// all trasnfers are 32 bits, when set to 1
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// all transfers are 8 bits, and when set to
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// 2 all xfers are 16 bits. If you want the
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// data to be lower order aligned, turn on
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// "align_data_bus" option in INC.H
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// sdram_busy_l Connect this to the wait or hold equivalent
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// input of the host. The host, must hold the
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// bus if it samples this signal as low.
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// sdram_mode_set_l When a write occurs with this set low,
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// the SDRAM's mode set register will be programmed
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// with the data supplied on the data_bus[10:0].
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//
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//
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// Author: Jeung Joon Lee joon.lee@quantum.com, cmosexod@ix.netcom.com
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//
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//*******************************************************************************
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//
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// Hierarchy:
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//
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// SDRAM.V Top Level Module
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// HOSTCONT.V Controls the interfacing between the micro and the SDRAM
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// SDRAMCNT.V This is the SDRAM controller. All data passed to and from
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// is with the HOSTCONT.
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// optional
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// MICRO.V This is the built in SDRAM tester. This module generates
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// a number of test logics which is used to test the SDRAM
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// It is basically a Micro bus generator.
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//
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/*
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*/
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module sdramcnt(
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// system level stuff
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sys_rst_l,
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sys_clk,
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// SDRAM connections
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sd_wr_l,
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sd_cs_l,
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sd_ras_l,
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sd_cas_l,
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sd_dqm,
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// Host Controller connections
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do_mode_set,
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do_read,
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do_write,
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doing_refresh,
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sd_addx_mux,
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sd_addx10_mux,
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sd_rd_ena,
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sd_data_ena,
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modereg_cas_latency,
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modereg_burst_length,
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mp_data_mux,
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decoded_dqm,
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do_write_ack,
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do_read_ack,
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do_modeset_ack,
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pwrup,
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// debug
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next_state,
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autorefresh_cntr,
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autorefresh_cntr_l,
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cntr_limit
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);
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parameter N1 = 4;
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// ****************************************
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//
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// I/O DEFINITION
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//
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// ****************************************
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// System level stuff
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input sys_rst_l;
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input sys_clk;
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// SDRAM connections
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output sd_wr_l;
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output sd_cs_l;
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output sd_ras_l;
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output sd_cas_l;
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output [(N1-1):0] sd_dqm;
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// Host Controller connections
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input do_mode_set;
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input do_read;
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input do_write;
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output doing_refresh;
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output [1:0] sd_addx_mux;
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output [1:0] sd_addx10_mux;
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output sd_rd_ena;
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output sd_data_ena;
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input [2:0] modereg_cas_latency;
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input [2:0] modereg_burst_length;
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output mp_data_mux;
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input [3:0] decoded_dqm;
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output do_write_ack;
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output do_read_ack;
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output do_modeset_ack;
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output pwrup;
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// Debug
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output [3:0] next_state;
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output [3:0] autorefresh_cntr;
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output autorefresh_cntr_l;
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output [12:0] cntr_limit;
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// ****************************************
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//
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// Memory Elements
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//
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// ****************************************
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//
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reg [3:0] next_state;
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reg [7:0] refresh_timer;
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reg sd_wr_l;
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reg sd_cs_l;
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reg sd_ras_l;
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reg sd_cas_l;
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reg [3:0] sd_dqm;
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reg [1:0] sd_addx_mux;
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reg [1:0] sd_addx10_mux;
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reg sd_data_ena;
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reg pwrup; // this variable holds the power up condition
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reg [12:0] refresh_cntr; // this is the refresh counter
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reg refresh_cntr_l; // this is the refresh counter reset signal
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reg [3:0] burst_length_cntr;
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reg burst_cntr_ena;
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reg sd_rd_ena; // read latch gate, active high
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reg [12:0] cntr_limit;
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reg [3:0] modereg_burst_count;
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reg [2:0] refresh_state;
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reg mp_data_mux;
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wire do_refresh; // this bit indicates autorefresh is due
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reg doing_refresh; // this bit indicates that the state machine is
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// doing refresh.
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reg [3:0] autorefresh_cntr;
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reg autorefresh_cntr_l;
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reg do_write_ack;
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reg do_read_ack;
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reg do_modeset_ack;
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reg do_refresh_ack;
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wire Trc_expired, Ref_expired;
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assign Trc_expired = (autorefresh_cntr == 4'h6);
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assign Ref_expired = (refresh_cntr == cntr_limit);
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// State Machine
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always @(posedge sys_clk or negedge sys_rst_l)
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if (~sys_rst_l) begin
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next_state <= `state_powerup;
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autorefresh_cntr_l <= `LO;
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refresh_cntr_l <= `LO;
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pwrup <= `HI; // high indicates we've just power'd up or RESET
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sd_wr_l <= `HI;
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sd_cs_l <= `HI;
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sd_ras_l <= `HI;
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sd_cas_l <= `HI;
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sd_dqm <= 4'hF;
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sd_data_ena <= `LO;
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sd_addx_mux <= 2'b10; // select the mode reg default value
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sd_addx10_mux <= 2'b11; // select 1 as default
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sd_rd_ena <= `LO;
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mp_data_mux <= `LO;
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// refresh_cntr<= 13'h0000;
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burst_cntr_ena <= `LO; // do not enable the burst counter
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doing_refresh <= `LO;
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do_write_ack <= `LO; // do not ack as reset default
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do_read_ack <= `LO; // do not ack as reset default
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do_modeset_ack <= `LO; // do not ack as reset default
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do_refresh_ack <= `LO;
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end
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else case (next_state)
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// Power Up state
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`state_powerup: begin
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next_state <= `state_precharge;
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sd_wr_l <= `HI;
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sd_cs_l <= `HI;
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sd_ras_l <= `HI;
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sd_cas_l <= `HI;
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sd_dqm <= 4'hF;
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sd_data_ena <= `LO;
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sd_addx_mux <= 2'b10;
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sd_rd_ena <= `LO;
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pwrup <= `HI; // this is the power up run
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burst_cntr_ena <= `LO; // do not enable the burst counter
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refresh_cntr_l <= `HI; // allow the refresh cycle counter to count
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end
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// PRECHARGE both (or all) banks
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`state_precharge: begin
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sd_wr_l <= `LO;
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sd_cs_l <= `LO;
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sd_ras_l <= `LO;
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sd_cas_l <= `HI;
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sd_dqm <= 4'hF;
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sd_addx10_mux <= 2'b11; // A10 = 1'b1
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next_state <= `state_idle;
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if (do_write_ack)
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do_write_ack<= `LO; // done acknowledging the write request
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if (do_read_ack)
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do_read_ack <= `LO; // done acknowledging the read request
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end
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// Delay Trp
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// this delay is needed to meet the minimum precharge to new command
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// delay. For most parts, this is 20nS, which means you need 1 clock cycle
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// of NOP at 100MHz
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`state_delay_Trp: begin
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sd_wr_l <= `HI;
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sd_cs_l <= `HI;
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sd_ras_l <= `HI;
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if ( (refresh_cntr == cntr_limit) & (pwrup == `HI) ) begin
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doing_refresh <= `LO; // refresh cycle is done
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refresh_cntr_l <= `LO; // ..reset refresh counter
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next_state <= `state_modeset; // if this was power-up, then go and set mode reg
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end else begin
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doing_refresh <= `HI; // indicate that we're doing refresh
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next_state <= `state_auto_refresh;
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end
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end
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// Autorefresh
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`state_auto_refresh: begin
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sd_wr_l <= `HI;
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sd_cs_l <= `LO;
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sd_ras_l <= `LO;
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sd_cas_l <= `LO;
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sd_addx10_mux <= 2'b01; // A10 = 0
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next_state <= `state_auto_refresh_dly;
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autorefresh_cntr_l <= `HI; //allow refresh delay cntr (Trc) to tick
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do_refresh_ack <= `HI; // acknowledge refresh request
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end
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// This state generates the Trc delay.
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// this delay is the delay from the refresh command to the next valid command
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// most parts require this to be 60 to 70nS. So at 100MHz, we need at least
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// 6 NOPs.
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`state_auto_refresh_dly: begin
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sd_wr_l <= `HI;
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sd_cs_l <= `HI;
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sd_ras_l <= `HI;
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sd_cas_l <= `HI;
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sd_addx10_mux <= 2'b00; // select ROW again A10 = A20
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/*
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casex ( {Trc_expired, Ref_expired, pwrup, (do_write|do_read)} )
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// Trc not expired yet
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4'b0xxx: begin
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next_state <= `state_auto_refresh_dly;
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do_refresh_ack <= `LO;
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end
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// Back-back refreshes not done yet
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4'b10xx: begin
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autorefresh_cntr_l <= `LO; // reset Trc delay counter
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next_state <= `state_auto_refresh;
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end
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// This is powerup run, so go and set modereg
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4'b110x: begin
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autorefresh_cntr_l <= `LO; // reset Trc delay counter
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doing_refresh <= `LO; // refresh cycle is done
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refresh_cntr_l <= `LO; // ..reset refresh counter
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next_state <= `state_modeset;
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end
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4'b1111: begin
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autorefresh_cntr_l <= `LO; // reset Trc delay counter
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doing_refresh <= `LO; // refresh cycle is done
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refresh_cntr_l <= `LO; // ..reset refresh counter
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next_state <= `state_set_ras; // go service a pending read or write if any
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end
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4'b1110: begin
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autorefresh_cntr_l <= `LO; // reset Trc delay counter
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doing_refresh <= `LO; // refresh cycle is done
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refresh_cntr_l <= `LO; // ..reset refresh counter
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next_state <= `state_idle; // go service a pending read or write if any
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end
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endcase
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*/
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// Wait for Trc
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if (autorefresh_cntr == 4'h6) begin
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autorefresh_cntr_l <= `LO; // reset Trc delay counter
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// Check if the number of specified back-back refreshes are done
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if (refresh_cntr == cntr_limit) begin
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doing_refresh <= `LO; // refresh cycle is done
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refresh_cntr_l <= `LO; // ..reset refresh counter
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// if this is not a power-up sequence, and there are pending
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// requests, then service it.
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if (~pwrup)
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if (do_write | do_read)
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next_state <= `state_set_ras; // go service a pending read or write if any
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else
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next_state <= `state_idle; // if there are no peding RD or WR, then go to idle state
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// if this is part of power-up sequencing, we need to go and
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// set mode register.
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else
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next_state <= `state_modeset;
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end
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// IF refresh cycles not done yet, keep issuing autorefresh commands
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else
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next_state <= `state_auto_refresh;
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end
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// If Trc has not expired
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else begin
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next_state <= `state_auto_refresh_dly;
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do_refresh_ack <= `LO;
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end
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end
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// MODE SET state
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`state_modeset: begin
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next_state <= `state_idle;
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sd_wr_l <= `LO;
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sd_cs_l <= `LO;
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sd_ras_l <= `LO;
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sd_cas_l <= `LO;
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sd_addx_mux <= 2'b10;
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sd_addx10_mux <= 2'b10;
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doing_refresh <= `LO; // deassert
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if (pwrup)
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pwrup <= `LO; // ..no more in power up mode
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if (do_mode_set)
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do_modeset_ack <= `LO;
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end
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// IDLE state
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`state_idle: begin
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sd_wr_l <= `HI;
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sd_cs_l <= `HI;
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sd_ras_l <= `HI;
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sd_cas_l <= `HI;
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sd_data_ena <= `LO; // turn off the data bus drivers
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mp_data_mux <= `LO; // drive the SD data bus with normal data
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sd_addx_mux <= 2'b00; // select ROW (A[19:10]) of mp_addx to SDRAM
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sd_addx10_mux <= 2'b00; // select ROW (A[20]) " "
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// if we've just come out of system reset (or powerup)
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// then we need to go and do initialization sequence.
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// Or, if a refresh is requested, go and service it.
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if (do_refresh | pwrup) begin
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doing_refresh <= `HI; // indicate that we're doing refresh
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refresh_cntr_l <= `HI; // allow refresh cycle counter to count up
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next_state <= `state_auto_refresh;
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end
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// if a single word rad or write request is pending, go and service it
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else if (do_write | do_read )
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next_state <= `state_set_ras;
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// if a mode register set is requested, go and service it
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else if (do_mode_set) begin
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do_modeset_ack <= `HI; // acknowledge the mode set request
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next_state <= `state_modeset;
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doing_refresh <= `HI; // techincally we're not doing refresh, but
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end // this signal is used to prevent the do_write be deasserted
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// by the mode_set command.
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end
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// SET RAS state
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`state_set_ras: begin
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sd_cs_l <= `LO; // enable SDRAM
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sd_ras_l <= `LO; // enable the RAS
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next_state <= `state_ras_dly; // wait for a bit
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end
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// RAS delay state.
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// This delay is needed to meet Trcd delay. This is the RAS to CAS delay.
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// for most parts this is 20nS. So for 100MHz operation, there needs to be
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// at least 1 NOP cycle.
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`state_ras_dly: begin
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sd_cs_l <= `HI; // disable SDRAM
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sd_ras_l <= `HI; // disble the RAS
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sd_addx_mux <= 2'b01; // select COLUMN
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sd_addx10_mux <= 2'b01; // select COLUMN
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if (do_write) begin
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sd_data_ena <= `HI; // turn on the data bus drivers
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sd_dqm <= decoded_dqm; // masks the data which is meant to be
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next_state <= `state_write; // if write, do the write
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end else begin
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sd_dqm <= 4'h0;
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next_state <= `state_set_cas; // if read, do the read
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end
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end
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// WRITE state
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`state_write: begin
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sd_cs_l <= `LO; // enable SDRAM
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sd_cas_l <= `LO; // enable the CAS
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sd_wr_l <= `LO; // enable the write
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do_write_ack<= `HI; // acknowledge the write request
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sd_dqm <= 4'hF;
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next_state <= `state_delay_Tras1;
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end
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`state_delay_Tras1: begin
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sd_wr_l <= `HI;
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sd_cs_l <= `HI;
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sd_ras_l <= `HI;
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sd_cas_l <= `HI;
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sd_dqm <= 4'hF;
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sd_addx_mux <= 2'b00; // send ROW (A[19:10]) of mp_addx to SDRAM
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sd_addx10_mux <= 2'b00; // send ROW (A[20]) " "
|
|
mp_data_mux <= `HI; // drive the SD data bus with all zeros
|
|
next_state <= `state_delay_Tras2;
|
|
end
|
|
|
|
`state_delay_Tras2: begin
|
|
next_state <= `state_precharge;
|
|
end
|
|
|
|
|
|
// SET CAS state
|
|
`state_set_cas: begin
|
|
sd_cs_l <= `LO;
|
|
sd_cas_l <= `LO;
|
|
sd_dqm <= 4'h0;
|
|
next_state <= `state_cas_latency1;
|
|
end
|
|
|
|
`state_cas_latency1: begin
|
|
sd_cs_l <= `HI; // disable CS
|
|
sd_cas_l <= `HI; // disable CAS
|
|
sd_dqm <= 4'hF;
|
|
if (modereg_cas_latency==3'b010) begin
|
|
do_read_ack <= `HI; // acknowledge the read request (do it here due to the latency)
|
|
next_state <= `state_read; // 2 cycles of lantency done.
|
|
burst_cntr_ena <= `HI; // enable he burst lenght counter
|
|
end else
|
|
next_state <= `state_cas_latency2; // 3 cycles of latency
|
|
end
|
|
|
|
`state_cas_latency2: begin
|
|
next_state <= `state_read;
|
|
burst_cntr_ena <= `HI; // enable the burst lenght counter
|
|
do_read_ack <= `HI; // acknowledge the read request (do it here due to the latency)
|
|
end
|
|
|
|
`state_read: begin
|
|
if (burst_length_cntr == modereg_burst_count) begin
|
|
burst_cntr_ena <= `LO; // done counting;
|
|
sd_rd_ena <= `LO; // done with the reading
|
|
next_state <= `state_precharge;
|
|
|
|
sd_wr_l <= `HI;
|
|
sd_cs_l <= `HI;
|
|
sd_ras_l <= `HI;
|
|
sd_cas_l <= `HI;
|
|
sd_addx_mux <= 2'b00; // send ROW (A[19:10]) of mp_addx to SDRAM
|
|
sd_addx10_mux <= 2'b00; // send ROW (A[20]) " "
|
|
mp_data_mux <= `HI; // drive the SD data bus with all zeros
|
|
|
|
end else begin
|
|
sd_rd_ena <= `HI; // enable the read latch on the next state
|
|
next_state <= `state_read;
|
|
end
|
|
end
|
|
|
|
endcase
|
|
|
|
|
|
// This counter is used to generate a delay right after the
|
|
// auto-refresh command is issued to the SDRAM
|
|
always @(posedge sys_clk or negedge autorefresh_cntr_l)
|
|
if (~autorefresh_cntr_l)
|
|
autorefresh_cntr <= 4'h0;
|
|
else
|
|
autorefresh_cntr <= autorefresh_cntr + 1;
|
|
|
|
|
|
|
|
// This mux selects the cycle limit value for the
|
|
// auto refresh counter.
|
|
// During power-up sequencing, we need to do `power_up_ref_cntr_limit
|
|
// number of back=back refreshes.
|
|
// During regular operation, we need to do `auto_ref_cntr_limit number of
|
|
// back-back refreshes. This, for most cases is just 1, but if we're doing
|
|
// "burst" type of refreshes, it could be more than 1.
|
|
always @(pwrup)
|
|
case (pwrup)
|
|
`HI: cntr_limit <= `power_up_ref_cntr_limit;
|
|
default: cntr_limit <= `auto_ref_cntr_limit;
|
|
endcase
|
|
|
|
|
|
//
|
|
// BURST LENGHT COUNTER
|
|
//
|
|
// This is the burst length counter.
|
|
always @(posedge sys_clk or negedge burst_cntr_ena)
|
|
if (~burst_cntr_ena)
|
|
burst_length_cntr <= 3'b000; // reset whenever 'burst_cntr_ena' is low
|
|
else
|
|
burst_length_cntr <= burst_length_cntr + 1;
|
|
|
|
//
|
|
// REFRESH_CNTR
|
|
//
|
|
// This counter keeps track of the number of back-back refreshes we're
|
|
// doing. For most cases this would just be 1, but it allows "burst"
|
|
// refresh, where all refrehses are done back to back.
|
|
always @(posedge sys_clk or negedge refresh_cntr_l)
|
|
if (~refresh_cntr_l)
|
|
refresh_cntr <= 13'h0000;
|
|
else if (next_state == `state_auto_refresh)
|
|
refresh_cntr <= refresh_cntr + 1;
|
|
|
|
//
|
|
// BURST LENGTH SELECTOR
|
|
//
|
|
always @(modereg_burst_length)
|
|
case (modereg_burst_length)
|
|
3'b000: modereg_burst_count <= 4'h1;
|
|
3'b001: modereg_burst_count <= 4'h2;
|
|
3'b010: modereg_burst_count <= 4'h4;
|
|
default modereg_burst_count <= 4'h8;
|
|
endcase
|
|
|
|
|
|
//
|
|
// REFRESH Request generator
|
|
//
|
|
assign do_refresh = (refresh_state == `state_halt);
|
|
|
|
|
|
always @(posedge sys_clk or negedge sys_rst_l)
|
|
if (~sys_rst_l) begin
|
|
refresh_state <= `state_count;
|
|
refresh_timer <= 8'h00;
|
|
end
|
|
else case (refresh_state)
|
|
// COUNT
|
|
// count up the refresh interval counter. If the
|
|
// timer reaches the refresh-expire time, then go next state
|
|
`state_count:
|
|
if (refresh_timer != `RC) begin
|
|
refresh_timer <= refresh_timer + 1;
|
|
refresh_state <= `state_count;
|
|
end else begin
|
|
refresh_state <= `state_halt;
|
|
refresh_timer <= 0;
|
|
end
|
|
|
|
// HALT
|
|
// wait for the SDRAM to complete any ongoing reads or
|
|
// writes. If the SDRAM has acknowledged the do_refresh,
|
|
// (i.e. it is now doing the refresh)
|
|
// then go to next state
|
|
`state_halt:
|
|
/* if (next_state==`state_auto_refresh |
|
|
next_state==`state_auto_refresh_dly |
|
|
next_state==`state_precharge )
|
|
refresh_state <= `state_reset;
|
|
*/
|
|
if (do_refresh_ack)
|
|
refresh_state <= `state_count;
|
|
|
|
// RESET
|
|
// if the SDRAM refresh is completed, then reset the counter
|
|
// and start counting up again.
|
|
`state_reset:
|
|
if (next_state==`state_idle) begin
|
|
refresh_state <= `state_count;
|
|
refresh_timer <= 8'h00;
|
|
end
|
|
endcase
|
|
|
|
|
|
endmodule
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
