URL https://opencores.org/ocsvn/sdram_controller/sdram_controller/trunk

Subversion Repositories sdram_controller

[/] [sdram_controller/] [trunk/] [scratch.vhd] - Diff between revs 4 and 6

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Rev 4	Rev 6
Line 55...	Line 55...

`type DRAM_DRIVER_STATES is ( STATE0, STATE1, STATE2, STATE3, STATE4, STATE5 );`	`type DRAM_DRIVER_STATES is ( STATE0, STATE1, STATE2, STATE3, STATE4, STATE5 );`
`signal dram_driver_state : DRAM_DRIVER_STATES := STATE0;`	`signal dram_driver_state : DRAM_DRIVER_STATES := STATE0;`

`signal clk_bufd : std_logic;`	`signal clk_bufd : std_logic;`
`signal clk133mhz : std_logic;`
`signal dcm_locked : std_logic;`

`signal op : std_logic_vector(1 downto 0);`	`signal op : std_logic_vector(1 downto 0);`
`signal addr : std_logic_vector(25 downto 0);`	`signal addr : std_logic_vector(25 downto 0);`
`signal op_ack : std_logic;`	`signal op_ack : std_logic;`
`signal busy_n : std_logic;`	`signal busy_n : std_logic;`
`signal data_o : std_logic_vector(7 downto 0);`
`signal data_i : std_logic_vector(7 downto 0);`	`signal data_i : std_logic_vector(7 downto 0);`
`signal debug : std_logic_vector(7 downto 0);`	`signal debug : std_logic_vector(7 downto 0);`

`signal reg0 : std_logic_vector(7 downto 0) := x"55";`

`begin`	`begin`

`BUFG_CLK: BUFG`	`BUFG_CLK: BUFG`
`port map(`	`port map(`
`O => clk_bufd,`	`O => clk_bufd,`
Line 117...	Line 112...
`dram_driver_state <= STATE1;`	`dram_driver_state <= STATE1;`
`end if;`	`end if;`

`when STATE1 =>`	`when STATE1 =>`
`addr <= "01000000000000000000000111";`	`addr <= "01000000000000000000000111";`
`data_i <= "10101010";`	`data_i <= "11111111";`
`op <= "10";`	`op <= "10";`
`if (op_ack = '1') then`	`if (op_ack = '1') then`
`dram_driver_state <= STATE2;`	`dram_driver_state <= STATE2;`
`end if;`	`end if;`

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[/] [sdram_controller/] [trunk/] [scratch.vhd] - Diff between revs 4 and 6