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Line 231... |
constant CMD_LOAD_MR : std_logic_vector(2 downto 0) := "000";
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constant CMD_LOAD_MR : std_logic_vector(2 downto 0) := "000";
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-- various wait counter values
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-- various wait counter values
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constant AUTO_REFRESH_CLKS : integer := 700; -- spec says 7.8us, which is 780 clocks @ 100Mhz, I'm setting it to 700
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constant AUTO_REFRESH_CLKS : integer := 700; -- spec says 7.8us, which is 780 clocks @ 100Mhz, I'm setting it to 700
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constant WRITE_RECOVER_CLKS : integer := 5; -- these are fudged a bit, you *might* be able to shave a clock or two off
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constant WRITE_RECOVER_CLKS : integer := 5; -- these are fudged a bit, you *might* be able to shave a clock or two off
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constant READ_DONE_CLKS : integer := 5;
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constant READ_DONE_CLKS : integer := 4; -- or shave a clock or two off if your board timing is a bit wedgy
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type CMD_STATES is ( STATE_START, STATE_INIT, STATE_WAIT_INIT, STATE_IDLE, STATE_IDLE_AUTO_REFRESH,
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type CMD_STATES is ( STATE_START, STATE_INIT, STATE_WAIT_INIT, STATE_IDLE, STATE_IDLE_AUTO_REFRESH,
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STATE_IDLE_CHECK_OP_PENDING, STATE_IDLE_WAIT_AR_CTR, STATE_IDLE_WAIT_AUTO_REFRESH,
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STATE_IDLE_CHECK_OP_PENDING, STATE_IDLE_WAIT_AR_CTR, STATE_IDLE_WAIT_AUTO_REFRESH,
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STATE_WRITE_ROW_OPEN, STATE_WRITE_WAIT_ROW_OPEN, STATE_WRITE_ISSUE_CMD, STATE_WRITE_WAIT_RECOVER,
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STATE_WRITE_ROW_OPEN, STATE_WRITE_WAIT_ROW_OPEN, STATE_WRITE_ISSUE_CMD, STATE_WRITE_WAIT_RECOVER,
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STATE_READ_ROW_OPEN, STATE_READ_WAIT_ROW_OPEN, STATE_READ_ISSUE_CMD, STATE_READ_WAIT_CAPTURE );
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STATE_READ_ROW_OPEN, STATE_READ_WAIT_ROW_OPEN, STATE_READ_ISSUE_CMD, STATE_READ_WAIT_CAPTURE );
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Line 456... |
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debug_reg <= x"00";
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debug_reg <= x"00";
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dram_cs <= '0';
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dram_cs <= '0';
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data_o <= data1_o when addr_save(0) = '1' else data0_o;
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data_o <= data1_o when addr_save(0) = '1' else data0_o;
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-- process (clk_000)
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-- begin
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-- if (cap_en = '1') then
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-- if (rising_edge(clk_000)) then
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-- addr_save <= addr;
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-- datai_save <= data_i;
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-- op_save <= op;
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-- end if;
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-- end if;
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-- end process;
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-- this will probably make the synthesizer scream bloody murder
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-- over either a transparent latch or gated clock or both
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-- but i've got it working again with my SoC and I'll see about
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-- changing it back to something less icky later
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-- capture addr, data_i and op for the cmd fsm
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-- capture addr, data_i and op for the cmd fsm
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-- op needs to be captured during AR or it might get dropped
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-- op needs to be captured during AR or it might get dropped
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process (clk_000)
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addr_save <= addr when cap_en = '1' else addr_save;
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begin
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datai_save <= data_i when cap_en = '1' else datai_save;
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if (rising_edge(clk_000)) then
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op_save <= op when cap_en = '1' else op_save;
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if (cap_en = '1') then
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addr_save <= addr;
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datai_save <= data_i;
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op_save <= op;
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end if;
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end if;
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end process;
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-- command state machine
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-- command state machine
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process (clk_000)
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process (clk_000)
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begin
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begin
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if (rising_edge(clk_000)) then
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if (rising_edge(clk_000)) then
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Line 522... |
busy_n <= '0';
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busy_n <= '0';
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cmd_state <= STATE_IDLE_AUTO_REFRESH;
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cmd_state <= STATE_IDLE_AUTO_REFRESH;
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elsif (op = "01") then
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elsif (op = "01") then
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busy_n <= '0';
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busy_n <= '0';
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op_ack <= '1';
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op_ack <= '1';
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cap_en <= '0';
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cmd_state <= STATE_READ_ROW_OPEN;
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cmd_state <= STATE_READ_ROW_OPEN;
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elsif (op = "10") then
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elsif (op = "10") then
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busy_n <= '0';
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busy_n <= '0';
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op_ack <= '1';
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op_ack <= '1';
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cap_en <= '0';
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cmd_state <= STATE_WRITE_ROW_OPEN;
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cmd_state <= STATE_WRITE_ROW_OPEN;
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else
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else
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cmd_state <= cmd_state;
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cmd_state <= cmd_state;
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end if;
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end if;
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Line 568... |
else
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else
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cmd_state <= cmd_state;
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cmd_state <= cmd_state;
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end if;
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end if;
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when STATE_IDLE_CHECK_OP_PENDING =>
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when STATE_IDLE_CHECK_OP_PENDING =>
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if ( cap_en = '0') then
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if (op_save = "01") then
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if (op_save = "01") then
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op_ack <= '1';
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op_ack <= '1';
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cmd_state <= STATE_READ_ROW_OPEN;
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cmd_state <= STATE_READ_ROW_OPEN;
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elsif (op_save = "10") then
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elsif (op_save = "10") then
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op_ack <= '1';
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op_ack <= '1';
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cmd_state <= STATE_WRITE_ROW_OPEN;
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cmd_state <= STATE_WRITE_ROW_OPEN;
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else
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else
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cmd_state <= STATE_IDLE;
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cmd_state <= STATE_IDLE;
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end if;
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end if;
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else
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cmd_state <= STATE_IDLE;
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end if;
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when STATE_WRITE_ROW_OPEN =>
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when STATE_WRITE_ROW_OPEN =>
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cap_en <= '0';
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dqs_dir <= '1';
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dqs_dir <= '1';
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dq_dir <= '1';
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dq_dir <= '1';
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main_cmd <= CMD_ACTIVE;
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main_cmd <= CMD_ACTIVE;
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main_bank <= addr_save(25 downto 24);
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main_bank <= addr_save(25 downto 24);
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main_addr <= addr_save(23 downto 11);
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main_addr <= addr_save(23 downto 11);
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| Line 603... |
Line 616... |
else
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else
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cmd_state <= cmd_state;
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cmd_state <= cmd_state;
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end if;
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end if;
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when STATE_READ_ROW_OPEN =>
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when STATE_READ_ROW_OPEN =>
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cap_en <= '0';
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dqs_dir <= '0';
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dqs_dir <= '0';
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dq_dir <= '0';
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dq_dir <= '0';
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main_cmd <= CMD_ACTIVE;
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main_cmd <= CMD_ACTIVE;
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main_bank <= addr_save(25 downto 24);
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main_bank <= addr_save(25 downto 24);
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main_addr <= addr_save(23 downto 11);
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main_addr <= addr_save(23 downto 11);
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