| Line 129... |
Line 129... |
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component inout_switch_2 is
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component inout_switch_2 is
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port (
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port (
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ioport : inout std_logic_vector(1 downto 0);
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ioport : inout std_logic_vector(1 downto 0);
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dir : in std_logic;
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dir : in std_logic;
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data_o : out std_logic_vector(1 downto 0);
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data_i : in std_logic_vector(1 downto 0)
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data_i : in std_logic_vector(1 downto 0)
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);
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);
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end component;
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end component;
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component inout_switch_16 is
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component inout_switch_16 is
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| Line 145... |
Line 144... |
);
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);
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end component;
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end component;
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component sdram_reader is
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component sdram_reader is
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port(
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port(
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clk000 : in std_logic;
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clk270 : in std_logic;
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clk270 : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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dq : in std_logic_vector(15 downto 0);
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dq : in std_logic_vector(15 downto 0);
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data0 : out std_logic_vector(7 downto 0);
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data0 : out std_logic_vector(7 downto 0);
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data1 : out std_logic_vector(7 downto 0)
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data1 : out std_logic_vector(7 downto 0)
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| Line 165... |
Line 163... |
rst : in std_logic;
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rst : in std_logic;
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addr : in std_logic;
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addr : in std_logic;
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data_o : in std_logic_vector(7 downto 0);
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data_o : in std_logic_vector(7 downto 0);
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dqs : out std_logic_vector(1 downto 0);
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dqs : out std_logic_vector(1 downto 0);
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dm : out std_logic_vector(1 downto 0);
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dm : out std_logic_vector(1 downto 0);
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dq : out std_logic_vector(15 downto 0);
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dq : out std_logic_vector(15 downto 0)
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done : out std_logic
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);
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);
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end component;
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end component;
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component wait_counter is
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component wait_counter is
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generic(
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generic(
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| Line 237... |
Line 234... |
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signal cmd_oddr2_rising : std_logic_vector(2 downto 0) := CMD_NOP;
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signal cmd_oddr2_rising : std_logic_vector(2 downto 0) := CMD_NOP;
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signal bank_oddr2_rising : std_logic_vector(1 downto 0) := "00";
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signal bank_oddr2_rising : std_logic_vector(1 downto 0) := "00";
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signal addr_oddr2_rising : std_logic_vector(12 downto 0) := "0000000000000";
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signal addr_oddr2_rising : std_logic_vector(12 downto 0) := "0000000000000";
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|
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signal dqs_in : std_logic_vector(1 downto 0);
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signal dqs_out : std_logic_vector(1 downto 0);
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signal dqs_out : std_logic_vector(1 downto 0);
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signal dqs_dir : std_logic;
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signal dqs_dir : std_logic;
|
|
|
signal dq_in : std_logic_vector(15 downto 0);
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signal dq_in : std_logic_vector(15 downto 0);
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signal dq_out : std_logic_vector(15 downto 0);
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signal dq_out : std_logic_vector(15 downto 0);
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signal dq_dir : std_logic;
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signal dq_dir : std_logic;
|
|
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signal reader_rst : std_logic := '1';
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signal reader_rst : std_logic := '1';
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|
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signal writer_rst : std_logic := '1';
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signal writer_rst : std_logic := '1';
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signal writer_done : std_logic := '0';
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|
|
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signal dcm_locked : std_logic;
|
signal dcm_locked : std_logic;
|
signal clk_000 : std_logic;
|
signal clk_000 : std_logic;
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signal clk_090 : std_logic;
|
signal clk_090 : std_logic;
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signal clk_180 : std_logic;
|
signal clk_180 : std_logic;
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| Line 363... |
Line 357... |
|
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DQS_SWITCH: inout_switch_2
|
DQS_SWITCH: inout_switch_2
|
port map(
|
port map(
|
ioport => dram_dqs,
|
ioport => dram_dqs,
|
dir => dqs_dir,
|
dir => dqs_dir,
|
data_o => dqs_in,
|
|
data_i => dqs_out
|
data_i => dqs_out
|
);
|
);
|
|
|
DQ_SWITCH: inout_switch_16
|
DQ_SWITCH: inout_switch_16
|
port map(
|
port map(
|
| Line 421... |
Line 414... |
done => read_wait_done
|
done => read_wait_done
|
);
|
);
|
|
|
READER: sdram_reader
|
READER: sdram_reader
|
port map(
|
port map(
|
clk000 => clk_000,
|
|
clk270 => clk_270,
|
clk270 => clk_270,
|
rst => reader_rst,
|
rst => reader_rst,
|
dq => dq_in,
|
dq => dq_in,
|
data0 => data0_o,
|
data0 => data0_o,
|
data1 => data1_o
|
data1 => data1_o
|
| Line 440... |
Line 432... |
rst => writer_rst,
|
rst => writer_rst,
|
addr => addr(0),
|
addr => addr(0),
|
data_o => data_i,
|
data_o => data_i,
|
dqs => dqs_out,
|
dqs => dqs_out,
|
dm => dram_dm,
|
dm => dram_dm,
|
dq => dq_out,
|
dq => dq_out
|
done => writer_done
|
|
);
|
);
|
-- end component allocs
|
-- end component allocs
|
|
|
|
debug_reg <= x"00";
|
dram_cs <= '0';
|
dram_cs <= '0';
|
data_o <= data1_o when addr(0) = '1' else data0_o;
|
data_o <= data1_o when addr(0) = '1' else data0_o;
|
|
|
-- command state machine
|
-- command state machine
|
process (clk_000)
|
process (clk_000)
|
| Line 487... |
Line 479... |
main_sel <= '1';
|
main_sel <= '1';
|
writer_rst <= '1';
|
writer_rst <= '1';
|
reader_rst <= '1';
|
reader_rst <= '1';
|
if (need_ar = '1') then
|
if (need_ar = '1') then
|
cmd_state <= STATE_IDLE_AUTO_REFRESH;
|
cmd_state <= STATE_IDLE_AUTO_REFRESH;
|
elsif (op = "01") then
|
elsif (op = "01" and en = '1') then
|
cmd_state <= STATE_READ_ROW_OPEN;
|
cmd_state <= STATE_READ_ROW_OPEN;
|
elsif (op = "10") then
|
elsif (op = "10" and en = '1') then
|
cmd_state <= STATE_WRITE_ROW_OPEN;
|
cmd_state <= STATE_WRITE_ROW_OPEN;
|
else
|
else
|
cmd_state <= cmd_state;
|
cmd_state <= cmd_state;
|
end if;
|
end if;
|
|
|
