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-- Design Name: DDR SDRAM Controller
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-- Design Name: DDR SDRAM Controller
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-- Module Name: sdram_controller - impl
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-- Module Name: sdram_controller - impl
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-- Project Name:
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-- Project Name:
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-- Target Devices: Spartan3e Starter Board
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-- Target Devices: Spartan3e Starter Board
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-- Tool versions: ISE 11.2
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-- Tool versions: ISE 11.2
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-- Description: This is the main controller module. This is where the signals to/from the DDR SDRAM chip happen.
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-- Description: This is the main controller module. This is where the signals
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-- to/from the DDR SDRAM chip happen.
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--
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--
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-- Dependencies:
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-- Dependencies:
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--
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--
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-- Revision:
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-- Revision:
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-- Revision 0.01 - File Created
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-- Revision 0.01 - File Created
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- Uncomment the following library declaration if instantiating
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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---- any Xilinx primitives in this code.
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library UNISIM;
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--library UNISIM;
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use UNISIM.VComponents.all;
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--use UNISIM.VComponents.all;
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-- This is not meant to be a high performance controller. No fancy command scheduling, does the bare minimum to work without screwing up timing.
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-- This is not meant to be a high performance controller. No fancy command
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-- Do NOT put this controller in something mission critical! This is the creation of a guy in his bedroom, learning digital circuits.
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-- scheduling, does the bare minimum to work without screwing up timing.
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-- Intended to be used exclusively with the Spartan3e Starter Board and targets the mt46v32m16 chip. Dunno if it will work anywhere else.
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-- Do NOT put this controller in something mission critical! This is the creation
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-- Uses the ODDR2 and DCM Xilinx primitives, for other FPGAs, you'll need to patch in equivalents. See sdram_support for the details.
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-- of a guy in his bedroom, learning digital circuits.
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-- I'd strongly recommend running it through a post-PAR simulation if you're porting to any other FPGA, as the timings will change on you.
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-- Intended to be used exclusively with the Spartan3e Starter Board and targets
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-- Consumes two DCMs, runs off of the main 50mhz board clock. Could possibly consume one DCM if you want to feed it the 100mhz clock directly.
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-- the mt46v32m16 chip. Dunno if it will work anywhere else.
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-- Has an 8bit wide datapath, moderate changes could support 16bits, 32 bits you'll have to work some. You want more than that, you'll
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-- Uses the ODDR2 and DCM Xilinx primitives, for other FPGAs, you'll need to
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-- be doing brain surgery on the FSMs - good luck.
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-- patch in equivalents. See sdram_support for the details.
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-- I'd strongly recommend running it through a post-PAR simulation if you're
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-- porting to any other FPGA, as the timings will probably change on you.
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-- Consumes two DCMs, runs off of the main 50mhz board clock. Could possibly
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-- consume one DCM if you want to feed it the 100mhz clock directly.
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-- Has an 8bit wide datapath, moderate changes could support 16bits, 32 bits
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-- you'll have to work some. You want more than that, you'll be doing brain
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-- surgery on the FSMs - good luck.
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-- This design has been tested with the testbench only. There may be glitches hidden in here somewhere still. Consider this to be an alpha release.
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-- This design has been tested with the testbench only. There may be glitches
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-- hidden in here somewhere still. Consider this to be an alpha release.
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-- Did I mention that you shouldn't put this in anything mission critical?
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-- Did I mention that you shouldn't put this in anything mission critical?
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-- Be careful with the synthesizer settings too. Do not let the FSM extractor choose something other than one-hot. Be careful with register
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-- Be careful with the synthesizer settings too. Do not let the FSM extractor
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-- removal.
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-- choose something other than one-hot. Be careful with equivalent register
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-- removal. I've rolled all synthesizer settings back to default and things
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-- seem to be OK, but pay attention to the synthesizer reports!
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-- TODO: implement reset signal
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-- TODO: implement reset signal
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entity sdram_controller is
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entity sdram_controller is
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port( -- user facing signals
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port( -- user facing signals
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clk50mhz : in std_logic;
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clk50mhz : in std_logic;
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