| Line 56... |
Line 56... |
-- seem to be OK, but pay attention to the synthesizer reports!
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-- seem to be OK, but pay attention to the synthesizer reports!
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|
|
-- TODO: implement reset signal
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-- TODO: implement reset signal
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entity sdram_controller is
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entity sdram_controller is
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port( -- user facing signals
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port( -- user facing signals
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clk50mhz : in std_logic;
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clk100mhz : in std_logic;
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en : in std_logic;
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en : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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op : in std_logic_vector(1 downto 0); -- 00/11: NOP, 01: READ, 10: write
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op : in std_logic_vector(1 downto 0); -- 00/11: NOP, 01: READ, 10: write
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addr : in std_logic_vector(25 downto 0); -- address to read/write
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addr : in std_logic_vector(25 downto 0); -- address to read/write
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op_ack : out std_logic; -- op, addr and data_i should be captured when this goes high
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op_ack : out std_logic; -- op, addr and data_i should be captured when this goes high
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| Line 89... |
Line 89... |
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-- component decls begin here
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-- component decls begin here
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component sdram_dcm is
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component sdram_dcm is
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port(
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port(
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reset : in std_logic;
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reset : in std_logic;
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clk50mhz : in std_logic;
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clk100mhz : in std_logic;
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locked : out std_logic;
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locked : out std_logic;
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dram_clkp : out std_logic;
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dram_clkp : out std_logic;
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dram_clkn : out std_logic;
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dram_clkn : out std_logic;
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clk_000 : out std_logic;
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clk_000 : out std_logic;
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clk_090 : out std_logic;
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clk_090 : out std_logic;
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| Line 290... |
Line 290... |
signal read_wait_done : std_logic;
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signal read_wait_done : std_logic;
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|
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signal data0_o : std_logic_vector(7 downto 0);
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signal data0_o : std_logic_vector(7 downto 0);
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signal data1_o : std_logic_vector(7 downto 0);
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signal data1_o : std_logic_vector(7 downto 0);
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--
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signal cap_en : std_logic;
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signal addr_save : std_logic_vector(25 downto 0);
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signal datai_save : std_logic_vector(7 downto 0);
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begin
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begin
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-- component instantiations begin here
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-- component instantiations begin here
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DRAM_DCM: sdram_dcm
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DRAM_DCM: sdram_dcm
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port map(
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port map(
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reset => reset,
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reset => reset,
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clk50mhz => clk50mhz,
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clk100mhz => clk100mhz,
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locked => dcm_locked,
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locked => dcm_locked,
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dram_clkp => dram_clkp,
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dram_clkp => dram_clkp,
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dram_clkn => dram_clkn,
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dram_clkn => dram_clkn,
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clk_000 => clk_000,
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clk_000 => clk_000,
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clk_090 => clk_090,
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clk_090 => clk_090,
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| Line 439... |
Line 444... |
clk => clk_000,
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clk => clk_000,
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clk090 => clk_090,
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clk090 => clk_090,
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clk180 => clk_180,
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clk180 => clk_180,
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clk270 => clk_270,
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clk270 => clk_270,
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rst => writer_rst,
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rst => writer_rst,
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addr => addr(0),
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addr => addr_save(0),
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data_o => data_i,
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data_o => datai_save,
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dqs => dqs_out,
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dqs => dqs_out,
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dm => dram_dm,
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dm => dram_dm,
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dq => dq_out
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dq => dq_out
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);
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);
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-- end component allocs
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-- end component allocs
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|
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debug_reg <= x"00";
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debug_reg <= x"00";
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dram_cs <= '0';
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dram_cs <= '0';
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data_o <= data1_o when addr(0) = '1' else data0_o;
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data_o <= data1_o when addr_save(0) = '1' else data0_o;
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|
|
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process (clk_000)
|
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begin
|
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if (rising_edge(clk_000)) then
|
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if (cap_en = '1') then
|
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addr_save <= addr;
|
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datai_save <= data_i;
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end if;
|
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end if;
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end process;
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|
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-- command state machine
|
-- command state machine
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process (clk_000)
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process (clk_000)
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begin
|
begin
|
if (rising_edge(clk_000)) then
|
if (rising_edge(clk_000)) then
|
| Line 461... |
Line 476... |
case cmd_state is
|
case cmd_state is
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when STATE_START =>
|
when STATE_START =>
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busy_n <= '0';
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busy_n <= '0';
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op_ack <= '0';
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op_ack <= '0';
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init_reset <= '1';
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init_reset <= '1';
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cap_en <= '0';
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main_sel <= '0';
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main_sel <= '0';
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main_cmd <= CMD_NOP;
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main_cmd <= CMD_NOP;
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main_bank <= "00";
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main_bank <= "00";
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main_addr <= "0000000000000";
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main_addr <= "0000000000000";
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cmd_state <= STATE_INIT;
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cmd_state <= STATE_INIT;
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| Line 485... |
Line 501... |
-- this is the main hub state
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-- this is the main hub state
|
-- this is where reads and writes return to after being completed
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-- this is where reads and writes return to after being completed
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busy_n <= '1';
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busy_n <= '1';
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op_ack <= '0';
|
op_ack <= '0';
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need_ar_rst <= '0';
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need_ar_rst <= '0';
|
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cap_en <= '1';
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main_sel <= '1';
|
main_sel <= '1';
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writer_rst <= '1';
|
writer_rst <= '1';
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reader_rst <= '1';
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reader_rst <= '1';
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if (need_ar = '1') then
|
if (need_ar = '1') then
|
|
busy_n <= '0';
|
cmd_state <= STATE_IDLE_AUTO_REFRESH;
|
cmd_state <= STATE_IDLE_AUTO_REFRESH;
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elsif (op = "01" and en = '1') then
|
elsif (op = "01" and en = '1') then
|
|
busy_n <= '0';
|
cmd_state <= STATE_READ_ROW_OPEN;
|
cmd_state <= STATE_READ_ROW_OPEN;
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elsif (op = "10" and en = '1') then
|
elsif (op = "10" and en = '1') then
|
|
busy_n <= '0';
|
cmd_state <= STATE_WRITE_ROW_OPEN;
|
cmd_state <= STATE_WRITE_ROW_OPEN;
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else
|
else
|
cmd_state <= cmd_state;
|
cmd_state <= cmd_state;
|
end if;
|
end if;
|
|
|
| Line 524... |
Line 544... |
else
|
else
|
cmd_state <= cmd_state;
|
cmd_state <= cmd_state;
|
end if;
|
end if;
|
|
|
when STATE_WRITE_ROW_OPEN =>
|
when STATE_WRITE_ROW_OPEN =>
|
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op_ack <= '1';
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busy_n <= '0';
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busy_n <= '0';
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dqs_dir <= '1';
|
dqs_dir <= '1';
|
dq_dir <= '1';
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dq_dir <= '1';
|
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cap_en <= '0';
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main_cmd <= CMD_ACTIVE;
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main_cmd <= CMD_ACTIVE;
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main_bank <= addr(25 downto 24);
|
main_bank <= addr_save(25 downto 24);
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main_addr <= addr(23 downto 11);
|
main_addr <= addr_save(23 downto 11);
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cmd_state <= STATE_WRITE_WAIT_ROW_OPEN;
|
cmd_state <= STATE_WRITE_WAIT_ROW_OPEN;
|
|
|
when STATE_WRITE_WAIT_ROW_OPEN =>
|
when STATE_WRITE_WAIT_ROW_OPEN =>
|
main_cmd <= CMD_NOP;
|
main_cmd <= CMD_NOP;
|
main_bank <= addr(25 downto 24); -- timing kludge
|
main_bank <= addr_save(25 downto 24); -- timing kludge
|
main_addr <= "001" & addr(10 downto 1); -- last bit determines upper/lower byte in word
|
main_addr <= "001" & addr_save(10 downto 1); -- last bit determines upper/lower byte in word
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cmd_state <= STATE_WRITE_ISSUE_CMD;
|
cmd_state <= STATE_WRITE_ISSUE_CMD;
|
|
|
when STATE_WRITE_ISSUE_CMD =>
|
when STATE_WRITE_ISSUE_CMD =>
|
writer_rst <= '0';
|
writer_rst <= '0';
|
write_reco_rst <= '1';
|
write_reco_rst <= '1';
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main_cmd <= CMD_WRITE;
|
main_cmd <= CMD_WRITE;
|
main_bank <= addr(25 downto 24);
|
main_bank <= addr_save(25 downto 24);
|
main_addr <= "001" & addr(10 downto 1); -- last bit determines upper/lower byte in word
|
main_addr <= "001" & addr_save(10 downto 1); -- last bit determines upper/lower byte in word
|
cmd_state <= STATE_WRITE_WAIT_RECOVER;
|
cmd_state <= STATE_WRITE_WAIT_RECOVER;
|
|
|
when STATE_WRITE_WAIT_RECOVER =>
|
when STATE_WRITE_WAIT_RECOVER =>
|
op_ack <= '1';
|
|
write_reco_rst <= '0';
|
write_reco_rst <= '0';
|
main_cmd <= CMD_NOP;
|
main_cmd <= CMD_NOP;
|
main_bank <= "00";
|
main_bank <= "00";
|
main_addr <= "0000000000000";
|
main_addr <= "0000000000000";
|
if (write_reco_done = '1') then
|
if (write_reco_done = '1') then
|
| Line 559... |
Line 580... |
else
|
else
|
cmd_state <= cmd_state;
|
cmd_state <= cmd_state;
|
end if;
|
end if;
|
|
|
when STATE_READ_ROW_OPEN =>
|
when STATE_READ_ROW_OPEN =>
|
|
op_ack <= '1';
|
busy_n <= '0';
|
busy_n <= '0';
|
dqs_dir <= '0';
|
dqs_dir <= '0';
|
dq_dir <= '0';
|
dq_dir <= '0';
|
|
cap_en <= '0';
|
main_cmd <= CMD_ACTIVE;
|
main_cmd <= CMD_ACTIVE;
|
main_bank <= addr(25 downto 24);
|
main_bank <= addr_save(25 downto 24);
|
main_addr <= addr(23 downto 11);
|
main_addr <= addr_save(23 downto 11);
|
cmd_state <= STATE_READ_WAIT_ROW_OPEN;
|
cmd_state <= STATE_READ_WAIT_ROW_OPEN;
|
|
|
when STATE_READ_WAIT_ROW_OPEN =>
|
when STATE_READ_WAIT_ROW_OPEN =>
|
main_cmd <= CMD_NOP;
|
main_cmd <= CMD_NOP;
|
main_bank <= addr(25 downto 24); -- timing kludge
|
main_bank <= addr_save(25 downto 24); -- timing kludge
|
main_addr <= "001" & addr(10 downto 1); -- last bit determines upper/lower byte
|
main_addr <= "001" & addr_save(10 downto 1); -- last bit determines upper/lower byte
|
cmd_state <= STATE_READ_ISSUE_CMD;
|
cmd_state <= STATE_READ_ISSUE_CMD;
|
|
|
when STATE_READ_ISSUE_CMD =>
|
when STATE_READ_ISSUE_CMD =>
|
read_wait_rst <= '1';
|
read_wait_rst <= '1';
|
main_cmd <= CMD_READ;
|
main_cmd <= CMD_READ;
|
main_bank <= addr(25 downto 24);
|
main_bank <= addr_save(25 downto 24);
|
main_addr <= "001" & addr(10 downto 1); -- last bit determines upper/lower byte
|
main_addr <= "001" & addr_save(10 downto 1); -- last bit determines upper/lower byte
|
cmd_state <= STATE_READ_WAIT_CAPTURE;
|
cmd_state <= STATE_READ_WAIT_CAPTURE;
|
|
|
when STATE_READ_WAIT_CAPTURE =>
|
when STATE_READ_WAIT_CAPTURE =>
|
op_ack <= '1';
|
|
read_wait_rst <= '0';
|
read_wait_rst <= '0';
|
reader_rst <= '0';
|
reader_rst <= '0';
|
main_cmd <= CMD_NOP;
|
main_cmd <= CMD_NOP;
|
main_bank <= "00";
|
main_bank <= "00";
|
main_addr <= "0000000000000";
|
main_addr <= "0000000000000";
|
